JPH01103084A - Emphasis/de-emphasis circuit - Google Patents

Abstract

PURPOSE:To improve an S/N and to obtain a large degree of freedom of frequency characteristic by adopting the constitution of stable inverse filter having lots of parameters and introducing a nonlinear circuit to an edge processing section. CONSTITUTION:A unit delay element 1 receives an input or output signal and retards the reception signal by a unit time and delay elements 2, 3 retard the signal by an integral number of mutliple. A subtractor 4 subtracts output signals of delay elements 1-3 from the reception signal. A cascade connection circuit connecting at least a coefficient circuit 5 to the edge detection circuit is provided as plural numbers. Then each output signal of each cascade connection circuit is added by an adder 11. Thus, the stable inverse filter is constituted while having lots of dispersion to obtain a large degree of freedom of frequency characteristic.

Description

[Detailed Description of the Invention] (Industrial Application Field) This invention relates to an emphasis/de-emphasis circuit for reducing noise mixed in during transmission of video signals, etc. The present invention relates to an emphasis/de-emphasis circuit that can obtain a high degree of S/N improvement without causing waveform transmission distortion by having the circuit configuration described in detail.

(Summary of the Invention) The present invention relates to an emphasis/de-emphasis circuit during transmission of video signals, audio signals, etc.
The edge detection circuit consisting of a delay element and a subtracter has a plurality of cascaded circuits each having a coefficient circuit connected thereto, and the output signals of each of these cascaded circuits are added to form an emphasis/deemphasis circuit. By having it as a component of the The object of the present invention is to provide an emphasis/de-emphasis circuit that is a stable digital circuit and can be easily converted into a bird's eye.

(Conventional technology) Conventionally, emphasis/de-emphasis circuit section, resistor (
It was composed of an analog circuit using R), a coil (L), and a capacitor (C), or it was a simple structure consisting of one unit delay element. L, C.

Since the circuit using R is widely known, the explanation thereof will be omitted here.

Figure 4 shows a conventional example of emphasis using a unit delay element.
The configuration of a de-emphasis circuit is shown.

z-1 is the unit delay element L k,1-, 1/(1-k)
represents coefficient multiplier 14.16.15. In this case, k is selected to be a positive number smaller than 1, and as shown in Figure 5, the emphasis circuit exhibits high-frequency emphasis (a), the de-emphasis circuit exhibits high-frequency suppression (b), and both filters exhibit the following characteristics: They have opposite characteristics to each other. Here, if the delay time of a unit delay element is t, then f,=2 (1) t.

Since the emphasis circuit and de-emphasis circuit have an inverse filter relationship, the signal does not change between transmission and reception, but the noise mixed in during transmission is reduced by the de-emphasis high-frequency suppression bone, and the S/N ratio is reduced. Improvements will be made.

(Problems to be Solved by the Invention) Although the conventional analog emphasis/de-emphasis circuit using C and R elements has a simple configuration, it has problems such as deterioration over time and difficulty in adjustment. On the other hand, delay elements can be configured with digital elements, and there is no problem with stability, but the degree of freedom in changing the frequency characteristics is small, as shown in Figure 5 (in Figure 5, a can be changed). Therefore, it was not possible to design an optimal emphasis/de-emphasis circuit for the signal and transmission line noise spectra.

FIG. 6 shows a level diagram of FM transmission. Due to emphasis, the dotted line portion of the transient waveform generated at the edge portion is outside the transmission band, and if this portion is deleted, it appears as truncation noise. Therefore, large emphasis could not be applied.

Therefore, it is an object of the present invention to provide a large S/R signal that can be configured with a stable digital circuit that eliminates the above-mentioned problems, has a large degree of freedom in frequency characteristics, and eliminates waveform distortion during transmission such as truncation noise that occurs during FM transmission. It is an object of the present invention to provide an emphasis/de-emphasis circuit in which N improvement degree can be measured.

(Means for Solving the Problem) In order to achieve this object, the emphasis/de-emphasis circuit of the present invention provides an emphasis/de-emphasis circuit for noise reduction in television signal transmission. an edge detection circuit that includes at least a unit delay element that receives and delays the received signal by a unit time or a delay element that delays the received signal by an integral multiple thereof, and a subtracter that subtracts the output signal of the delay element from the received signal. The present invention is characterized in that a plurality of cascade-connected circuits each having coefficient circuits connected thereto is provided, and a circuit portion for adding the respective output signals of the cascade-connected circuits is included as a component of the emphasis/de-emphasis circuit.

(Examples) The present invention will be described in detail below by way of examples with reference to the accompanying drawings.

The configuration block diagrams of the first embodiment of the emphasis circuit and de-emphasis circuit according to the present invention are shown in FIG.
), Φ). The first embodiment of the emphasis circuit includes an edge extraction circuit composed of a unit delay element 1 and a subtracter 4, a coefficient multiplier 5 whose coefficient value is /(1-k)(l-1),
and an edge processing circuit consisting of a nonlinear circuit 8 of cascaded Q, a 2-sample delay element 2 of which unit delay elements are cascaded, and a coefficient multiplier 6 of l/(1-k)(1-1). , and an edge processing circuit consisting of a nonlinear circuit 9 of Q2 and a 3-sample delay element 3, −k N/(1−k
)(1-1), and the nonlinear circuit 1 of Q3.
This is a nonlinear emphasis circuit consisting of an edge processing circuit consisting of 0 and an adder 12 that adds input signals.

- The structure of the de-emphasis circuit of the embodiment of the power cylinder 1 is a recursive nonlinear emphasis circuit having an edge processing circuit having the same structure as the edge processing circuit of the emphasis circuit.

The transmission function of the conventional example shown in FIGS. 4(a) and 4(b) is as follows.

0≦k<1 )1(z): Transfer function H-'(
z): Transfer function of de-emphasis circuit (2) Here, the zero point and pole of H(z) are zero point: z=k (<1) pole: z=0, both are within the unit circle in the complex plane, and H (
z) satisfies the minimum phase condition. Therefore, a stable inverse filter exists, which is H-'(z). This shows that the emphasis/de-emphasis circuit based on the conventional circuit shown in Figure 4 can be realized as stable hardware, and the emphasis/de-emphasis circuit of the present invention must satisfy the minimum phase condition. .

First, we derive a general form of the emphasis/deemphasis circuit that does not include nonlinear circuits.

When formula (2) is extended, the emphasis transfer function H(z) at which the filter characteristic has the minimum phase becomes the following formula.

0≦, l<1 N: Positive integer value (3) That is, zero point of H(z): z= r[<1 pole: z=0<1, and H(Z) satisfies the minimum phase condition. Therefore, a stable inverse filter exists, and if this is designated as H-' (z), then this becomes the transfer function of the de-emphasis circuit.

Next, a nonlinear circuit is introduced to suppress waveform distortion such as truncation noise that occurs at the edge.
This must work only on the edges. H(t) is modified and defined as follows.

Here, if , then from this, X (2): 2 conversions of input signal Y (2): 2 conversions of output signal (7
). The second term on the right side of equation (7) (X(z)
(z)z-'') represents edge extraction of the signal. From this, the equation introducing the nonlinear circuit becomes the following equation.

The first example is +−k, kz=p,
This is the case of (9). Equation (8) is Y(z)=X(z)+(口Bkcr(χ(z)−X
(z)z-') tena, -1・tx (K(z) -X
(z)z-”J10oz(-knri・a(X(
z) -

On the other hand, for H-' (Z), it becomes by analogy with the expansion of the equation for H(z), and the equation that introduces the nonlinear circuit becomes.

In the first example, −Y(z)=X(z) −(Q+ ・kα(Y(z)−
Y(z)z-1]+Qt ・l ・ex (Y(z)
-Y(2)Z-")+Q*(-klri ・ex (Y(
Z) -Y(Z)! -') ) Q4), and the first
The configuration shown in Figure (b) is obtained. Here, the characteristics of the nonlinear circuit Q are shown in FIG. Although it has a clip characteristic, a general nonlinear circuit may be used.

FIG. 7 shows the case where the input of the emphasis/de-emphasis circuit according to the first embodiment is a step waveform.
The waveforms at each point in the figure are shown. thl to ths are the threshold values (th) of the nonlinear circuits Q, .about.Q.

Since the edge processing sections of the emphasis and de-emphasis circuits in Fig. 1 have the same circuit configuration, as is clear from Fig. 7, the output signal of the de-emphasis circuit is the same as the input signal of the emphasis circuit and is not subject to distortion. .

The threshold cold values th+ to th are set so that the truncation noise shown in FIG. 6 does not occur. In addition, the signal on the transmission line is E=P=A+ (B+ +C+ 10+) in Figure 7.
05).

A block diagram of the configuration of the second embodiment is shown in FIG.

Here, the difference from the first embodiment is that one nonlinear circuit is inserted into all the sums of the edge processing section (output of the adder 11). Although the degree of freedom in design is lower than in the first embodiment, it has the advantage of simplifying the circuit. The characteristics of the Q nonlinear circuit 13 are shown in FIG. 3, and the threshold value th is set at a point at which truncation noise does not occur.

In Example 1.2, the number of delay elements is three, but if equation (8) and Q3) are followed, there is no limit to the number.

(Effects of the Invention) Conventional emphasis and de-emphasis circuits have problems with aging and adjustment when configured with analog circuits.

Furthermore, in digital circuits, the degree of freedom in frequency characteristics, that is, the degree of freedom in design, is small and there is no nonlinear characteristic, so there is no countermeasure against truncation noise, and it has not been possible to increase the degree of S/N improvement.

According to the present invention, a large degree of freedom can be obtained in frequency characteristics by adopting a stable inverse filter configuration with a large number of parameters, and by introducing a nonlinear circuit into the edge processing section, waveforms such as truncation noise during FM transmission can be It enables a large degree of S/N improvement without generating distortion, and has the advantage that stable hardware can be realized because digital elements can be used.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) show the nonlinear emphasis of the present invention. A first embodiment of the de-emphasis circuit is shown, FIGS. 2(a) and 2(b) respectively show the second embodiment, and FIG. Figure (a),
5(b) shows conventional emphasis and de-emphasis circuits using unit delay elements, and FIGS. 5(a) and 5(b) show the frequency characteristics of the configurations shown in FIGS. FIG. 6 shows the relationship between the transmission bandwidth and the video signal during FM transmission, and FIG. 7 shows the waveform at each point when the step waveform is input in the first embodiment of the present invention. 1...Unit delay element 2...2 sample delay element 3...3 sample delay element 4...Subtractor 5, 6. 7.14.15.16...Each coefficient unit 8,
9.10.13...Non-linear circuits 11, 12...
Adder by patent attorney Oki Sugimura 1st
Turn ship, f) Accidental example (a) Non-linear theanymphasis day 1 each ＼ Figure 2 Chaotic example in the second (a) lt = Deprivation Ethophasi 21K (b) Nonlinear theanymphasis circuit Figure 3 Output Figure 4 Grass position slow release element 1ft, Tsume Takugi Izumi example (a) Emphasis times) Each (b) Appetizer en 7 ance circuit Figure 5 Figure 4 0 special 4 raw Figure 6 Relationship when sending FM Buddha No. 7 Figure Step-1 input Q-type, Vi-type output

Claims (1)

[Claims] 1. In an emphasis/de-emphasis circuit for noise reduction in television signal transmission, a unit delay element or an integral multiple thereof that receives an input or output signal and delays the received signal by a unit time. A plurality of cascaded circuits are provided in which at least a coefficient circuit is connected to an edge detection circuit including a delay element that delays the signal, and a subtracter that subtracts the output signal of the delay element from the received signal, and each output of each of the cascaded circuits. Emphasis is added to the circuit section that adds signals.
An emphasis/de-emphasis circuit comprising the de-emphasis circuit as a component of the de-emphasis circuit.