JPH02198205A - Phase modulator and demodulator - Google Patents
Phase modulator and demodulatorInfo
- Publication number
- JPH02198205A JPH02198205A JP1019045A JP1904589A JPH02198205A JP H02198205 A JPH02198205 A JP H02198205A JP 1019045 A JP1019045 A JP 1019045A JP 1904589 A JP1904589 A JP 1904589A JP H02198205 A JPH02198205 A JP H02198205A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- carrier
- circuit
- phase
- modulation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000003044 adaptive effect Effects 0.000 claims abstract description 17
- 238000001228 spectrum Methods 0.000 abstract description 6
- 230000008030 elimination Effects 0.000 abstract 1
- 238000003379 elimination reaction Methods 0.000 abstract 1
- 230000036039 immunity Effects 0.000 abstract 1
- 239000003623 enhancer Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000001360 synchronised effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000027311 M phase Effects 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、位相変調信号の搬送波位相及び周波数同期に
関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to carrier phase and frequency synchronization of phase modulated signals.
（従来の技術）
従来、変調のかかった搬送波信号の位相、周波数同期回
路には一般にフェーズロックループ回路が用いられてい
た。これには多くの文献があり、例えば文献（Ｆｌｏｙ
ｄ、Ｍ、 Ｇａｒｄｎｅｒ著” ｐｈａｓｅｌｏｃｋｔ
ｅｃｈｎｉｑｕｅｓ”、 Ｊｈｏｎ Ｗｉｌｅｙ ＆
５ｏｎｓ、 Ｉｎｃ、、 Ｎｅｗｙｏｒｋ。(Prior Art) Conventionally, a phase-locked loop circuit has generally been used as a phase and frequency synchronization circuit for a modulated carrier signal. There is a lot of literature on this, for example in the literature (Floy
d. M. Gardner” phaselockt
echniques”, John Wiley &
5ons, Inc., New York.
１９６６年刊がある。There is a version published in 1966.
（発明が解決しようとする問題点）
従来技術では、低信号電力対雑音比での同期特性と広範
囲での同期引き込み特性とは相反する条件とされ同時に
みたされず、更、に低信号電力対雑音比では同期引き込
みに要する時間が非常に長かったことが問題としてあげ
られる。本発明はこれを解決しようとしている。(Problems to be Solved by the Invention) In the prior art, the synchronization characteristics at a low signal power to noise ratio and the synchronization pull-in characteristics over a wide range are contradictory conditions and cannot be satisfied at the same time. The problem with the noise ratio was that the time required to acquire synchronization was extremely long. The present invention seeks to solve this problem.
（問題を解決するための手段）
本発明の位相変調復調器は、位相変調信号を入力し、該
信号の変調成分を取り除き変調除去信号を出力する変調
除去回路と変調除去信号を入力し信号のキャリア成分を
強調する適応輝線強調回路と該適応輝線強調回路の出力
に対して逐次キャリア同期を行う同期回路と該同期回路
で得られたキャリア信号の周波数位相値により前記位相
変調信号の同期を行う補正器とを含んで構成される。(Means for Solving the Problem) The phase modulation demodulator of the present invention includes a modulation removal circuit that inputs a phase modulation signal, removes the modulation component of the signal, and outputs a modulation removal signal; an adaptive bright line emphasizing circuit that emphasizes a carrier component; a synchronization circuit that sequentially performs carrier synchronization on the output of the adaptive bright line emphasizing circuit; and synchronization of the phase modulation signal using the frequency phase value of the carrier signal obtained by the synchronization circuit. and a corrector.
（作用）
第１図に本発明の基本的な構成図を示す。受信された位
相変調信号は、キャリア信号成分のみを得るために変調
除去回路１に入力され、変調成分を取り除かれる。この
信号をスペクトルでみると、線スペクトル（キャリア信
号成分）にガウス雑音が加わった様に見える。変調除去
された信号は、続いて適応輝線強調回路２に入力される
。適応輝線強調回路２は線スペクトルを適応的に抽出す
る狭帯域のバンドパスフィルタで、線スペクトル以外の
ランダム雑音を抑圧する。この適応輝線強調回路２によ
り受信信号のキャリア信号成分電力対雑音電力比は非常
に改善される。第２図に適応輝線強調器の入力及び出力
スペクトラムを示し、キャリア信号成分電力対雑音電力
比が改善された様子を示す。この改善された適応輝線強
調回路出力信号を同期回路３に入力する。同期回路３で
はキャリア位相及び周波数に同期した推定キャリアを作
り出し、補正器４で受信信号を推定キャリアで復調する
。(Operation) FIG. 1 shows a basic configuration diagram of the present invention. The received phase modulated signal is input to a modulation removal circuit 1 to remove the modulation component in order to obtain only the carrier signal component. When looking at the spectrum of this signal, it looks like Gaussian noise has been added to the line spectrum (carrier signal component). The modulated signal is then input to the adaptive bright line enhancement circuit 2. The adaptive bright line enhancement circuit 2 is a narrow band pass filter that adaptively extracts the line spectrum, and suppresses random noise other than the line spectrum. This adaptive bright line enhancement circuit 2 greatly improves the carrier signal component power to noise power ratio of the received signal. FIG. 2 shows the input and output spectra of the adaptive bright line enhancer, showing how the carrier signal component power to noise power ratio is improved. This improved adaptive bright line enhancement circuit output signal is input to the synchronization circuit 3. A synchronization circuit 3 generates an estimated carrier synchronized with the carrier phase and frequency, and a corrector 4 demodulates the received signal with the estimated carrier.
（実施例）
第３図に本発明の一実施例を２相位相変調信号を例にと
って示す。受信された位相変調信号の変調を除去する変
調除去回路１としては図に示すように逓倍器を用いる。(Embodiment) FIG. 3 shows an embodiment of the present invention using a two-phase phase modulation signal as an example. As the modulation removal circuit 1 for removing the modulation of the received phase modulation signal, a multiplier is used as shown in the figure.
例えばＭ相位相変調にはＭ倍の逓倍器を用いる。第３図
に示す例では２相位相変調信号が入力されるので、入力
信号を自乗している。For example, an M-times multiplier is used for M-phase phase modulation. In the example shown in FIG. 3, since a two-phase phase modulation signal is input, the input signal is squared.
この逓倍器１の出力を適応輝線強調器２に入力する。適
応輝線強調器２は文献（Ｂ、 Ｗｉｄｒｏｗ、 ｅｔ、
ａｌ。The output of this multiplier 1 is input to an adaptive bright line enhancer 2. The adaptive bright line enhancer 2 is described in the literature (B, Widrow, et.
al.
“Ａｄｐｔｉｖｅ Ｎｏ１ｓｅ Ｃａｎｃｅｌｌｉｎｇ
： Ｐｒ１ｎｃｉｐｌｅｓ ａｎｄＡｐｐｌｉｃａｔ
ｉｏｎｓ”、 Ｐｒｏｃ、 ＩＥＥＥ、 Ｖｏｌ、 ６
３． Ｄｅｃ、、 １９７５）に記載のものを用いる。“Adaptive No.1 Canceling
: Pr1nciples and Applications
ions”, Proc, IEEE, Vol. 6
3. Dec., 1975) is used.
この文献によれば、適応＃線強調器２は相関分離器２１
、適応フィルタ２２加算器２３、適応アルゴリズム回路
２４から構成される。According to this document, the adaptive # line enhancer 2 includes a correlation separator 21
, an adaptive filter 22, an adder 23, and an adaptive algorithm circuit 24.
又、同期回路３としては、逐次制御系ならば通常用いら
れているフェーズロックループでも良いし、特開昭６１
−１５４３１７号公報［周波数・位相推定装置Ｊに記載
のものでも良い。但し、これら同期回路で追従する位相
・周波数は逓倍後の値であるから、補正回路４に渡す前
に１／Ｍ倍する必要がある。In addition, the synchronous circuit 3 may be a commonly used phase-locked loop in the case of a sequential control system, or a
-154317 [Frequency/phase estimation device J] may be used. However, since the phase and frequency tracked by these synchronization circuits are multiplied values, it is necessary to multiply them by 1/M before passing them to the correction circuit 4.
（発明の効果）
本発明によれば実時間処理性を失わずに、従来方式の位
相同期と比較して対雑音特性、同期引き込み範囲、同期
引き込みの高速性の面で優れている。(Effects of the Invention) According to the present invention, the present invention is superior in terms of noise resistance, synchronization pull-in range, and high-speed synchronization pull-in compared to conventional phase synchronization without losing real-time processing performance.
第１図は本発明の基本的な構成を示す図、第２図は本発
明の効果を示す図、第３図は本発明の一実施例を示す図
である。図中、１・・・変調除去回路、２・・・適応輝
線強調器、３・・・同１期回路、４．１．補正器である
。FIG. 1 is a diagram showing the basic configuration of the invention, FIG. 2 is a diagram showing the effects of the invention, and FIG. 3 is a diagram showing an embodiment of the invention. In the figure, 1...Modulation removal circuit, 2...Adaptive bright line enhancer, 3...Synchronized first period circuit, 4.1. It is a corrector.
Claims (1)
調除去信号を出力する変調除去回路と変調除去信号を入
力し信号のキャリア成分を強調する適応輝線強調回路と
該提供輝線強調回路の出力に対して逐次キャリア同期を
行う同期回路と該同期回路で得られたキャリア信号の周
波数位相値により前記位相変調信号の同期を行う補正器
とから構成されることを特徴とする位相変調復調器。A modulation removal circuit that inputs a phase modulation signal, removes the modulation component of the signal, and outputs a modulation removal signal; an adaptive bright line enhancement circuit that inputs the modulation removal signal and emphasizes the carrier component of the signal; and an output of the provided bright line enhancement circuit. A phase modulation demodulator comprising: a synchronization circuit that sequentially performs carrier synchronization with respect to the carrier signals; and a corrector that synchronizes the phase modulation signal based on the frequency phase value of the carrier signal obtained by the synchronization circuit.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1019045A JP2513292B2 (en) | 1989-01-26 | 1989-01-26 | Phase modulation demodulator |
| US07/470,215 US5090027A (en) | 1989-01-26 | 1990-01-25 | Coherent PSK demodulator with adaptive line enhancer |
| CA002008595A CA2008595C (en) | 1989-01-26 | 1990-01-25 | Coherent psk demodulator with adaptive line enhancer |
| AU48878/90A AU623484B2 (en) | 1989-01-26 | 1990-01-29 | Coherent psk demodulator with adaptive line enhancer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1019045A JP2513292B2 (en) | 1989-01-26 | 1989-01-26 | Phase modulation demodulator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02198205A true JPH02198205A (en) | 1990-08-06 |
| JP2513292B2 JP2513292B2 (en) | 1996-07-03 |
Family
ID=11988449
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1019045A Expired - Lifetime JP2513292B2 (en) | 1989-01-26 | 1989-01-26 | Phase modulation demodulator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2513292B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0563743A (en) * | 1991-09-03 | 1993-03-12 | Nec Corp | Adaptive carrier recovery demodulation system and adaptive carrier recovery demodulator |
| US6125151A (en) * | 1995-03-11 | 2000-09-26 | Nec Corporation | Carrier recovery circuit |
| JP2013502102A (en) * | 2009-08-13 | 2013-01-17 | 富士通株式会社 | Phase recovery apparatus, phase recovery method, and receiver for 16QAM data modulation |
-
1989
- 1989-01-26 JP JP1019045A patent/JP2513292B2/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0563743A (en) * | 1991-09-03 | 1993-03-12 | Nec Corp | Adaptive carrier recovery demodulation system and adaptive carrier recovery demodulator |
| US6125151A (en) * | 1995-03-11 | 2000-09-26 | Nec Corporation | Carrier recovery circuit |
| JP2013502102A (en) * | 2009-08-13 | 2013-01-17 | 富士通株式会社 | Phase recovery apparatus, phase recovery method, and receiver for 16QAM data modulation |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2513292B2 (en) | 1996-07-03 |
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