JP2513292B2 - Phase modulation demodulator - Google Patents
Phase modulation demodulatorInfo
- Publication number
- JP2513292B2 JP2513292B2 JP1019045A JP1904589A JP2513292B2 JP 2513292 B2 JP2513292 B2 JP 2513292B2 JP 1019045 A JP1019045 A JP 1019045A JP 1904589 A JP1904589 A JP 1904589A JP 2513292 B2 JP2513292 B2 JP 2513292B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- modulation
- phase
- adaptive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は、位相変調信号の搬送波位相及び周波数同期
に関するものである。The present invention relates to carrier phase and frequency synchronization of a phase modulation signal.
（従来の技術） 従来、変調のかかった搬送波信号の位相、周波数同期
回路には一般にフェーズロックループ回路が用いられて
いた。これには多くの文献があり、例えば文献（Floyd,
M.Gardner著"phaselock techniques",Jhon Wiley ＆ So
ns,Inc.,Newyork,1966年刊がある。(Prior Art) Conventionally, a phase-locked loop circuit is generally used for the phase and frequency synchronization circuit of a modulated carrier signal. There are many references to this, for example the references (Floyd,
"Phase lock techniques" by M. Gardner, Jhon Wiley & So
ns, Inc., Newyork, 1966.
（発明が解決しようとする問題点） 従来技術では、低信号電力対雑音比での同期特性と広
範囲での同期引き込み特性とは相反する条件とされ同期
にみたされず、更に低信号電力対雑音比では同期引き込
みに要する時間が非常に長かったことが問題としてあげ
られる。本発明はこれを解決しようとしている。(Problems to be Solved by the Invention) In the prior art, the synchronization characteristics at a low signal power-to-noise ratio and the synchronization pull-in characteristics at a wide range are contradictory conditions and are not observed in synchronization. In terms of the ratio, the problem is that the time required for synchronous pull-in was very long. The present invention seeks to solve this.
（問題を解決するための手段） 本発明の位相変調復調器は、位相変調信号を入力し、
該信号の変調成分を取り除き変調除去信号を出力する変
調除去回路と、変調除去信号を入力し信号のキャリア成
分を強調する適応輝線強調回路と、該適応輝線強調回路
の出力に対して逐次キャリア同期を行う同期回路と、該
同期回路に得られたキャリア信号の周波数と位相値によ
り前記位相変調信号の同期を行う補正値とを含んで構成
される。(Means for Solving the Problem) The phase modulation demodulator of the present invention inputs a phase modulation signal,
A modulation removal circuit that removes the modulation component of the signal and outputs a modulation removal signal, an adaptive bright line enhancement circuit that inputs the modulation removal signal and enhances the carrier component of the signal, and a sequential carrier synchronization with the output of the adaptive bright line enhancement circuit. And a correction value for synchronizing the phase modulation signal with the frequency and phase value of the carrier signal obtained by the synchronization circuit.
（作用） 第１図に本発明の基本的な構成図を示す。受信された
位相変調信号は、送受信搬送波の差の成分、すなわちキ
ャリア信号成分のみを得るために変調除去回路１に入力
され、変調成分を取り除かれる。この信号とスペクトル
でみると、線スペクトル（キャリア信号成分）にガウス
雑音が加わった様に見える。変調除去された信号は、続
いて適応輝線強調回路２に入力される。適応輝線強調回
路２は線スペクトルを適応的に抽出する狭帯域のバンド
パスフィルタで、線スペクトル以外のランダム雑音を抑
圧する。この適応輝線強調回路２により変調除去された
信号成分電力対雑音電力比は非常に改善される。第２図
に適応輝線強調回路の入力及び出力スペクトラムを示
し、変調除去された信号成分電力対雑音電力比が改善さ
れた様子を示す。この改善された適応輝線強調回路出力
信号を同期回路３に入力する。適応輝線強調回路の出力
は、変調除去された信号成分であるので、同期回路３で
は変調除去回路１へ入力される前のキャリア信号成分に
交換しキャリア信号の周波数と位相値の推定値を求め、
補正器４で受信信号を同期回路出力により復調する。(Operation) FIG. 1 shows a basic configuration diagram of the present invention. The received phase-modulated signal is input to the modulation removal circuit 1 to obtain only the difference component between the transmitted and received carriers, that is, the carrier signal component, and the modulation component is removed. Looking at this signal and spectrum, it seems that Gaussian noise is added to the line spectrum (carrier signal component). The signal from which the modulation has been removed is subsequently input to the adaptive bright line emphasizing circuit 2. The adaptive bright line emphasizing circuit 2 is a narrow band bandpass filter that adaptively extracts the line spectrum, and suppresses random noise other than the line spectrum. The signal-to-noise power ratio of the signal component demodulated by the adaptive bright line emphasizing circuit 2 is greatly improved. FIG. 2 shows the input and output spectra of the adaptive bright line emphasizing circuit, and shows how the demodulated signal component power to noise power ratio is improved. The improved adaptive bright line emphasizing circuit output signal is input to the synchronizing circuit 3. Since the output of the adaptive bright line emphasizing circuit is the signal component with the modulation removed, the synchronizing circuit 3 exchanges the carrier signal component before being input to the modulation removing circuit 1 to obtain the estimated values of the frequency and phase value of the carrier signal. ,
The corrector 4 demodulates the received signal by the output of the synchronous circuit.
（実施例） 第３図に本発明の一実施例を２相位相変調信号を例に
とって示す。受信された位相変調信号の変調を除去する
変調除去回路１としては図に示すように逓倍器を用い
る。例えばＭ相位相変調にはＭ倍の逓倍器を用いる。Ｍ
倍の逓倍器は、入力Ｍ相位相変調信号ｒ（ｉ）とする
と、 Ｓ（ｉ）＝ｒ（ｉ）Ｍ の演算を行う。入力Ｍ相位相変調信号は変調情報をｋ
（ｋ＝1,2,・・・Ｍ）とすると、 ｒ（ｉ） ＝ｅj2π（ωｉ＋θ＋ｋ（ｉ）/M）＋ｗ（ｉ） 但し、ｊは虚数、ωはキャリア信号周波数、θはキャ
リア信号位相、ｗ（ｉ）は熱雑音である と表される。この信号の逓倍器出力ｓ（ｉ）は、 ｓ（ｉ）＝ｅj2πＭ（ωｉ＋θ）＋ｗ（ｉ）Ｍ となって出力される。逓倍器Ｍ逓倍することにより、変
調成分は除去され、Ｍ逓倍されたキャリア信号と雑音の
みの変調除去された信号が変調除去回路から出力され
る。第３図に示す例では２相位相変調信号が入力される
ので、入力信号を自乗している。この逓倍器１の出力を
適応輝線強調回路２に入力する。(Embodiment) FIG. 3 shows an embodiment of the present invention by taking a two-phase phase modulation signal as an example. As the modulation removing circuit 1 for removing the modulation of the received phase modulation signal, a multiplier is used as shown in the figure. For example, a multiplier of M times is used for M phase modulation. M
The double multiplier calculates S (i) = r (i) M when the input M-phase phase modulated signal r (i) is used. The input M-phase phase-modulated signal has modulation information k
(K = 1,2, ... M), r (i) = e j2π (ωi + θ + k (i) / M) + w (i) where j is an imaginary number, ω is a carrier signal frequency, and θ is a carrier signal. The phase, w (i), is represented as thermal noise. The multiplier output s (i) of this signal is output as s (i) = e j2πM (ωi + θ) + w (i) M. By multiplying the multiplier M, the modulation component is removed, and the carrier signal that has been M-multiplied and the signal that has been subjected to the modulation removal of only noise are output from the modulation removal circuit. In the example shown in FIG. 3, since the two-phase modulation signal is input, the input signal is squared. The output of the multiplier 1 is input to the adaptive bright line emphasizing circuit 2.
適応輝線強調回路２は、相関分離器21、適応フィルタ
22、加算器23、適応アルゴリズム回路24から構成され、
以下の演算を行う。The adaptive bright line emphasis circuit 2 includes a correlation separator 21 and an adaptive filter.
22, an adder 23, an adaptive algorithm circuit 24,
The following calculation is performed.
相関分離器は位相変調信号のシンボル時間（Td）だけ
遅延させる遅延素子である。これにより、逓倍器１の出
力ｓ（ｉ）と適応フィルタ22の出力ｙ（ｉ）との相関成
分はキャリア信号成分のみとなり、他の成分に対しては
両者の間に相関がなくなる。適応輝線強調回路は、適応
フィルタ22が変調除去された信号ｓ（ｉ）と相関のある
成分を抽出するフィルタを作り出すように適応フィルタ
の係数Ｃを制御する。この場合、相関分離器を介して入
力される信号と変調除去された信号との間の相関成分は
逓倍されたキャリア信号のみであるので、フィルタはキ
ャリア信号のみを出力する挟帯域フィルタになる。The correlation separator is a delay element that delays by the symbol time (T d ) of the phase modulation signal. As a result, the correlation component between the output s (i) of the multiplier 1 and the output y (i) of the adaptive filter 22 is only the carrier signal component, and the other components have no correlation between them. The adaptive bright line emphasizing circuit controls the coefficient C of the adaptive filter so that the adaptive filter 22 creates a filter that extracts a component correlated with the demodulated signal s (i). In this case, since the correlation component between the signal input through the correlation separator and the demodulated signal is only the multiplied carrier signal, the filter is a narrow band filter that outputs only the carrier signal.
適応フィルタをFIRフィルタで構成するとフィルタの
タップ長Ｌ（タップ係数C1・・・・CL）からなるトラン
スバーサルフィルタで、出力ｙ（ｉ）は ｙ（ｉ）＝CTXi Ｃ＝［C1C2C3・・・CL］Ｔ Ｘ＝［ｘ（ｉ−Td）ｘ（ｉ−１−Td） ・・・ｘ（ｉ−Ｌ−１−Td）］Ｔ 但し、ATはベクトルＡの転置を示す となる。また、加算器22の出力である誤差信号ｅ（ｉ）
は、 ｅ（ｉ）＝ｓ（ｉ）−ｙ（ｉ） で表される。係数ベクトルＣは、ｅ（ｉ）X1の平均値が
０に保たれるように適応アルゴリズム回路で制御され
る。このとき、適応輝線強調回路はＭ逓倍されたキャリ
ア信号を抽出する挟帯域フィルタになる。When the adaptive filter is composed of an FIR filter, it is a transversal filter having a filter tap length L (tap coefficient C 1 ... C L ), and the output y (i) is y (i) = C T X i C = [ C 1 C 2 C 3 ... C L ] T X = [x (i-T d ) x (i-1-T d ) ... x (i-L-1-T d )] T However, A T is the transpose of the vector A. In addition, the error signal e (i) which is the output of the adder 22
Is represented by e (i) = s (i) -y (i). The coefficient vector C is controlled by the adaptive algorithm circuit so that the average value of e (i) X 1 is kept at zero. At this time, the adaptive bright line emphasizing circuit serves as a narrow band filter for extracting the carrier signal multiplied by M.
係数を制御するアルゴリズムの例としては、ｅ（ｉ）
の自乗平均誤差を最小にするLMSアルゴリズムを用いる
と、係数ベクトルは適応乗数をμとすると次式により制
御される C1+1＝C1＋μｅ（ｉ）Xi 適応アルゴリズム回路24は上式を演算する。又、同期
回路３としては、信号を復調するために、キャリア信号
の周波数、位相成分が必要であり、振幅成分ひ必要でな
い。適応輝線強調回路の出力の位相・周波数は逓倍後の
値であるから、補正器４に渡す前に1/M倍に分周した信
号の複素共役（但し、Ａ＊はＡの複素共役を示す）を出
力する必要がある。1/M逓倍は、 ｚ（ｉ）＝ｙ（ｉ）1/M//|y（ｉ）｜ の演算をすればよいが、実際ｙ（ｉ）は複素数なので、
この演算は不可能である。同期回路としては、出力とし
ては、位相成分が必要なのであるから、同等の演算とし
て、以下の様な演算で実現される。An example of an algorithm for controlling the coefficient is e (i)
When the LMS algorithm that minimizes the root mean square error of is used, the coefficient vector is controlled by the following equation when the adaptive multiplier is μ C 1 + 1 = C 1 + μe (i) X i The adaptive algorithm circuit 24 Calculate Further, the synchronizing circuit 3 needs the frequency and phase components of the carrier signal in order to demodulate the signal, and does not need the amplitude component. Since the phase / frequency of the output of the adaptive bright line emphasizing circuit is the value after multiplication, the complex conjugate of the signal divided by 1 / M times before passing to the corrector 4 (where A * represents the complex conjugate of A). ) Should be output. For 1 / M multiplication, z (i) = y (i) 1 / M // | y (i) | may be calculated, but since y (i) is actually a complex number,
This operation is impossible. Since a phase component is required as an output for the synchronizing circuit, it is realized by the following calculation as an equivalent calculation.
ｚ（ｉ）＝ｅ
ｊ（ATMN（Ｚ（ｉ−１）＋ATAN（ｙ（ｉ）ｙ（ｉ）＊）
／Ｍ） この演算により、L/Mに分周されたキャリア信号を得
られる。z (i) = e
j (ATMN (Z (i-1) + ATAN (y (i) y (i) *)
/ M) By this calculation, the carrier signal divided into L / M can be obtained.
補正器は、複素乗算器であり、同期回路の出力信号Ｚ
（ｉ）＊栄と受信した位相変調信号ｒ（ｉ）＝ｅ
j2π（ωｉ＋θ＋ｋ（ｉ）/M）＋ｗ（ｉ）と補正器で複
素乗算することにより、キャリア信号成分が除去され復
調信号が出力される。これらは、マイクロプロセッサに
より実現されるが、またはディジタル信号処理回路によ
り実現される。The corrector is a complex multiplier, and outputs the output signal Z of the synchronous circuit.
(I) * Sakae and the received phase modulation signal r (i) = e
The carrier signal component is removed and a demodulated signal is output by performing a complex multiplication with j2π (ωi + θ + k (i) / M) + w (i) by the corrector. These are implemented by a microprocessor or digital signal processing circuits.
（発明の効果） 本発明によれば実時間処理性を失わずに、従来方式の
位相同期と比較して対雑音特性、同期引き込み範囲、同
期引き込みの高速性の面で優れている。(Effects of the Invention) According to the present invention, the anti-noise characteristic, the sync pull-in range, and the speed of sync pull-in are superior to the conventional phase synchronization without losing the real-time processability.
第１図は本発明の基本的な構成を示す図、第２図は本発
明の効果を示す図、第３図は本発明の一実施例を示す図
である。図中、１……変調除去回路、２……適応輝線強
調器、３……同期回路、４……補正器である。FIG. 1 is a diagram showing a basic configuration of the present invention, FIG. 2 is a diagram showing effects of the present invention, and FIG. 3 is a diagram showing an embodiment of the present invention. In the figure, 1 ... Modulation removal circuit, 2 ... Adaptive bright line enhancer, 3 ... Synchronization circuit, 4 ... Corrector.
Claims (1)
を取り除き変調除去信号を出力する変調除去回路と、変
調除去信号を入力し信号のキャリア成分を強調する適応
輝線強調回路と、該適応輝線強調回路の出力に対して逐
次キャリア同期を行う同期回路と、該同期回路で得られ
たキャリア信号の周波数と位相値により前記位相変調信
号の同期を行う補正器とから構成されることを特徴とす
る位相変調復調器。1. A modulation removal circuit for inputting a phase modulation signal and removing a modulation component of the signal and outputting a modulation removal signal; an adaptive bright line enhancement circuit for inputting the modulation removal signal and enhancing a carrier component of the signal; A synchronous circuit that sequentially performs carrier synchronization with the output of the adaptive bright line emphasizing circuit, and a corrector that synchronizes the phase-modulated signal based on the frequency and phase value of the carrier signal obtained by the synchronous circuit. Characteristic phase modulation demodulator.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1019045A JP2513292B2 (en) | 1989-01-26 | 1989-01-26 | Phase modulation demodulator |
| CA002008595A CA2008595C (en) | 1989-01-26 | 1990-01-25 | Coherent psk demodulator with adaptive line enhancer |
| US07/470,215 US5090027A (en) | 1989-01-26 | 1990-01-25 | Coherent PSK demodulator with adaptive line enhancer |
| AU48878/90A AU623484B2 (en) | 1989-01-26 | 1990-01-29 | Coherent psk demodulator with adaptive line enhancer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1019045A JP2513292B2 (en) | 1989-01-26 | 1989-01-26 | Phase modulation demodulator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02198205A JPH02198205A (en) | 1990-08-06 |
| JP2513292B2 true JP2513292B2 (en) | 1996-07-03 |
Family
ID=11988449
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1019045A Expired - Lifetime JP2513292B2 (en) | 1989-01-26 | 1989-01-26 | Phase modulation demodulator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2513292B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3138509B2 (en) * | 1991-09-03 | 2001-02-26 | 日本電気株式会社 | Adaptive carrier recovery demodulation method and adaptive carrier recovery demodulator |
| JP2806296B2 (en) * | 1995-03-11 | 1998-09-30 | 日本電気株式会社 | Carrier recovery circuit |
| CN102160350B (en) * | 2009-08-13 | 2013-05-22 | 富士通株式会社 | Phase recovery device, phase recovery method and receiver for 16 quadrature amplitude modulation data modulation |
-
1989
- 1989-01-26 JP JP1019045A patent/JP2513292B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02198205A (en) | 1990-08-06 |
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