JPH01102964A - Semiconductor device and production thereof - Google Patents

Abstract

PURPOSE:To enable the overlapping length between a gate electrode and a first spacing film, and the length of source and drain regions to be independently changed each other, and to enhance the breakdown voltage of a device by making the gate electrode to extend under only the first spacing layer, and by forming a second spacing layer so as to cover over the sidewall of the extending part of the gate electrode. CONSTITUTION:A gate electrode 3 extends under the lower part of an insulating film 8 for spacer so that the length of the extending part of the gate electrode 3 can be controlled by the thickness of the insulating film 8 for spacer. An insulating film 81 for spacer is covered over the sidewall of the extending part of the gate electrode 3, and the length of lightly doped source and drain regions 7 is controlled by the thickness of the insulating film 81 for spacer. As a result, the length L1 of the extending part of the gate electrode 3 which overlaps with the source and drain regions 7, and the length (L1+L2) which corresponds to the length of the lightly doped source and drain regions 7 can be independently controlled. Accordingly, these elements can be optimized, respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a fine MOS transistor, and particularly to a high-voltage and high-speed semiconductor device and a method for manufacturing the same.

[Conventional technology]

L D D (Lightly Doped Drai
n) In order to improve the hot carrier withstand voltage of the 411 transistor, the structure in which the gate electrode protrudes below the gate sidewall spacer insulating film (abbreviated as spacer) is proposed by IDM 86. Page 742 (IEDM86.P
742). In this structure, the length Ln- of the lightly doped source/drain (n-layer) region and the gate/drain (source) overlap length are uniquely determined.

[Problem that the invention aims to solve]

The above-mentioned conventional technology does not take into account the fact that the length of the lightly doped source/drain region and the gate/drain (source) overlap length can be arbitrarily changed. However, the length of the lightly doped source/drain region and the gate/drain (source) overlap length have independent effects on increasing the breakdown voltage. Therefore, it is necessary to individually optimize these parameters, but there is a problem in that this cannot be done with the conventional technology. Furthermore, if the gate/drain overlap length is increased, a problem arises in that the gate capacitance increases. Therefore, the overlap length needs to be optimized to achieve high breakdown voltage while suppressing the increase in gate capacitance to the necessary minimum.

An object of the present invention is to independently change the overlap length of the gate/drain (source) and the length of the low concentration source/drain region to realize a semiconductor device with high breakdown voltage and an appropriate increase in gate capacitance, and a method for manufacturing the same. Our goal is to provide the following.

[Means for solving problems]

The above purpose is to first extend a thin conductive film to the side wall of the gate electrode, form a first layer of spacers on top of the thin conductive film and on the side walls of the gate electrode, and only under the spacer. This is achieved by creating a structure in which the gate electrode extends, forming a second layer of spacers on the side walls of the spacer, and forming highly doped sources and drains using the second layer of spacers as a mask.

[Effect]

The first layer spacer described above acts to control the gate/drain (source) overlap length. Further, the second layer spacer functions to control the length of the lightly doped source/drain region. Therefore, the overlap length and the length of the lightly doped source/drain regions can be changed as desired.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG.

N-type or p-type trench type Si substrate 1. Gate insulating film 2
．． Gate electrode film 3, 4, 5. Low-concentration source/drain 7 and high-concentration source/drain 9 formed with impurities of the opposite conductivity type to the Si substrate 1. Spacer insulating film 8 formed on the sidewall of the gate electrode. -81 and the insulating protective film 6 of the gate electrode film. FIG. Note that holes for source/drain electrode contact, electrode wiring, etc. are omitted in FIG. The first feature of this embodiment is that the gate electrode 3 protrudes from the bottom of the spacer insulating film 8, and the length of the protruding portion can be controlled by the thickness of the film 8'. The second feature is that the side walls of the projecting gate electrode 3 are covered with a spacer insulating film 81, and at the same time, the length of the low concentration source/drain 7 region is controlled by the thickness of the film 81.

According to this embodiment, the length Ll of the gate electrode 3 overlapping with the low concentration source/drain 7 and the length L corresponding to the length of the region of the low concentration source/drain 7
1+L2 can be controlled independently. Therefore, optimization can be performed for each.

Furthermore, since a film with high insulation properties, such as a 5iOz film deposited by high temperature and low pressure CVD, can be selected as the spacer insulating film 81, short circuits between the gate electrode 3 and the source/drain electrode wiring can be prevented.

FIG. 2 shows a cross-sectional structural diagram of an intermediate step in the process flow for realizing the structure shown in FIG. 1.

First, the steps from forming a gate insulating film 2 on a Si substrate 1 to forming a goo 1-electrode film 3 made of a polycrystalline silicon film are the same as those for forming a normal MOS transistor. However, the thickness of [3 is made as thin as 30 to 70 nm. After depositing the electrode film 3, the film 3 is exposed to the atmosphere, and 5 to 10 natural oxide films 4 are formed on the upper surface of the film. Thereafter, after the polycrystalline silicon film 5 is deposited again on the entire surface, the gate electrode film 3.5 is doped with impurities such as phosphorus. Then S,
After the tOz film 6 is deposited over the entire surface and a photoresist film gate mass pattern is formed (not shown), the 5iOz film 6 is pressurized using an anisotropic dry etching technique using the pattern as a mask. After this, the processed 5iOz
Using the film 6 as a mask, the gate electrode film 5 is processed by microwave etching technology. Since the etching rate ratio between the polycrystalline silicon film 5 and the natural oxide film 4 by microwave etching can be set to 100=1, the etching of the film 5 can be accurately stopped by the natural oxide film 4.

Thereafter, low concentration sources and drains 7 are formed by performing ion implantation using the film 6 as a mask. Figure 2 (
a) is a cross-sectional structural diagram at a stage in which a low concentration source/drain 7 is formed.

After that, an insulating film 8 is deposited on the entire surface. Then, the film 8 is etched back and a spacer film 8 is formed on the side wall of the gate electrode.
remain. At this stage, the gate electrode film 3 protrudes below the spacer insulating film 8. Next, using the film 8 as a mask, the gate electrode film 3 is anisotropically dry etched.

This allows the gate electrode film 3 to remain only under the spacer insulating film 8. The cross-sectional structure diagram at this stage is shown in Figure 2 (
In step b), an insulating film 81 is then deposited on the entire surface, and the spacer insulating film 81 is left on the sidewalls of the gate electrode by etching back technique using anisotropic etching as in the case of the spacer insulating film 8. Next, by performing ion implantation using the film 81 as a mask, a highly doped source/drain 9 is formed, and the cross-sectional structure shown in FIG. 1 is obtained.

FIG. 3 shows an embodiment in which a film 51 is used in place of the gate electrode film 5 of FIG. 1, and the film 51 is processed by an anisotropic etching technique. For the film 51, a silicide film such as tungsten silicide or molybdenum silicide, a high melting point metal film such as tungsten or molybdenum, or a composite film thereof is used.

4 and 5 are examples in which an insulating film 41 is provided on the side wall of the gate electrode film 3 in FIGS. 1 and 3.
In this embodiment, the insulating film 41 is formed by processing the gate electrode film 3 using the spacer insulating film 8 as a mask and then performing oxidation treatment.

FIG. 6 shows an embodiment in which the lateral scraped portion of the gate electrode film 5 formed under the 5-ins film 6 in the embodiment of FIG. 1 is filled with a conductive film 61. After filling, insulating films 8 and 81 for spacers are formed in the same manner as in the embodiment shown in FIG.
In this example, after forming the structure shown in FIG. 2(a), a polycrystalline silicon film is deposited on the entire surface, doped with impurities such as phosphorus, and then etched back using an isotropic etching technique so that only the film 61 remains. . At this time, the natural oxide film 4 serves to prevent etching from reaching the gate electrode film 3.

FIG. 7 shows another embodiment in which a conductive film 71 is used in place of the spacer insulating film 8 shown in FIG.

A conductive film 71 made of polycrystalline silicon or the like is deposited over the entire surface of the structure shown in FIG. 2(a). After this, the film 71 is subjected to anisotropic dry etching. As a result, the film 7 is formed only on the side wall of the gate electrode 5.
1 remains, resulting in the structure shown in FIG. 8(a). The film 3 is processed by anisotropic etching using the etched film 71 as a mask.6 Next, an insulating film 81 is deposited on the entire surface, and the result is shown in FIG. 8(b). After leaving the film 81 only in the area, a highly doped source/drain 9 is formed using this as a mask, as shown in FIG.

This embodiment also makes it possible to compensate for the thinning of the gate electrode 5, and to obtain the same effects as the previous embodiments.

Note that the film 71 is not limited to a polycrystalline silicon film, and may be a silicide film or a high melting point metal film.

Further, it is clear that the insulating film 81 may be composed of a composite film of two or more layers of insulating films.

FIG. 9 shows an embodiment in which a conductive film 71 is used in place of the film 8 in the embodiment shown in FIG. Forming an insulating film 81 to cover the processed film 71 is the same as in the embodiment shown in FIG.

This embodiment also reduces the resistance of the gate electrode.

Moreover, the same effect as described in FIG. 3 can be obtained.

FIG. 10 shows another embodiment, in which an insulating film 81 and a conductive film 7
This is an example in which an insulating film 101 is sandwiched between 1 and 1. The structure of this example is obtained by performing the steps described below. After depositing the conductive film 71 on the entire surface as shown in FIG. 2(a), an insulating film 101 is subsequently deposited on the entire surface.
is etched back so that it remains only on the side walls of the gate electrode.

Next, using the film 101 as a mask, the films 71 and 3 are anisotropically etched. Thereafter, the surfaces of the film 71 and film 3 exposed at the gate sidewall portions are oxidized to form an insulating film 102. Subsequently, a spacer insulating film 81 is deposited on the entire surface and left on the side walls of the gate electrode by anisotropic etching.

This embodiment also provides the same effects as those of the previous embodiments, and also has the effect that the insulation protection of the conductive film 71 is more sufficient than in the embodiment shown in FIG.

FIG. 11 shows an example in which a gate electrode 51 processed by anisotropic etching is used in place of the gate electrode 5 in the embodiment shown in FIG. Moreover, the film 51 is not provided with the natural oxide film 4.
This is a case where only the film 51 is processed by utilizing the difference in etching speed between the film 3 and the film 3.

It is clear that other embodiments may have a structure in which the membrane 4 is omitted.

FIG. 12 shows the drain structure in the embodiment shown in FIG.
(Lightly Doped Drain) structure to DDD (Double Diffused Drain)
This is an example in which the structure is changed to in ) structure. It is clear that in other embodiments the drain structure may be ODD4.

FIG. 13 shows an example in which a conductive W452 is provided on the upper part of the gate electrode film 5 in the example shown in FIG.

The conductive film 52 is formed of a silicide film or a high melting point metal film. It is clear that the gate electrode of this embodiment may be applied to other embodiments, and similar effects can be obtained by the embodiments shown in FIGS. 11 to 13.

〔Effect of the invention〕

According to the present invention, the gate/drain (source) overlap length and the length of the lightly doped source/drain regions can be changed independently, and each can be optimized. As a result, the breakdown voltage is 2 times higher than that of conventional LDD structure devices.
Since the breakdown voltage is increased to ~3V and an unnecessary increase in gate capacitance is suppressed, an increase in gate capacitance drive delay can be suppressed. Rather, the overlap structure produces the effect of increasing the current (about 20%), so the circuit has a 20% increase in current.
% to 30% speedup can be achieved.

[Brief explanation of the drawing]

Figures 1, 3 to 7, and 9 to 13 are longitudinal cross-sectional views of an embodiment of the present invention, and Figures 2 and 8 are longitudinal cross-sections corresponding to the process flow. It is a structural diagram. 1...Si substrate, 2...gate insulating film, 3, 5, 5
1゜52...Gate electrode film, 4...Natural oxide film, 6
...5ift film, 7...low concentration source/drain,
8,81...Insulating film for spacer, 9...High concentration source/drain, 41.101,102...Insulating film, 6
1.71... Conductive film. 2nd port 51-・Retto electronic network counterfeit 6th port 79 6119. Conductivity proposal 71... No. 812] No. 812? No. 70 ■ No. 12 IO≦ ・ No. 15 No. 52...Put electric book membrane

Claims (1)

[Claims] 1. In a semiconductor device consisting of a gate electrode, a source/drain, and a semiconductor substrate, a first spacer film is provided on at least one sidewall of the gate electrode, and a gate electrode is provided between the spacer film and the semiconductor substrate. is formed such that the gate electrode overlaps the depleted region of the drain/source substrate surface, and a second spacer film is formed on the sidewall of the gate electrode overlapping with the first spacer film and the drain/source. A semiconductor device characterized in that a spacer film is provided. 2. In the semiconductor device according to claim 1,
A semiconductor device characterized in that a first spacer film and a second spacer film are made of an insulating film. 3. In the semiconductor device according to claim 1,
A semiconductor device characterized in that the first spacer film is a conductive film and the second spacer film is an insulating film. 4. In the semiconductor device according to claim 1, a low concentration source/drain in a direction away from the gate electrode;
A semiconductor device characterized in that a source and a drain are configured in the order of a highly doped source and a drain, and the highly doped source and drain are configured in self-alignment with the second spacer film. 5. A semiconductor device according to claim 1, wherein the second spacer film is composed of a plurality of insulating film layers. 6. A semiconductor device according to claim 1, wherein the gate electrode is composed of a plurality of conductor films. 7. In a semiconductor device consisting of a gate electrode, a source/drain, and a semiconductor substrate, a first spacer film is provided on at least one sidewall of the gate electrode, a gate electrode is provided between the spacer film and the semiconductor substrate, and the gate electrode overlaps the depletion region of the substrate surface and portion of the drain and source, and a second spacer film is provided on the sidewall of the gate electrode overlapping with the first spacer film and the drain and source. In the method of manufacturing a semiconductor device, the gate electrode is etched using the first spacer film as a mask to form a gate/drain (source) overlap structure. manufacturing method.