JPH01102935U - - Google Patents

Info

Publication number
JPH01102935U
JPH01102935U JP19759987U JP19759987U JPH01102935U JP H01102935 U JPH01102935 U JP H01102935U JP 19759987 U JP19759987 U JP 19759987U JP 19759987 U JP19759987 U JP 19759987U JP H01102935 U JPH01102935 U JP H01102935U
Authority
JP
Japan
Prior art keywords
computer program
bus cycle
cycle state
address
setting means
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19759987U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP19759987U priority Critical patent/JPH01102935U/ja
Publication of JPH01102935U publication Critical patent/JPH01102935U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Tests Of Electronic Circuits (AREA)
  • Debugging And Monitoring (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

図はこの考案に係るコンピユータプログラムト
レース装置の一実施例を示すブロツク図である。 １０…コンピユータプログラムトレース装置、
１１…端末部、１２〜１４…レジスタ、１５，１
６…比較器、１７…アンドゲート、１８…記憶及
び評価部、２０…被測定コンピユータ装置、２１
…バスライン。 The figure is a block diagram showing one embodiment of a computer program tracing device according to this invention. 10...computer program tracing device,
11...Terminal section, 12-14...Register, 15,1
6... Comparator, 17... AND gate, 18... Storage and evaluation section, 20... Computer device under test, 21
...bus line.

Claims (1)

【実用新案登録請求の範囲】 被測定コンピユータプログラムにおける実行中
のアドレスを示すアドレ情報を取り込むための取
り込み手段と、 検出すべきバスサイクル状態に対応して前記被
測定コンピユータプログラムにおける所望のアド
レス領域を設定入力するための設定手段と、 前記取り込み手段によつて取り込んだアドレス
情報と前記設定手段の設定データとを比較し、前
記被測定コンピユータプログラムにおいて現在実
行中のアドレスが前記設定手段で設定された領域
に該当するとき前記バスサイクル状態を検出した
ことを示す信号を出力するバスサイクル状態検出
手段と を具えたコンピユータプログラムトレース装置。[Claims for Utility Model Registration] A capture means for capturing address information indicating an address being executed in a computer program under test; a setting means for inputting settings, and comparing the address information taken in by the importing means with the setting data of the setting means, and determining whether the address currently being executed in the computer program under test is set by the setting means. A computer program tracing device comprising bus cycle state detection means for outputting a signal indicating that the bus cycle state has been detected when the bus cycle state falls within the range.
JP19759987U 1987-12-28 1987-12-28 Pending JPH01102935U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19759987U JPH01102935U (en) 1987-12-28 1987-12-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19759987U JPH01102935U (en) 1987-12-28 1987-12-28

Publications (1)

Publication Number Publication Date
JPH01102935U true JPH01102935U (en) 1989-07-12

Family

ID=31488144

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19759987U Pending JPH01102935U (en) 1987-12-28 1987-12-28

Country Status (1)

Country Link
JP (1) JPH01102935U (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4874147A (en) * 1971-12-29 1973-10-05
JPS59191659A (en) * 1983-04-15 1984-10-30 Matsushita Electric Works Ltd Program debugging device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4874147A (en) * 1971-12-29 1973-10-05
JPS59191659A (en) * 1983-04-15 1984-10-30 Matsushita Electric Works Ltd Program debugging device

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