JPH01100544U - - Google Patents

Info

Publication number
JPH01100544U
JPH01100544U JP19583787U JP19583787U JPH01100544U JP H01100544 U JPH01100544 U JP H01100544U JP 19583787 U JP19583787 U JP 19583787U JP 19583787 U JP19583787 U JP 19583787U JP H01100544 U JPH01100544 U JP H01100544U
Authority
JP
Japan
Prior art keywords
circuit
write
read
memories
frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19583787U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP19583787U priority Critical patent/JPH01100544U/ja
Publication of JPH01100544U publication Critical patent/JPH01100544U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】
第１図は、本考案の一実施例の回路構成図、第
２図は、第１図のタイムチヤート、第３図は、従
来の回路構成図である。 １……フレーム同期回路、２……メモリ、３…
…選択回路、４……書き込みアドレスカウンタ、
５……書き込み制御回路、６……読み出しアドレ
スカウンタ、７……アドレス制御回路、８……よ
み出し制御回路。

Claims (1)

    【実用新案登録請求の範囲】
  1. フレーム同期回路と、メモリと、外部入力クロ
    ツクと内部クロツクの位相比較回路と、書きこみ
    カウンタと読みだしカウンタと、アドレス制御回
    路とより成るフレーム位相同期回路において、書
    き込みと読みだしタイミングを完全に切りかえる
    複数のメモリとこれを制御する書き込み、読みだ
    し制御回路と、選択回路を設けた事を特徴とする
    フレーム位相同期回路。
JP19583787U 1987-12-25 1987-12-25 Pending JPH01100544U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19583787U JPH01100544U (ja) 1987-12-25 1987-12-25

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19583787U JPH01100544U (ja) 1987-12-25 1987-12-25

Publications (1)

Publication Number Publication Date
JPH01100544U true JPH01100544U (ja) 1989-07-06

Family

ID=31486493

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19583787U Pending JPH01100544U (ja) 1987-12-25 1987-12-25

Country Status (1)

Country Link
JP (1) JPH01100544U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1991001601A1 (fr) * 1989-07-19 1991-02-07 Hitachi, Ltd. Dispositif d'alignement de blocs, son procede de commande et appareil prevu a cet effet

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1991001601A1 (fr) * 1989-07-19 1991-02-07 Hitachi, Ltd. Dispositif d'alignement de blocs, son procede de commande et appareil prevu a cet effet

Similar Documents

Publication Publication Date Title
JPH01100544U (ja)
JPS59192706U (ja) パラメ−タ設定装置
JPS6413568U (ja)
JPS62120460U (ja)
JPS62101195U (ja)
JPH03124248U (ja)
JPS6223349U (ja)
JPS5999556U (ja) 位相同期回路
JPS62121652U (ja)
JPS63103151U (ja)
JPS62187500U (ja)
JPH03127947U (ja)
JPH03110527U (ja)
JPH022751U (ja)
JPS6093200U (ja) ダイナミツクメモリアクセス回路
JPH0246998U (ja)
JPS6087050U (ja) デ−タ転送制御装置
JPS60139373U (ja) デ−タ出力装置
JPS61119199U (ja)
JPS58140599U (ja) ダイナミツクランダムアクセスメモリ制御回路
JPS6397148U (ja)
JPH03110544U (ja)
JPS59187237U (ja) タイマ−回路
JPS61133847U (ja)
JPH0394698U (ja)