JP7841200B2 - Semiconductor memory element and method for manufacturing the same - Google Patents

Description

This invention relates to a semiconductor memory element and a method for manufacturing the same, and more particularly to a semiconductor memory element including an SRAM cell and a method for manufacturing the same.

Due to characteristics such as miniaturization, multi-functionality, and/or low manufacturing cost, semiconductor devices are attracting attention as a crucial element in the electronics industry. Semiconductor devices can be classified into semiconductor memory devices for storing logical data, semiconductor logic devices for processing logical data, and hybrid semiconductor devices containing both memory and logic elements. As the electronics industry develops, the demands on the characteristics of semiconductor devices are increasing. For example, there is a growing demand for high reliability, high speed, and/or multi-functionality in semiconductor devices. To satisfy these demands, the internal structure of semiconductor devices is becoming increasingly complex, and semiconductor devices are becoming increasingly highly integrated.

U.S. Patent No. 9,202,751

The problem that this invention aims to solve is to provide a semiconductor memory element with improved electrical characteristics.

Another problem that this invention aims to solve is to provide a method for manufacturing semiconductor memory elements with improved electrical characteristics.

A semiconductor memory element according to the concept of the present invention may include: an active pattern on a substrate, the active pattern including a source/drain pattern on its upper surface; a gate electrode provided on the active pattern and extending in a first direction, wherein the gate electrode and the source/drain pattern are adjacent to each other in a second direction intersecting the first direction; and a shared contact connected to the source/drain pattern and the gate electrode, electrically connecting them to each other. The shared contact includes an active contact electrically connected to the source/drain pattern and a gate contact electrically connected to the gate electrode, the gate contact including a body connected to the gate electrode and a projection extending from the body in the second direction, the projection extending into the active contact and being embedded within the active contact.

A semiconductor memory element according to other concepts of the present invention may include an SRAM cell on a substrate. The SRAM cell may include a first pull-up/down transistor and a second pull-up/down transistor, and a first node connecting a first common source/drain of the first pull-up/down transistor and a first common gate of the second pull-up/down transistor. The first node includes a first shared contact connected to the first common source/drain and the first common gate, electrically connecting them to each other. The first shared contact includes an active contact electrically connected to the first common source/drain and a gate contact electrically connected to the first common gate. The gate contact includes a body connected to the first common gate and a projection extending from the body toward the active contact. The upper surface of the body is coplane with the upper surface of the active contact, the projection overlaps with the active contact, and the body may be horizontally offset from the active contact.

A semiconductor memory element according to other concepts of the present invention includes a substrate including a bit cell region, a first active pattern and a second active pattern on the bit cell region, wherein the first active pattern is separated from the second active pattern in a first direction, the first active pattern includes a first source/drain pattern on its upper part, and the second active pattern includes a second source/drain pattern on its upper part, an element isolation film provided on the substrate and covering the lower side walls of each of the first and second active patterns, wherein the upper parts of each of the first and second active patterns protrude onto the element isolation film, a gate electrode provided on the first active pattern and extending in a first direction, wherein the gate electrode and the first source/drain pattern are adjacent to each other in a second direction The present invention may include a gate electrode, a gate insulating film between the gate electrode and the first active pattern, a gate spacer on at least one sidewall of the gate electrode, a gate capping pattern on the gate electrode, an interlayer insulating film on the gate capping pattern, an active contact penetrating the interlayer insulating film and connecting to the first and second source/drain patterns, wherein the active contact extends in the first direction while the first and second source/drain patterns are connected to each other, a silicide pattern between each of the first and second source/drain patterns and the active contact, a gate contact penetrating the gate capping pattern and connecting to the gate electrode, and first, second, and third wiring layers sequentially laminated on the interlayer insulating film. The gate contact includes a body portion connected to the gate electrode and a projection protruding from the body portion in the second direction, the projection being extended into the active contact and embedded within the active contact.

A method for manufacturing a semiconductor memory element according to other concepts of the present invention may include forming an active pattern on a substrate, forming a gate electrode extending in a first direction on the active pattern, forming a source/drain pattern on the upper part of the active pattern such that the gate electrode and the source/drain pattern are adjacent to each other in a second direction intersecting the first direction, forming an active contact connected to the source/drain pattern, forming a gate contact connected to the active contact and the gate electrode such that at least a portion of the gate contact is superimposed perpendicularly to the active contact, and performing a planarization step until the upper surface of the active contact is exposed. The active contact and the gate contact can be connected to each other to form a single shared contact.

According to the present invention, each of the first and second nodes of an SRAM cell may include a shared contact composed of an active contact and a gate contact. By including a projection extending toward the active contact, the electrical resistance of the shared contact can be reduced, preventing misalignment between the gate contact and the active contact. As a result, the reliability and electrical characteristics of the semiconductor memory element according to the present invention can be improved.

This is an equivalent circuit diagram of an SRAM cell according to an embodiment of the present invention. This is a perspective view showing the wiring layer of a semiconductor memory element according to an embodiment of the present invention. Figure 2 is a plan view showing a memory cell. This is a plan view illustrating a semiconductor memory element according to an embodiment of the present invention. This is a cross-sectional view along the line A-A' in Figure 4. This is a cross-sectional view along the line B-B' in Figure 4. This is a cross-sectional view along the line C-C' in Figure 4. This is a cross-sectional view along the line D-D' in Figure 4. This is a cross-sectional view along the line E-E' in Figure 4. This is an enlarged cross-sectional view of region M in Figure 5B. Figure 6A is a simplified perspective view of the first shared contact. This is an enlarged cross-sectional view of region M in Figure 5B, which is an example of the present invention. This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory element according to an embodiment of the present invention. This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory element according to an embodiment of the present invention. This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory element according to an embodiment of the present invention. This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory element according to an embodiment of the present invention. This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory element according to an embodiment of the present invention. This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory element according to an embodiment of the present invention. This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory element according to an embodiment of the present invention. This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory element according to an embodiment of the present invention. This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory element according to an embodiment of the present invention. This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory element according to an embodiment of the present invention. This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory element according to an embodiment of the present invention. This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory element according to an embodiment of the present invention. This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory element according to an embodiment of the present invention. This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory element according to an embodiment of the present invention. This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory element according to an embodiment of the present invention. This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory element according to an embodiment of the present invention. This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory element according to an embodiment of the present invention. This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory element according to an embodiment of the present invention. This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory element according to an embodiment of the present invention. This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory element according to an embodiment of the present invention. This drawing illustrates a semiconductor memory element according to another embodiment of the present invention, and is an enlarged cross-sectional view of region M in Figure 5B. This drawing illustrates a semiconductor memory element according to an embodiment of the present invention, and is a cross-sectional view taken along the line A-A' in Figure 4. This drawing illustrates a semiconductor memory element according to an embodiment of the present invention, and is a cross-sectional view taken along the line B-B' in Figure 4. This drawing illustrates a semiconductor memory element according to an embodiment of the present invention, and is a cross-sectional view taken along the line D-D' in Figure 4.

Figure 1 is an equivalent circuit diagram of an SRAM cell according to an embodiment of the present invention.

Referring to Figure 1, an SRAM cell according to an embodiment of the present invention may include a first pull-up transistor TU1, a first pull-down transistor TD1, a second pull-up transistor TU2, a second pull-down transistor TD2, a first pass-gate transistor TA1, and a second pass-gate transistor TA2. The first and second pull-up transistors TU1 and TU2 may be PMOS transistors. The first and second pull-down transistors TD1 and TD2 and the first and second pass-gate transistors TA1 and TA2 may be NMOS transistors.

The first source/drain of the first pull-up transistor TU1 and the first source/drain of the first pull-down transistor TD1 can be connected to the first node N1. The second source/drain of the first pull-up transistor TU1 can be connected to the power line VDD, and the second source/drain of the first pull-down transistor TD1 can be connected to the ground line VSS. The gates of the first pull-up transistor TU1 and the first pull-down transistor TD1 can be electrically connected to each other. The first pull-up transistor TU1 and the first pull-down transistor TD1 can constitute a first inverter. The connected gates of the first pull-up and first pull-down transistors TU1 and TD1 can correspond to the input terminal of the first inverter, and the first node N1 can correspond to the output terminal of the first inverter.

The first source/drain of the second pull-up transistor TU2 and the first source/drain of the second pull-down transistor TD2 can be connected to the second node N2. The second source/drain of the second pull-up transistor TU2 can be connected to the power line VDD, and the second source/drain of the second pull-down transistor TD2 can be connected to the ground line VSS. The gates of the second pull-up transistor TU2 and the second pull-down transistor TD2 can be electrically connected to each other. Therefore, the second pull-up transistor TU2 and the second pull-down transistor TD2 can constitute a second inverter. The interconnected gates of the second pull-up and second pull-down transistors TU2 and TD2 can correspond to the input terminal of the second inverter, and the second node N2 can correspond to the output terminal of the second inverter.

The first and second inverters can be coupled to form a latch structure. Specifically, the gates of the first pull-up and first pull-down transistors TU1 and TD1 can be electrically connected to the second node N2, and the gates of the second pull-up and second pull-down transistors TU2 and TD2 can be electrically connected to the first node N1. The first source/drain of the first pass-gate transistor TA1 can be connected to the first node N1, and the second source/drain of the first pass-gate transistor TA1 can be connected to the first bit line BL1. The first source/drain of the second pass-gate transistor TA2 can be connected to the second node N2, and the second source/drain of the second pass-gate transistor TA2 can be connected to the second bit line BL2. The gates of the first and second pass-gate transistors TA1 and TA2 can be electrically connected to the word line WL. Therefore, an SRAM cell according to an embodiment of the present invention can be realized.

Figure 2 is a perspective view showing the wiring layer of a semiconductor memory element according to an embodiment of the present invention. Figure 3 is a plan view showing the memory cell of Figure 2.

Referring to Figures 2 and 3, a memory cell CE can be provided on the substrate 100. Referring to Figure 3, the memory cell CE may include first to fourth bit cells CE1-CE4 arranged in a 2x2 configuration. Each of the first to fourth bit cells CE1-CE4 may be an SRAM cell, as previously described with reference to Figure 1. A typical example of the specific structure of the first bit cell CE1 will be described later with reference to Figures 4 and 5A to 5E. Each of the second to fourth bit cells CE2, CE3, and CE4 may have a symmetrical structure with respect to the first bit cell CE1.

A first wiring layer M1, a second wiring layer M2, and a third wiring layer M3 can be provided on a memory cell CE. The first to third wiring layers M1, M2, and M3 can be stacked sequentially. The first to third wiring layers M1, M2, and M3 may include at least one of a conductive metal nitride (e.g., titanium nitride or tantalumium nitride) and a metallic substance (e.g., titanium, tantalum, tungsten, copper, or aluminum).

The first wiring layer M1 may include a first bit line BL1, a second bit line BL2, and a power line VDD extending in the second direction D2. The power line VDD may be interposed between the first bit line BL1 and the second bit line BL2. In a plan view, the first bit line BL1, the second bit line BL2, and the power line VDD may have a line shape. The width of the power line VDD in the first direction D1 may be greater than the width of the first and second bit lines BL1 and BL2 in the first direction D1, respectively.

The first wiring layer M1 may further include a first lower landing pad LLP1 and a second lower landing pad LLP2 adjacent to the first and second bit lines BL1 and BL2. The first and second lower landing pads LLP1 and LLP2 may be arranged along a second direction D2. In plan view, the first and second lower landing pads LLP1 and LLP2 may have an island shape.

The first wiring layer M1 may further include first vias provided beneath the first bit line BL1, the second bit line BL2, the power line VDD, the first lower landing pad LLP1, and the second lower landing pad LLP2, respectively. The memory cell CE and the first wiring layer M1 can be electrically connected through the first vias.

The second wiring layer M2 may include a grounding line VSS and an upper landing pad ULP. The grounding line VSS may be a mesh-shaped conductive structure. The grounding line VSS may have at least one first opening OP1. Specifically, the grounding line VSS may include a first portion P1 extending in a second direction D2 and a second portion P2 extending in the first direction D1. The width of the first portion P1 may be greater than the width of the second portion P2. The first opening OP1 can be defined by a pair of adjacent first portions P1 and a pair of adjacent second portions P2.

A pair of upper landing pads (ULPs) can be positioned within the first opening OP1. The pair of upper landing pads (ULPs) within the first opening OP1 can be arranged in the second direction D2. In plan view, the upper landing pads (ULPs) may have an island shape.

The second portion P2 of the landing line VSS can be superimposed vertically on the first lower landing pad LLP1. The upper landing pad ULP can be superimposed vertically on the second lower landing pad LLP2.

The second wiring layer M2 may further include a second via VI2 provided beneath the grounding line VSS and the upper landing pad ULP, respectively. The grounding line VSS can be electrically connected to the first lower landing pad LLP1 of the first wiring layer M1 through the second via VI2. Since multiple second vias VI2 are provided beneath the grounding line VSS, multiple first lower landing pads LLP1 can be commonly connected to a single grounding line VSS. The upper landing pad ULP can be electrically connected to the second lower landing pad LLP2 of the first wiring layer M1 through the second via VI2.

According to embodiments of the present invention, the second wiring layer M2 may consist only of the ground line VSS, the upper landing pad ULP, and the second via VI2. In other words, the second wiring layer M2 may not include any other lines (e.g., bit lines, power lines, and word lines) except for the ground line VSS.

The third wiring layer M3 may include word lines WL extending in the first direction D1. The word lines WL may be arranged in the second direction D2. In a plan view, the word lines WL may have a line shape.

The third wiring layer M3 may further include a third via VI3 provided beneath the word line WL. The word line WL can be electrically connected to the upper landing pad ULP of the second wiring layer M2 through the third via VI3. Again, the word line WL can be electrically connected to the second lower landing pad LLP2 of the first wiring layer M1 through the third via VI3, the upper landing pad ULP, and the second via VI2.

According to embodiments of the present invention, the third wiring layer M3 can consist only of a word line WL and a third via VI3. In other words, the third wiring layer M3 does not need to include other lines (e.g., bit lines, power lines, and ground lines) other than the word line WL.

Figure 4 is a plan view illustrating a semiconductor memory element according to an embodiment of the present invention. Figures 5A to 5E are cross-sectional views along lines A-A', B-B', C-C', D-D', and E-E' in Figure 4, respectively. Figure 6A is an enlarged cross-sectional view of region M in Figure 5B. Figure 6B is a simplified perspective view showing the first shared contact in Figure 6A. Figure 4 is a plan view of the first and second bit cells of Figure 3, showing an SRAM cell according to the circuit diagram in Figure 1.

Referring to Figures 1, 3, 4, and 5A to 5E, each of the first bit cell CE1 and the second bit cell CE2 on the substrate 100 can include the SRAM cell shown in Figure 1. The second bit cell CE2 can be arranged adjacent to the first bit cell CE1 in the second direction D2. First and second active patterns AP1 and AP2, a gate electrode GE, an active contact AC, and a gate contact GC can be provided on the first and second bit cells CE1 and CE2. The first bit cell CE1 will be described in detail below as a representative example.

An element isolation film ST can be provided on the substrate 100. The element isolation film ST can define first and second active patterns AP1 and AP2. The substrate 100 may be a semiconductor substrate containing silicon, germanium, silicon-germanium, etc., or a compound semiconductor substrate. The element isolation film ST may include an insulating material such as a silicon oxide film.

The first and second active patterns AP1 and AP2 may be parts of the substrate 100. A trench TR can be defined between adjacent first and second active patterns AP1 and AP2. The element isolation film ST may fill the trench TR. The upper parts of the first and second active patterns AP1 and AP2 may protrude vertically relative to the element isolation film ST. Each of the upper parts of the first and second active patterns AP1 and AP2 may have a fin shape that protrudes vertically onto the element isolation film ST. In other words, each of the first and second active patterns AP1 and AP2 may be an active fin.

According to this embodiment, the first bit cell CE1 can include a pair of first activation patterns AP1 and two pairs of second activation patterns AP2. One pair of the two pairs of second activation patterns AP2 can constitute the body of the first pass-gate transistor TA1 and the body of the first pull-down transistor TD1. The remaining pair of the two pairs of second activation patterns AP2 can constitute the body of the second pass-gate transistor TA2 and the body of the second pull-down transistor TD2. One of the pair of first activation patterns AP1 can constitute the body of the first pull-up transistor TU1. The other of the pair of first activation patterns AP1 can constitute the body of the second pull-up transistor TU2. The spacing between adjacent pairs of first activation patterns AP1 can be greater than the spacing between adjacent pairs of second activation patterns AP2.

According to another embodiment of the present invention, two second active patterns AP2 can be provided instead of two pairs of second active patterns AP2. In other words, a pair of adjacent second active patterns AP2 can be merged to provide a single second active pattern AP2.

A first channel pattern CH1 and a first source/drain pattern SD1 can be provided on top of the first active pattern AP1. A second channel pattern CH2 and a second source/drain pattern SD2 can be provided on top of the second active pattern AP2. The first source/drain pattern SD1 may be a p-type impurity region. The second source/drain pattern SD2 may be an n-type impurity region. Each of the first channel patterns CH1 can be interposed between a pair of first source/drain patterns SD1, and each of the second channel patterns CH2 can be interposed between a pair of second source/drain patterns SD2.

The first and second source/drain patterns SD1 and SD2 may be epitaxial patterns formed by a selective epitaxial growth process. The upper surfaces of the first and second source/drain patterns SD1 and SD2 may be located at a higher level than the upper surfaces of the first and second channel patterns CH1 and CH2. The first and second source/drain patterns SD1 and SD2 may be identical to the substrate 100 or may contain other semiconductor elements. For example, the first source/drain pattern SD1 may contain a semiconductor element having a lattice constant greater than that of the semiconductor element in the substrate 100. Therefore, the first source/drain pattern SD1 can impart compressive stress to the first channel pattern CH1. For example, the second source/drain pattern SD2 may contain the same semiconductor element as the semiconductor element in the substrate 100.

Two adjacent second source/drain patterns SD2 on two second active patterns AP2 can merge to form a single second source/drain pattern SD2. This is because the distance between the pair of second active patterns AP2 is relatively small (see Figure 5C).

The gate electrodes GE may include first to fourth gate electrodes GE1-GE4 on the first bit cell CE1. The first to fourth gate electrodes GE1-GE4 may extend across the first and second activation patterns AP1 and AP2 in the first direction D1. The first to fourth gate electrodes GE1-GE4 may be superimposed perpendicularly with the first and second channel patterns CH1 and CH2. The first gate electrode GE1 may be symmetrical with the fourth gate electrode GE4, and the second gate electrode GE2 may be symmetrical with the third gate electrode GE3.

The second gate electrode GE2 and the fourth gate electrode GE4 can be aligned in the first direction D1. An insulating pattern SP can be interposed between the second gate electrode GE2 and the fourth gate electrode GE4 to separate them. The first gate electrode GE1 and the third gate electrode GE3 can be aligned in the first direction D1. An insulating pattern SP can be interposed between the first gate electrode GE1 and the third gate electrode GE3 to separate them.

A pair of gate spacers GS can be placed on both side walls of the gate electrode GE. The pair of gate spacers GS can extend along the gate electrode GE in a first direction D1. The upper surfaces of the pair of gate spacers GS are higher than the upper surface of the gate electrode GE. The upper surfaces of the pair of gate spacers GS can be covered by a gate capping pattern GP, which will be described later.

The gate spacer GS may include at least one of SiO, SiCN, SiCON, and SiN. As another example, the gate spacer GS may include a multi-layer made of at least two of SiO, SiCN, SiCON, and SiN.

A gate insulating film GI can be interposed between the gate electrode GE and the first and second active patterns AP1 and AP2. The gate insulating film GI can be extended along the bottom surface of the gate electrode GE.

In one embodiment of the present invention, the gate insulating film GI may include a high dielectric film or a combination of a silicon oxide film and a high dielectric film. The high dielectric film may include a high dielectric constant material with a dielectric constant higher than that of the silicon oxide film. As an example, the high dielectric constant material may include at least one of the following: hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

In other embodiments, the semiconductor device of the present invention may include a Negative Capacitance (NC) FET utilizing a negative capacitor. For example, the gate insulating film GI may include a ferroelectric material film having ferroelectric properties and a paraelectric material film having paraelectric properties.

Ferroelectric material films can have negative capacitance, while paraelectric material films can have positive capacitance. For example, if two or more capacitors are connected in series and each capacitor has a positive capacitance, the total capacitance will be less than the capacitance of each individual capacitor. Conversely, if at least one of the capacitances of two or more capacitors connected in series has a negative capacitance, the total capacitance can be positive while still being greater than the absolute value of each individual capacitance.

When a ferroelectric material film with negative capacitance and a paraelectric material film with positive capacitance are connected in series, the overall capacitance value of the series-connected ferroelectric and paraelectric materials can increase. By utilizing this increase in overall capacitance, a transistor containing a ferroelectric material film can have a threshold voltage swing (subthreshold swing (SS)) of less than 60 mV/decade at room temperature.

Ferroelectric material films can possess ferroelectric properties. Ferroelectric material films may include at least one of the following: hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. Here, as an example, hafnium zirconium oxide may be a substance obtained by doping hafnium oxide with zirconium (Zr). As another example, hafnium zirconium oxide may be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

Ferroelectric material films may further contain doped dopants. For example, the dopants may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (CE), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (GE), scandium (SC), strontium (Sr), and tin (Sn). The types of dopants contained in a ferroelectric material film can vary depending on the ferroelectric material it comprises.

If the ferroelectric material film contains hafnium oxide, the dopant contained in the ferroelectric material film may include at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y).

When the dopant is aluminum (Al), the ferroelectric material film can contain 3 to 8 at% (atomic%) of aluminum. Here, the dopant ratio may be the ratio of aluminum to the total of hafnium and aluminum.

When the dopant is silicon (Si), the ferroelectric material film can contain 2 to 10 at% silicon. When the dopant is yttrium (Y), the ferroelectric material film can contain 2 to 10 at% yttrium. When the dopant is gadolinium (Gd), the ferroelectric material film can contain 1 to 7 at% gadolinium. When the dopant is zirconium (Zr), the ferroelectric material film can contain 50 to 80 at% zirconium.

A paraelectric material film can possess paraelectric properties. A paraelectric material film may contain at least one of silicon oxide and a metal oxide having a high dielectric constant. The metal oxide contained in the paraelectric material film may, but is not limited to, at least one of hafnium oxide, zirconium oxide, and aluminum oxide.

The ferroelectric and paraelectric material films may contain the same material. The ferroelectric material film may possess ferroelectric properties, while the paraelectric material film may not. For example, if both the ferroelectric and paraelectric material films contain hafnium oxide, the crystal structure of the hafnium oxide contained in the ferroelectric material film will differ from the crystal structure of the hafnium oxide contained in the paraelectric material film.

A ferroelectric material film can have a thickness that exhibits ferroelectric properties. The thickness of the ferroelectric material film may be between 0.5 and 10 nm, but is not limited to this. Since the critical thickness at which ferroelectric properties are exhibited varies for each ferroelectric material, the thickness of the ferroelectric material film can vary depending on the ferroelectric material.

As an example, the gate insulating film GI may include a single ferroelectric material film. As another example, the gate insulating film GI may include multiple ferroelectric material films spaced apart from each other. The gate insulating film GI can have a multilayer structure in which multiple ferroelectric material films and multiple paraelectric material films are alternately stacked.

The gate electrode GE may include a first metal pattern and a second metal pattern on the first metal pattern. The first metal pattern is provided on the gate insulating film GI and may be adjacent to the first and second channel patterns CH1 and CH2. The first metal pattern may include a work function metal that adjusts the threshold voltage of the transistor. The desired threshold voltage can be achieved by adjusting the thickness and composition of the first metal pattern.

The first metallic pattern may include a metal nitride film. For example, the first metallic pattern may include at least one metal selected from the group consisting of titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo), and nitrogen (N). The first metallic pattern may further include carbon (C). The first metallic pattern may include multiple stacked work function metallic films.

The second metal pattern may include a metal with lower resistance than the first metal pattern. For example, the second metal pattern may include at least one metal selected from the group consisting of tungsten (W), aluminum (Al), titanium (Ti), and tantalum (Ta).

Referring again to Figure 5D, the second gate electrode GE2 can be provided on the first upper surface TS1 of the first channel pattern CH1 and on at least one first sidewall SW1 of the first channel pattern CH1. The fourth gate electrode GE4 can be provided on the second upper surface TS2 of the second channel pattern CH2 and on at least one second sidewall SW2 of the second channel pattern CH2. Again, the transistor according to this embodiment may be a three-dimensional field-effect transistor (e.g., a FinFET) in which the gate electrode three-dimensionally surrounds the channel.

A gate capping pattern GP can be provided on each gate electrode GE. The gate capping pattern GP can be extended along the gate electrode GE in a first direction D1. The gate capping pattern GP may contain materials that exhibit etching selectivity with respect to the first to fourth interlayer insulating films 110, 120, 130, and 140, as described later. Specifically, the gate capping pattern GP may contain at least one of SiON, SiCN, SiCON, and SiN.

A first interlayer insulating film 110 can be provided on the substrate 100. The first interlayer insulating film 110 can cover the gate spacer GS and the first and second source/drain patterns SD1 and SD2.

The first interlayer insulating film 110 may include a lower insulating film LIL and an upper insulating film UIL. The upper insulating film UIL can cover the gate capping pattern GP and the recess portion RSP of the active contact AC (described later). The upper insulating film UIL may be identical to or contain a different insulating material than the lower insulating film LIL. For example, the lower insulating film LIL may contain SiO, and the upper insulating film UIL may contain SiO, SiOC, or SiC.

The active contact AC can penetrate the first interlayer insulating film 110 and connect to the first and second source/drain patterns SD1 and SD2. The upper surface of the active contact AC can be coplane with the upper surface of the first interlayer insulating film 110. The active contact AC may include the first to eighth active contacts AC1-AC8 on the first bit cell CE1.

The active contact AC can be a self-aligned contact. Again, the active contact AC can be formed self-aligned by the gate capping pattern GP and the gate spacer GS. For example, the active contact AC can cover at least a portion of the sidewall of the gate capping pattern GP.

The active contact AC may include a connecting portion CNP and a recess portion RSP. The upper surface of the connecting portion CNP of the active contact AC is higher than the upper surface of the recess portion RSP. The upper surface of the connecting portion CNP of the active contact AC can be coplane with the upper surface of the first interlayer insulating film 110. An upper insulating film UIL can be provided on the upper surface of the recess portion RSP of the active contact AC.

A first via VI1 can be placed on the connecting portion CNP. Again, the connecting portion CNP can be extended in a direction perpendicular to the first via VI1, i.e., in the third direction D3. The active contact AC can be electrically connected to the first wiring layer M1 through the connecting portion CNP and the first via VI1.

Within the active contact AC, the connecting portion CNP of the second active contact AC2 can contact the first gate contact GC1 (see Figure 5B). The second active contact AC2 can be electrically connected to the first gate contact GC1 through the connecting portion CNP. Within the active contact AC, the connecting portion CNP of the fifth active contact AC5 can contact the second gate contact GC2 (see Figure 5B). The fifth active contact AC5 can be electrically connected to the second gate contact GC2 through the connecting portion CNP.

A silicide pattern SC can be interposed between the active contact AC and the source/drain patterns SD1 and SD2 connected to it. The active contact AC can be electrically connected to the source/drain patterns SD1 and SD2 through the silicide pattern SC. The silicide pattern SC may contain metal-silicides, and as an example, it may include at least one of titanium-silicide, tantalum-silicide, tungsten-silicide, nickel-silicide, and cobalt-silicide.

A gate contact GC can be provided that is electrically connected to the gate electrode GE. The gate contact GC can be connected to the gate electrode GE by penetrating the first interlayer insulating film 110, the gate spacer GS, and the gate capping pattern GP.

The upper surface of the gate contact GC and the upper surface of the connecting portion CNP of the active contact AC can be coplane with the upper surface of the first interlayer insulating film 110. The bottom surface of the gate contact GC is higher than the bottom surface of the active contact AC. The bottom surface of the gate contact GC can be higher than the upper surface of the recess portion RSP of the active contact AC and lower than the upper surface of the connecting portion CNP.

Each of the active contact AC and gate contact GC may include a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM. For example, the conductive pattern FM may include at least one metal from among aluminum, copper, tungsten, molybdenum, and cobalt. The barrier pattern BM may cover the sidewalls and bottom surface of the conductive pattern FM. The barrier pattern BM may include a metal nitride film or a metal film/metal nitride film. The metal film may include at least one from among titanium, tantalum, tungsten, nickel, cobalt, and platinum. The metal nitride film may include at least one from among titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN).

The gate contact GC may include first and second gate contacts GC1 and GC2 on the first bit cell CE1. The first gate contact GC1 can be connected to the third gate electrode GE3, and the second gate contact GC2 can be connected to the second gate electrode GE2.

Referring again to Figures 4 and 5B, on the first bit cell CE1, the first gate contact GC1 and the second active contact AC2 in contact with it can constitute a first shared contact SHC1. Through the first shared contact SHC1, the third gate electrode GE3 can be electrically connected to the adjacent first source/drain pattern SD1. The second gate contact GC2 and the fifth active contact AC5 in contact with it can constitute a second shared contact SHC2.

A second interlayer insulating film 120, a third interlayer insulating film 130, and a fourth interlayer insulating film 140 can be sequentially laminated on a first interlayer insulating film 110. As an example, the second to fourth interlayer insulating films 120, 130, and 140 may include silicon oxide films.

A first wiring layer M1 can be provided within the second interlayer insulating film 120. As previously described with reference to Figure 2, the first wiring layer M1 may include a first bit line BL1, a second bit line BL2, a power line VDD, a first lower landing pad LLP1, a second lower landing pad LLP2, and a first via VI1.

A second wiring layer M2 can be provided within the third interlayer insulating film 130. The second wiring layer M2 may include a ground line VSS, an upper landing pad ULP, and a second via VI2, as previously described with reference to Figure 2.

A third wiring layer M3 can be provided within the fourth interlayer insulating film 140. The third wiring layer M3 may include a word line WL and a third via VI3, as previously described with reference to Figure 2.

In the first bit cell CE1, the first and second activation patterns AP1 and AP2 and the first to fourth gate electrodes GE1-GE4 can constitute a memory transistor. The memory transistor of the first bit cell CE1 may include the first pull-up transistor TU1, the first pull-down transistor TD1, the second pull-up transistor TU2, the second pull-down transistor TD2, the first pass-gate transistor TA1, and the second pass-gate transistor TA2, as previously described with reference to Figure 1.

The first gate electrode GE1 may be the gate of the first pass-gate transistor TA1. The first gate electrode GE1 can be electrically connected to the word line WL. The second gate electrode GE2 may be the common gate of the first pull-down and first pull-up transistors TD1 and TU1. The third gate electrode GE3 may be the common gate of the second pull-down and second pull-up transistors TD2 and TU2. The fourth gate electrode GE4 may be the gate of the second pass-gate transistor TA2. The fourth gate electrode GE4 can be electrically connected to the word line WL.

The first active contact AC1 can be electrically connected to the second source/drain of the first pull-down transistor TD1. The first active contact AC1 can also be electrically connected to the ground line VSS.

The second active contact AC2 can be electrically connected to the common source/drain (first source/drain) of the first pull-down transistor TD1 and the first pass-gate transistor TA1. The second active contact AC2 can be extended in the first direction D1 and electrically connected to the first source/drain of the first pull-up transistor TU1.

The first gate contact GC1 and the second active contact AC2 can constitute the first shared contact SHC1. Through the first shared contact SHC1, the second active contact AC2 and the third gate electrode GE3 can be electrically connected to each other. Again, through the first shared contact SHC1, the common source/drain of the first pull-up and first pull-down transistors TU1 and TD1 can be electrically connected to the common gate of the second pull-up and second pull-down transistors TU2 and TD2. The first shared contact SHC1 can correspond to the first node N1 in Figure 1.

The third active contact AC3 can be electrically connected to the second source/drain of the first pass-gate transistor TA1. The third active contact AC3 can also be electrically connected to the first bit line BL1 via the first via VI1 (see Figure 5A).

The fourth active contact AC4 can be electrically connected to the second source/drain of the first pull-up transistor TU1. The fourth active contact AC4 can also be electrically connected to the power line VDD through the first via VI1 (see Figure 5B).

The fifth active contact AC5 can be electrically connected to the first source/drain of the second pull-up transistor TU2. The fifth active contact AC5 extends in the first direction D1 and can be electrically connected to the common source/drain (first source/drain) of the second pull-down transistor TD2 and the second pass-gate transistor TA2.

The second gate contact GC2 and the fifth active contact AC5 can constitute a second shared contact SHC2. Through the second shared contact SHC2, the fifth active contact AC5 and the second gate electrode GE2 can be electrically connected to each other. Again, through the second shared contact SHC2, the common source/drain of the second pull-up and second pull-down transistors TU2 and TD2 can be electrically connected to the common gate of the first pull-up and first pull-down transistors TU1 and TD1. The second shared contact SHC2 can correspond to the second node N2 in Figure 1.

The sixth active contact AC6 can be electrically connected to the second source/drain of the second pull-up transistor TU2. The sixth active contact AC6 can also be electrically connected to the power line VDD via the first via VI1 (see Figure 5C).

The seventh active contact AC7 can be electrically connected to the second source/drain of the second pass-gate transistor TA2. The seventh active contact AC7 can also be electrically connected to the second bit line BL2 via the first via VI1.

The eighth active contact AC8 can be electrically connected to the second source/drain of the second pull-down transistor TD2. The eighth active contact AC8 can also be electrically connected to the ground line VSS.

Referring to Figures 6A and 6B, each of the first gate contact GC1 and the second active contact AC2 of the first shared contact SHC1 can include a barrier pattern BM and a conductive pattern FM. The barrier pattern BM of the first gate contact GC1 can be interposed between the conductive pattern FM of the first gate contact GC1 and the conductive pattern FM of the second active contact AC2.

The first gate contact GC1 may include a main body BDP connected to the third gate electrode GE3 and a protruding portion PRP projecting horizontally from the main body BDP in the second direction D2. The protruding portion PRP can be superimposed perpendicularly with the second active contact AC2. The main body BDP can be offset without superimposing with the second active contact AC2. The protruding portion PRP can directly contact the second active contact AC2. In other words, the first gate contact GC1 can be connected to the second active contact AC2 through the protruding portion PRP.

The protruding PRP can extend from the main body BDP toward the center of the second active contact AC2. The protruding PRP can have a shape that extends into the upper part of the second active contact AC2. The protruding PRP can also have a shape that is embedded inside the second active contact AC2.

The protruding PRP can be positioned at a higher level than the bottom surface of the main body BDP. Again, the lowest point of the protruding PRP is higher than the upper surface of the third gate electrode GE3. In one embodiment, the upper surface of the protruding PRP can be coplane with the upper surface of the main body BDP. In another embodiment, the upper surface of the protruding PRP may be lower than the upper surface of the main body BDP.

The protruding PRP portion of the first gate contact GC1 is embedded inside the second active contact AC2, thereby relatively increasing the contact area between the first gate contact GC1 and the second active contact AC2. Consequently, the contact resistance between the first gate contact GC1 and the second active contact AC2 can be relatively reduced.

The protruding portion PRP of the first gate contact GC1 can be provided so as to overlap with the second active contact AC2. Therefore, during the formation of the first gate contact GC1, the alignment margin between the first gate contact GC1 and the second active contact AC2 can be ensured through the protruding portion PRP. In other words, misalignment between the first gate contact GC1 and the second active contact AC2 can be prevented through the protruding portion PRP. As a result, the reliability of the semiconductor memory element can be improved.

Figure 7 shows a comparative example of the present invention and is an enlarged cross-sectional view of region M in Figure 5B. Referring to Figure 7, the first gate contact GC1 does not include the protruding PRP portion shown in Figure 6. That is, the first gate contact GC1 can be composed solely of the main body portion BDP. The upper sidewall of the first gate contact GC1 and the upper sidewall of the second active contact AC2 can contact each other in a two-dimensional plane. In this case, the contact area between the first gate contact GC1 and the second active contact AC2 can be relatively reduced. Therefore, the contact resistance between the first gate contact GC1 and the second active contact AC2 can be relatively increased.

According to embodiments of the present invention, the gate contact GC and the active contact AC can contact a three-dimensional structure, rather than a two-dimensional plane, to form a single shared contact SHC. Therefore, the electrical resistance of the shared contact SHC, i.e., the first node N1, is reduced, improving the operating speed and electrical characteristics of the SRAM cell.

Figures 8A to 12D are cross-sectional views illustrating a method for manufacturing a semiconductor memory element according to an embodiment of the present invention. Figures 8A, 9A, 10A, 11A, and 12A are cross-sectional views along the line A-A' in Figure 4. Figures 8B, 9B, 10B, 11B, and 12B are cross-sectional views along the line B-B' in Figure 4. Figures 8C, 9C, 10C, 11C, and 12C are cross-sectional views along the line C-C' in Figure 4. Figures 8D, 9D, 10D, 11D, and 12D are cross-sectional views along the line D-D' in Figure 4.

Referring to Figures 4 and 8A to 8D, the substrate 100 can be patterned to form trenches TR that define the first and second active patterns AP1 and AP2. In other words, trenches TR can be formed between the first and second active patterns AP1 and AP2.

An element isolation film ST can be formed on the substrate 100, filling the trench TR. The element isolation film ST may include an insulating material such as a silicon oxide film. The element isolation film ST can be recessed until the upper parts of the first and second active patterns AP1 and AP2 are exposed. Therefore, the upper parts of the first and second active patterns AP1 and AP2 can protrude vertically onto the element isolation film ST.

Referring to Figures 4 and 9A to 9D, a sacrificial pattern PP can be formed across the first and second active patterns AP1 and AP2. The sacrificial pattern PP can be formed in a line shape (lines hope) extending in the first direction D1. Specifically, forming the sacrificial pattern PP includes forming a sacrificial film on the entire surface of the substrate 100, forming a hard mask pattern MA on the sacrificial film, and patterning the sacrificial film using the hard mask pattern MA as an etching mask. The sacrificial film may contain polysilicon.

A pair of gate spacers GS can be formed on each side wall of the sacrificial pattern PP. Forming the gate spacers GS may include conformally forming a gate spacer film on the front surface of the substrate 100 and anisotropically etching the gate spacer film. The gate spacer film may include at least one of SiCN, SiCON, and SiN. As another example, the gate spacer film may be a multi-layer film containing at least two of SiCN, SiCON, and SiN.

A first source/drain pattern SD1 can be formed on the upper part of the first active pattern AP1. A pair of first source/drain patterns SD1 can be formed on each side of the sacrificial pattern PP. Specifically, the upper part of the first active pattern AP1 can be etched using the hard mask pattern MA and gate spacer GS as etching masks to form a first recess region RS1. While etching the upper part of the first active pattern AP1, the element isolation film ST between the first active patterns AP1 can be recessed.

A first source/drain pattern SD1 can be formed by performing a selective epitaxial growth process using the inner wall of the first recess region RS1 of the first active pattern AP1 as a seed layer. By forming the first source/drain pattern SD1, a first channel pattern CH1 can be defined between a pair of first source/drain patterns SD1. As an example, the first source/drain pattern SD1 may include a semiconductor element (e.g., SiGe) having a lattice constant greater than that of the semiconductor element in the substrate 100. Each first source/drain pattern SD1 can be formed from a multilayer semiconductor layer.

In one embodiment, impurities can be injected in-situ during the selective epitaxial growth process for forming the first source/drain pattern SD1. In another embodiment, impurities can be injected into the first source/drain pattern SD1 after it has been formed. The first source/drain pattern SD1 can be doped to have a first conductivity type (e.g., p-type).

A second source/drain pattern SD2 can be formed on the upper part of the second active pattern AP2. A pair of second source/drain patterns SD2 can be formed on each side of the sacrificial pattern PP. Specifically, the upper part of the second active pattern AP2 can be etched using the hard mask pattern MA and gate spacer GS as etching masks to form the second recess region RS2.

A second source/drain pattern SD2 can be formed by performing a selective epitaxial growth process using the inner wall of the second recess region RS2 of the second active pattern AP2 as a seed layer. By forming the second source/drain pattern SD2, a second channel pattern CH2 can be defined between the pair of second source/drain patterns SD2. As an example, the second source/drain pattern SD2 may contain the same semiconductor element as the substrate 100 (e.g., Si). The second source/drain pattern SD2 can be doped to have a second conductivity type (e.g., n-type).

The first source/drain pattern SD1 and the second source/drain pattern SD2 can be formed sequentially through different processes. In other words, the first source/drain pattern SD1 and the second source/drain pattern SD2 do not necessarily have to be formed simultaneously.

Referring to Figures 4 and 10A to 10D, the lower insulating film LIL can be formed to cover the first and second source/drain patterns SD1 and SD2, the hard mask pattern MA, and the gate spacer GS. As an example, the lower insulating film LIL may include a silicon oxide film.

The lower insulating film LIL can be planarized until the upper surface of the sacrificial pattern PP is exposed. Planarization of the first interlayer insulating film 110 can be performed using an etch-back or CMP (Chemical Mechanical Polishing) process. During the planarization process, the hard mask pattern MA can be completely removed. As a result, the upper surface of the first interlayer insulating film 110 can be coplane with the upper surface of the sacrificial pattern PP and the upper surface of the gate spacer GS.

By removing a portion of the exposed sacrificial pattern PP and filling it with insulating material, an insulating pattern SP can be formed. The insulating pattern SP allows the subsequently formed gate electrode GE to be divided into first to fourth gate electrodes GE1-GE4.

The sacrificial pattern PP can be replaced by the gate electrode GE. Specifically, the exposed sacrificial pattern PP can be selectively removed. By removing the sacrificial pattern PP, an empty space can be formed. The gate insulating film GI and the gate electrode GE can be sequentially formed within the empty space where the sacrificial pattern PP was removed.

The gate electrode GE and gate spacer GS can be recessed, and a gate capping pattern GP can be formed on the recessed gate electrode GE and gate spacer GS. The gate capping pattern GP may contain a material having an etching selectivity ratio with respect to the lower insulating film LIL.

Active contacts AC can be formed that penetrate the lower insulating film LIL and are electrically connected to the first and second source/drain patterns SD1 and SD2. Specifically, a first contact hole can be formed within the lower insulating film LIL through a first photolithography process. The first contact hole can define the active contact AC. The first contact hole can expose the first and second source/drain patterns SD1 and SD2. The first contact hole can be formed self-aligned using the gate capping pattern GP as a mask.

A silicide pattern SC can be formed on the first and second source/drain patterns SD1 and SD2 exposed through the first contact hole. An active contact AC can be formed by sequentially forming a barrier pattern BM and a conductive pattern FM within the first contact hole. The upper surface of the active contact AC can be coplane with the upper surface of the gate capping pattern GP and the upper surface of the lower insulating film LIL.

Referring to Figures 4 and 11A to 11D, a mask pattern MAP can be formed on a portion of the active contact AC. The mask pattern MAP can define the region where the connecting portion CNP of the active contact AC is formed.

Using the mask pattern MAP as the etching mask, the remaining area excluding the mask pattern MAP can be etched to form a recessed hole RSH. During the etching process for forming the recessed hole RSH, the upper part of the gate capping pattern GP can be recessed. During the etching process, the remaining area of the active contact AC not covered by the mask pattern MAP can be recessed to form a recessed portion RSP. The upper surface of the recessed portion RSP of the active contact AC can be lower than the upper surface of the gate electrode GE. During the etching process, the upper part of the lower insulating film LIL can also be recessed.

Referring to Figures 4 and 12A to 12D, an upper insulating film UIL can be formed to fill the recess hole RSH. The upper insulating film UIL may be identical to the lower insulating film LIL, or it may contain other insulating materials. The upper insulating film UIL can cover the upper surface of the recess portion RSP of the active contact AC. The upper insulating film UIL and the lower insulating film LIL can constitute the first interlayer insulating film 110.

A sacrificial insulating film (SAL) can be formed on the first interlayer insulating film (110). A gate contact (GC) can be formed, electrically connected to the gate electrode (GE), penetrating the sacrificial insulating film (SAL) and the gate capping pattern (GP).

Specifically, a second contact hole can be formed through a second photolithography process, penetrating the sacrificial insulating film (SAL). This second contact hole can define a gate contact (GC). The second contact hole can expose the upper surface of the gate electrode (GE). The gate contact (GC) can be formed by sequentially forming a barrier pattern (BM) and a conductive pattern (FM) within the second contact hole. The upper surface of the gate contact (GC) can be coplane with the upper surface of the sacrificial insulating film (SAL).

Within the gate contact GC, the first gate contact GC1 can be formed so as to partially overlap with the second active contact AC2. Therefore, the first gate contact GC1 can connect to the upper surface of the third gate electrode GE3 while penetrating the upper part of the second active contact AC2. The first gate contact GC1 can form the first shared contact SHC1 while directly contacting the second active contact AC2.

Referring again to Figures 4 and 5A to 5E, the planarization process can be performed on the gate contact GC and the sacrificial insulating film SAL until the upper surface of the active contact AC is exposed. Therefore, the sacrificial insulating film SAL can be completely removed. The upper surface of the gate contact GC can be coplane with the upper surface of the active contact AC.

Second to fourth interlayer insulating films 120, 130, and 140 can be sequentially formed on the first interlayer insulating film 110. Through a BEOL (Backend of Line) process, the first wiring layer M1 can be formed within the second interlayer insulating film 120, the second wiring layer M2 within the third interlayer insulating film 130, and the third wiring layer M3 within the fourth interlayer insulating film 140.

According to the semiconductor memory element manufacturing method of the present invention, after forming the active contact AC, the gate contact GC can be formed such that a portion of it is superimposed on the active contact AC. Therefore, a protruding portion PRP (see Figure 6) embedded within the active contact AC can be formed on the gate contact GC. As a result, the electrical resistance of the shared contact SHC, i.e., the first node N1, is reduced, improving the operating speed and electrical characteristics of the SRAM cell.

Figure 13 is a diagram illustrating a semiconductor memory element according to another embodiment of the present invention, and is an enlarged cross-sectional view of region M in Figure 5B. In this embodiment, detailed explanations of technical features that overlap with those previously described with reference to Figures 4 and 7 are omitted, and the differences are explained in detail.

Referring to Figure 13, the upper surface TS_P of the protruding portion PRP of the first gate contact GC1 can be lower than the upper surface TS_B of the main body portion BDP. The conductive pattern FM of the protruding portion PRP can be surrounded by a barrier pattern BM. The upper surface of the conductive pattern FM of the protruding portion PRP can be covered by the barrier pattern BM. By forming the upper surface TS_P of the protruding portion PRP lower than the upper surface TS_B of the main body portion BDP, the contact area between the protruding portion PRP of the first gate contact GC1 and the third active contact AC3 can be further increased. As a result, the electrical resistance of the first shared contact SHC1 in this embodiment can be reduced, improving the operating speed and electrical characteristics of the SRAM cell.

Figures 14A, 14B, and 14C are diagrams illustrating a semiconductor memory element according to an embodiment of the present invention, and are cross-sectional views along lines A-A', B-B', and D-D' in Figure 4, respectively. In this embodiment, detailed explanations of technical features that overlap with those previously described with reference to Figures 4 and 5A to 5E are omitted, and differences are explained in detail.

Referring to Figures 4, 14A, 14B, and 14C, first and second active patterns AP1 and AP2 can be provided on the substrate 100. The first active pattern AP1 may include a first channel pattern CH1 stacked vertically. The stacked first channel patterns CH1 can be separated from each other in a third direction D3. The stacked first channel patterns CH1 can be superimposed perpendicularly to each other. The second active pattern AP2 may include a second channel pattern CH2 stacked vertically. The stacked second channel patterns CH2 can be separated from each other in a third direction D3. The stacked second channel patterns CH2 can be superimposed perpendicularly to each other. The first and second channel patterns CH1 and CH2 may include at least one of silicon (Si), germanium GE, and silicon-germanium (SiGe).

The first active pattern AP1 may further include a first source/drain pattern SD1. A stacked first channel pattern CH1 can be interposed between a pair of adjacent first source/drain patterns SD1. The stacked first channel pattern CH1 can connect a pair of adjacent first source/drain patterns SD1.

The second active pattern AP2 may further include a second source/drain pattern SD2. A stacked second channel pattern CH2 can be interposed between a pair of adjacent second source/drain patterns SD2. The stacked second channel pattern CH2 can connect a pair of adjacent second source/drain patterns SD2.

A gate electrode GE can be provided that crosses the first and second channel patterns CH1 and CH2 and extends in the first direction D1. Each gate electrode GE can be superimposed perpendicularly to the first and second channel patterns CH1 and CH2.

The gate electrode GE can surround each first channel pattern CH1. Specifically, the gate electrode GE can be provided on each first upper surface TS1, first side wall SW1, and first bottom surface BS1 of the first channel pattern CH1 (see Figure 14C). The gate electrode GE can surround each second channel pattern CH2. Specifically, the gate electrode GE can be provided on each second upper surface TS2, second side wall SW2, and second bottom surface BS2 of the second channel pattern CH2 (see Figure 14C). The transistor according to this embodiment may be a three-dimensional field-effect transistor (e.g., MBCFET or GAAFET) in which the gate electrode GE three-dimensionally surrounds channels CH1 and CH2.

A gate insulating film GI can be provided between the respective first and second channel patterns CH1 and CH2 and the gate electrode GE. The gate insulating film GI can surround the respective first and second channel patterns CH1 and CH2.

On the second active pattern AP2, an insulating pattern IP can be interposed between the gate insulating film GI and the second source/drain pattern SD2. The gate electrode GE can be separated from the second source/drain pattern SD2 by the gate insulating film GI and the insulating pattern IP. Conversely, on the first active pattern AP1, the insulating pattern IP can be omitted.

The embodiments of the present invention have been described above with reference to the attached drawings. However, the present invention can be implemented in other specific forms without altering its technical concept or essential features. Therefore, the embodiments described above should be understood to be illustrative and not limiting in all respects.

100 Substrate 110, 120, 130, 140 Interlayer insulating film AC Active contact CE1 First bit cell CE2 Second bit cell GC Gate contact GE Gate electrode GI Gate insulating film GS Gate spacer ST Element isolation film

Claims (20)

An active pattern on a substrate, wherein the active pattern includes a source/drain pattern on its upper surface,
A gate electrode provided on the activation pattern and extending in a first direction, wherein the gate electrode and the source/drain pattern are adjacent to each other in a second direction intersecting the first direction,
Includes a shared contact connected to the source/drain pattern and the gate electrode, which electrically connects them to each other.
The shared contact includes an active contact electrically connected to the source/drain pattern and a gate contact electrically connected to the gate electrode.
The gate contact includes a main body connected to the gate electrode, and a projection extending from the main body in the second direction.
The protruding portion extends into the active contact and is embedded within the active contact.
A semiconductor memory element wherein the main body connected to the gate electrode is convex in shape, and the side surface of the protrusion embedded in the active contact is curved . The aforementioned protrusion is superimposed on the active contact,
The semiconductor memory element according to claim 1, wherein the main body is offset horizontally from the active contact. Each of the active contact and the gate contact includes a barrier pattern and a conductive pattern.
The barrier pattern covers the surface of the conductive pattern.
The semiconductor memory element according to claim 1 or 2, wherein the barrier pattern of the protrusion is interposed between the conductive pattern of the protrusion and the conductive pattern of the active contact. The semiconductor memory element according to any one of claims 1 to 3, wherein the upper surface of the main body is coplane with the upper surface of the active contact. The semiconductor memory element according to claim 4, wherein the upper surface of the protruding portion is coplane with the upper surface of the active contact. The semiconductor memory element according to claim 4, wherein the upper surface of the protruding portion is lower than the upper surface of the active contact. The semiconductor memory element according to any one of claims 1 to 6, wherein the protruding portion is located at a level higher than the bottom surface of the main body. The active contact includes a connecting portion and a recessed portion excluding the connecting portion.
The connecting portion contacts the protruding portion,
The semiconductor memory element according to any one of claims 1 to 7, wherein the upper surface of the recess is lower than the upper surface of the connecting portion. The upper insulating film on the recess portion further includes,
The semiconductor memory element according to claim 8, wherein the upper surface of the connecting portion is coplane with the upper surface of the upper insulating film. The semiconductor memory element according to any one of claims 1 to 9, wherein the active pattern includes active fins protruding above the upper surface of the element isolation film, or a plurality of vertically stacked channel patterns. Including SRAM cells on the circuit board,
The aforementioned SRAM cell is
A first pull-up/down transistor and a second pull-up/down transistor,
It includes a first node connecting the first common source/drain of the first pull-up/down transistor and the first common gate of the second pull-up/down transistor,
The first node includes a first shared contact that connects to the first common source/drain and the first common gate, electrically linking them together.
The first shared contact includes an active contact electrically connected to the first common source/drain and a gate contact electrically connected to the first common gate.
The gate contact includes a main body portion connected to the first common gate, and a protruding portion extending from the main body portion toward the active contact.
The upper surface of the main body is in the same plane as the upper surface of the active contact.
The aforementioned protrusion is superimposed on the active contact,
The main body is offset horizontally from the active contact ,
A semiconductor memory element wherein the main body connected to the first common gate is convex in shape, and the side surface of the protrusion superimposed on the active contact is curved . The semiconductor memory element according to claim 11, wherein the upper surface of the protruding portion is coplane with the upper surface of the active contact. The semiconductor memory element according to claim 11, wherein the upper surface of the protruding portion is lower than the upper surface of the active contact. The active contact includes recessed portions excluding connecting portions and linking portions.
The connecting portion contacts the protruding portion,
The semiconductor memory element according to any one of claims 11 to 13, wherein the upper surface of the recess is lower than the upper surface of the connecting portion. The SRAM cell further includes a second node connecting the second common source/drain of the second pull-up/down transistor and the second common gate of the first pull-up/down transistor,
The semiconductor memory element according to any one of claims 11 to 14, wherein the second node includes a second shared contact connected to the second common source/drain and the second common gate, electrically linking them together. A substrate including a bit cell region,
A first activation pattern and a second activation pattern on the bit cell region, wherein the first activation pattern is separated from the second activation pattern in a first direction, the first activation pattern includes a first source/drain pattern on its upper part, and the second activation pattern includes a second source/drain pattern on its upper part,
An element isolation film provided on the substrate and covering the lower sidewalls of each of the first and second active patterns, wherein the upper parts of each of the first and second active patterns protrude above the upper surface of the element isolation film,
A gate electrode provided on the first active pattern and extending in a first direction, wherein the gate electrode and the first source/drain pattern are adjacent to each other in a second direction,
The gate insulating film between the gate electrode and the first active pattern,
A gate spacer on at least one side wall of the gate electrode,
The gate capping pattern on the gate electrode,
The interlayer insulating film on the gate capping pattern,
An active contact that penetrates the interlayer insulating film and connects to the first and second source/drain patterns, wherein the active contact extends in the first direction, and the first and second source/drain patterns are connected to each other,
The silicide pattern between each of the first and second source/drain patterns and the active contact,
A gate contact that penetrates the gate capping pattern and connects to the gate electrode,
It includes a first wiring layer, a second wiring layer, and a third wiring layer sequentially laminated on the interlayer insulating film,
The gate contact includes a main body connected to the gate electrode, and a projection extending from the main body in the second direction.
The protruding portion extends into the active contact and is embedded within the active contact.
The main body portion connected to the gate electrode has a convex shape, and the side surface of the protruding portion embedded in the active contact has a curved shape.
Semiconductor memory element. The first wiring layer includes a bit line,
The semiconductor memory element according to claim 16, wherein the third wiring layer includes a word line. The first source/drain pattern has a p-type conductivity,
The semiconductor memory element according to claim 16 or 17, wherein the second source/drain pattern has an n-type conductivity. The aforementioned protrusion is superimposed on the active contact,
The semiconductor memory element according to any one of claims 16 to 18, wherein the main body is offset horizontally from the active contact. The gate contact and the active contact are connected to each other to form a single shared contact.
The semiconductor memory element according to any one of claims 16 to 19, wherein the shared contact electrically connects the first and second source/drain patterns and the gate electrode to each other.