JP7713526B2 - 共有可能な電力リソースのために構成された集積デバイスを備えるパッケージ - Google Patents

共有可能な電力リソースのために構成された集積デバイスを備えるパッケージ

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Publication number
JP7713526B2
JP7713526B2 JP2023544408A JP2023544408A JP7713526B2 JP 7713526 B2 JP7713526 B2 JP 7713526B2 JP 2023544408 A JP2023544408 A JP 2023544408A JP 2023544408 A JP2023544408 A JP 2023544408A JP 7713526 B2 JP7713526 B2 JP 7713526B2
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JP
Japan
Prior art keywords
power
integrated device
core
switch
interconnect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
JP2023544408A
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English (en)
Japanese (ja)
Other versions
JP2024505471A5 (https=
JP2024505471A (ja
Inventor
チャバ、バラニ
ロイ、アビナシュ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
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Publication date
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Publication of JP2024505471A publication Critical patent/JP2024505471A/ja
Publication of JP2024505471A5 publication Critical patent/JP2024505471A5/ja
Application granted granted Critical
Publication of JP7713526B2 publication Critical patent/JP7713526B2/ja
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/427—Power or ground buses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H10W72/07254—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/247—Dispositions of multiple bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/823—Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Structure Of Printed Boards (AREA)
JP2023544408A 2021-01-29 2021-12-15 共有可能な電力リソースのために構成された集積デバイスを備えるパッケージ Active JP7713526B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US17/162,621 US11764186B2 (en) 2021-01-29 2021-01-29 Package comprising an integrated device configured for shareable power resource
US17/162,621 2021-01-29
PCT/US2021/063630 WO2022164527A1 (en) 2021-01-29 2021-12-15 Package comprising an integrated device configured for shareable power resource

Publications (3)

Publication Number Publication Date
JP2024505471A JP2024505471A (ja) 2024-02-06
JP2024505471A5 JP2024505471A5 (https=) 2024-11-26
JP7713526B2 true JP7713526B2 (ja) 2025-07-25

Family

ID=80445787

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2023544408A Active JP7713526B2 (ja) 2021-01-29 2021-12-15 共有可能な電力リソースのために構成された集積デバイスを備えるパッケージ

Country Status (7)

Country Link
US (2) US11764186B2 (https=)
EP (1) EP4285410B1 (https=)
JP (1) JP7713526B2 (https=)
KR (1) KR20230137325A (https=)
CN (1) CN116711075A (https=)
BR (1) BR112023014301A2 (https=)
WO (1) WO2022164527A1 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11764186B2 (en) 2021-01-29 2023-09-19 Qualcomm Incorporated Package comprising an integrated device configured for shareable power resource
US11978697B2 (en) * 2021-07-16 2024-05-07 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130285739A1 (en) 2010-09-07 2013-10-31 Corporation De L ' Ecole Polytechnique De Montreal Methods, apparatus and system to support large-scale micro- systems including embedded and distributed power supply, thermal regulation, multi-distributedsensors and electrical signal propagation
US20140210097A1 (en) 2013-01-29 2014-07-31 Altera Corporation Integrated circuit package with active interposer
JP2016085733A (ja) 2014-10-27 2016-05-19 インテル コーポレイション ダイ上インターコネクトのためのアーキテクチャ
JP2016539504A (ja) 2013-11-21 2016-12-15 ツェットエフ、フリードリッヒスハーフェン、アクチエンゲゼルシャフトＺｆ Ｆｒｉｅｄｒｉｃｈｓｈａｆｅｎ Ａｇ 多機能型高電流用回路基板
US20170125383A1 (en) 2015-10-29 2017-05-04 Qualcomm Incorporated Hybrid three-dimensional integrated circuit reconfigurable thermal aware and dynamic power gating interconnect architecture
US20190064906A1 (en) 2017-08-31 2019-02-28 Qualcomm Incorporated Reconfigurable power delivery networks
US20200144186A1 (en) 2017-09-13 2020-05-07 Intel Corporation Active silicon bridge
JP2021536672A (ja) 2018-08-31 2021-12-27 ザイリンクス インコーポレイテッドXilinx Incorporated 積層ダイ構造におけるパワーゲーティング

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9064715B2 (en) 2010-12-09 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Networking packages based on interposers
KR102252643B1 (ko) * 2014-10-20 2021-05-17 삼성전자주식회사 시스템 온 칩의 전원 경로 제어기
US9935052B1 (en) * 2014-11-26 2018-04-03 Altera Corporation Power line layout in integrated circuits
US11764186B2 (en) 2021-01-29 2023-09-19 Qualcomm Incorporated Package comprising an integrated device configured for shareable power resource

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130285739A1 (en) 2010-09-07 2013-10-31 Corporation De L ' Ecole Polytechnique De Montreal Methods, apparatus and system to support large-scale micro- systems including embedded and distributed power supply, thermal regulation, multi-distributedsensors and electrical signal propagation
US20140210097A1 (en) 2013-01-29 2014-07-31 Altera Corporation Integrated circuit package with active interposer
JP2016539504A (ja) 2013-11-21 2016-12-15 ツェットエフ、フリードリッヒスハーフェン、アクチエンゲゼルシャフトＺｆ Ｆｒｉｅｄｒｉｃｈｓｈａｆｅｎ Ａｇ 多機能型高電流用回路基板
JP2016085733A (ja) 2014-10-27 2016-05-19 インテル コーポレイション ダイ上インターコネクトのためのアーキテクチャ
US20170125383A1 (en) 2015-10-29 2017-05-04 Qualcomm Incorporated Hybrid three-dimensional integrated circuit reconfigurable thermal aware and dynamic power gating interconnect architecture
US20190064906A1 (en) 2017-08-31 2019-02-28 Qualcomm Incorporated Reconfigurable power delivery networks
US20200144186A1 (en) 2017-09-13 2020-05-07 Intel Corporation Active silicon bridge
JP2021536672A (ja) 2018-08-31 2021-12-27 ザイリンクス インコーポレイテッドXilinx Incorporated 積層ダイ構造におけるパワーゲーティング

Also Published As

Publication number Publication date
EP4285410A1 (en) 2023-12-06
EP4285410C0 (en) 2025-04-30
TW202247369A (zh) 2022-12-01
US11764186B2 (en) 2023-09-19
KR20230137325A (ko) 2023-10-04
US20220246580A1 (en) 2022-08-04
BR112023014301A2 (pt) 2023-12-12
JP2024505471A (ja) 2024-02-06
WO2022164527A1 (en) 2022-08-04
US12057436B2 (en) 2024-08-06
US20230387077A1 (en) 2023-11-30
EP4285410B1 (en) 2025-04-30
CN116711075A (zh) 2023-09-05

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