JP7572012B2 - Photodetector and solid-state imaging device - Google Patents

Description

The present invention relates to a photogate type light detection element and a photogate type solid-state imaging device in which a large number of pixels are arranged on a semiconductor chip, with the light detection element serving as the pixel.

Pixels are known that have a photoelectric conversion section (hereinafter referred to as a "photogate type photoelectric conversion section") in which a MOS type gate electrode is made a transparent electrode for the purpose of radiation resistance (see Patent Document 1). The photogate type photoelectric conversion section has an n-type charge generation buried layer provided on top of a p-type substrate region, and a p-type shield layer with a higher impurity density than the substrate region provided on the upper surface of the n-type charge generation buried layer. The transparent electrode is provided as a gate electrode of a MOS structure via an insulating film on the charge generation buried layer and the shield layer. The transparent electrode is generally a polycrystalline silicon (doped polysilicon: DOPOS) film doped with n-type impurities. A channel section is then formed in the charge generation buried layer arranged under the transparent electrode.

In the case of a solid-state imaging device having a photogate-type photoelectric conversion unit described in Patent Document 1 (hereinafter referred to as a "photogate-type solid-state imaging device"), the charge generated by the photoelectric conversion of the photogate-type photoelectric conversion unit is stored in a charge generation buried layer and an n-type charge readout region (charge storage unit) provided adjacent to the charge generation buried layer, and the potential change in the charge readout region is read out as a signal. Here, when the signal charge is an electron, in order to suppress the generation of dark current in the photogate-type photoelectric conversion unit, a "pinning operation" is performed in which the charge is filled with holes present in a shield layer formed on the semiconductor surface to inactivate it. In the invention described in Patent Document 1, this pinning operation requires an operation to constantly apply a constant zero or slightly positive voltage to the transparent electrode of the photogate-type photoelectric conversion unit.

JP 2018-182044 A

The invention described in Patent Document 1 did not take into consideration the difference between the effect of a p-type transparent electrode and the effect of an n-type transparent electrode. The inventors of the present invention first considered the case where the transparent electrode is n-type, in a structure in which the charge generation buried layer and the charge readout region are n-type, and the shield layer is p-type. The problem with the n-type transparent electrode is that when a photogate-type solid-state imaging device is driven with a constant zero or slightly positive voltage constantly applied to the transparent electrode, the semiconductor interface of the shield layer is slightly depleted, and dark current suppression is not complete. On the other hand, when the transparent electrode is p-type, the depletion of the semiconductor interface is sufficiently suppressed, which is effective in suppressing dark current, but the electric field concentration between the transparent electrode and the charge readout region becomes large, which is a trade-off problem that adversely affects the readout operation.

In view of the above problems, the present invention aims to provide a photodetector element that suppresses electric field concentration between the transparent electrode and the charge readout region while simultaneously suppressing depletion of the semiconductor interface of the shield layer, completely suppressing dark current, and that has high sensitivity and a wide dynamic range even in a radiation environment, and a solid-state imaging device that uses this photodetector element as a pixel.

In order to achieve the above object, a first aspect of the present invention is a photodetector element comprising: (a) a substrate region of a first conductivity type; (b) a charge generation buried layer of a second conductivity type that is embedded in a portion of the upper part of the substrate region and generates signal charges at a p-n junction with the substrate region; (c) a shield layer of the first conductivity type that is in contact with the upper surface of the charge generation buried layer and has a higher impurity density than the substrate region and is embedded in another portion of the upper part of the substrate region; (d) a charge readout region of the second conductivity type that is embedded in another portion of the upper part of the substrate region and in contact with the charge generation buried layer and has a higher impurity density than the charge generation buried layer; (e) a photogate insulating film in contact with the upper surface of the shield layer; (f) a relaxation region portion of the second conductivity type that is a transparent electrode provided on the end of the photogate insulating film on the charge readout region side above a portion of the shield layer; and (g) a main transparent electrode layer of the first conductivity type that is a transparent electrode that is continuous with the relaxation region portion and is provided on the photogate insulating film located above the other portion of the shield layer. In the photodetector element according to the first aspect of the present invention, the potential of the main transparent electrode layer is stronger than the potential of the relaxation region, pinning the first conductivity type charge to the semiconductor interface of the shield layer.

A second aspect of the present invention includes: (a) a substrate region of a first conductivity type; (b) a charge generation buried layer of a second conductivity type that is embedded in a portion of the upper part of the substrate region and generates signal charges at a p-n junction with the substrate region; (c) a shield layer of the first conductivity type that is in contact with the upper surface of the charge generation buried layer and is embedded in another portion of the upper part of the substrate region and has a higher impurity density than the substrate region; (d) a charge readout region of the second conductivity type that is embedded in yet another portion of the upper part of the substrate region and in contact with the charge generation buried layer, and has a higher impurity density than the charge generation buried layer; and (e) a photogate insulating film in contact with the upper surface of the shield layer. The gist of the invention is that the photodetector includes: (f) a relaxation region of the second conductivity type, which is a transparent electrode provided on the end of the photogate insulating film on the charge readout region side, above a portion of the shield layer; (g) a main transparent electrode layer of the first conductivity type, which is a transparent electrode provided on the photogate insulating film located above another portion of the shield layer and continuous with the relaxation region; and (h) a resistance increase portion of the second conductivity type, which is a transparent electrode provided on the photogate insulating film, which is continuous with the main transparent electrode layer on the opposite side of the relaxation region and continuous with the main transparent electrode layer above yet another portion of the shield layer. In the photodetector according to the second aspect of the invention, the potential of the main transparent electrode layer is stronger than the potential of the relaxation region and the resistance increase portion, pinning the first conductivity type charge to the semiconductor interface of the shield layer.

The third aspect of the present invention is a solid-state imaging device that includes an array of pixels including: (a) a substrate region of a first conductivity type; (b) a charge generation buried layer of a second conductivity type that is embedded in a portion of the upper part of the substrate region and generates signal charges at a p-n junction with the substrate region; (c) a shield layer of the first conductivity type that is in contact with the upper surface of the charge generation buried layer and has a higher impurity density than the substrate region and is embedded in another portion of the upper part of the substrate region; (d) a charge readout region of the second conductivity type that is embedded in another portion of the upper part of the substrate region and in contact with the charge generation buried layer and has a higher impurity density than the charge generation buried layer; (e) a photogate insulating film in contact with the upper surface of the shield layer; (f) a relaxation region portion of the second conductivity type that is a transparent electrode provided on the end of the photogate insulating film on the charge readout region side above a portion of the shield layer; and (g) a main transparent electrode layer of the first conductivity type that is a transparent electrode that is continuous with the relaxation region portion and is provided on the photogate insulating film located above the other portion of the shield layer. In each pixel constituting the solid-state imaging device according to the third aspect of the present invention, the potential of the main transparent electrode layer is stronger than the potential of the relaxation region, pinning the first conductivity type charge to the semiconductor interface of the shield layer.

A fourth aspect of the present invention is a semiconductor device comprising: (a) a substrate region of a first conductivity type; (b) a charge generation buried layer of a second conductivity type that is embedded in a portion of the upper part of the substrate region and generates signal charges at a p-n junction with the substrate region; (c) a shield layer of the first conductivity type that is in contact with the upper surface of the charge generation buried layer and is embedded in another portion of the upper part of the substrate region and has a higher impurity density than the substrate region; (d) a charge readout region of the second conductivity type that is embedded in yet another portion of the upper part of the substrate region and in contact with the charge generation buried layer and has a higher impurity density than the charge generation buried layer; (e) a photogate insulating film in contact with the upper surface of the shield layer; and (f) a shield layer. The gist of the present invention is that the solid-state imaging device is an array of pixels each including: (a) a relaxation region portion of a second conductivity type, which is a transparent electrode provided on the end of the photogate insulating film on the charge readout region side, which is above a part of the shield layer; (b) a main transparent electrode layer of a first conductivity type, which is a transparent electrode provided on the photogate insulating film located above another part of the shield layer and continuous with the relaxation region portion; and (c) a resistance increase portion of a second conductivity type, which is a transparent electrode provided on the photogate insulating film located above another part of the shield layer, which is continuous with the main transparent electrode layer on the opposite side of the relaxation region portion. In each of the pixels constituting the solid-state imaging device according to the fourth aspect of the present invention, the potential of the main transparent electrode layer is stronger than the potential of the relaxation region portion and the resistance increase portion, thereby pinning the first conductivity type charge to the semiconductor interface of the shield layer.

The present invention makes it possible to provide a photodetector element that suppresses electric field concentration between the transparent electrode and the charge readout region while simultaneously suppressing depletion of the semiconductor interface of the shield layer, completely suppressing dark current, and that is highly sensitive and has a wide dynamic range even in a radiation environment, as well as a solid-state imaging device that uses this photodetector element as a pixel.

1 is a circuit diagram for illustrating an outline of the overall configuration of a solid-state imaging device according to a first embodiment of the present invention. FIG. 2(a) is a plan view for explaining the outline of the photodetection element according to the first embodiment, FIG. 2(b) is a cross-sectional view taken from the IIB-IIB direction in FIG. 2(a), and FIG. 2(c) shows the potential distribution along the direction of FIG. 2(b). Figure 3(a) is a diagram showing the depth-wise potential distribution in a photogate photoelectric conversion unit when a uniform n-layer is used as the transparent electrode, and Figure 3(b) is a diagram showing the depth-wise potential distribution in a photogate photoelectric conversion unit when a uniform p-layer is used as the transparent electrode. FIG. 4(a) is a plan view for explaining the outline of the photodetection element according to the second embodiment, FIG. 4(b) is a cross-sectional view taken from the IVB-IVB direction of FIG. 4(a), and FIG. 4(c) shows the potential distribution along the direction of FIG. 4(b). FIG. 5(a) is a plan view for explaining the outline of the photodetection element according to the third embodiment, FIG. 5(b) is a cross-sectional view taken from the VB-VB direction of FIG. 5(a), and FIG. 5(c) shows the potential distribution along the direction of FIG. 5(b). FIG. 6(a) is a plan view for explaining the outline of the photodetection element according to the fourth embodiment, FIG. 6(b) is a cross-sectional view taken from the VIB-VIB direction of FIG. 6(a), and FIG. 6(c) shows the potential distribution along the direction of FIG. 6(b).

Next, first to fourth embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are given the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc., differ from the actual ones. Therefore, the specific thicknesses and dimensions should be determined with reference to the following explanation. In addition, it goes without saying that the drawings include parts where the dimensional relationships and ratios differ from one another.

In addition, the first to fourth embodiments shown below are examples of devices and methods for embodying the technical idea of the present invention, and the technical idea of the present invention does not specify the materials, shapes, structures, arrangements, etc. of the components as described below. For example, in the explanation of the first to fourth embodiments, the photogate is made of DOPOS, but this is merely an example. The electrode material used for the photogate is not limited to silicon-based DOPOS, as long as it is a conductor that is transparent to the wavelength of light used to generate signal charges and has a work function that can be specified for the shield layer directly below. Furthermore, the directions of "left and right" and "up and down" in the following explanation are simply definitions for the convenience of explanation and do not limit the technical idea of the present invention. Therefore, for example, if the paper is rotated 90 degrees, "left and right" and "up and down" are read interchangeably, and of course, if the paper is rotated 180 degrees, "left" becomes "right" and "right" becomes "left". This is a definition that is merely for convenience, so of course you can choose to read "left" as "right" and "right" as "left" without rotating the page 180 degrees.

In the following description of the first to fourth embodiments, the members with the modifiers "of the first conductivity type" and "of the second conductivity type" refer to members made of semiconductor materials exhibiting p-type or n-type conductivity. In the description of the first to fourth embodiments, the first conductivity type is p-type and the second conductivity type is n-type, but this is merely a selection of conductivity types. Therefore, even if the first conductivity type is n-type and the second conductivity type is p-type, the same technical idea can be established as long as attention is paid to polarity, such as reversing the direction of potential. In addition, it is obvious to those skilled in the art that the regions and layers with n or p in the drawings refer to members and components made of semiconductor materials, such as semiconductor regions and semiconductor layers. In addition, the superscript + attached to n or p in the drawings means that the semiconductor region has a relatively high impurity density compared to the semiconductor region without +.

First Embodiment
The solid-state imaging device according to the first embodiment of the present invention is a photogate type solid-state imaging device having a pixel region in which a plurality of photogate type pixels Q _ij , Q _(i+1),j , Q _i,(j+1) , Q _(i+1),(j+1) are arranged in a two-dimensional matrix, and a peripheral circuit region in which various circuits are arranged around the pixel region, as shown in Fig. 1. For convenience, Fig. 1 shows a 2 row x 2 column matrix extracted as a representative part of the layout of the two-dimensional matrix. For example, pixel _Qij in row i and column j, indicated by a dashed rectangle in the upper left corner of the 2×2 matrix portion extracted and illustrated in Fig. 1, includes a photogate PG(i,j), a photodiode section PD(i,j) provided adjacent to the photogate PG(i,j), a charge readout region FD(i,j) connected to the photodiode section PD(i,j), a reset transistor RT(i,j) that resets the potential of the charge readout region FD(i,j), an amplifier transistor SF(i,j) that amplifies the potential change of the charge readout region FD(i,j), and a selection transistor SL(i,j) that selects the output of the amplifier transistor SF(i,j). The photogate PG(i,j) and the photodiode section PD(i,j) constitute a photogate photoelectric conversion section of pixel _Qij . As indicated by the symbol of a capacitor in the equivalent circuit of FIG. 1, a photogate PG(i,j) means a transparent MOS capacitor portion of the photogate photoelectric conversion unit of the pixel _Qij .

Furthermore, pixel Q _(i+1)j in row (i+1) and column j, which is indicated by a dashed rectangle in the lower left of FIG. 1, includes a photogate PG((i+1),j), a photodiode unit PD((i+1),j) provided adjacent to the photogate PG((i+1),j), a charge readout region FD((i+1),j) connected to the photodiode unit PD((i+1),j), a reset transistor RT((i+1),j) that resets the potential of the charge readout region FD((i+1),j), an amplification transistor SF((i+1),j) that amplifies a change in the potential of the charge readout region FD((i+1),j), and a selection transistor SL((i+1),j) that selects the output of the amplification transistor SF((i+1),j). The photogate PG((i+1),j) and photodiode unit PD((i+1),j) constitute the photogate photoelectric conversion unit of pixel Q _(i+1)j . As can be seen from the equivalent circuit representation in Figure 1, the photogate PG((i+1),j) corresponds to the transparent MOS capacitor portion of the photogate photoelectric conversion unit of pixel Q _(i+1)j . Similarly, pixel _Qi(j+1) in row i and column (j+1), which is indicated by a dashed rectangle in the upper right of FIG. 1, includes a photogate PG(i,(j+1)), a photodiode unit PD(i,(j+1)) provided adjacent to the photogate PG(i,(j+1)), a charge readout region FD(i,(j+1)) connected to the photodiode unit PD(i,(j+1)), a reset transistor RT(i,(j+1)) that resets the potential of the charge readout region FD(i,(j+1)), an amplification transistor SF(i,(j+1)) that amplifies a change in potential of the charge readout region FD(i,(j+1)), and a selection transistor SL(i,(j+1)) that selects the output of the amplification transistor SF(i,(j+1)). The photogate photoelectric conversion unit of pixel _Qi(j+1) is composed of photogate PG(i,(j+1)) and photodiode unit PD(i,(j+1)). As shown in the equivalent circuit, photogate PG(i,(j+1)) corresponds to the transparent MOS capacitor portion of the photogate photoelectric conversion unit of pixel _Qi(j+1) .

Furthermore, pixel Q _(i+1)(j+1) in row (i+1) and column (j+1) shown in a dashed rectangle at the lower right of the 2×2 matrix portion extracted for convenience in FIG. 1 is made up of a photogate PG((i+1),(j+1)), a photodiode unit PD((i+1),(j+1)) provided adjacent to the photogate PG((i+1),(j+1)), and a photodiode unit PD((i+1), The pixel Q(i+1)(j+1) includes a charge readout region FD((i+1),(j+1)) connected to the charge readout region FD((i+1),(j+1)), a reset transistor RT((i+1),(j+1)) that resets the potential of the charge readout region FD((i+1),(j+1)), an amplification transistor SF((i+1),(j+1)) that amplifies the potential change of the charge readout region FD((i+1),(j+1)), and a selection transistor SL((i+1),(j+1)) that selects the output of the amplification transistor SF((i+1),(j+1)). The photogate PG((i+1),(j+1)) and the photodiode unit PD((i+1),(j+1)) form a photogate photoelectric conversion unit for the pixel Q _(i+1)(j+1) . That is, photogate PG((i+1),(j+1)) corresponds to the transparent MOS capacitor portion of the photogate photoelectric conversion unit of pixel Q _(i+1)(j+1) . However, when the matrix of the pixel region consists of m rows and n columns, i is one of 1 to m (m is a positive integer of 2 or more), and j is one of 1 to n (n is a positive integer of 2 or more). For example, m is a value within the range of 300 to 10,000, and n is a value within the range of 200 to 8,000, which are appropriately selected according to the design specifications.

Focusing on the periphery of the 2x2 matrix portion extracted in FIG. 1, the peripheral circuit region includes a reset transistor scan drive circuit (hereinafter referred to as the "RT scan circuit") 20 for driving reset transistors RT(i,j), RT((i+1),j), RT(i,(j+1)), RT((i+1),(j+1)), a select transistor scan drive circuit (hereinafter referred to as the "SL scan circuit") 30 for driving select transistors SL(i,j), SL((i+1),j), SL(i,(j+1)), SL((i+1),(j+1)), and a photogate scan drive circuit (hereinafter referred to as the "PG scan circuit") 40 for driving photogates PG(i,j), PG((i+1),j), PG(i,(j+1)), PG((i+1),(j+1)).

On a matrix consisting of m rows and n columns, m reset drive lines DRT(i) extend in the X direction corresponding to the m rows of the matrix, and one end of each line is connected to the RT scanning circuit 20. The reset drive line DRT(i) is commonly connected to the gates of the reset transistors RT(i,1) to RT(i,n) of the n pixels Q _i1 to _Q in belonging to the i row of the m×n matrix. The RT scanning circuit 20 controls the voltage applied to the gates of the reset transistors RT(i,1) to RT(i,n) on a row-by-row basis, that is, for the n pixels Q _i1 to Q _in belonging to the i row, via the reset drive line DRT(i). As the voltage applied to the gates of the reset transistors RT(i,1) to RT(i,n), a power supply voltage VDD can be adopted as the high-side voltage V(H) and a ground voltage VSS can be adopted as the low-side voltage V(L).

Moreover, in the m×n matrix, m selection drive lines DSL(i) extend in the X direction corresponding to m rows of the matrix, and one end of each line is connected to the SL scanning circuit 30. The selection drive line DSL(i) is commonly connected to the gates of the selection transistors SL(i,1) to SL(i,n) of n pixels Q _i1 to Q in belonging to row i of the m×n matrix. The SL scanning circuit 30 controls the voltage applied to the gates of the selection transistors SL(i,1 ₎ to SL(i,n) on a row-by-row basis, that is, for the n pixels Q _i1 to Q _in belonging to row i, via the selection drive line DSL(i). As for the voltage applied to the gates of the selection transistors SL(i,1) to SL(i,n), the power supply voltage VDD can be adopted as the high-side voltage V(H) and the ground voltage VSS can be adopted as the low-side voltage V(L).

Furthermore, on the m×n matrix, m photogate driving lines DPG(i) extend in the X direction corresponding to m rows of the matrix, and one end of each line is connected to the PG scanning circuit 40. The photogate driving line DPG(i) is commonly connected to the photogates PG(i,1) to PG(i,n) of the n pixels Q _i1 to _Q in belonging to the i row of the m×n matrix. The PG scanning circuit 40 controls the voltage applied to the transparent electrodes of the photogates PG(i,1) to PG(i,n) on a row-by-row basis, that is, for the n pixels Q _i1 to Q _in belonging to the i row, via the photogate driving line DPG(i). As for the voltage applied to the transparent electrodes of the photogates PG(i,1) to PG(i,n), the power supply voltage VDD can be used as the high-side voltage V(H) and the ground voltage VSS can be used as the low-side voltage V(L). It is also possible to apply a common direct current (DC) potential of 0 V or a positive voltage to the photogate PG(i,j) of each pixel, in which case the PG scanning circuit 40 applies the same DC voltage to all rows.

In the following description, the pixel Qij in the upper left corner of the 2×2 matrix portion extracted in FIG. 1 will be described. For convenience, the pixel _Qij will be described, but the other pixels Q(i+ _{1 ),j} , Qi _,(j+1) , Q _(i+1),(j+1) constituting the 2×2 matrix, and further the other pixels constituting the m×n matrix, of course, have the same basic structure. The pixel _Qij includes a photodetection element 10, an amplification transistor SF(i,j) connected to a charge readout region FD(i,j) which is the output node of the photodetection element 10, and a selection transistor SL(i,j) whose drain side is connected to the source side of the amplification transistor SF(i,j). The source side of the selection transistor SL(i,j) is connected to an output signal line _Vsig (j) extending in the Y direction. The signal generated in the photodiode unit PD(i,j) becomes the gate signal of the amplifier transistor SF(i,j) via the charge readout region FD(i,j). The signal amplified by the amplifier transistor SF(i,j) is guided to the output signal line V _sig (j) via the selection transistor SL(i,j) and is further transmitted to the readout circuit 50. In the readout circuit 50, a predetermined process is performed on the signal generated in the photodiode unit PD(i,j), and the signal is finally output to the outside of the semiconductor chip.

Inside the pixel _Qij in row i and column j, which is indicated by a dashed rectangle in FIG. 1, the photodetector element 10, which is indicated by another dashed rectangle, includes a photodiode portion PD(i,j) functioning as a charge generating portion, a photogate PG(i,j), and a reset transistor RT(i,j). A reset line RD(j) extending in the Y direction is connected to the drain side of the reset transistor RT(i,j), and a reset drain voltage RD, which is a DC voltage, is applied to the reset line RD(j). A power supply voltage line PS(j) extending in the Y direction is connected to the drain side of the amplification transistor SF(i,j), and a power supply voltage (amplification drain voltage) VDD, which is a DC voltage, is applied to the power supply voltage line PS(j). As shown in FIG. 1, the cathode side of the photodiode portion PD(i,j) is connected to a common connection point of the lower electrode side of the photogate PG(i,j), the source side of the reset transistor RT(i,j), and the gate side of the amplification transistor SF(i,j). The common connection point functions as a charge readout region FD(i,j).

As shown in FIG. 1, the anode side of the photodiode section PD(i,j) is connected to, for example, a ground (GND) point. The photogate PG(i,j) has a MOS capacitor structure that is transparent to the incident light hν. The planar layout of the photodetector element 10 is such that the photogate PG(i,j) and the reset transistor RT(i,j) are arranged side by side, as shown in FIG. 2(a). On one side (right side) of the reset gate RT of the reset transistor RT(i,j), that is, on the side where the photogate PG(i,j), which is a transparent electrode, is arranged, a charge readout region (charge detection section) 8 indicated as "FD" in the plan view of FIG. 2(a) is arranged. In FIG. 2(a), a reset drain region 7 indicated as RD is arranged on the other side (left side) of the reset gate RT.

2(a) and (b), the first conductive type (p-type) substrate region 1 and the second conductive type (n-type) charge generating buried layer 5 buried in the upper part of the substrate region 1 constitute the photodiode section PD(i,j) by a p-n junction. When light hν is incident on the photodiode section PD(i,j) through the transparent electrode of the photogate PG(i,j), the photodiode section PD(i,j) generates a signal charge. In addition, a p-type shield layer 6 having a higher impurity density than the substrate region 1 is provided on the upper surface of the charge generating buried layer 5. The shield layer 6 is sometimes called a "virtual electrode" in photodetection elements other than those having a photogate type structure. Furthermore, the photogate PG(i,j), which is a transparent electrode that constitutes a MOS capacitor together with the photogate insulating film (first gate insulating film) 4b, is provided on the upper surface of the shield layer 6. As shown in FIG. 2B, the reset drain region 7, charge readout region 8, charge generation buried layer 5, shield layer 6, and connection region 3 are contained within an active region surrounded by an element isolation insulating film 9 in a frame shape.

The element isolation insulating film 9 can be made of, for example, a silicon oxide film or the like, for example, by a shallow trench isolation (STI) structure. Furthermore, in FIG. 2(b), a first conductive type well region 2a and an element isolation buried region 2b are buried on both sides of the upper part of the substrate region 1 with a higher impurity density than the substrate region 1. In consideration of the manufacturing process, it is preferable to provide the element isolation buried region 2b with the same depth and impurity density as the well region 2a. The element isolation insulating film 9 and the element isolation buried region 2b buried under the element isolation insulating film 9 form an element isolation region (pixel isolation region). Inside the active region surrounded by the element isolation insulating film 9, the reset transistor RT(i,j) is formed using the left well region 2a (the gate portion of the reset transistor RT(i,j) is displayed as "RT" in the surface view representation of FIG. 2(a).).

The element isolation insulating film 9 that defines the range of the active region is buried in a part of the upper part of the element isolation buried region 2b arranged on the right side of the substrate region 1. A p ⁺ type connection region 3 having a higher impurity density than the element isolation buried region 2b is provided in another part of the upper part of the element isolation buried region 2b in contact with the element isolation insulating film 9. The shield layer 6 is arranged inside the active region whose periphery is defined by the element isolation insulating film 9 so that its right end is in contact with the connection region 3 above the element isolation buried region 2b and its left end is connected to the charge read region 8. The right end of the shield layer 6 is electrically connected to the element isolation buried region 2b via the connection region 3. As a result, the end of the shield layer 6 is electrically short-circuited to the substrate region 1 via the connection region 3 and becomes the ground potential.

As shown in FIGS. 2A and 2B, the reset transistor RT(i,j) includes an n ⁺ type charge readout region (reset source region) 8 having a higher impurity density than the charge generation buried layer 5, and an n ⁺ type reset drain region 7 having a higher impurity density than the charge generation buried layer 5. Furthermore, the reset transistor RT(i,j) includes a reset gate insulating film (second gate insulating film) 4a in contact with the upper surface of the well region 2a that functions as a channel region between the charge readout region 8 and the reset drain region 7, forming an insulating film/semiconductor interface. The reset transistor RT(i,j) includes a reset gate electrode 12 made of DOPOS of the second conductivity type (n ⁺ type) on the reset gate insulating film 4a. In the exemplary representation of FIG. 2B, the charge readout region 8 is embedded in the upper part of the well region 2a and the upper part of the substrate region 1 inside the active region so as to be in contact with the left end of the end of the charge generation buried layer 5 and the left end of the shield layer 6. The photogate PG(i,j) is divided into two regions: a relaxation region 14-1 allocated to the end of the reset transistor RT(i,j) on the charge readout region 8 side, and a main transparent electrode layer 14-2 provided on the connection region 3 side opposite the charge readout region 8 side. Dividing the transparent electrode into two continuous regions has the effect of generating an electrostatic potential that is non-uniformly distributed along the direction of the semiconductor interface. Both the relaxation region 14-1 and the main transparent electrode layer 14-2 are semiconductor electrodes transparent to incident light hν, and have different work function differences with respect to the shield layer 6.

In the solid-state imaging device according to the first embodiment, the relaxation region 14-1, which is a semiconductor transparent electrode, contains an impurity element of the second conductivity type (n ⁺ type) that is the same as that of the reset gate electrode 12 of the reset transistor RT(i,j). On the other hand, the main transparent electrode layer 14-2, which is a semiconductor transparent electrode, is doped with an impurity element of the first conductivity type (p ⁺ type) that is opposite to that of the reset gate electrode 12 of the reset transistor RT(i,j). The main transparent electrode layer 14-2 occupies a major portion of the photogate PG(i,j), which is a transparent electrode, and the area (size) defined by its planar pattern is larger than the area of the relaxation region 14-1, as can be seen from the planar pattern in FIG.

In the photodetector according to the first embodiment, the reason for setting the area of the planar pattern of the main transparent electrode layer 14-2 larger than the area of the relaxation region 14-1 will be described separately for the case where the transparent electrode of the photogate PG(i,j) is made of uniform n ⁺ DOPOS and the case where it is made of uniform p ⁺ DOPOS. However, the potential V(PG) of the photogate PG(i,j) is set to 0 V, which is the same as the potential (substrate potential) of the base region 1. FIG. 3(a) shows the depth profile of the conduction band edge E _c and the valence band edge E _v of the photogate photoelectric conversion unit when the transparent electrode of the photogate PG(i,j) is a uniform transparent n-type semiconductor layer. Meanwhile, FIG. 3(b) shows the depth profile of the conduction band edge E _c and the valence band edge E _v of the photogate photoelectric conversion unit when the transparent electrode of the photogate PG(i,j) is a uniform transparent p-type semiconductor layer. 3A and 3B, the curves shown by the dashed lines at the center of the bands indicate the depth profile of the intrinsic Fermi level _Ei located at the midpoint of the bands. In this case, as shown in FIG. 3A and 3B, in both cases, the curves showing the conduction band edge _Ec , the valence band edge _Ev, and the intrinsic Fermi level _Ei form a p-n-p hook structure that is convex downward at the n-layer that represents the charge generation buried layer 5.

In Fig. 3(a) and (b), the p-layer (p-substrate) shown to the right of the central n-layer, whose profile is shown by a downwardly convex curve, means the substrate region 1, and the p-layer shown to the left of the n-layer means the shield layer 6. The parallelogram further to the left of the shield layer 6 shows the band structure of the photogate insulating film 4b, and further to the left of the photogate insulating film 4b shows the band edge _Ec of the conduction band and the band edge _Ev of the valence band of the photogate PG(i,j). In both cases of Fig. 3(a) and (b), the curve showing the band edge _Ec of the conduction band of the n-layer (charge generating buried layer) is located below the Fermi level _Ef = 0V, indicating that it is depleted. In both cases of Fig. 3(a) and (b), the curve showing the band edge _Ev of the valence band of the p-layer (shield layer) is located near the Fermi level _Ef = 0V, indicating that it is neutralized, that is, pinned to 0V.

However, as shown in Fig. 3(a), when the transparent electrode of the photogate PG(i,j) is made of uniform n ⁺ DOPOS, the band edge _Ec of the conduction band and the band edge _Ev of the valence band of the shield layer 6 are bent downward at the semiconductor interface with the photogate insulating film 4b shown by a parallelogram. That is, when the transparent electrode of the photogate PG(i,j) is n-type, the semiconductor interface of the shield layer 6 on the photogate PG(i,j) side is slightly depleted. In Fig. 3(a), the left side of the band structure of the photogate insulating film 4b shows that the band edge _Ec of the conduction band of n ⁺ DOPOS approaches V(PG) = 0V. This is because, when the photogate PG(i,j) is made of n ⁺ DOPOS, a difference occurs between the intrinsic Fermi level E _i on the photogate PG(i,j) side and the intrinsic Fermi level E _i of the shield layer 6, resulting in a difference between the work function of the photogate PG(i,j) and the work function of the shield layer 6.

On the other hand, when the transparent electrode of the photogate PG(i,j) is made of uniform p ⁺ DOPOS, as shown in Fig. 3(b), the band edge _Ec of the conduction band and the band edge _Ev of the valence band of the shield layer 6 maintain a flat band profile toward the photogate insulating film 4b shown by a parallelogram. In Fig. 3(b), the left side of the band structure of the photogate insulating film 4b shows that the band edge _Ev of the valence band of p ⁺ DOPOS approaches V(PG) = 0 V. When the photogate PG(i,j) is made of p ⁺ DOPOS, the intrinsic Fermi level Ei on the photogate PG(i,j) side and the intrinsic Fermi level _Ei of the shield layer 6 can be made to be at almost the same level, so there is almost _no difference between the work function of the photogate PG(i,j) and the work function of the shield layer 6. Furthermore, if the impurity density of the p ⁺ DOPOS is higher than that of the shield p-layer 6, the interface of the intrinsic Fermi level E _i of the shield layer 6 is pulled slightly upward, further enhancing the pinning effect.

That is, without a large difference in work function, the band edge _Ec of the conduction band and the band edge _Ev of the valence band of the shield layer 6 are pulled in the negative direction of the p-n-p hook structure while maintaining the flat band profile in the depth direction, so that depletion does not occur at the semiconductor interface. In the shape of the potential distribution in which the band edge _Ec of the conduction band and the band edge _Ev of the valence band in the depth direction are flat as shown in FIG. 3(b), the semiconductor interface of the shield layer 6 is filled with holes (p-type charges) which are the majority carriers of the shield layer 6, and is strongly pinned. The pinned holes are charges of the opposite polarity to the electrons (n-type charges) which are the signal charges.

Therefore, considering that the semiconductor interface is inactivated because it is filled with a large number of holes, it is understood that the generation of dark current at the semiconductor interface on the photogate PG(i,j) side of the shield layer 6 is suppressed more when the transparent electrode of the photogate PG(i,j) is made of uniform p ⁺ DOPOS than when the transparent electrode of the photogate PG(i,j) is made of uniform n ⁺ DOPOS. The fact that the semiconductor interface is pinned by holes (p-type charges), which are the majority carriers of the shield layer 6, means that in terms of radiation resistance, the transparent electrode of the photogate PG(i,j) made of uniform p ⁺ DOPOS is more advantageous than the transparent electrode of the photogate PG(i,j) made of uniform n ⁺ DOPOS. In addition, the channel potential formed in the charge generating buried layer 5, which is an n-layer, does not change whether the transparent electrode of the photogate PG(i,j) is made of uniform p ⁺ DOPOS or uniform n ⁺ DOPOS, because the shield layer 6, which is a p-layer, maintains a pinned state at 0 V.

Considering the above results, as shown in Figures 2(a) and (b), the structure in which the main transparent electrode layer 14-2 of the photogate PG(i,j), which is a semiconductor electrode transparent to the incident light hν, is p-type, and the relaxation region portion 14-1 on the charge readout region 8 side of the reset transistor RT(i,j) is n-type, is extremely excellent in terms of the effect of suppressing the generation of dark current in the main transparent electrode layer 14-2, which has a large area. Also, if only the dark current suppression effect is considered, it is conceivable that all of the photogate PG(i,j), which is a transparent electrode, should be made uniformly p-type, but if all of the transparent electrodes are made uniformly p-type, as is clear from Figure 3(b), at the end of the photogate PG(i,j) on the charge readout region 8 side, the interface potential on the shield layer 6 side of the photogate PG(i,j) is strongly pinned, which leads to undesirable electric field concentration between the uniform photogate PG(i,j) and the charge readout region 8. Therefore, the most ideal structure is a non-uniform structure in which the photogate PG(i,j) is divided, the main transparent electrode layer 14-2 with a large area is p-type, and the relaxation region 14-1 on the charge readout region 8 side of the reset transistor RT(i,j) is n-type. The technical feature of dividing the region of the photogate PG(i,j) into multiple regions to generate different work function differences with respect to the shield layer 6 and generate an electrostatic potential that is non-uniformly distributed along the direction of the semiconductor interface is the same in the photodetectors of the second to fourth embodiments described below.

The potential distribution along the direction of the cross section shown in FIG. 2(b) is shown in FIG. 2(c). As shown in FIG. 2(c), by setting the reset drain voltage RD, which is the potential of the reset drain region 7, to a value lower than the depletion potential of the charge generation buried layer 5, the charge generated by photoelectric conversion can be stored in the charge generation buried layer 5 and the charge readout region 8. By setting the reset drain voltage RD lower than the depletion potential, the charge storage area of the charge generation buried layer 5 and the charge readout region 8 as the signal charge storage region can be kept constant regardless of the charge amount Qs, and the charge voltage conversion gain can be kept constant. As described above, the channel potential formed in the charge generation buried layer 5 remains unchanged and is kept at an equipotential regardless of whether the transparent electrode of the photogate PG(i,j) is p-type or n-type, because the shield layer 6 maintains a state pinned to 0V.

In the photogate type light detection element according to the first embodiment, the photogate PG(i,j) can be selected from materials transparent to the wavelength of light hν incident on the photogate PG(i,j). For example, when the photogate PG(i,j) is made of DOPOS doped with n-type impurity elements such as phosphorus (P) and arsenic (As), the photogate PG(i,j) and the charge readout region 8 can be aligned in a self-aligned manner, which is convenient in the manufacturing process. The photogate PG(i,j) may be tin oxide (SnO ₂ ) in addition to a polycrystalline film of a semiconductor transparent to the wavelength of incident light hν such as DOPOS. However, indium oxide (ITO) doped with tin (Sn) or the like becomes n-type because Sn acts as a donor. Tin oxide depends on the stoichiometric composition, SnO ₂ is n-type, and SnO is p-type. Oxide thin films (transparent conductive oxides) such as aluminum (Al)-doped zinc oxide (AZO), gallium (Ga)-doped zinc oxide (GZO), and indium (In)-doped zinc oxide (IZO) also depend on the stoichiometric composition, but are generally n-type semiconductor transparent conductors.

The p-type transparent conductor material is generally composed of DOPOS doped with a p-type impurity element such as boron (B), but in addition to silicon, nickel oxide (NiO), iridium oxide (IrO), etc. can be exemplified. Furthermore, delafossite oxides having a CuMeO ₂ delafossite structure such as copper aluminum oxide (CuAlO ₂ ), copper gallium oxide (CuGaO ₂ ), and copper indium oxide (CuInO ₂ ) may be used. CuFeO ₂ : Delafossite has a structure in which Cu ⁺ and FeO ₂ ^- form a two-dimensional plane perpendicular to the c-axis, and these are alternately stacked. In addition, copper strontium oxide (SrCu ₂ O ₂ ), copper lanthanum sulfate (LaCuOS), etc. may be used. "Layered oxychalcogenide: LnCuOC _n " is a compound in which Ln = lanthanide, Ch = chalcogenide, and Ln layers and CuCh layers are alternately laminated along the c-axis.

By forming the reset gate electrode 12 from n ⁺ DOPOS, the alignment of the reset gate electrode 12 with the charge readout region 8 and the alignment of the reset gate electrode 12 with the reset drain region 7 can be performed in a self-aligned manner, which is convenient in the manufacturing process. However, like the photogate PG(i,j), the reset gate electrode 12 may also be formed from an oxide thin film (transparent conductive oxide) such as i) tin oxide (SnO ₂ ), indium oxide (ITO) doped with tin (Sn), ii) zinc oxide (AZO) doped with aluminum (Al), iii) zinc oxide (GZO) doped with gallium (Ga), or iv) zinc oxide (IZO) doped with indium (In).

The photogate insulating film 4b and the reset gate insulating film 4a are not limited to silicon oxide film as in the case of a simple MOS transistor. That is, the photogate insulating film 4b and the reset gate insulating film 4a may be a single layer film of any one of a strontium oxide (SrO) film, a silicon nitride (Si ₃ N ₄ ) film, an aluminum oxide (Al ₂ O ₃ ) film, a magnesium oxide (MgO) film, an yttrium oxide (Y ₂ O ₃ ) film, a hafnium oxide (HfO ₂ ) film, a zirconium oxide (ZrO ₂ ) film, a tantalum oxide (Ta ₂ O ₅ ) film, and a bismuth oxide (Bi ₂ O ₃ ) film, or a composite film of a plurality of these films stacked, in addition to a silicon oxide film, to configure a MIS transistor. However, the material of the photogate insulating film 4b and the reset gate insulating film 4a must be resistant to radiation.

In Figs. 3(a) and (b), a p-type semiconductor substrate (Si substrate) is used as the base region 1, but instead of the semiconductor substrate, i) a p-type epitaxial growth layer having a lower impurity density than the semiconductor substrate may be formed on the p-type semiconductor substrate, and the epitaxial growth layer may be used as the base region 1, ii) an n-type epitaxial growth layer may be formed on an n-type semiconductor substrate, and the epitaxial growth layer may be used as the base region 1, or iii) a p-type semiconductor layer (SOI layer) of an SOI structure may be used as the base region 1.

In each pixel _Qij of the photogate type solid-state imaging device according to the first embodiment, a signal charge generated by photoelectric conversion of the photogate photoelectric conversion unit during a charge accumulation period is read out to the readout circuit 50 via the output signal line _Vsig (j). When reading out via the output signal line _Vsig (j), a photogate voltage VPG of a constant value (DC value) near 0V is applied to the photogate PG(i,j) which is a transparent electrode, so that the surface potential of the shield layer 6 can be pinned by holes which are majority carriers in the shield layer 6 directly below the photogate insulating film 4b of the photogate PG(i,j). As already explained in FIGS. 3(a) and 3(b), the pinning state changes non-uniformly along the interface direction at the semiconductor interface portion of the shield layer 6 directly below the relaxation region portion 14-1 and the semiconductor interface portion of the shield layer 6 directly below the main transparent electrode layer 14-2.

According to the photodetector element of the first embodiment, even if ionizing radiation such as X-rays or gamma rays is irradiated, the photogate insulating film 4b on the charge generating buried layer 5 is thin, about 4 nm to 10 nm, so that only a few electron-hole pairs are generated in the photogate insulating film 4b. Therefore, together with the effect of suppressing dark current by pinning the surface potential of the shield layer 6, radiation resistance can be improved. Moreover, in the photodetector element of the first embodiment, the main part of the transparent electrode of the photogate PG(i,j) is a p-type main transparent electrode layer 14-2, and the end of the reset transistor RT(i,j) on the charge readout region 8 side is an n-type relaxation region portion 14-1. Therefore, according to the photodetector element of the first embodiment, it is possible to suppress depletion of the semiconductor interface of the shield layer 6 directly below the main transparent electrode layer 14-2, which has a large area, while mitigating the electric field concentration between the photogate PG(i,j) and the charge readout region 8, thereby completely suppressing dark current. Therefore, the solid-state imaging device according to the first embodiment, which uses the photodetection elements according to the first embodiment as pixels, enables imaging with high sensitivity and a wide dynamic range even in a radiation environment.

Second Embodiment
The circuit configuration of the solid-state imaging device according to the second embodiment of the present invention is also basically the same as that of the first embodiment. That is, the solid-state imaging device according to the second embodiment includes a pixel region in which a plurality of photogate type pixels _Qij are arranged in a two-dimensional matrix, and peripheral circuits arranged around the pixel region and including an RT scanning circuit 20, an SL scanning circuit 30, and a PG scanning circuit 40, as in the configuration illustrated in Fig. 1. The internal circuit configuration of the pixel region of the solid-state imaging device according to the second embodiment is the same as that of the first embodiment, so a duplicated description will be omitted and the description will focus on the structure of the photodetection elements, which are pixels constituting the two-dimensional matrix.

The photodetector according to the second embodiment differs from the photodetector 10 described in the first embodiment in the structure of the photogate PG(i,j), which is a semiconductor electrode transparent to the incident light hν in the photodetector. As shown in FIGS. 4(a) and (b), the photodetector includes a photodiode portion PD(i,j) that functions as a charge generating portion, a photogate PG(i,j), and a reset transistor RT(i,j). In the planar pattern shown in FIG. 4(a), the photogate PG(i,j) and the reset transistor RT(i,j) are arranged side by side. A charge readout region (charge detection portion) 8 indicated by FD is arranged on one side (right side) of the band-shaped pattern indicating the reset gate RT of the reset transistor RT(i,j), i.e., on the side of the photogate PG(i,j), which is a transparent electrode, and a reset drain region 7 indicated by RD is arranged on the other side (left side) of the reset gate RT.

As shown in FIG. 4(b), the first conductive type (p-type) substrate region 1 and the second conductive type (n-type) charge generation buried layer 5 buried in the upper part of the substrate region 1 constitute the photodiode section PD(i,j) by a p-n junction. When light hν is incident on the photodiode section PD(i,j) through the transparent electrode of the photogate PG(i,j), the photodiode section PD(i,j) generates a signal charge. The charge readout region FD shown in FIG. 4(a) is connected to the second conductive type (n-type) charge generation buried layer 5 constituting the photodiode section PD(i,j) inside the substrate region 1. In addition, a p-type shield layer 6 having a higher impurity density than the substrate region 1 is provided on the upper surface of the charge generation buried layer 5.

The photogate insulating film (first gate insulating film) 4b is provided on the upper surface of the shield layer 6, thereby forming an insulating film/semiconductor interface with the shield layer 6. A photogate PG(i,j), which is a semiconductor electrode transparent to incident light hν, is provided on the photogate insulating film 4b. As shown in FIG. 4(a), the reset drain region 7, the charge readout region 8, the charge generation buried layer 5, and the connection region 3 are arranged within the site of an active region surrounded by an element isolation insulating film 9 in a frame shape. As shown in FIG. 4(b), the shield layer 6 and the charge generation buried layer 5 are also arranged within an active region whose periphery is defined by the element isolation insulating film 9. The element isolation insulating film 9 can be made of a silicon oxide film or the like, for example, by an STI structure.

In addition, in FIG. 4(b), a first conductivity type well region 2a and an element isolation buried region 2b, which have a higher impurity density than the substrate region 1, are buried at both sides of the upper portion of the substrate region 1. In consideration of the manufacturing process, the element isolation buried region 2b may be provided to the same depth and with the same impurity density as the well region 2a. The element isolation insulating film 9 and the element isolation buried region 2b buried under the element isolation insulating film 9 form an element isolation region (pixel isolation region).

The reset transistor RT(i,j) is provided in the left well region 2a. The element isolation insulating film 9 that defines the range of the active region is buried in a part of the upper part of the element isolation buried region 2b arranged on the right side of the substrate region 1. In addition, a p ⁺ type connection region 3 having a higher impurity density than the element isolation buried region 2b is provided in contact with the element isolation insulating film 9 in another part of the upper part of the element isolation buried region 2b. Therefore, the connection region 3 is also located inside the active region. The shield layer 6 is also provided in contact with the connection region 3 in the upper part of the element isolation buried region 2b so as to be located inside the active region. Since the right end of the shield layer 6 is electrically connected to the element isolation buried region 2b via the connection region 3, the shield layer 6 is electrically short-circuited to the substrate region 1 via the connection region 3 and becomes the ground potential.

The reset transistor RT(i,j) includes an n ⁺ type charge readout region 8 having a higher impurity density than the charge generation buried layer 5 as a reset source region, and further includes an n ⁺ type reset drain region 7 having a higher impurity density than the charge generation buried layer 5. Furthermore, the reset transistor RT(i,j) includes a reset gate insulating film (second gate insulating film) 4a in contact with the upper surface of the well region 2a that functions as a channel region between the charge readout region 8 and the reset drain region 7, forming an insulating film/semiconductor interface. A reset gate electrode 12 made of DOPOS of the second conductivity type (n ⁺ type) is provided on the reset gate insulating film 4a. The charge readout region 8 is embedded in a part of the upper part of the well region 2a and a part of the upper part of the base region 1 so as to be in contact with the end of the charge generation buried layer 5 and the end of the shield layer 6.

The transparent electrode of the photogate PG(i,j) is divided into three regions: a relaxation region 14-1 allocated to the left end portion on the charge readout region 8 side of the reset transistor RT(i,j), a resistance increase portion 14-3 allocated to the right end portion on the connection region 3 side, and a main transparent electrode layer 14-2 provided between the relaxation region 14-1 and the resistance increase portion 14-3. Dividing the transparent electrode into three continuous regions has the effect of generating an electrostatic potential that is non-uniformly distributed along the direction of the semiconductor interface. In the planar pattern shown in FIG. 4(a), the relaxation region 14-1 on the left side and the resistance increase portion 14-3 on the right side are strip-shaped patterns that face each other in parallel.

In the photodetector according to the second embodiment, the relaxation region 14-1 and the resistance increase region 14-3, which are semiconductor transparent electrodes, are made of DOPOS doped with an impurity element of the same second conductivity type (n ⁺ type) as the reset gate electrode 12 of the reset transistor RT(i,j). On the other hand, the main transparent electrode layer 14-2, which is a semiconductor transparent electrode, is made of DOPOS doped with an impurity element of the first conductivity type (p ⁺ type) opposite to that of the reset gate electrode 12. For this reason, p-n junctions are formed between the resistance increase region 14-3 and the main transparent electrode layer 14-2, and between the main transparent electrode layer 14-2 and the relaxation region 14-1. In addition, the main transparent electrode layer 14-2 occupies a major portion of the photogate PG(i,j), which is a transparent electrode, and the area (size) defined by its planar pattern is larger than the area of the relaxation region 14-1 and the area of the resistance increase region 14-3. The voltage applied to the photogate PG(i,j) which is a transparent electrode has the resistance increasing section 14-3 as an input end, and is supplied from the resistance increasing section 14-3 to the relaxation region section 14-1 via the main transparent electrode layer 14-2.

Since the main transparent electrode layer 14-2 is of the first conductivity type (p ⁺ type), the semiconductor surface of the shield layer 6 is pinned more strongly by holes, which are the majority carriers of the shield layer 6, due to the work function difference between the semiconductor surface (semiconductor interface) of the shield layer 6, as in the photodetector according to the first embodiment. The pinned holes (p-type charge) are charges of the opposite polarity to the electrons (n-type charge) which are the signal charge. Since the holes of the semiconductor surface (semiconductor interface) are strongly pinned, if a solid-state imaging device is constructed using the photodetector according to the second embodiment as a pixel, the semiconductor interface can be filled with a large number of holes to be inactivated, thereby completely suppressing the dark current, and imaging with high sensitivity and wide dynamic range can be achieved even in a radiation environment. In addition, by making the relaxation region portion 14-1 of the second conductivity type (n ⁺ type), it is possible to relax the electric field concentration between the photogate PG(i,j) and the charge readout region 8. Furthermore, by using the second conductivity type (n ⁺ type) resistance increasing portion 14-3 as an input terminal that supplies a voltage to the photogate PG(i,j), two p-n junctions exist between the resistance increasing portion 14-3 and the relaxation region portion 14-1, and the resistance of the electrical path from the resistance increasing portion 14-3 to the relaxation region portion 14-1 increases. By increasing the resistance of the electrical path from the resistance increasing portion 14-3 through the main transparent electrode layer 14-2 to the relaxation region portion 14-1, the electric field concentration between the photogate PG(i,j) and the charge readout region 8 can be further relaxed.

The potential distribution along the direction of the cross section shown in FIG. 4(b) is shown in FIG. 4(c). In the photodetector according to the second embodiment, the reset drain voltage RD, which is the potential of the reset drain region 7, is set to a value lower than the depletion potential of the charge generation buried layer 5, and the charge generated by photoelectric conversion is stored in the charge generation buried layer 5 and the charge readout region 8. By setting the reset drain voltage RD to a value lower than the depletion potential of the charge generation buried layer 5, the charge storage area of the charge generation buried layer 5 and the charge readout region 8 as the signal charge storage region is kept constant regardless of the charge amount Qs, and the charge voltage conversion gain can be kept constant. Note that the channel potential formed in the charge generation buried layer 5 remains unchanged and is kept at an equipotential regardless of whether the transparent electrode of the photogate PG(i,j) is p-type or n-type, because the shield layer 6 maintains a state pinned to 0V.

Even in the photodetector according to the second embodiment, even if ionizing radiation such as X-rays or gamma rays is irradiated, the photogate insulating film 4b on the charge generating buried layer 5 is thin, about 4 nm to 10 nm, so that only a few electron-hole pairs are generated in the photogate insulating film 4b. Therefore, together with the effect of suppressing dark current by pinning the surface potential of the shield layer 6, the radiation resistance performance can be improved. Moreover, the main part of the transparent electrode of the photogate PG(i,j) is the p-type main transparent electrode layer 14-2, the end of the charge readout region 8 side of the reset transistor RT(i,j) is the n-type relaxation region portion 14-1, and further the end of the connection region 3 side is the n-type resistance increase portion 14-3. As explained in Figures 3(a) and (b), the pinning state changes non-uniformly along the interface direction at the semiconductor interface portion of the shield layer 6 directly below the relaxation region portion 14-1 and the resistance increase portion 14-3 and at the semiconductor interface portion of the shield layer 6 directly below the main transparent electrode layer 14-2. Therefore, the photodetector according to the second embodiment can suppress depletion of the semiconductor interface of the shield layer 6 directly below the large-area main transparent electrode layer 14-2 while mitigating electric field concentration between the photogate PG(i,j) and the charge readout region 8, thereby completely suppressing dark current. Therefore, if the solid-state imaging device according to the second embodiment is configured using the photodetector according to the second embodiment, in which the transparent electrode is divided into three regions, as a pixel, dark current is suppressed, enabling imaging with high sensitivity and a wide dynamic range even in a radiation environment.

Third Embodiment
The solid-state imaging device according to the third embodiment of the present invention corresponds to an application example of the solid-state imaging device according to the first embodiment. The photodetecting elements functioning as pixels constituting the solid-state imaging device according to the third embodiment are modified in planar layout from the photodetecting element according to the first embodiment. That is, the photodetecting element according to the third embodiment further enhances radiation resistance by moving the element isolation insulating film such as a silicon oxide film, which is easily deteriorated by gamma ray irradiation, away from the charge generation buried layer 5. For this reason, in the photodetector according to the third embodiment, the planar layouts of the photogate PG(i,j) and the charge readout region FD are both concentric rings, and the reset transistor RT(i,j) having the ring-shaped reset gate electrode 12 is disposed in the center of the planar layout. In the photodetector according to the third embodiment illustrated in FIGS. 5(a) and (b), the planar layouts of the photogate PG(i,j) and the charge readout region FD are both octagonal rings, and the reset transistor RT(i,j) having the octagonal ring-shaped reset gate electrode 12 is disposed in the center of the photogate PG(i,j).

As shown in FIGS. 5(a) and (b), the part corresponding to the photodetector element in FIG. 1 includes a photodiode portion PD(i,j) which is a charge generating portion, a photogate PG(i,j), and a reset transistor RT(i,j). The photogate PG(i,j) has a layout that surrounds the reset transistor RT(i,j) in a ring shape. A charge readout region (charge detection portion) 8 indicated by FD is arranged on the outer periphery side of the reset gate RT of the reset transistor RT(i,j), that is, on the side of the photogate PG(i,j) which is a transparent electrode, and a reset drain region 7 indicated by RD is arranged on the inner periphery side. As shown in FIGS. 5(a) and (b), the photodetector according to the third embodiment has a layout in which the reset drain region 7 indicated by RD is surrounded by an octagonal ring-shaped reset gate electrode 12, and the reset gate electrode 12 is further surrounded by the charge readout region FD and the photogate PG(i,j).

As can be seen from FIG. 5(b), the first conductive type (p type) substrate region 1 and the second conductive type (n type) charge generation buried layer 5 buried in a part of the upper part of the substrate region 1 constitute the photodiode section PD(i,j) by a p-n junction. When light hν is incident on the photodiode section PD(i,j) through the transparent electrode of the photogate PG(i,j), the photodiode section PD(i,j) generates a signal charge. The charge readout region FD shown in FIG. 5(a) is connected to the charge generation buried layer 5 inside the substrate region 1. In addition, a p-type shield layer 6 having a higher impurity density than the substrate region 1 is provided on the upper surface of the charge generation buried layer 5, which is another part of the upper part of the substrate region 1. The charge generation buried layer 5 and the shield layer 6 have an annular shape, such as an octagonal ring shape. A photogate insulating film (first gate insulating film) 4b is provided in contact with the upper surface of the shield layer 6, forming an insulating film/semiconductor interface.

A photogate PG(i,j) which is a semiconductor electrode transparent to incident light hν is provided on the photogate insulating film 4b above the shield layer 6. A first conductive well region 2a is buried in the central portion of the upper part of the substrate region 1 with a higher impurity density than the substrate region 1. A first conductive element isolation buried region 2b is buried in the peripheral portion of the upper part of the substrate region 1 with a higher impurity density than the substrate region 1. In consideration of the manufacturing process, the element isolation buried region 2b may be buried to the same depth and with the same impurity density as the well region 2a. The reset transistor RT(i,j) is provided in a part of the upper part of the well region 2a in the central portion. Furthermore, a p ⁺ type connection region 3 with a higher impurity density than the element isolation buried region 2b is provided in a part of the upper part of the element isolation buried region 2b provided on the outer periphery side. The shield layer 6 is provided in a part of the upper part of the substrate region 1 in contact with the connection region 3 in the element isolation buried region 2b. Since the outer peripheral end of the shield layer 6 is electrically connected to the element isolation buried region 2b via the connection region 3, the shield layer 6 is electrically short-circuited to the base region 1 via the connection region 3 and is at the ground potential.

Although not shown in FIGS. 5A and 5B, an element isolation insulating film is arranged on the top of the substrate region 1, which is further outside, so as to surround the regular octagonal connection region 3. The element isolation insulating film (not shown) and the element isolation buried region 2b buried under the element isolation insulating film constitute an element isolation region (pixel isolation region). As in the solid-state imaging devices according to the first and second embodiments, the element isolation insulating film can be buried in the top of the substrate region 1 by, for example, an STI structure. In the photodetector according to the third embodiment, a layout is adopted in which the element isolation insulating film (not shown) is present further outside the first conductivity type element isolation buried region 2b or connection region 3 located on the outermost side of the photodetector, so that the radiation resistance of each pixel of the photogate type solid-state imaging device can be improved.

In the reset transistor RT(i,j) of the photodetector according to the third embodiment, an n ^{+ type reset drain region 7 having a higher impurity density than the charge generation buried layer 5 is disposed at the center of the upper part of the central well region 2a. Furthermore, as shown in FIG. 5B, an n+ type} charge readout region 8 having a higher impurity density than the charge generation buried layer 5 is disposed at a distance from the reset drain region 7. The charge readout region 8 is embedded in the periphery of the upper part of the well region 2a and in a part of the upper part of the base region 1 so as to protrude from the periphery of the upper part of the well region 2a. In addition, in the reset transistor RT(i,j), a reset gate insulating film (second gate insulating film) 4a is in contact with a part of the upper part of the well region 2a that becomes a channel region formed between the charge readout region 8 and the reset drain region 7, forming an insulating film-semiconductor interface. Furthermore, as shown in FIG. 5B, a reset gate electrode 12 made of DOPOS of the second conductivity type (n ⁺ type) is disposed on the reset gate insulating film 4a.

As shown in FIG. 5(a), the charge readout region 8 has an annular shape, such as an octagonal ring shape, centered on the reset drain region 7. As shown in FIG. 5(b), the charge readout region 8 is embedded in contact with the inner diameter end of the charge generation buried layer 5 and the inner diameter end of the shield layer 6. If the charge readout region 8 is an octagonal ring shape, it is preferable that the photogate PG(i,j), which is a semiconductor electrode transparent to the incident light hν, also has an annular shape, such as an octagonal ring shape. As shown in FIG. 5(a), the transparent electrode of the photogate PG(i,j) is divided into two regions: the inner peripheral relaxation region portion 14-1 assigned to the end of the charge readout region 8 side of the reset transistor RT(i,j), and the main transparent electrode layer 14-2 provided as the main portion surrounding the relaxation region portion 14-1. Dividing the transparent electrode into two continuous regions has the effect of generating an electrostatic potential that is non-uniformly distributed along the direction of the semiconductor interface.

In the photodetector according to the third embodiment, similarly to the first embodiment, the relaxation region 14-1 on the inner periphery side, which is a semiconductor transparent electrode, is DOPOS doped with an impurity element of the same second conductivity type (n ⁺ type) as the reset gate electrode 12 of the reset transistor RT(i,j). On the other hand, the main transparent electrode layer 14-2, which is a semiconductor transparent electrode, is DOPOS doped with an impurity element of the first conductivity type (p ⁺ type) opposite to that of the reset gate electrode 12 of the reset transistor RT(i,j). In addition, since the main transparent electrode layer 14-2 functions as a main part of the photogate PG(i,j), which is a transparent electrode, the area (size) defined by its planar pattern is larger than the area of the relaxation region 14-1. As already explained in Figures 3(a) and (b), the pinning state changes non-uniformly along the interface direction in the semiconductor interface portion of the shield layer 6 directly below the relaxation region portion 14-1 and in the semiconductor interface portion of the shield layer 6 directly below the main transparent electrode layer 14-2.

Since the main transparent electrode layer 14-2 is of the first conductivity type (p ⁺ type), the semiconductor surface of the shield layer 6 is stronger due to the work function difference between the semiconductor surface (semiconductor interface) of the shield layer 6, and the phenomenon of pinning with holes, which are the majority carriers of the shield layer 6, is the same as that of the photodetector element according to the first embodiment. The pinned holes (p-type charge) are charges of the opposite polarity to the electrons (n-type charge) which are the signal charges. Since the pinning of holes fills the semiconductor interface with a large number of holes to inactivate dark current, a solid-state imaging device in which these photodetector elements are arranged as each pixel can perform imaging with high sensitivity and a wide dynamic range even in a radiation environment. In addition, by making the relaxation region portion 14-1 of the second conductivity type (n ⁺ type), it is possible to alleviate the electric field concentration between the photogate PG(i,j) and the charge readout region 8. Furthermore, the planar layout has a concentric ring shape with the reset drain region 7 at the center, and the reset gate electrode 12, the photogate PG(i,j), and the charge readout region FD are arranged in a planar shape. Therefore, in the solid-state imaging device of the third embodiment, a structure can be easily realized within each pixel in which the element isolation insulating film, which is easily deteriorated by gamma ray irradiation, is located away from the charge generation buried layer 5, thereby further improving radiation resistance.

The potential distribution along the direction of the cross section shown in FIG. 5(b) is shown in FIG. 5(c). In FIG. 5(c), the reset drain voltage RD, which is the potential of the reset drain region 7, is set to a value lower than the depletion potential of the charge generation buried layer 5, so that the charge generated by photoelectric conversion can be stored in the charge generation buried layer 5 and the charge readout region 8. By setting the reset drain voltage RD to a value lower than the depletion potential, the charge storage area of the charge generation buried layer 5 and the charge readout region 8 as the signal charge storage region is kept constant regardless of the charge amount Qs, and the charge-voltage conversion gain can be kept constant. Note that the channel potential formed in the charge generation buried layer 5 remains unchanged and is kept at an equipotential level, regardless of whether the transparent electrode of the photogate PG(i,j) is p-type or n-type, because the shield layer 6 maintains a state pinned to 0V.

The photodetector according to the third embodiment has the same effect as the photodetector according to the first embodiment, that is, it is possible to suppress depletion of the semiconductor interface of the shield layer 6 directly below the main transparent electrode layer 14-2, which has a large area, while mitigating the electric field concentration between the photogate PG(i,j) and the charge readout region 8, thereby completely suppressing the dark current. Therefore, the solid-state imaging device according to the third embodiment can achieve the advantageous effect of enabling imaging with high sensitivity and a wide dynamic range even in a radiation environment. Moreover, since the pixel structure has a planar layout in which the reset gate electrode 12, the photogate PG(i,j), and the charge readout region FD are each concentrically arranged around the reset drain region 7, the element isolation insulating film, which is easily deteriorated by gamma ray irradiation, can be kept away from the charge generation buried layer 5 inside each pixel, and radiation resistance can be further improved.

Fourth Embodiment
The solid-state imaging device according to the fourth embodiment of the present invention corresponds to an application example of the solid-state imaging device according to the second embodiment. That is, the planar layout of the photodetecting elements that function as each pixel of the solid-state imaging device according to the second embodiment is devised. The photodetecting element according to the fourth embodiment provides a structure that can further improve radiation resistance by moving the element isolation insulating film such as a silicon oxide film, which is easily deteriorated by gamma ray irradiation, away from the charge generation buried layer 5. That is, in the photodetector according to the fourth embodiment, the planar layout of the photogate PG(i,j) and the charge readout region FD are both concentric rings, and the reset transistor RT(i,j) having the ring-shaped reset gate electrode 12 is arranged in the center. As shown in Figures 6(a) and (b), when the planar layout of the photogate PG(i,j) and the charge readout region FD is an octagonal ring shape, it is preferable to arrange the reset transistor RT(i,j) having the octagonal ring-shaped reset gate electrode 12 in the center.

As shown in Figs. 6(a) and (b), the photodetector according to the fourth embodiment is similar to the photodetector according to the first embodiment shown in Fig. 1 in that it includes a photodiode portion PD(i,j) which is a charge generating portion, a photogate PG(i,j), and a reset transistor RT(i,j). However, unlike the photodetector according to the first embodiment, the photogate PG(i,j) has a layout that surrounds the reset transistor RT(i,j) located at the center in an annular shape. A charge readout region (charge detection portion) 8 indicated by FD in Fig. 6(a) is arranged on the outer periphery of the reset gate RT of the reset transistor RT(i,j), i.e., on the side of the photogate PG(i,j) which is a transparent electrode, and a reset drain region 7 indicated by RD is arranged on the inner periphery.

As shown in FIG. 6(b), the first conductive type (p-type) substrate region 1 and the second conductive type (n-type) charge generation buried layer 5 buried in a part of the upper part of the substrate region 1 constitute the photodiode section PD(i,j) by a p-n junction. When light hν is incident on the photodiode section PD(i,j) through the transparent electrode of the photogate PG(i,j), the photodiode section PD(i,j) generates a signal charge. The charge readout region FD is connected to the charge generation buried layer 5 inside the substrate region 1. In addition, a p-type shield layer 6 having a higher impurity density than the substrate region 1 is buried in the substrate region 1, which is the upper surface of the charge generation buried layer 5. The charge generation buried layer 5 and the shield layer 6 have an annular shape, such as an octagonal ring shape. A photogate insulating film (first gate insulating film) 4b is provided in contact with the upper surface of the shield layer 6, and an insulating film/semiconductor interface is formed with the shield layer 6. Above the shield layer 6, a photogate PG(i,j) that is a semiconductor electrode that is transparent to the incident light hν is provided on the photogate insulating film 4b.

In addition, a first conductive well region 2a is embedded in the central portion of the upper part of the substrate region 1 with a higher impurity density than the substrate region 1, and a first conductive element isolation buried region 2b is embedded in the peripheral portion of the upper part of the substrate region 1 with a higher impurity density than the substrate region 1. The reset transistor RT(i,j) is provided in a part of the upper part of the well region 2a. Furthermore, a p ⁺ type connection region 3 with a higher impurity density than the element isolation buried region 2b is embedded in the upper part of the element isolation buried region 2b. The element isolation buried region 2b may have the same depth and impurity density as the well region 2a. The shield layer 6 is provided in a ring shape so as to contact the connection region 3 in the element isolation buried region 2b and to extend from the element isolation buried region 2b to the upper part of the substrate region 1 on the inside. Since the outer peripheral end of the shield layer 6 is electrically connected to the element isolation buried region 2b via the connection region 3, the shield layer 6 is electrically short-circuited to the substrate region 1 via the connection region 3 and becomes the ground potential.

Although not shown in FIGS. 6(a) and (b), an element isolation insulating film is arranged on the top of the substrate region 1, which is further outside, so as to surround the regular octagonal connection region 3. The element isolation insulating film (not shown) and the element isolation buried region 2b that is buried under the element isolation insulating film constitute an element isolation region (pixel isolation region). As in the photodetectors according to the first to third embodiments, the element isolation insulating film can be buried in the top of the substrate region 1, for example, by an STI structure. As shown in FIGS. 6(a) and (b), the photodetector element that becomes the pixel constituting the photodetector according to the fourth embodiment has a layout in which the reset drain region 7 indicated by RD is surrounded by an octagonal ring-shaped reset gate electrode 12, which is further surrounded by a charge readout region FD and a photogate PG(i,j). In the photodetector according to the fourth embodiment, the element isolation insulating film (not shown) is structured to be present on the outside of the outermost element isolation buried region 2b or connection region 3, thereby improving the radiation resistance of each pixel constituting the photogate solid-state imaging device.

In the reset transistor RT(i,j) of the photodetector according to the fourth embodiment, an n ^{+ type reset drain region 7 having a higher impurity density than the charge generation buried layer 5 is disposed at the center of the upper part of the central well region 2a. Furthermore, the reset transistor RT(i,j) has an n+ type} charge readout region 8 having a higher impurity density than the charge generation buried layer 5 as a reset source region, disposed apart from the reset drain region 7. The charge readout region 8 is embedded in the periphery of the upper part of the well region 2a and in a part of the upper part of the base region 1 so as to protrude from the periphery of the upper part of the well region 2a to the outer periphery. In addition, the reset transistor RT(i,j) has a reset gate insulating film (second gate insulating film) 4a in contact with a part of the upper part of the well region 2a, which is a channel region formed between the charge readout region 8 and the reset drain region 7, and forms an insulating film-semiconductor interface. Furthermore, in the reset transistor RT(i,j), a reset gate electrode 12 made of DOPOS of the second conductivity type (n ⁺ type) is disposed on the reset gate insulating film 4a.

As shown in FIG. 6(a), the charge readout region 8 is annular, such as an octagonal ring, and surrounds the reset drain region 7. As shown in FIG. 6(b), the charge readout region 8 contacts the inner diameter end of the charge generation buried layer 5 and the inner diameter end of the shield layer 6 inside the substrate region 1, and is embedded in a ring shape in a part of the region extending from the top of the well region 2a to the top of the surrounding substrate region 1. The photogate PG(i,j) has an annular shape, such as an octagonal ring, and is divided into three regions: an inner peripheral relaxation region portion 14-1 assigned to the end of the reset transistor RT(i,j) on the charge readout region 8 side, a resistance increase portion 14-3 assigned to the end on the connection region 3 side, and a main transparent electrode layer 14-2 provided between the relaxation region portion 14-1 and the resistance increase portion 14-3. Dividing the transparent electrode into three continuous regions produces the effect of generating an electrostatic potential that is non-uniformly distributed along the direction of the semiconductor interface. As can be seen from the explanations of Figures 3(a) and (b), the pinning state is different between the semiconductor interface portion of the shield layer 6 directly below the relaxation region portion 14-1 and the resistance increase portion 14-3, and the semiconductor interface portion of the shield layer 6 directly below the main transparent electrode layer 14-2.

In the photodetector according to the fourth embodiment of the present invention, similarly to the photodetector according to the second embodiment, the relaxation region 14-1 and the resistance increasing portion 14-3 are DOPOS doped with an impurity element of the same second conductivity type (n ⁺ type) as the reset gate electrode 12 of the reset transistor RT(i,j). On the other hand, the main transparent electrode layer 14-2 is DOPOS doped with an impurity element of the first conductivity type (p ⁺ type) opposite to that of the reset gate electrode 12 of the reset transistor RT(i,j). For this reason, p-n junctions are respectively formed between the relaxation region 14-1 and the main transparent electrode layer 14-2, and between the main transparent electrode layer 14-2 and the resistance increasing portion 14-3. In addition, since the main transparent electrode layer 14-2 functions as a main part of the photogate PG(i,j), which is a transparent electrode, the radial length of the concentric ring of the main transparent electrode layer 14-2 is set to be longer than the radial length of the relaxation region 14-1 or the resistance increase portion 14-3, as shown in Figure 6 (a). As a result, the area (size) defined by the planar pattern of the main transparent electrode layer 14-2 is larger than the area of the relaxation region 14-1 or the resistance increase portion 14-3.

Since the main transparent electrode layer 14-2 is of the first conductivity type (p ⁺ type), the semiconductor surface of the shield layer 6 is stronger due to the work function difference between the semiconductor surface (semiconductor interface) of the shield layer 6, and the phenomenon of pinning by holes, which are the majority carriers of the shield layer 6, is the same as that of the photodetector element according to the second embodiment. The pinned holes (p-type charges) are charges of the opposite polarity to the electrons (n-type charges) which are the signal charges. Since the pinning of holes completes the dark current suppression, the solid-state imaging device in which the photodetector elements according to the fourth embodiment are arranged as each pixel can achieve high sensitivity and wide dynamic range imaging even in a radiation environment by completing the dark current suppression. In addition, by making the relaxation region portion 14-1 the second conductivity type (n ⁺ type), the electric field concentration between the photogate PG(i,j) and the charge readout region 8 can be alleviated. In particular, by adopting bias conditions for applying a voltage to the photogate PG(i,j) using the resistance increasing portion 14-3 of the second conductivity type (n ⁺ type) as an input end, the resistance of the electrical path passing through the two p-n junctions to the relaxation region portion 14-1 via the main transparent electrode layer 14-2 is increased.

By increasing the resistance of the electrical path from the resistance increasing portion 14-3 through the main transparent electrode layer 14-2 to the relaxation region portion 14-1, the electric field concentration between the photogate PG(i,j) and the charge readout region 8 can be further alleviated. Furthermore, the photodetector element according to the fourth embodiment has a planar layout in which the reset gate electrode 12, the charge readout region FD, and the photogate PG(i,j) are each concentrically arranged around the reset drain region 7. By arranging the photodetector elements with a ring layout on the same semiconductor chip as the pixels of the solid-state imaging device, a structure is easily realized in which the element isolation insulating film, which is easily deteriorated by gamma ray irradiation, is far from the charge generation buried layer 5 inside each pixel, and radiation resistance can be further improved.

The potential distribution along the direction of the cross section shown in FIG. 6(b) is shown in FIG. 6(c). In FIG. 6(c), the reset drain voltage RD, which is the potential of the reset drain region 7, is set to a value lower than the depletion potential of the charge generation buried layer 5, so that the charge generated by photoelectric conversion can be stored in the charge generation buried layer 5 and the charge readout region 8. By setting the reset drain voltage RD to a value lower than the depletion potential, the charge storage area of the charge generation buried layer 5 and the charge readout region 8 as the signal charge storage region is kept constant regardless of the charge amount Qs, and the charge-voltage conversion gain can be kept constant. Note that the channel potential formed in the charge generation buried layer 5 remains unchanged and is kept at an equipotential level, regardless of whether the transparent electrode of the photogate PG(i,j) is p-type or n-type, because the shield layer 6 maintains a state pinned to 0V.

The photodetector according to the fourth embodiment has the same effect as the photodetector according to the second embodiment, that is, it is possible to suppress depletion of the semiconductor interface of the shield layer 6 directly below the main transparent electrode layer 14-2, which has a large area, while mitigating the electric field concentration between the photogate PG(i,j) and the charge readout region 8, and to completely suppress dark current. Therefore, according to the solid-state imaging device according to the fourth embodiment, in which the photodetectors according to the fourth embodiment are arranged as pixels, it is possible to achieve the advantageous effect of enabling imaging with high sensitivity and a wide dynamic range even in a radiation environment. Moreover, since the pixel structure has a planar layout in which the reset gate electrode 12, the charge readout region FD, and the photogate PG(i,j) are each concentrically arranged around the reset drain region 7, the element isolation insulating film, which is easily deteriorated by gamma ray irradiation, can be kept away from the charge generation buried layer 5 inside each pixel, and radiation resistance can be further improved.

Other Embodiments
Although the present invention has been described with reference to the first to fourth embodiments, the description and drawings forming part of this disclosure should not be understood as limiting the present invention. Various alternative embodiments, examples, and operating techniques will become apparent to those skilled in the art from this disclosure.

For example, for a pixel (corresponding to the photodetector element in FIG. 1) according to the third or fourth embodiment, the planar layout of the reset gate electrode 12, photogate PG(i,j), and charge readout region FD is illustrated as an octagonal ring shape in the drawings, but is not limited to this and may be a square ring shape, a hexagonal ring shape, a polygonal ring shape with 10 or more sides, a circular ring shape, an elliptical ring shape, etc. Also, the planar layout of the reset gate electrode 12, photogate PG(i,j), and charge readout region FD is illustrated as a concentric ring shape in the drawings, but these rings do not have to be concentric.

In the first to fourth embodiments, the first conductivity type is p-type and the second conductivity type is n-type, but the first conductivity type may be n-type and the second conductivity type may be p-type. For example, in the first to fourth embodiments, the signal charge is an electron (first conductivity type charge), the pinned charge is a hole (second conductivity type charge), and the transistor in the pixel, for example, the reset transistor RT(i,j), is an nMOS transistor. However, the signal charge may be a hole, and the transistor in the pixel, for example, the reset transistor RT(i,j), may be a pMOS transistor. For example, it is possible to reverse the polarity of all the elements of the solid-state imaging device in the first to fourth embodiments. The type of transistor in the pixel is not limited to a MOS transistor such as a MOSFET, and MIS transistors, etc. may be used.

Furthermore, in the first to fourth embodiments, a two-dimensional photogate type solid-state imaging device (area sensor) has been described as an example, but the present invention should not be interpreted as being limited to a two-dimensional photogate type solid-state imaging device. For example, in the two-dimensional matrix arrangement, a part of which is illustratively shown in Figure 1, it should be easily understood from the contents of the technical ideas disclosed in the first to fourth embodiments that a one-dimensional photogate type solid-state imaging device (line sensor) may be configured in which pixels _Qij are arranged one-dimensionally by fixing i = 1 or j = 1.

As described above, the present invention includes various embodiments not described above, and the technical scope of the present invention is determined only by the invention-specific matters related to the scope of the claims that are appropriate from the above explanation.

1...substrate region, 2a...well region, 2b...element isolation buried region, 3...connection region, 4a...reset gate insulating film (second gate insulating film), 4b...photogate insulating film (first gate insulating film), 5...charge generation buried layer, 6...shield layer, 7...reset drain region, 8...charge readout region (reset source region), 9...element isolation insulating film, 10...photodetector element, 12...reset gate electrode, 14-1...relaxation region portion, 14-2...main transparent electrode layer, 14-3...resistance increase portion, 20...reset transistor scan drive circuit (RT scan circuit), 30...selection transistor scan drive circuit (SL scan circuit), 40...photogate scan drive circuit (PG scan circuit)

Claims (7)

a substrate region of a first conductivity type;
a charge generating buried layer of a second conductivity type buried in a portion of the upper part of the substrate region and configured to generate signal charges at a p-n junction with the substrate region;
a shield layer of the first conductivity type and having a higher impurity density than the base region, the shield layer being in contact with an upper surface of the charge generating buried layer and buried in another part of the upper portion of the base region;
a charge readout region of a second conductivity type, the charge readout region being buried in contact with the charge generation buried layer in another part of the upper portion of the base region and having a higher impurity density than the charge generation buried layer;
a photogate insulating film in contact with an upper surface of the shield layer;
a relaxation region of a second conductivity type, which is a transparent electrode provided on an end of the photogate insulating film on the charge read region side, the end being above a portion of the shield layer;
a first conductive type main transparent electrode layer which is a transparent electrode provided on the photogate insulating film, the first conductive type main transparent electrode layer being continuous with the relaxation region and located above another part of the shield layer;
a potential of the main transparent electrode layer being stronger than a potential of the relaxation region portion, thereby pinning charges of a first conductivity type to a semiconductor interface of the shield layer. a substrate region of a first conductivity type;
a charge generating buried layer of a second conductivity type buried in a portion of the upper part of the substrate region and configured to generate signal charges at a p-n junction with the substrate region;
a shield layer of the first conductivity type and having a higher impurity density than the base region, the shield layer being in contact with an upper surface of the charge generating buried layer and buried in another part of the upper portion of the base region;
a charge readout region of a second conductivity type, the charge readout region being buried in contact with the charge generation buried layer in another part of the upper portion of the base region and having a higher impurity density than the charge generation buried layer;
a photogate insulating film in contact with an upper surface of the shield layer;
a relaxation region of a second conductivity type, which is a transparent electrode provided on an end of the photogate insulating film on the charge read region side, the end being above a portion of the shield layer;
a first conductive type main transparent electrode layer which is a transparent electrode provided on the photogate insulating film, the first conductive type main transparent electrode layer being continuous with the relaxation region and located above another part of the shield layer;
a second conductivity type resistance increasing portion which is a transparent electrode provided on the photogate insulating film, the second conductivity type resistance increasing portion being continuous with the main transparent electrode layer on the side opposite to the relaxation region portion and above another part of the shield layer;
a potential of the main transparent electrode layer that is stronger than the potentials of the relaxation region and the resistance increase region, thereby pinning charges of a first conductivity type to a semiconductor interface of the shield layer. a well region of a first conductivity type having a higher impurity concentration than the base region, the well region being partly overlapping a part of the charge readout region and being embedded in another part of the upper portion of the base region;
a reset drain region of a second conductivity type, the reset drain region being spaced apart from the charge readout region and embedded in a portion of the upper portion of the well region, and having a higher impurity concentration than the charge generation buried layer;
a reset gate insulating film in contact with an upper surface of the well region between the charge read region and the reset drain region;
a reset gate electrode provided on the reset gate insulating film;
3. The light detection element according to claim 1, further comprising: The photodetector element according to claim 3, characterized in that the charge generated by photoelectric conversion is stored in the charge readout region, and the stored charge is discharged to the reset drain region by a voltage applied to the reset gate electrode. a substrate region of a first conductivity type;
a charge generating buried layer of a second conductivity type buried in a portion of the upper part of the substrate region and configured to generate signal charges at a p-n junction with the substrate region;
a shield layer of the first conductivity type and having a higher impurity density than the base region, the shield layer being in contact with an upper surface of the charge generating buried layer and buried in another part of the upper portion of the base region;
a charge readout region of a second conductivity type, which is buried in contact with the charge generation buried layer in yet another part of the upper portion of the base region and has a higher impurity density than the charge generation buried layer;
a photogate insulating film in contact with an upper surface of the shield layer;
a relaxation region of a second conductivity type which is a transparent electrode provided on an end of the photogate insulating film on the charge read region side, the end being above a part of the shield layer;
a first conductive type main transparent electrode layer which is a transparent electrode provided on the photogate insulating film, the first conductive type main transparent electrode layer being continuous with the relaxation region and located above another part of the shield layer;
and within each of the pixels, a potential of the main transparent electrode layer is stronger than a potential of the relaxation region portion, thereby pinning a first conductivity type charge to a semiconductor interface of the shield layer. a substrate region of a first conductivity type;
a charge generating buried layer of a second conductivity type buried in a portion of the upper part of the substrate region and configured to generate signal charges at a p-n junction with the substrate region;
a shield layer of the first conductivity type and having a higher impurity density than the base region, the shield layer being in contact with an upper surface of the charge generating buried layer and buried in another part of the upper portion of the base region;
a charge readout region of a second conductivity type, the charge readout region being buried in contact with the charge generation buried layer in another part of the upper portion of the base region and having a higher impurity density than the charge generation buried layer;
a photogate insulating film in contact with an upper surface of the shield layer;
a relaxation region of a second conductivity type which is a transparent electrode provided on an end of the photogate insulating film on the charge read region side, the end being above a part of the shield layer;
a first conductive type main transparent electrode layer which is a transparent electrode provided on the photogate insulating film, the first conductive type main transparent electrode layer being continuous with the relaxation region and located above another part of the shield layer;
a second conductivity type resistance increasing portion which is a transparent electrode provided on the photogate insulating film, the second conductivity type resistance increasing portion being continuous with the main transparent electrode layer on the side opposite to the relaxation region portion and above another part of the shield layer;
and within each of the pixels, a potential of the main transparent electrode layer is stronger than a potential of the relaxation region portion and the resistance increase portion, thereby pinning a first conductivity type charge to a semiconductor interface of the shield layer. Each of the pixels is
a well region of a first conductivity type having a higher impurity concentration than the base region, the well region being partly overlapping a part of the charge readout region and being embedded in another part of the upper portion of the base region;
a reset drain region of a second conductivity type, the reset drain region being spaced apart from the charge readout region and embedded in a portion of the upper portion of the well region, and having a higher impurity concentration than the charge generation buried layer;
a reset gate insulating film in contact with an upper surface of the well region between the charge read region and the reset drain region;
a reset gate electrode provided on the reset gate insulating film;
7. The solid-state imaging device according to claim 5, further comprising:

Images