JP2013239866A - Solid-state imaging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state imaging device which can easily transfer electric charge to a read-out region.SOLUTION: A solid-state imaging device 1 comprises: a substrate 11 composed of a first conductivity type semiconductor; a gate insulation film 12 which is formed on a top face of the substrate 11 and composed of an insulator; a photogate 16 formed on a top face of the gate insulation film 12; a first electrode 17P and a second electrode 17N which are electrically connected with the photogate 16 and which are formed at a distance form each other; a read-out region 14 in the substrate, which is composed of a second conductivity type semiconductor; and a transfer gate 15 formed on the top face of the gate insulation film 12 and between the photogate 16 and the read-out region 14. The first electrode 17P is formed at an end of the photogate 16 on the transfer gate 15 side. The second electrode 17N is formed at an end of the photogate 16 on the side opposite to the transfer gate 15 side.

Description

  The present invention relates to a solid-state imaging device typified by a complementary metal oxide semiconductor (CMOS) image sensor and a charge coupled device (CCD) image sensor.

  Solid-state imaging devices such as CCD image sensors and CMOS image sensors are used in various electronic devices equipped with imaging devices such as digital video cameras and digital still cameras, and mobile phones with cameras, scanners, copiers, and facsimiles. It is installed.

  The solid-state imaging device includes a pixel unit that generates and accumulates charges by photoelectric conversion, and generates pixel data based on the charges obtained from the pixel unit. An example of the structure of the pixel portion will be described with reference to FIGS. 10 and 11 are cross-sectional views illustrating structural examples of the pixel portion. Note that each of the pixel portions illustrated in FIGS. 10 and 11 accumulates electrons generated by photoelectric conversion.

  10A includes a substrate 101 made of a p-type semiconductor (hereinafter referred to as “p-type”), a gate insulating film 102 made of an insulator formed on the upper surface of the substrate 101, and the like. , An accumulation region 103 that is an n-type semiconductor region (hereinafter referred to as “n-type”) formed in the substrate 101, and a read region 104 that is an n-type region formed in the substrate 101. And a transfer gate 105 formed of a conductor and formed between the upper surface of the gate insulating film 102 and between the accumulation region 103 and the read region 104. Note that the concentration of the n-type impurity in the readout region 104 is higher than that in the accumulation region 103.

  In the pixel portion 100, electrons generated by photoelectric conversion of the substrate 101 and the accumulation region 103 (photodiode) are accumulated in the accumulation region 103. Then, by setting the transfer gate 105 to a positive potential, an inversion layer is formed between the accumulation region 103 and the readout region 104 in the substrate 101, and electrons are transferred from the accumulation region 103 to the readout region 104 through the inversion layer. Is done.

  10B includes a p-type substrate 201, a gate insulating film 202 formed on the upper surface of the substrate 201, and an accumulation region that is an n-type region formed in the substrate 201. 203, a read region 204 which is an n-type region formed in the substrate 201, a transfer gate 205 formed of a conductor and formed between the accumulation region 203 and the read region 204 on the upper surface of the gate insulating film 202, A surface region 206 that is a p-type region formed in the substrate 201 and is located between the upper surface of the substrate 201 and the accumulation region 203. Note that the concentration of the n-type impurity in the readout region 204 is higher than that in the accumulation region 203.

  In the pixel portion 200, electrons generated by photoelectric conversion of the substrate 201 and the accumulation region 203 (photodiode) are accumulated in the accumulation region 203. When the transfer gate 205 is set to a positive potential, an inversion layer is formed between the accumulation region 203 and the readout region 204 in the substrate 201, and electrons are transferred from the accumulation region 203 to the readout region 204 through the inversion layer. Is done. In the pixel portion 200, the accumulation region 203 is separated from the upper surface of the substrate 201 by forming the surface region 206. This makes it difficult for electrons to be trapped by a defect or the like on the upper surface of the substrate 201, so that the electrons can be easily transferred from the accumulation region 203 to the reading region 204.

  11A includes a p-type substrate 301, a gate insulating film 302 formed on the upper surface of the substrate 301, and a reading region which is an n-type region formed in the substrate 301. 303, a transfer gate 304 made of a conductor and formed on the upper surface of the gate insulating film 302 and adjacent to the readout region 303, and an upper surface of the gate insulating film 302 made of a conductor and formed at a position adjacent to the transfer gate. And a photogate 305 that transmits light (for example, a thin film or a light-transmitting material, and so on).

  In the pixel portion 300, the storage region 306 is formed immediately below the photogate 305 by setting the photogate 305 to a positive potential, and electrons generated by photoelectric conversion of the substrate 301 are stored in the storage region 306. By setting the transfer gate 304 to a positive potential, an inversion layer is formed between the accumulation region 306 and the readout region 303 in the substrate 301, and electrons are transferred from the accumulation region 306 to the readout region 303 through the inversion layer. Is done. A solid-state imaging device including a pixel portion having a structure similar to that of the pixel portion 300 is proposed in Patent Document 1.

  A pixel portion 400 shown in FIG. 11B includes a p-type substrate 401, a gate insulating film 402 made of an insulator formed on the upper surface of the substrate 401, and an n-type region formed in the substrate 401. Storage region 403, a read region 404 that is an n-type region formed in the substrate 401, and a transfer formed between the upper surface of the gate insulating film 402 and between the storage region 403 and the read region 404 made of a conductor. A gate 405 and a photogate 406 made of a conductor and formed on the upper surface of the gate insulating film 302 and immediately above the accumulation region 403 and transmit light are provided. Note that the concentration of the n-type impurity in the readout region 404 is higher than that in the accumulation region 403.

  In the pixel portion 400, electrons generated by photoelectric conversion of the substrate 401 and the accumulation region 403 (photodiode) are accumulated in the accumulation region 403. By setting the transfer gate 405 to a positive potential, an inversion layer is formed between the accumulation region 403 and the readout region 404 in the substrate 401, and electrons are transferred from the accumulation region 403 to the readout region 404 through the inversion layer. Is done. In the pixel portion 400, electrons stored in the storage region 403 are separated from the upper surface of the substrate 401 by setting the photogate 406 to a negative potential. This makes it difficult for electrons to be trapped by a defect or the like on the upper surface of the substrate 401, so that the electrons can be easily transferred from the accumulation region 403 to the reading region 404.

  A solid-state imaging device can be obtained by arranging the pixel portions as described above in a predetermined direction (for example, linear or matrix). For example, Patent Document 2 proposes a solid-state imaging device (line sensor) in which pixel portions are arranged in a straight line. Note that, in the pixel portion of the solid-state imaging device, the accumulation region is elongated with respect to the charge transfer direction in each pixel portion (in this case, the direction perpendicular to the alignment direction of the pixel portions). Thus, it is preferable to lengthen the accumulation region (increase the area of the accumulation region) because high sensitivity can be achieved.

JP 2000-209504 A JP 2011-22442 A

  However, as in the solid-state imaging device proposed in Patent Document 2, if the accumulation region is lengthened with respect to the charge transfer direction, the sensitivity can be improved, but it is difficult to transfer away from the readout region. This is a problem because the electric charge is present until.

  SUMMARY An advantage of some aspects of the invention is that it provides a solid-state imaging device capable of easily transferring charges to a readout region.

  In order to achieve the above object, the present invention provides a substrate made of a first conductivity type semiconductor, a gate insulating film made of an insulator formed on the upper surface of the substrate, and a photo film formed on the upper surface of the gate insulating film. A gate, a first electrode and a second electrode electrically connected to the photogate, a region in the substrate, and a readout region made of a semiconductor of a second conductivity type different from the first conductivity type; A transfer gate formed on an upper surface of a gate insulating film and between the photogate and the readout region, wherein the first electrode is formed at an end of the photogate on the transfer gate side, The second electrode is formed at an end of the photogate opposite to the transfer gate, and is separated from each other.

  According to this solid-state imaging device, the potential of the photogate can be graded by controlling the potentials of the first electrode and the second electrode provided at both ends of the photogate, respectively. Therefore, it is possible to easily move the charge accumulated in the region immediately below the photogate.

  The “first conductivity type substrate” means that the portion of the substrate where the element structure is formed is the first conductivity type, and is not limited to the substrate of the first conductivity type as a whole. Naturally, a substrate whose well is of the first conductivity type (for example, a substrate in which the first conductivity type well is formed by implanting the first conductivity type impurity into the substrate of the second conductivity type as a whole) is also natural. included.

Furthermore, in the solid-state imaging device having the above characteristics, when the first conductivity type is p-type and the second conductivity type is n-type, electrons accumulated in a region immediately below the photogate in the substrate are When transferred to the readout region, the potential of the first electrode becomes equal to or higher than the potential of the second electrode;
When the first conductivity type is n-type and the second conductivity type is p-type, holes accumulated in the region immediately below the photogate in the substrate are transferred to the readout region. It is preferable that the potential of the first electrode is equal to or lower than the potential of the second electrode.

  According to this solid-state imaging device, when transferring the charge accumulated in the region immediately below the photogate to the readout region, the charge accumulated in the region immediately below the photogate is drawn to the transfer gate side. It becomes possible to give a gradient to the potential of the gate.

  Furthermore, the solid-state imaging device having the above characteristics further includes: a first power source that supplies a first potential; and a second power source that supplies a second potential lower than the first potential, wherein the first conductivity type is p. And the second conductivity type is n-type, the electrons accumulated in the region immediately below the photogate in the substrate are transferred to the readout region, and the first electrode is connected to the first electrode. A first operation in which one potential is supplied and the second potential is not supplied to the second electrode; and the second potential is supplied to the second electrode and the first potential is applied to the first electrode. And the second operation in which the first conductivity type is n-type and the second conductivity type is p-type, at least once. Holes accumulated in the area immediately below are transferred to the readout area. A third operation in which the second potential is supplied to the first electrode and the first potential is not supplied to the second electrode, and the first potential is supplied to the second electrode. In addition, it is preferable that the fourth operation in which the second potential is not supplied to the first electrode is performed at least once.

  According to this solid-state imaging device, electrons can be brought to the transfer gate side by both the first operation and the second operation. Further, according to this solid-state imaging device, it is possible to bring holes to the transfer gate side by both the third operation and the fourth operation.

  Furthermore, in the solid-state imaging device having the above characteristics, when the first conductivity type is p-type and the second conductivity type is n-type, the second operation is performed after the first operation, and the first operation is performed. When the conductivity type is n-type and the second conductivity type is p-type, it is preferable that the fourth operation is performed after the third operation.

  According to this solid-state imaging device, in the second operation, since the potential of the photogate is lowered as a whole, electrons brought to the transfer gate side are transferred to the readout region. Therefore, by performing the second operation after the first operation, it is possible to effectively transfer the electrons brought to the transfer gate side in the first operation and the second operation to the reading region. Further, according to this solid-state imaging device, in the fourth operation, since the potential of the photogate increases as a whole, holes brought toward the transfer gate are transferred to the readout region. Therefore, by performing the fourth operation after the third operation, holes brought to the transfer gate side in the third operation and the fourth operation can be effectively transferred to the reading region.

Furthermore, in the solid-state imaging device having the above characteristics, a first transistor that is a p-channel transistor whose drain is electrically connected to the first power source, and a source that is electrically connected to the second power source and a gate is the A second transistor that is an n-channel transistor electrically connected to a gate of the first transistor, wherein the first conductivity type is p-type and the second conductivity type is n-type The source of the first transistor is electrically connected to the first electrode, the drain of the second transistor is electrically connected to the second electrode,
When the first conductivity type is n-type and the second conductivity type is p-type, the source of the first transistor is electrically connected to the second electrode, and the drain of the second transistor is the first It is preferable to be electrically connected to one electrode.

  According to this solid-state imaging device, the first operation and the second operation, or the third operation and the fourth operation can be performed only by controlling one control potential supplied to the gates of the first transistor and the second transistor. It becomes possible to execute the operation. Therefore, it is possible to simplify the control of the operation of the solid-state imaging device.

  Furthermore, in the solid-state imaging device having the above characteristics, a region immediately below the photogate in the substrate may be made of the second conductivity type semiconductor.

  According to the solid-state imaging device having the above characteristics, a gradient is applied to the potential of the photogate by controlling the potential of each of the first electrode and the second electrode provided at both ends of the photogate, so that the region immediately below the photogate The accumulated charge can be easily moved. Therefore, charges can be easily transferred to the reading region.

The top view and sectional drawing shown about the structural example of the pixel part with which the solid-state image sensor which concerns on embodiment of this invention is provided. The circuit diagram which modeled the accumulation | storage area | region, the gate insulating film, and the photogate. The graph which shows a time-dependent change of the distribution of the electric potential of the photogate when a predetermined electric potential is supplied to the 1st photogate contact. The graph which shows a time-dependent change of the distribution of the electric potential of the photogate when a predetermined electric potential is supplied to the 2nd photogate contact. The circuit diagram shown about the structural example of the solid-state image sensor which concerns on embodiment of this invention. The timing chart shown about the operation example of the solid-state image sensor which concerns on embodiment of this invention. FIG. 7 shows a potential state of a pixel portion in an initial period of the transfer period shown in FIG. FIG. 7 is a diagram showing the state of the potential of the pixel portion in the first period of the transfer period shown in FIG. 6. FIG. 7 shows a potential state of a pixel portion in a second period of the transfer period shown in FIG. Sectional drawing shown about the structural example of a pixel part. Sectional drawing shown about the structural example of a pixel part.

  Hereinafter, a solid-state imaging device according to an embodiment of the present invention will be described with reference to the drawings. In the following, for the sake of concrete explanation, a case where the solid-state imaging device according to the embodiment of the present invention includes a pixel portion in which an n-type accumulation region is formed in a p-type substrate will be exemplified.

  The “p-type substrate” refers to a substrate in which a portion where an element structure is formed is p-type, and is not limited to a substrate that is entirely p-type, and a substrate in which a well is p-type. (For example, a substrate in which a p-type well is formed by implanting a p-type impurity into a substrate that is entirely n-type) is naturally included. However, in each drawing referred to in the following description, the entire substrate is illustrated as if it is p-type.

  Further, silicon can be used as a material for the substrate. In this case, boron or the like can be used as the p-type impurity. In this case, phosphorus, arsenic, or the like can be used as the n-type impurity. Further, these impurities can be implanted into the substrate by applying a method such as ion implantation.

  A solid-state imaging device according to an embodiment of the present invention will be described below with reference to the drawings. First, a structural example of a pixel portion included in a solid-state imaging device according to an embodiment of the present invention will be described with reference to FIG. 1A and 1B are a plan view and a cross-sectional view illustrating a structural example of a pixel unit included in a solid-state imaging device according to an embodiment of the present invention. 1A is a plan view of one pixel portion included in the solid-state imaging device, and FIG. 1B is a cross-sectional view showing a cross section taken along the line AA in FIG.

  As shown in FIGS. 1A and 1B, the pixel unit 10 includes a p-type substrate 11, a gate insulating film 12 made of an insulator formed on the upper surface of the substrate 11, and a substrate 11. An accumulation region 13 which is an n-type region to be formed, a read region 14 which is an n-type region formed in the substrate 11, an upper surface of the gate insulating film 12 made of a conductor, and the accumulation region 13 and the read region 14 A transfer gate 15 formed between the photogate 16 and the photogate 16 made of a conductor and formed on the upper surface of the gate insulating film 12 and immediately above the storage region 13 and transmits light, and electrically connected to the photogate 16. A first photogate contact 17P (first electrode) and a second photogate contact 17N (second electrode); a first photogate wiring 18P electrically connected to the first photogate contact 17P; and a second photogate A second photogate wiring 18N electrically connected to the gate contact 17N, a transfer gate contact 19 electrically connected to the transfer gate 15, a transfer gate wiring 20 electrically connected to the transfer gate contact 19, and a substrate 11 A read region contact 21 electrically connected to the read region 14 on the upper surface and a read region wiring 22 electrically connected to the read region contact 21 are provided. Note that the concentration of the n-type impurity in the readout region 14 is higher than that in the accumulation region 13. In FIGS. 1A and 1B, an interlayer insulating film formed on the gate insulating film 12 is omitted for simplification of illustration.

  For example, the substrate 11 is made of silicon, the gate insulating film 12 is made of silicon oxide, the transfer gate 15 and the photogate 16 are made of polysilicon, various contacts 17P, 17N, 19, 21 and various wirings 18P, 18N, 20,. 22 is made of metal.

  The first photogate contact 17P is formed at the end of the photogate 16 on the transfer gate 15 side. The second photogate contact 17N is formed at the end of the photogate 16 opposite to the transfer gate 15 side. Therefore, the first photogate contact 17P and the second photogate contact 17N are separated from each other.

  In the pixel unit 10, electrons generated by photoelectric conversion of the substrate 11 and the accumulation region 13 (photodiode) are accumulated in the accumulation region 13. Then, by setting the transfer gate 15 to a positive potential, an inversion layer is formed between the accumulation region 13 and the readout region 14 in the substrate 11, and electrons are transferred from the accumulation region 13 to the readout region 14 through the inversion layer. Is done. At this time, by setting the photogate 16 to a negative potential, electrons accumulated in the accumulation region 13 can be separated from the upper surface of the substrate 11. In this case, electrons are not easily trapped by a defect or the like on the upper surface of the substrate 11, and it is possible to easily transfer the electrons from the accumulation region 13 to the reading region 14.

  Changes with time in the distribution of the potential of the photogate will be described with reference to FIGS. FIG. 2 is a circuit diagram modeling the storage region, the gate insulating film, and the photogate. FIG. 3 is a graph showing the change over time in the distribution of the potential of the photogate when a predetermined potential is supplied to the first photogate contact. FIG. 4 is a graph showing the change over time in the distribution of the potential of the photogate when a predetermined potential is supplied to the second photogate contact. 3 and 4 are graphs when the distance between the first photogate contact 17P and the second photogate contact 17N is assumed to be 100 μm, the vertical axis represents the potential (V), and the horizontal axis represents the first. The distance is from the photogate contact 17P. Therefore, on the horizontal axis of these graphs, the position of the first photogate contact 17P is 0 μm, and the position of the second photogate contact 17N is 100 μm.

  As shown in FIG. 2, the structure in which the accumulation region 13, the gate insulating film 12, and the photogate 16 are stacked is modeled as an RC circuit including the resistance component R of the photogate 16 and the capacitance component C of the gate insulating film 12. . For this reason, when the potential of the photogate 16 is partially changed, the entire potential does not change immediately but changes transiently over a predetermined time.

FIG. 3 shows that when the potential of the photogate 16 is uniform at 0V, a potential of 5V is supplied to the first photogate contact 17P and no potential is supplied to the second photogate contact 17N from the outside. It is a graph when it is in a state. In this graph, the time constant of the RC circuit is assumed to be 1.75 × 10 ⁻¹² . Each graph shown in FIG. 3 shows the photogate 16 when a predetermined time (0.1 ns, 0.8 ns, 6 ns, and 20 ns) has elapsed since the start of supplying a potential of 5 V to the first photogate contact 17P. It shows the distribution of potential.

  As shown in FIG. 3, when a potential of 5 V is supplied to the first photogate contact 17P, the potential increases faster toward the first photogate contact 17P side of the photogate 16, and increases more slowly toward the opposite side. Therefore, at any point in time, the potential increases toward the first photogate contact 17P side of the photogate 16 (the respective graphs monotonously decrease from the first photogate contact 17P toward the second photogate contact 17N. ). If a sufficiently long time has elapsed, the potential of the photogate 16 becomes uniform at 5V.

In FIG. 4, when the entire potential of the photogate 16 is uniform at 5V, a potential of 0V is supplied to the second photogate contact 17N, and a potential is externally applied to the first photogate contact 17P. It is a graph at the time of making it the state which is not supplied. In this graph as well, the time constant of the RC circuit is assumed to be 1.75 × 10 ⁻¹² . Each graph shown in FIG. 4 shows the photogate 16 when a predetermined time (0.1 ns, 0.8 ns, 6 ns, and 20 ns) has elapsed since the start of supplying a potential of 0 V to the second photogate contact 17N. It shows the distribution of potential.

  As shown in FIG. 4, when a potential of 0 V is supplied to the second photogate contact 17N, the potential decreases more rapidly toward the second photogate contact 17N side of the photogate 16, and decreases more slowly toward the opposite side. Therefore, at any time point, the potential of the photogate 16 becomes lower toward the second photogate contact 17N (the respective graphs monotonously decrease from the first photogate contact 17P toward the second photogate contact 17N). ). If a sufficiently long time has elapsed, the potential of the photogate 16 becomes uniform at 0V.

  Next, a configuration example of a solid-state imaging device according to an embodiment of the present invention including the pixel unit 10 illustrated in FIG. 1 will be described with reference to FIG. FIG. 5 is a circuit diagram illustrating a configuration example of the solid-state imaging device according to the embodiment of the present invention. In the solid-state imaging device 1 illustrated in FIG. 5, the plurality of pixel units 10 are arranged in an electron transfer direction (a direction in which the accumulation region 13, the transfer gate 15, and the readout region 14 are arranged, and FIGS. It is the line sensor arranged in the direction perpendicular | vertical with respect to (b) and the left-right direction in FIG.

As shown in FIG. 5, the solid-state imaging device 1 includes a plurality of pixel portions 10, and the first power supply EP for supplying the first electric potential V _P, second supplies lower than the first potential second potential V _N A power supply EN, a first transistor TP that is a p-channel transistor whose drain is electrically connected to the first power supply EP and whose source is electrically connected to the first photogate contact 17P of each pixel unit 10, An n-channel type having a source electrically connected to the second power supply EN, a drain electrically connected to the second photogate contact 17N of each pixel unit 10, and a gate electrically connected to the gate of the first transistor TP. transistor second transistor TN and, electrically connected is in the read area contact 21 of the reset potential V _R is supplied drains each pixel portion 10 in the source is in A reset transistor TR whose gate the reset control potential V _RST is provided the same number and is the pixel portion 10 are n-channel transistor supplied, the gate is output an output signal from the drain is supplied reset potential V _R to the source of each An n-channel transistor electrically connected to the readout region contact 21 of the pixel portion 10 and the same number of output transistors TD as the pixel portion 10.

The first photogate wiring 18P of the pixel unit 10 is shared by the pixel units 10 and connected to the source of the first transistor TP. In addition, the second photogate wiring 18N of the pixel unit 10 is shared by the pixel units 10 and connected to the drain of the second transistor TN. Further, the transfer gate wiring 20 of the pixel unit 10 is shared by the respective pixel units 10 and supplied with the transfer control potential V _TX . The photogate control potential V _GX is supplied to the gates of the first transistor TP and the second transistor TN.

  An example of the operation of the solid-state imaging device 1 will be described with reference to FIGS. FIG. 6 is a timing chart showing an operation example of the solid-state imaging device according to the embodiment of the present invention. 7 to 9 are diagrams illustrating potential states of the pixel portion in the predetermined period illustrated in FIG. 6 (the initial period of the transfer period, the first period of the transfer period, and the second period of the transfer period).

As shown in FIG. 6, first, the solid-state imaging device 1 resets the readout region 14 in the reset period P1. In the reset period P1, the reset control potential _VRST becomes high. Thus, the reset transistor TR is turned on, the read area 14 is in the reset potential V _R.

Next, the solid-state imaging device 1 outputs a reference output signal in the reference setting period P2. In the reference setting period P2, the reset control potential V _RST becomes low, and the reading region 14 becomes the initial potential V _S. Therefore, an output signal corresponding to the initial potential V _S is output from the drain of the output transistor TD to which the initial potential V _S is supplied to the gate. Note that the potential of the readout region 14 decreases due to capacitive coupling (feedthrough occurs) when the reset control potential V _RST changes from high to low. Therefore, initial potential _{V S} is lower than the reset potential _{V R.}

In the reset period P1 and the reference setting period P2, the transfer control potential V _TX is low. Therefore, transfer of electrons from the storage area 13 to the reading area 14 is not performed. In the reset period P1 and the reference setting period P2, the photogate control potential V _GX becomes high (first potential V _P ). Therefore, the first transistor TP is turned off, the first potential V _P is a state of not being supplied to the first photo gate contact 17P. The second transistor TN is turned on, the second voltage _{V N} is supplied to the second photo gate contact 17N.

Next, the solid-state imaging device 1 transfers electrons from the accumulation region 13 to the reading region 14 in the transfer period P3. In the transfer period P3, the transfer control potential _VTX becomes high. Therefore, electrons in the storage area 13 are transferred to the reading area 14.

In the initial period Q0 at the beginning, the photogate control potential V _GX is maintained high (first potential V _P ). In this initial period Q0, as shown in FIG. 7, electrons are transferred from the storage area 13 to the reading area.

In the first period Q1 following the initial period Q0, the photogate control potential V _GX becomes low (second potential V _N ). Therefore, the first transistor TP is turned on, the first potential _{V P} is supplied to the first photo gate contact 17P. On the other hand, the second transistor TN turned off, the second voltage V _N in a state that is not supplied to the second photo gate contact 17N.

In the first period Q1, the potential increases faster toward the first photogate contact 17P side of the photogate 16, and increases more slowly toward the opposite side. Therefore, at any time, the potential increases toward the first photogate contact 17P side of the photogate 16 (see FIG. 3). Therefore, in the first period Q1, the electrons in the storage region 13 are drawn to the first photogate contact 17P side (transfer gate 15 side). Incidentally, if the elapsed is sufficiently long time, the potential of the photogate 16 becomes uniform in the first potential V _P.

In the second period Q2 following the first period Q1, the photogate control potential V _GX becomes high (first potential V _P ). Therefore, the first transistor TP is turned off, the first potential V _P is a state of not being supplied to the first photo gate contact 17P. The second transistor TN is turned on, the second voltage _{V N} is supplied to the second photo gate contact 17N.

In the second period Q2, the potential decreases more rapidly toward the second photogate contact 17N side of the photogate 16, and the potential decreases later toward the opposite side. Therefore, at any time point, the potential increases toward the first photogate contact 17P side of the photogate 16 (see FIG. 4). Therefore, in the second period Q2, electrons in the storage region 13 are drawn toward the first photogate contact 17P side (transfer gate 15 side). Incidentally, if the elapsed is sufficiently long time, the potential of the photogate 16 becomes uniform in the second potential V _N.

  In the second period Q2, since the potential of the photogate 16 is lowered as a whole, electrons brought to the first photogate contact 17P side (transfer gate 15 side) are transferred to the reading region. Therefore, by providing the second period Q2 after the first period Q1, in the first period Q1 and the second period Q2, the electrons brought closer to the first photogate contact 17P side (transfer gate 15 side) in the storage region 13 Can be effectively transferred to the reading area 14.

  In the operation example shown in FIG. 6, the first period Q1 and the second period Q2 are repeated twice in one transfer period P3. The first period Q1 and the second period Q2 may be included once in one transfer period P3, or may be included three or more times.

Next, the solid-state imaging device 1 outputs an output signal corresponding to the electrons generated and accumulated by the pixel unit 10 in the output period P4. In this output period P4, the transfer control potential _VTX becomes low, and an output signal corresponding to the potential is output from the drain of the output transistor TD to which the potential corresponding to the electrons transferred to the read region 14 is supplied to the gate. Is done. However, the potential of the readout region 14 decreases due to capacitive coupling (feedthrough occurs) when the transfer control potential V _TX changes from high to low.

In the transfer period P3 and the output period P4, the reset control potential V _RST is kept low. In the output period P4, the photogate control potential V _GX becomes high (first potential V _P ). Therefore, the first transistor TP is turned off, the first potential V _P is a state of not being supplied to the first photo gate contact 17P. The second transistor TN is turned on, the second voltage _{V N} is supplied to the second photo gate contact 17N.

  The solid-state imaging device 1 generates pixel data by repeatedly performing the reset period P1, the reference setting period P2, the transfer period P3, and the output period P4. At this time, a difference between the reference output signal obtained in the reference setting period P2 and the output signal corresponding to the electrons generated and accumulated by the pixel unit 10 obtained in the output period P4 is obtained (correlated double sampling is performed). ) To generate pixel data. By generating pixel data in this way, it is possible to generate pixel data in which noise due to, for example, the above-described capacitive coupling (feedthrough) is canceled.

  As described above, in the solid-state imaging device 1, by controlling the potentials of the first photogate contact 17P and the second photogate contact 17N provided at both ends of the photogate 16, the potential of the photogate 16 is increased. It becomes possible to attach. Therefore, the electrons accumulated in the accumulation area 13 can be easily moved, and the electrons can be easily transferred to the reading area 14.

  In particular, in the solid-state imaging device 1, in the transfer period P3 in which the electrons accumulated in the accumulation region 13 are transferred to the readout region 14, the photogate 16 is arranged so that the electrons accumulated in the accumulation region 13 are brought closer to the transfer gate 15 side. It is possible to give a gradient to the potential. Specifically, it becomes possible to bring electrons to the transfer gate 15 side in both the first period Q1 and the second period Q2.

In addition, the solid-state imaging device 1 has only the simple control of controlling one photogate control potential V _GX supplied to the gates of the first transistor TP and the second transistor TN, and the first period Q1 and the second period. It is possible to execute the operation in Q2.

<Deformation, etc.>
As an example of the solid-state imaging device 1 according to the embodiment of the present invention, the solid-state imaging device 1 includes the pixel unit 10 having the structure having the n-type accumulation region 13 as illustrated in FIG. You may provide the pixel part of structure other than. For example, the solid-state imaging device 1 may include a pixel portion having a structure that does not include the n-type accumulation region 13 as illustrated in FIG.

The case where the n-type accumulation region 12 and the n-type readout region 14 are formed in the p-type substrate 11 (the case where electrons are accumulated in the accumulation region 13 and the readout region 14) is illustrated. The n-type may be reversed. That is, a p-type accumulation region and a read region may be formed in the n-type substrate (holes are accumulated in the accumulation region and the read region). Even in this case, the same effect as that of the solid-state imaging device 1 described above can be obtained. However, in this case, in the circuit diagram shown in FIG. 5, the first photogate contact 17P and the drain of the second transistor TN are connected, and the second photogate contact 17N and the source of the second transistor TP are connected. In the flowchart shown in FIG. 6, the high and low of the transfer control potential V _TX are reversed.

  As the solid-state imaging device 1 according to the embodiment of the present invention, a line sensor in which the pixel units 10 are arranged in a straight line is illustrated as an example. It may be. The solid-state imaging device according to the present invention may be a CMOS image sensor as described above, or may be other than a CMOS image sensor (for example, a CCD image sensor).

  The solid-state image pickup device according to the present invention can be used for a solid-state image pickup device mounted on various electronic devices having an image pickup function, for example, and can be preferably used particularly for a line sensor.

DESCRIPTION OF SYMBOLS 1: Solid-state image sensor 10: Pixel part 11: Substrate 12: Gate insulating film 13: Storage area 14: Read-out area 15: Transfer gate 16: Photogate 17P: 1st photogate contact (1st electrode)
17N: second photogate contact (second electrode)
18P: First photogate wiring 18N: Second photogate wiring 19: Transfer gate contact 20: Transfer gate wiring 21: Read area contact 22: Read area wiring TP: First transistor TN: Second transistor EP: First power supply EN : Second power supply TR: Reset transistor TD: Output transistor

Claims (6)

A substrate made of a first conductivity type semiconductor;
A gate insulating film made of an insulator formed on the upper surface of the substrate;
A photogate formed on an upper surface of the gate insulating film;
A first electrode and a second electrode electrically connected to the photogate;
A readout region comprising a semiconductor of a second conductivity type different from the first conductivity type, which is a region in the substrate;
A transfer gate formed on the top surface of the gate insulating film and between the photogate and the readout region;
The first electrode is formed at an end portion of the photogate on the transfer gate side, and the second electrode is formed at an end portion of the photogate on the opposite side to the transfer gate side, and separated from each other. A solid-state imaging device. When the first conductivity type is p-type and the second conductivity type is n-type,
When electrons accumulated in the region immediately below the photogate in the substrate are transferred to the readout region, the potential of the first electrode becomes equal to or higher than the potential of the second electrode,
When the first conductivity type is n-type and the second conductivity type is p-type,
The potential of the first electrode becomes equal to or lower than the potential of the second electrode when holes accumulated in a region immediately below the photogate in the substrate are transferred to the readout region. Item 2. The solid-state imaging device according to Item 1. A first power supply for supplying a first potential;
A second power source for supplying a second potential lower than the first potential;
When the first conductivity type is p-type and the second conductivity type is n-type,
The first potential is supplied to the first electrode and the second potential is applied to the second electrode when electrons accumulated in the region immediately below the photogate in the substrate are transferred to the readout region. And a second operation in which the second potential is supplied to the second electrode and the first potential is not supplied to the first electrode at least once. Done,
When the first conductivity type is n-type and the second conductivity type is p-type,
When the holes accumulated in the region immediately below the photogate in the substrate are transferred to the readout region, the second potential is supplied to the first electrode and the first potential is applied to the second electrode. A third operation in which no potential is supplied and a fourth operation in which the first potential is supplied to the second electrode and the second potential is not supplied to the first electrode are at least once. The solid-state imaging device according to claim 2, wherein the solid-state imaging device is performed step by step. When the first conductivity type is p-type and the second conductivity type is n-type, the second operation is performed after the first operation,
4. The solid-state imaging device according to claim 3, wherein when the first conductivity type is n-type and the second conductivity type is p-type, the fourth operation is performed after the third operation. 5. . A first transistor that is a p-channel transistor having a drain electrically connected to the first power source;
A second transistor that is an n-channel transistor having a source electrically connected to the second power supply and a gate electrically connected to the gate of the first transistor;
When the first conductivity type is p-type and the second conductivity type is n-type,
A source of the first transistor is electrically connected to the first electrode; a drain of the second transistor is electrically connected to the second electrode;
When the first conductivity type is n-type and the second conductivity type is p-type,
5. The solid according to claim 3, wherein a source of the first transistor is electrically connected to the second electrode, and a drain of the second transistor is electrically connected to the first electrode. Image sensor.   6. The solid-state imaging device according to claim 1, wherein a region immediately below the photogate in the substrate is made of the second conductivity type semiconductor.

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