KR20130007121A - A unit pixel of depth sensor, 3d image sensor including the unit pixel and method of the same - Google Patents

A unit pixel of depth sensor, 3d image sensor including the unit pixel and method of the same Download PDF

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KR20130007121A
KR20130007121A KR1020110063786A KR20110063786A KR20130007121A KR 20130007121 A KR20130007121 A KR 20130007121A KR 1020110063786 A KR1020110063786 A KR 1020110063786A KR 20110063786 A KR20110063786 A KR 20110063786A KR 20130007121 A KR20130007121 A KR 20130007121A
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South Korea
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charge collection
gate
region
collection region
threshold voltage
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KR1020110063786A
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Korean (ko)
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홍성권
진영구
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삼성전자주식회사
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Publication of KR20130007121A publication Critical patent/KR20130007121A/en

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
    • G01B11/00—Measuring arrangements characterised by the use of optical techniques
    • G01B11/02—Measuring arrangements characterised by the use of optical techniques for measuring length, width or thickness
    • G01B11/026—Measuring arrangements characterised by the use of optical techniques for measuring length, width or thickness by measuring distance between sensor and object
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/1461—Pixel-elements with integrated switching, control, storage or amplification elements characterised by the photosensitive area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14689—MOS based technologies

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

PURPOSE: A unit pixel of a depth sensor, a three dimensional image sensor including the same, and a manufacturing method thereof are provided to improve the quality of distance information by accelerating charges with a drift speed. CONSTITUTION: A bonding gate is arranged near a semiconductor substrate. Two photo gates(130,140) include a plurality of finger gates. The plurality of finger gates are extended from the bonding gate in parallel. Two transmission gates(151,161) are connected to the end of the photo gate. Two floating diffusion regions receive charges collected in a charge collection region.

Description

Unit pixel of depth sensor, 3D image sensor including the same and manufacturing method thereof {A UNIT PIXEL OF DEPTH SENSOR, 3D IMAGE SENSOR INCLUDING THE UNIT PIXEL AND METHOD OF THE SAME}

The present invention relates to a depth sensor, and more particularly, to a structure of a device for sensing image or distance information and a unit pixel thereof.

The depth sensor is a device that converts image or distance information provided through optical information into an electrical signal. Currently, research and development of 3D depth image sensor (3D depth image sensor) that provides distance information to existing image information has been actively conducted recently.

The 3D stereoscopic image sensor is mainly based on a CMOS image sensor (CIS) manufactured by using a conventional CMOS process technology. Each pixel of the CIS includes a photo-detecting region in which incident light generates a charge corresponding to an intensity, and a floating diffusion region in which the generated charge is accumulated.

The present invention provides a unit pixel of a depth sensor that can improve the efficiency of charge transfer to a floating diffusion region.

In order to solve the above technical problem, the unit pixel of the depth sensor according to an embodiment of the present invention is a semiconductor substrate; A junction gate disposed proximately on the semiconductor substrate and extending in a first direction; And two photogates extending from the junction gate in parallel with each other in a second direction perpendicular to the first direction; Two charge collection regions disposed under each of the photo gates to collect charges generated in the semiconductor substrate; Two transfer gates connected to the ends of the photo gate; And two floating diffusion regions connected to each of the transfer gates to receive the charges collected in the charge collection region in response to a transfer control signal, wherein each of the finger gates is disposed between the finger gates of the other counterpart. Each of the charge collection regions gradually decreases as the voltage approaches the junction gates in the second direction.

In order to solve the above technical problem, the unit pixel of the depth sensor according to another embodiment of the present invention is a semiconductor substrate; A photogate disposed close to the semiconductor substrate; A charge collection region for collecting charges in the lower layer at an end thereof with respect to the photo gate; Two transfer gates connected to the ends of the photo gates; And two floating diffusion regions connected to each of the transfer gates to receive the charges collected in the charge collection region in response to a transfer control signal, wherein the charge collection region is to be close to the floating diffusion region in a longitudinal direction. The threshold voltage gradually decreases.

The charge collection region has N multi-threshold voltages by injecting (N-1) impurities into the charge collection region to gradually reduce the threshold voltage, respectively, using different (N-1) masks.

The charge collection region adjusts the thickness of the charge collection region to become thinner gradually so that the threshold voltage gradually decreases, and the thickness is in the range of 1 to 100 nm.

The charge collecting region may be formed such that a passage of charge is narrower than a width of the charge collecting region.

In order to solve the above technical problem, a method of manufacturing a unit pixel of a depth sensor according to another embodiment of the present invention includes forming a photo gate and a floating diffusion region on a semiconductor substrate; Forming a charge collection region under the photo gate in the semiconductor substrate; And making the threshold voltage lower as the charge collection region approaches the floating diffusion region.

The unit pixel of the depth sensor, the 3D image sensor including the same, and a method of manufacturing the same according to embodiments of the present disclosure may improve charge transfer efficiency to a floating diffusion region by implementing charge to be accelerated at a drift speed. This improves the quality of the image and distance information.

1 is a block diagram of a depth sensor according to an exemplary embodiment of the present invention.
FIG. 2 is a cross-sectional view of an embodiment of a unit pixel of the depth sensor illustrated in FIG. 1.
FIG. 3 is a cross-sectional view for describing an operation of a unit pixel of FIG. 2 cut by II ′. FIG.
4A is a potential diagram for describing an operation of a unit pixel of FIG. 1.
4B is a potential diagram for describing an operation of a unit pixel of FIG. 1.
5A is a diagram illustrating a potential level of a unit pixel of FIG. 3.
5B is a diagram illustrating a potential level of a unit pixel of FIG. 3.
FIG. 6 is a cross-sectional view illustrating an example embodiment of implementing a potential level of a unit pixel illustrated in FIG. 5.
FIG. 7A is a cross-sectional view illustrating a side cross-sectional view of an embodiment in which a potential level of a unit pixel illustrated in FIG. 6 is implemented.
FIG. 7B is a cross-sectional view illustrating a side cross-sectional view of an embodiment in which the potential level of the unit pixel illustrated in FIG. 6 is implemented.
FIG. 8A illustrates a side view of each portion of the photo gate among the unit pixels illustrated in FIG. 2.
FIG. 8B is a side view of each portion of the photo gate of the unit pixel illustrated in FIG. 2.
FIG. 9A illustrates a cross-sectional view of another unit pixel of FIG. 1.
FIG. 9B illustrates a cross-sectional view of another unit pixel of FIG. 1.
10A is a flowchart of a first embodiment illustrating a method of implementing unit pixels of the depth sensor of FIG. 2.
FIG. 10B is a flowchart of a second embodiment illustrating a method of implementing unit pixels of the depth sensor of FIG. 2.
11 is a block diagram of an image processing system including a color image sensor and a depth sensor according to an exemplary embodiment of the present disclosure.
12 is a block diagram of a signal processing system including a depth sensor according to an exemplary embodiment of the present disclosure.

Specific structural and functional descriptions of embodiments of the present invention disclosed herein are illustrated for purposes of illustrating embodiments of the inventive concept only, And can be embodied in various forms and should not be construed as limited to the embodiments set forth herein.

The embodiments according to the concept of the present invention can make various changes and have various forms, so that specific embodiments are illustrated in the drawings and described in detail herein. It is to be understood, however, that it is not intended to limit the embodiments according to the concepts of the present invention to the particular forms of disclosure, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

Terms such as first and / or second may be used to describe various components, but the components should not be limited by the terms. The terms are intended to distinguish one element from another, for example, without departing from the scope of the invention in accordance with the concepts of the present invention, the first element may be termed the second element, The second component may also be referred to as a first component.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between. Other expressions describing the relationship between components, such as "between" and "immediately between," or "neighboring to," and "directly neighboring to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this specification, the terms "comprises ", or" having ", or the like, specify that there is a stated feature, number, step, operation, , Steps, operations, components, parts, or combinations thereof, as a matter of principle.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art, and are not construed in ideal or excessively formal meanings unless expressly defined herein. Do not.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in detail with reference to the preferred embodiments of the present invention with reference to the accompanying drawings.

1 is a block diagram of a depth sensor according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a depth sensor 10 capable of measuring distance using a time of flight (TOF) principle includes a semiconductor integrated circuit including a pixel array 40 in which a plurality of depth pixels 100 are arranged. 20, a light source 32 and a lens module 34.

The pixel array 40 includes a plurality of depth pixels 100.

The row decoder 24 selects any one of the plurality of rows in response to a row address output from the timing controller 26. Here, the row refers to a set of a plurality of depth pixels arranged in the X-direction in the pixel array 40.

The photo gate controller 28 may generate a plurality of photo gate control signals and supply them to the pixel array 40 under the control of the timing controller 26.

The light source driver 30 may generate a clock signal MLS capable of driving the light source 32 under the control of the timing controller 26.

The light source 32 emits a modulated optical signal to the target object 1 in response to the clock signal MLS. As the light source 32, a light emitting diode (LED), an organic light-emitting diode (OLED), or a laser diode may be used. The modulated optical signal may be a sine wave or a square file.

The light source driver 30 supplies the clock signal MLS or the information about the clock signal MLS to the photo gate controller 28.

The logic circuit 36 processes signals sensed by the plurality of depth pixels 100 implemented in the pixel array 40 under the control of the timing controller 26, and processes the processed signals into a processor (not shown). Can be printed as The processor may calculate a distance based on the processed signals. When the depth sensor 10 includes the processor, the depth sensor 10 may be a distance measuring device.

According to an embodiment, the depth sensor 10 and the processor may be implemented as separate chips.

According to an embodiment, the logic circuit 36 may include an analog-to-digital conversion block (not shown) capable of converting sensing signals output from the pixel array 40 into digital signals. The logic circuit 36 may further include a CDS block (not shown) for performing correlated double sampling (CDS) on the digital signals output from the analog-digital conversion block.

According to another embodiment, the logic circuit 36 may include a CDS block for performing a CDS on sensing signals output from the pixel array 40, and an analog for converting the signals CDS by the CDS block into digital signals. May comprise a digital conversion block.

In addition, the logic circuit 36 may further include a column decoder for outputting the output signals of the analog-to-digital conversion block or the CDS block to the processor under the control of the timing controller 26.

The modulated optical signal output from the light source 32 is reflected at the target object 1, and when the target object 1 has different distances Z1, Z2, and Z3, the distance Z is calculated as follows. do.

For example, when the modulated optical signal is cos ωt and the optical signal incident on the depth pixel 100 or the optical signal detected by the depth pixel 100 is cos (ωt + Φ), a phase shift by TOF; Φ) is as follows.

Φ = 2 * ω * Z / C = 2 * (2πf) * Z / C

Here, C represents the luminous flux. Therefore, the distance Z from the light source 32 or the pixel array 40 to the target object 1 is calculated as follows.

Z = Φ * C / (2 * ω) = Φ * C / (2 * (2πf))

The reflected optical signals are incident to the pixel array 40 through the lens module 34.

The depth sensor 10 includes a plurality of light sources arranged in a circle around the lens module 34, but only one light source 32 is shown for convenience of description.

Optical signals incident on the pixel array 40 through the lens module 34 may be demodulated by the plurality of depth pixels 100. That is, the optical signals incident on the pixel array 40 through the lens module 34 may form an image.

FIG. 2 illustrates a cross-sectional view of a unit pixel of a depth pixel illustrated in FIG. 1.

2, the unit pixel 100 may include a first photogate 130, a second photo gate 140, a first transfer gate 151, a second transfer gate 161, and a first floating diffusion region ( 153, a second floating diffusion region 163, a first output unit 170, and a second output unit 180.

The first photo gate 130 and the second photo gate 140 may be formed on the upper portion of the semiconductor substrate 110 so as not to overlap each other. The first photo gate 130 and the second photo gate 140 may generate a charge collection region 120 in the semiconductor substrate 110 that collects charges generated in the semiconductor substrate 110. The charge collection region 120 may collect electrons among electron-hole pairs generated by incident photons in the semiconductor substrate 110.

In some embodiments, the first photo gate 130 and the second photo gate 140 may include polysilicon or may include transparent conducting oxide (TCO). For example, the first photo gate 130 and the second photo gate 140 may be indium tin oxide (ITO), indium zinc oxide (IZO), or zinc oxide (ZnO). , Titanium dioxide (TiO 2), or a combination thereof.

The first photo gate 130 includes a first junction gate 133 extending in a first direction, and a plurality of first junction gates 133 extending in parallel with each other in a second direction substantially perpendicular to the first direction from the first junction gate 133. May include first finger gates 131a, 131b, 131c, 131d, and 131e. The first junction gate 133 and the first finger gates 131a, 131b, 131c, 131d, and 131e may be integrally formed in the same layer, or may be formed in different layers and electrically connected through the contact 137. .

The first junction gate 133 and the first finger gates 131a, 131b, 131c, 131d, and 131e may collect charges generated in the semiconductor substrate 110 in the lower charge collection region. The first junction gate 133 may provide a path through which charges collected under each of the first finger gates 131a, 131b, 131c, 131d, and 131e are transferred.

The second photo gate 140 may include a second junction gate 143 and a plurality of second finger gates 141a, 141b, 141c, 141d, and 141e. The second photo gate 140 may not overlap with the first photo gate 130 and may be disposed to be point-symmetrical to the first photo gate 130. In addition, each of the second finger gates 141a, 141b, 141c, 141d, and 141e may be disposed between the first finger gates 131a, 131b, 131c, 131d, and 131e. That is, the first finger gates 131a, 131b, 131c, 131d, and 131e and the second finger gates 141a, 141b, 141c, 141d, and 141e may be alternately disposed. Accordingly, a data error due to an imbalance between the first photogate 130 and the second photo gate 140 may be reduced. In this case, the second photo gates 140 are symmetrically implemented in the same manner as the first photo gates 130.

In one example, each of the first finger gates 131a, 131b, 131c, 131d and 131e and the second finger gates 141a, 141b, 141c, 141d and 141e are each about 0.25 to about 1 μm wide and about 3 μm. To about 30 μm in length. Adjacent first and second finger gates may have a spacing of about 0.25 to about 3 μm. Each of the first junction gate 133 and the second junction gate 143 may have a width of about 1 μm and a length of about 3 μm to about 30 μm. The width, length, and spacing of the finger gate and the junction gate may be changed according to the size of the unit pixel, the design rule, and the like. In addition, although an example in which each photo gate includes five finger gates is illustrated in FIG. 1, the number of finger gates may be changed according to a pixel size, a design rule, or the like.

Contacts 137 and 147 may be formed in the first photo gate 130 and the second photo gate 140, respectively. Control signals may be applied to the first photo gate 130 and the second photo gate 140 through the contacts 137 and 147, respectively. The first photo gate 130 and the second photo gate 140 may generate the charge collection region 120 in response to the control signals.

The first transfer gate 151 and the second transfer gate 161 are formed over the semiconductor substrate 110. The first transfer gate 151 is disposed between the first junction gate 133 and the first floating diffusion region 153, and the second transfer gate 161 is the second junction gate 143 and the second floating diffusion region. May be disposed between 163. The first transfer gate 151 and the second transfer gate 161 may collect charges collected by the first photo gate 130 and charges collected by the second photo gate 140 in the first floating diffusion region 153. ) And the second floating diffusion region 163, respectively.

The first finger gates 131a, 131b, 131c, 131d, and 131e are connected to the first junction gate 133, and the first transfer gate 151 is formed adjacent to the first junction gate 133. The first junction gate 133 and the first transfer gate 151 have a first floating diffusion in which charges collected under each of the first finger gates 131a, 131b, 131c, 131d, and 131e are responded to in response to a transmission control signal. It may provide a route to the area 153. In addition, the second junction gate 143 and the second transfer gate 161 may have charges collected under the second finger gates 141a, 141b, 141c, 141d, and 141e in response to the transmission control signal. 2 may provide a path transmitted to the floating diffusion region 163.

The drift speed has a faster moving speed than the diffusion speed. Each of the first finger gates 131a, 131b, 131c, 131d, and 131e moves from the lower charge collection region to the charge collection region 121 under the first junction gate 133. This can be achieved by adjusting the surface potential level to move faster by adding not only the diffusion rate but also the drift rate. At this time, if the potential level is gradually increased closer to the first junction gate 133 in the second direction, the generated electrons are combined in the charge collection region under the first junction gate with a drift speed according to the directionality of the surface potential. Move to the first floating diffusion region 153. In the same manner, each of the second finger gates 141a, 141b, 141c, 141d, and 141e gradually becomes closer to the second junction gate 143 in the second direction in the lower charge collection region 122. In this case, the generated electrons are combined in the charge collection region under the second junction gate 143 and move to the second floating diffusion region 163 at a drift speed according to the direction of the surface potential.

As a result, all the charges generated at the respective finger gates are added not only to the diffusion speed but also to the drift speed due to the level difference of the surface potential, so that each floating diffusion region 153 and 163 is faster. Go to). That is, a low surface potential value is given to the charge collection region under the terminal of the finger gate, and a high surface potential value is given to the charge collection region below the finger gate near the floating diffusion region to control the drift rate of the collected charges. Specific embodiments of the level difference of the surface potential will be described with reference to FIGS. 3 to 5.

The first floating diffusion region 153 and the second floating diffusion region 163 may accumulate charges transferred by the first transfer gate 151 and the second transfer gate 161, respectively. The first output unit 170 and the second output unit 180 may output electrical signals corresponding to the charges accumulated in the first floating diffusion region 153 and the second floating diffusion region 163, respectively. . For example, the first output unit 170 may include a first reset transistor 171 for discharging charges accumulated in the first floating diffusion region 153 and a first amplifying voltage of the first floating diffusion region 153. A first select transistor 175 for outputting a voltage amplified by the drive transistor 173 and the first drive transistor 173 to a first column line, and the second output unit 180 includes a second floating diffusion region. Amplified by the second reset transistor 181 for discharging the charges accumulated in the 163, the second drive transistor 183 for amplifying the voltage of the second floating diffusion region 163, and the second drive transistor 183. And a second select transistor 185 for outputting the output voltage to the second column line.

As described above, the present invention gives a low surface potential value (high threshold voltage value) to the charge collection region under the terminal of the finger gate, and a high surface potential value for the charge collection region under the finger gate near the floating diffusion region. The gate modulation rate can be increased by adjusting the drift rate of the collected charges by giving (a low threshold voltage value).

FIG. 3 is a cross-sectional view illustrating the operation of the unit pixel of FIG. 2 cut by II ′, FIG. 4 is a potential diagram illustrating the operation of the unit pixel of FIG. 1, and FIG. 5 is a unit of FIG. 3. Diagram showing the surface potential level of a pixel.

Referring to FIG. 3, the unit pixel 100 may include a first photo gate 130, a first photo gate oxide 135, a second photo gate 140, a second photo gate oxide 145, and a first transfer gate. 151, the first transfer gate oxide 157, the second transfer gate 161, the second transfer gate oxide 167, the first floating diffusion region 153, the second floating diffusion region 163, and And a first output unit 170 and a second output unit 180.

The first photo gate 130 and the second photo gate 140 may include a first control signal PGCS1 periodically toggling between the first logic level and the second logic level during an integration time, and Each second control signal PGCS2 may be applied.

The first charge collection region 121 under the first photo gate 130 collects charges generated in the semiconductor substrate 110 when the first control signal PGCS1 has the first logic level. The second charge collection region 122 under the second photo gate 140 may collect charges generated in the semiconductor substrate 110 when the second control signal PGCS2 has the first logic level.

During the condensing time, the first control signal PGCS1 and the second control signal PGCS2 may have different phases. For example, the second control signal PGCS2 may have an inverted phase with respect to the first control signal PGCS1. Accordingly, the first photo gate 130 and the second photo gate 140 are selectively turned on, and the first charge collection region 121 and the second charge collection region 122 may selectively collect charges. Can be. This is called gate modulation.

The depth sensor 10 including the unit pixel 100 periodically turns on and off the light emitting device 32 to transmit light having a periodically varying intensity, and the transmitted light is reflected by the subject. The received light can be received. As a result, the depth sensor 10 uses the ratio of the charges collected by the first charge collection region 121 and the charges collected by the second charge collection region 122 to determine a delay time of the received light, that is, a TOF or The delay phase can be measured.

In this case, the first charge collection region 121 and the second charge collection region 122 are implemented to sequentially decrease the threshold voltage Vth. That is, the threshold voltage Vth gradually decreases as the threshold voltage Vth approaches the first floating diffusion region 153 in the second direction so that the charges in the first charge collection region 121 move faster by adding a drift rate when the charges move. Implement to In the same manner, the threshold voltage Vth in the second charge collection region 122 may be gradually decreased as the second floating diffusion region 163 approaches the second floating diffusion region 163 in the second direction. 4 and 5, examples of potential levels of a unit pixel when the first charge collection region 121 and the second charge collection region 122 collect charges are illustrated. The positive direction of the Y axis is a direction in which the potential level is lowered.

In order to collect the charge more effectively, the unit pixel may further include a bridging diffusion region (BD, 155, 165). Bridging diffusion regions 155 and 165 are formed adjacent to the gate in the semiconductor substrate. The bridging diffusion region may have a higher voltage level than the charge collection region when the charge collection regions 121 and 122 collect charges and have a lower level than the charge collection region when the charge collection region collects holes. As such, the bridging diffusion regions 155 and 165 have a voltage level that attracts the collected charges, thereby improving charge transfer efficiency from the charge collection regions 121 and 122 to the floating diffusion regions 153 and 163. In addition, the bridging diffusion region may further improve the charge transfer efficiency by suppressing a potential barrier that may occur between the charge collection region and the substrate region under the transfer gate.

Referring to FIG. 4, the threshold voltage Vth distribution of the lower charge collection region of the photogate is shown. As shown in FIG. 4A, when a high voltage V High is applied to the photogate, charges in the charge collection region are induced to the surface and held in the state of being collected on the photogate surface. After the On state is completed, as shown in FIG. 4B, a low voltage V Low is applied to the photogate so that the charges collected on the photogate surface are transferred to the floating diffusion region. In this case, the gate threshold voltage Vth is lowered closer to the floating diffusion region to move the charge at a drift speed in order to move the charge quickly. That is, the high frequency characteristic of the pixel is improved by increasing the speed of charge movement.

In FIG. 5A, when the first control signal PGCS1 has a first logic level and the second control signal PGCS2 has a second logic level, a first generated by the first photo gate 130. The charge collection region 121 collects charges generated in the semiconductor substrate 110. At this time, the first charge collection region has a low potential level at the finger gate end, and has a high potential level closer to the floating gate FD, so that the collected charges drift easily to the junction gate. When the second control signal PGCS2 has the second logic level, the substrate region (ie, the transfer channel) under the second transfer gate 161 may be the second charge collection region 122 under the second photo gate 140. Has a potential level higher than). Accordingly, charges previously collected in the second charge collection region 122 are transferred to and accumulated in the second floating diffusion region 163 through the transfer channel.

As such, when the first control signal PGCS1 has the first logic level and the second control signal PGCS2 has the second logic level, the first half-including the first photo gate 130. The pixel may perform charge collection, and the second half-pixel including the second photo gate 140 may perform charge transfer.

FIG. 5B illustrates a case in which the first control signal PGCS1 has the second logic level and the second control signal PGCS2 has the first logic level in a phase opposite to that of FIG. 5A. The first half-pixel including the first photo gate 130 may perform charge transfer, and the second half-pixel including the second photo gate 140 may perform charge collection.

A third control signal TGCS having a constant voltage level during the condensing time may be commonly applied to the first transmission gate 151 and the second transmission gate 161. The first transfer gate 151 and the second transfer gate 161 are controlled by a third control signal TGCS to between the first charge collection region 121 and the first floating diffusion region 153 and to collect the second charge. Transmission channels may be respectively formed between the region 122 and the second floating diffusion region 163.

The first floating diffusion region 153 and the second floating diffusion region 163 are formed in the semiconductor substrate 110. In one example, the first floating diffusion region 153 and the second floating diffusion region 163 may be doped high (to a high concentration) with n-type impurities. The first floating diffusion region 153 may collect in the first charge collection region 121 and accumulate charges transferred through a transfer channel under the first transfer gate 151. In addition, the second floating diffusion region 163 may collect in the second charge collection region 122 and accumulate charges transferred through the transfer channel under the second transfer gate 161.

The first output unit 170 and the second output unit 180 transmit electrical signals corresponding to the charges accumulated in the first floating diffusion region 153 and the second floating diffusion region 163 in the first column line ( 177 and the second column line 187, respectively. The first drive transistor 173 and the second drive transistor 183 amplify the voltage of the first floating diffusion region 153 and the voltage of the second floating diffusion region 163, respectively. The first select transistor 175 and the second select transistor 185 apply the voltage amplified by the first drive transistor 173 and the voltage amplified by the second drive transistor 183 in response to the select signal SEL. Output to the first column line 177 and the second column line 187, respectively.

3 illustrates a unit pixel in which each half-pixel has one output unit, some or all of the output units may be shared by a plurality of half-pixels.

6 is a cross-sectional view illustrating an embodiment of implementing the unit pixel illustrated in FIGS. 3 and 5.

As shown in FIG. 6, the first finger gates 131a, 131b, 131c, 131d, and 131e and the second finger gates 141a, 141b, 141c, 141d, and 141e have a floating diffusion region FD at their ends. In the second direction, the threshold voltage is gradually lowered. At this time, according to the sectional view II-II 'of the second finger gate 141a, the left side of the second finger gate 141a is positioned toward the end and the right side of the second floating diffusion region. For convenience of explanation, the description is based on the assumption that there are three threshold voltages (high Vth, middle Vth, and low Vth). However, the present invention is not limited thereto. Any N threshold voltage values preset according to the photogate length are not limited thereto. It can be variously implemented to have.

FIG. 7 is a cross-sectional view illustrating a II-II 'side of a unit pixel illustrated in FIG. 6.

According to the first embodiment, as shown in FIG. 7A, the threshold voltage may be implemented as shown at the bottom of FIG. 6 according to the ion implantation method to implement the multi-threshold voltage value.

In one embodiment, in the charge collection region, the middle threshold voltage region is left at the original concentration of the semiconductor substrate 110, and first, a primary photoresist is formed to pattern the high threshold voltage region. Thereafter, the high threshold voltage region is doped by implanting n-type impurities at about 1E14 to 1E19. Subsequently, after removing the primary photoresist, the secondary photoresist is again formed to pattern the low threshold voltage region. The low threshold voltage region is implanted with p-type impurities in the range of 1E14 to 1E19 to remove the secondary photoresist.

In order to collect the charge more effectively, the unit pixel may further include a bridging diffusion region (BD). The bridging diffusion region is formed in the semiconductor substrate adjacent to the junction gate. The bridging diffusion region may have a higher voltage level than the charge collection region when the charge collection region collects charges and may have a lower level than the charge collection region when the charge collection region collects holes. As such, the bridging diffusion region has a voltage level that attracts the collected charges, thereby improving charge transfer efficiency from the charge collection region to the floating diffusion region. In addition, the bridging diffusion region may further improve the charge transfer efficiency by suppressing a potential barrier that may occur between the charge collection region and the substrate region under the transfer gate.

In another embodiment, the high threshold voltage region may be left at the original concentration of the semiconductor substrate 110. First, the primary photoresist is formed to pattern the middle threshold voltage region. The intermediate threshold voltage region is then doped by implanting low n-type impurities and removing the primary photoresist. A secondary photoresist is then formed and the low threshold voltage region is patterned. The low threshold voltage region is doped by implanting high n type impurities and removes the secondary photoresist. In this case, the n-type impurity implantation is in the range of 1E14 to 1E19.

In another embodiment, the low threshold voltage region is left at the original concentration of the semiconductor substrate 110. First, the primary photoresist is formed to pattern the middle threshold voltage region, and the middle threshold voltage region is doped by implanting a low p-type impurity. The primary photoresist is then removed and a secondary photoresist is formed to pattern the high threshold voltage region. The high threshold voltage region is doped by injecting high p-type impurities and removes the secondary photoresist. At this time, the p-type impurity implantation is in the range of 1E14 to 1E19.

As described above, an additional mask is used according to the number of multi-threshold voltage regions during additional ion implantation. In the above embodiment, two masks are used to implement three threshold voltage regions. That is, since the mask is used to implement the original substrate concentration (eg, epitaxial concentration) and the remaining threshold voltage regions, (N-1) masks are used to implement the N threshold voltage regions.

According to the second embodiment, as shown in FIG. 7B, the threshold voltage may be implemented according to the gate oxide thickness of the photogate. Since the thickness of the photo gate oxide affects the threshold voltage region of the transfer gate, the thickness of the gate oxide becomes thinner as it approaches the floating diffusion region from the end of the photo gate. That is, as the thickness of the photo gate oxide increases, the threshold voltage of the transfer gate increases, and the difference in the threshold voltage becomes a difference in the surface potential level in the charge collection region, thereby adding a drift rate to the charge.

In an exemplary embodiment, when three multi-threshold voltages are implemented, as illustrated in FIG. 7B, the gate oxide has a thickness of a in a high threshold voltage region and a middle threshold voltage region. With a thickness of b, it is realized with a thickness of c in the low threshold voltage region. At this time, the thickness of a, b and c is within 1 to 100nm.

In order to implement various gate oxide thicknesses, first, a first gate oxide is formed in the entire photogate region, a first photoresist is formed only in a high threshold voltage region, and then gate oxide is removed. After removing the primary photoresist and forming the secondary gate oxide in the entire photogate region, the secondary photoresist is formed only in the high threshold voltage region and the middle threshold voltage region, and then the oxide is removed. After removing the secondary photoresist and forming the tertiary gate oxide in the entire photogate region, the tertiary photoresist is formed in the high threshold voltage region, the middle threshold voltage region, and the low threshold voltage region, and then the oxide is removed. The high threshold voltage region thus formed has the thickest thickness due to the formation of primary, secondary and tertiary gate oxides, and the middle threshold voltage region has a medium thickness due to the formation of secondary and tertiary gate oxides and the low threshold voltage. The region has the thinnest thickness due to tertiary gate oxide formation. However, the implementation of the thickness is not limited to the above embodiment and may be variously implemented according to the step of the multi-threshold voltage value.

FIG. 8 is a cross-sectional view illustrating A-A 'and B-B' side surfaces of a unit pixel illustrated in FIG. 6.

Referring to FIG. 6, the side A-A 'of the first finger gate is shown as shown in FIG. 8A. When patterning by the photoresist of the multi-threshold voltage, the charge collection region at the bottom of the finger gate may be formed to be narrower than the width of the finger gate. For example, assuming that the width (1) of the finger gate is 0.4 um, the charge collection region (2) at the bottom of the finger gate is formed to have a narrow width of about 0.34 um.

When the charge collection region ② is formed to be narrower than the width ① of the finger gate, the charge transfer path is narrowed, thereby reducing charge leakage between the finger gates 131a, 131b, 131c, 131d, and 131e. The implementation may be similarly implemented in the case of the second finger gate PG2.

Referring to FIG. 6, the side surface B-B ′ of the junction gate 133 or 143 is shown as shown in FIG. 8B. The charge collection region at the bottom of the junction gate may be further separated from the finger gate side B during patterning so as to be formed narrower than the width of the junction gate. For example, assuming that the junction gate width ③ is 1.5 um, the charge collection region on the side connected to the finger gate is formed from about 0.2 um from the end of the junction gate, and the charge collection region on the opposite side ( ⑤) is formed inward about 0.1um from the end of the junction gate.

The charge collection region ③ at the bottom of the junction gate may be formed a little farther from the finger gate (④) and narrower than the width of the junction gate (⑤) to reduce charge leakage between the finger gates. The implementation may be similarly implemented for the second junction gate.

FIG. 9 is a cross-sectional view of another unit pixel of FIG. 1. Referring to FIG.

Referring to FIG. 9A, unlike the unit of FIG. 2, the unit pixel 200 is implemented as a photo gate having a simpler structure. The unit pixel 200 includes the charge collection region 230, the photo gate 220, the photo gate oxide 225, the first transfer gate 261, the first transfer gate oxide 265, and the second transfer gate 262. And a second transfer gate oxide 266, a first floating diffusion region 251, and a second floating diffusion region 252. The unit pixel 200 may further include a separate barrier 210 to reduce charge leakage between other pixels.

The unit pixel 200 performs a gate modulation operation using the first transfer gate 261 and the second transfer gate 262. In other words, the depth sensor includes the charges collected in the first floating diffusion region 251 when the first transfer gate 261 is turned on and the second floating diffusion region (2) when the second transfer gate 262 is turned on. The ratio of charges collected at 252 can be used to measure the delay time, ie TOF or delay phase, for the transmitted light of the received light.

The charge collection region 230 at the bottom of the photo gate 220 may be implemented to have a multi-threshold voltage level. That is, the closer the floating diffusion regions 251 and 252 are, the lower the threshold voltage level may be, so that the charge transfer efficiency of the unit pixel 200 may be improved through charge transfer with a drift speed.

FIG. 9B is a side view of the unit pixel 200 shown in FIG. 9A.

According to the first embodiment, the unit pixel 200 is implemented to have three multi-threshold voltages in the charge collection region 230. That is, the charge collection region is implemented as the high threshold voltage region 231, the middle threshold voltage region 232, and the low threshold voltage region 233, respectively. In this case, the method of implementing the multi-threshold voltage is as described with reference to FIG. 7.

The charge collection region shown in Fig. 9B is a case where the high threshold voltage region is left at the original concentration of the semiconductor substrate. First, the primary photoresist is formed to pattern the middle threshold voltage region. The intermediate threshold voltage region is then doped by implanting low n-type impurities and removing the primary photoresist. A secondary photoresist is then formed and the low threshold voltage region is patterned. The low threshold voltage region is doped by implanting high n type impurities and removes the secondary photoresist. In this case, the n-type impurity implantation is in the range of 1E14 to 1E19.

The unit pixel 200 may further include a separate well 255 before forming the floating diffusion regions 251 and 252. The well 255 may prevent charge from being transferred directly from the charge collection region 230 to the floating diffusion regions 251 and 252 regardless of whether the transfer gate is turned on or off.

According to the second embodiment, the multi-threshold voltage may be implemented by the thickness of the gate oxide of the photo gate. The closer the gate oxide thickness is to the floating diffusion region, the thinner the gate oxide thickness is, thereby increasing the drift rate of charge.

However, the present invention is not limited to the embodiment of FIG. 9, and the multi-threshold voltage may be implemented as a plurality of preset numbers (for example, N).

FIG. 10A is a flowchart of a first embodiment implementing unit pixels of the depth sensor of FIG. 2, and FIG. 10B is a flowchart of a second embodiment implementing unit pixels of the depth sensor of FIG. 2.

Referring to FIG. 10A, first, a photo gate and a floating diffusion region are formed on a semiconductor substrate (S10), and a charge collection region is formed on the bottom of the photo gate (S11). In order to implement the multi-threshold voltage level in the charge collection region, impurities are implanted into some of the charge collection regions by using a mask (S12).

For example, in order to sequentially implement N multi-threshold voltage levels, one threshold voltage region uses the original substrate concentration (eg, epitaxial concentration) of the semiconductor substrate, and the remaining (N-1) threshold voltage regions. For this purpose, (N-1) masks having different patterning areas are used. That is, the k-th impurity is implanted using the k-th mask for patterning the k-th region. In this case, k is a natural number of 1 or more, and the k-th impurity is injected into the charge collection region so that the threshold voltage is lowered as the floating diffusion region approaches the photogate terminal. The k-th impurity is n-type or p-type and is in the concentration range of 1E14 to 1E19.

If all N multi-threshold voltages are implemented using (N-1) masks (S13), N multi-threshold voltage regions are formed in which the threshold voltage decreases as the closer to the floating diffusion region near the photogate terminal (S14). . As a result, the drift rate is added to the charge transfer during gate modulation by the TOF, thereby increasing the charge transfer efficiency to the floating diffusion region.

Referring to FIG. 10B, according to the second embodiment, first, a photo gate and a floating diffusion region are formed on a semiconductor substrate (S20), and a charge collection region is formed in the semiconductor substrate under the photo gate (S21). Oxide thickness is controlled within the range of 1 nm to 100 nm of the photo gate to implement multi-threshold voltage levels in the charge collection region.

For example, after forming the k-th gate oxide on the photogate (S22) and forming a portion of the k-th photoresist (S23), the k-th gate oxide is removed (S24). In order to sequentially implement the N multi-threshold voltage levels by repeating the above method, the oxide thickness of the photogate becomes thinner as it approaches the floating diffusion region at the end of the photogate (S25 and S26).

When all N multi-threshold voltages are implemented, N multi-threshold voltage regions are formed in which the threshold voltage decreases as the closer to the floating diffusion region near the photogate terminal (S27). As a result, the drift rate is added to the charge transfer during gate modulation by the TOF, thereby increasing the charge transfer efficiency to the floating diffusion region.

11 is a block diagram of an image processing system including a color image sensor and a depth sensor according to an exemplary embodiment of the present disclosure.

Referring to FIG. 11, the image processing system 400 may include a depth sensor 10, a color image sensor 330 including RGB color pixels, and a processor 310.

11 illustrates a depth sensor 10 and a color image sensor 330 that are physically separated from each other for convenience of description, but a signal processing circuit in which the depth sensor 10 and the color image sensor 330 are physically overlapped with each other. Can include them.

Here, the color image sensor 330 may refer to an image sensor including a pixel array implemented as a red pixel, a green pixel, and a blue pixel without including a depth pixel. Accordingly, the processor 310 may determine depth information calculated by the depth sensor 10 and each color information (eg, red information, green information, blue information, magenta information, cyan) output from the color image sensor 330. 3D image information may be generated based on the cyan information or at least one of yellow information) and the generated 3D image information may be displayed on the display.

3D image information generated by the processor 310 may be stored in the memory device 320 through the bus 401.

The image processing system 400 shown in FIG. 11 may be used in a three-dimensional range finder, game controller, depth camera, or gesture sensing apparatus.

12 illustrates an electronic system and interface including an image sensor in accordance with one embodiment of the present invention. Referring to FIG. 12, the electronic system 1000 may be implemented as a data processing device capable of using or supporting a MIPI interface, such as a mobile phone, a PDA, a PMP, an IPTV, or a smart phone.

The electronic system 1000 includes an application processor 1010, an image sensor 1040, and a display 1050.

The CSI host 1012 implemented in the application processor 1010 may serially communicate with the CSI device 1041 of the image sensor 1040 through a camera serial interface (CSI). In this case, for example, an optical deserializer may be implemented in the CSI host 1012, and an optical serializer may be implemented in the CSI device 1041.

The DSI host 1011 implemented in the application processor 1010 can communicate with the DSI device 1051 of the display 1050 through a display serial interface (DSI). In this case, for example, an optical serializer may be implemented in the DSI host 1011, and an optical deserializer may be implemented in the DSI device 1051.

The electronic system 1000 may further include an RF chip 1060 that can communicate with the application processor 1010. The PHY 1013 of the electronic system 1000 and the PHY 1061 of the RF chip 1060 may exchange data according to the MIPI DigRF.

The electronic system 1000 may further include a GPS 1020, a storage 1070, a microphone 1080, a DRAM 1085, and a speaker 1090, wherein the electronic system 1000 includes a Wimax 1030, a WLAN. 1100 and UWB 1110 may be used for communication.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

1: object 10: depth sensor
20 semiconductor integrated circuit 24 row decoder
26: timing controller 28: photo gate controller
30: light source driver 32: light source
34 lens module 36 logic circuit
40: cell array 100, 200: unit pixel
121, 122: charge collection region
130, 140: photogate
131a, 131b, 131c, 131d, 131e, 141a, 141b, 141c, 141d, 141e: fingergate
133 and 143: junction gates 137 and 147: contacts
151, 161: transmission gates 153, 163: floating diffusion region
170, 180: output unit
210: Barrier
220: photogate 230: charge collection region
261 and 262: transmission gates 251 and 252: floating diffusion region
400: Image Processing System

Claims (10)

A semiconductor substrate;
A junction gate disposed proximately on the semiconductor substrate and extending in a first direction; And two photogates including a plurality of finger gates extending in parallel from each other in a second direction perpendicular to the first direction from the junction gate.
Two charge collection regions disposed under each of the photo gates to collect charges generated in the semiconductor substrate;
Two transfer gates connected to the ends of the photo gates; And
Two floating diffusion regions connected to each of the transfer gates to receive the charges collected in the charge collection region in response to a transfer control signal;
Each of the finger gates is disposed to be inserted between each other's finger gates,
Each of the charge collection regions is a unit pixel of a depth sensor, the threshold voltage gradually decreases closer to each of the junction gates in a second direction. A semiconductor substrate;
A photogate disposed close to the semiconductor substrate;
A charge collection region for collecting charges in the lower layer at an end thereof with respect to the photo gate;
Two transfer gates connected to the ends of the photo gates; And
Two floating diffusion regions connected to each of the transfer gates to receive the charges collected in the charge collection region in response to a transfer control signal;
The unit pixel of the depth sensor, the charge collection region is gradually reduced as the closer to the floating diffusion region in the longitudinal direction. The method of claim 2, wherein the charge collection region is
A unit pixel of a depth sensor having N multi-threshold voltages by injecting (N-1) impurities into the charge collection region to reduce the threshold voltage gradually using different (N-1) masks. The method of claim 2, wherein the charge collection region is
Adjust the thickness of the charge collection region to become thinner so that the threshold voltage gradually decreases,
Wherein said thickness is in unit pixels of a depth sensor in the range of 1 to 100 nm. The method of claim 2, wherein the charge collection region is
The unit pixel of the depth sensor, the path of the charge is formed narrower than the width of the charge collection region. A light source emitting the modulated first optical signal to the target object;
A lens module configured to receive a second optical signal reflected from the target object; And
A depth sensor comprising a pixel array in which a plurality of unit pixels of claim 2 are arranged, and sensing depth information using the first optical signal and a second optical signal incident to the pixel array through the lens module. A depth sensor including a pixel array in which a plurality of unit pixels of claim 2 are arranged and sensing depth information from the pixel array using an optical flight time; And
And an image processor configured to process the depth information to generate an image. Forming a photo gate and a floating diffusion region over the semiconductor substrate;
Forming a charge collection region under the photo gate in the semiconductor substrate; And
And making the threshold voltage lower as the charge collection region approaches the floating diffusion region. The method of claim 8, wherein the step of making the threshold voltage lower
Fabrication of a unit pixel of a depth sensor that implements N multi-threshold voltages by injecting (N-1) impurities into the charge collection region gradually by using different (N-1) masks to respectively reduce the threshold voltages Way. The method of claim 8, wherein the step of making the threshold voltage lower
As the proximity to the floating diffusion region increases, the thickness of the charge collection region becomes thinner and thinner.
And the thickness is in the range of 1 to 100 nm.
KR1020110063786A 2011-06-29 2011-06-29 A unit pixel of depth sensor, 3d image sensor including the unit pixel and method of the same KR20130007121A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150094297A (en) * 2014-02-11 2015-08-19 에스케이하이닉스 주식회사 Nonvolatile memory device
US9240512B2 (en) 2013-10-31 2016-01-19 Samsung Electronics Co., Ltd. Image sensors having transfer gate electrodes in trench
US9762890B2 (en) 2013-11-08 2017-09-12 Samsung Electronics Co., Ltd. Distance sensor and image processing system including the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9240512B2 (en) 2013-10-31 2016-01-19 Samsung Electronics Co., Ltd. Image sensors having transfer gate electrodes in trench
US9762890B2 (en) 2013-11-08 2017-09-12 Samsung Electronics Co., Ltd. Distance sensor and image processing system including the same
US9805476B2 (en) 2013-11-08 2017-10-31 Samsung Electronics Co., Ltd. Distance sensor and image processing system including the same
KR20150094297A (en) * 2014-02-11 2015-08-19 에스케이하이닉스 주식회사 Nonvolatile memory device

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