JP7516203B2 - SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING SYSTEM - Google Patents

Description

This disclosure relates to a substrate processing method and a substrate processing system.

Patent Document 1 discloses a processing system that includes a reduced pressure processing device, a structure discrimination device, and a system control device. The reduced pressure processing device performs an etching process on a wafer using a resist pattern as a mask. The structure discrimination device measures the dimensions of the pattern structure on the wafer surface before the etching process using a scatterometry method. The system control device stores correlation data between the processing conditions during the etching process and the amount of removal of the pattern structure on the wafer surface due to the etching process. Then, based on the measurement results of the dimensions of the pattern structure on the wafer surface and the correlation data, the system control device sets the processing conditions during the etching process so that the pattern structure on the wafer surface after the etching process has the desired dimensions.

JP 2011-86965 A

The technology disclosed herein makes it possible to appropriately set processing conditions for a substrate having a laminated film.

One aspect of the present disclosure is a substrate processing method that includes the steps of: generating, for each layer constituting a laminate film on a substrate, an image of the substrate after processing for that layer; and acquiring information indicating feature amounts estimated based on the image for each of a plurality of layers, including the outermost layer, of the laminate film on the substrate.

This disclosure makes it possible to appropriately set processing conditions for substrates having laminated films.

1 is a diagram illustrating a schematic configuration of a substrate processing system according to a first embodiment. FIG. 2 is a diagram illustrating a wafer to be processed. 2 is a diagram illustrating a film formed on a wafer to be processed by the coating and developing apparatus. FIG. 2 is a diagram showing a schematic diagram of a resist pattern formed on a wafer to be processed by a coating and developing apparatus; 2 is a vertical cross-sectional view showing a schematic configuration of an imaging module included in the coating and developing apparatus; FIG. 2 is a cross-sectional view showing a schematic outline of the configuration of an imaging module provided in the coating and developing apparatus; FIG. 2A to 2C are diagrams illustrating the state of a wafer after various etching processes performed by an etching apparatus included in the substrate processing system. FIG. 2 is a diagram for explaining a captured image of a wafer. 2 is a flowchart illustrating an example of a process during mass production in the processing system of FIG. 1 . FIG. 11 is a diagram illustrating a schematic configuration of a substrate processing system according to a second embodiment. FIG. 13 is a diagram illustrating a schematic configuration of a substrate processing system according to a third embodiment.

In the manufacturing process of semiconductor devices, etc., predetermined processes are performed to form a resist pattern on a semiconductor wafer (hereinafter sometimes referred to as "wafer"). The above-mentioned predetermined processes include, for example, a resist coating process in which a resist liquid is supplied onto the wafer to form a resist film, an exposure process in which the resist film is exposed to a predetermined pattern, a PEB process in which a chemical reaction in the resist film is promoted after exposure, and a development process in which the exposed resist film is developed. Then, after forming the resist pattern, etching is performed using this resist pattern as a mask. In addition, when forming the resist pattern, a film other than the resist film, such as an undercoat film for the resist film, may be formed on the wafer to form a laminated film.

However, since etching using a resist pattern as a mask is affected by the shape of the resist pattern, conventionally, the dimensions of the pattern structure on the wafer surface are evaluated before the etching process, and the processing conditions for the etching process are set based on the evaluation results.

For example, in the processing system disclosed in Patent Document 1, the dimensions of the pattern structure on the wafer surface before the etching process are measured using a scatterometry method. In addition, in the above processing system, correlation data between the processing conditions during the etching process and the amount of removal of the pattern structure on the wafer surface due to the etching process is obtained in advance. Then, based on the measurement results of the dimensions of the pattern structure on the wafer surface and the correlation data, the processing conditions during the etching process are set so that the pattern structure on the wafer surface after the etching process has the desired dimensions.

However, when a laminated film including a resist film is formed on the film to be etched on the wafer, the thickness of films other than the resist film may affect the etching process using the resist pattern as a mask. Specifically, for example, when an undercoat film is formed in addition to the resist film, the thickness of the undercoat film may affect the results of the etching process using the resist pattern as a mask.

Therefore, the technology disclosed herein makes it possible to appropriately set processing conditions for a substrate having a laminated film.

The substrate processing method and substrate processing system according to this embodiment will be described below with reference to the drawings. Note that in this specification and the drawings, elements having substantially the same functional configurations are designated by the same reference numerals, and duplicated descriptions will be omitted.

First Embodiment
FIG. 1 is a diagram showing a schematic overview of the configuration of a substrate processing system according to a first embodiment. FIG. 2 is a diagram showing a wafer to be processed. FIG. 3 is a diagram showing a film formed on a wafer to be processed by a coating and developing apparatus. FIG. 4 is a diagram showing a resist pattern formed on a wafer to be processed by a coating and developing apparatus. FIG. 5 and FIG. 6 are vertical and horizontal cross-sectional views showing a schematic overview of the configuration of an imaging module included in the coating and developing apparatus, respectively. FIG. 7 is a diagram showing a schematic view of the state of a wafer after various etchings by an etching apparatus included in the substrate processing system. FIG. 8 is a diagram for explaining an imaged image described later.

As shown in FIG. 1, processing system 1, which serves as a substrate processing system, includes a coating and developing apparatus 2 and an etching apparatus 3, which serve as semiconductor manufacturing equipment. Although not shown in the figure, the coating and developing apparatus 2 and the etching apparatus 3 are provided with a cassette station and a wafer transport mechanism. The cassette station is where cassettes containing multiple wafers are loaded and unloaded. The wafer transport mechanism is used to transport wafers between the cassette station and various modules, and between various modules.

The coating and developing apparatus 2 forms a laminated film including a resist film on a wafer and develops the resist film after exposure. In the following explanation, the wafer W to be processed and loaded into the coating and developing apparatus 2 is assumed to have an oxide film F1, a TiN film F2, and a low-temperature oxide (LTO) film F3 laminated in that order from the bottom on a base wafer W1, as shown in FIG. 2, and the LTO film F3 is patterned to form an LTO pattern.

The coating and developing apparatus 2 has an underlayer film forming module 11, an intermediate layer film forming module 12, a resist film forming module 13, and a developing module 14 in order to stack a film on the wafer W (specifically, for example, on the LTO film F3) and to process the stacked film that has been formed. These modules 11 to 14 are spin coating modules that apply a processing liquid to the wafer W by a spin coating method. In the spin coating method, for example, a processing liquid is ejected onto the wafer W from a coating nozzle (not shown), and the wafer W is rotated to diffuse the processing liquid onto the surface of the wafer W. The underlayer film forming module 11, the intermediate layer film forming module 12, the resist film forming module 13, and the developing module 14 can be configured as known in the art.

The underlayer film forming module 11 applies an underlayer film material as a processing liquid onto the wafer W to form an underlayer film that is a base film for the resist film. Specifically, the underlayer film forming module 11 forms an SOC (spin-on carbon) film F4 as an underlayer film on the LTO film F3 (LTO pattern) of the wafer W, for example, as shown in FIG. 3.

The intermediate layer film forming module 12 applies an intermediate layer film forming material as a processing liquid onto the wafer W to form an intermediate layer film that is a base film for the resist film. Specifically, the intermediate layer film forming module 12 forms an SOG (spin-on-glass) film F5 as an intermediate layer film on the SOC film F4 film of the wafer W, for example, as shown in FIG. 3.

The resist film forming module 13 applies a resist liquid as a processing liquid onto the wafer W to form a resist film. Specifically, the resist film forming module 13 forms a resist film F6 on the SOG film F5 of the wafer W, for example, as shown in FIG. 3.

The developing module 14 applies a developing solution as a processing solution onto the wafer W and develops the wafer W. Specifically, the developing module 14 develops the resist film F6 exposed by an exposure device (not shown) integrally connected to the coating and developing apparatus 2, for example, to form a resist pattern P1 on the wafer W as shown in FIG. 4.

As shown in FIG. 1, the coating and developing apparatus 2 also has a heat treatment module 21 that uses a hot plate on which the wafer W is placed to perform heat treatment of the wafer W. The heat treatment module 21 is used, for example, after the formation of the SOC film F4, after the formation of the SOG film F5, after the formation of the resist film F6 and before exposure, after exposure and before development, and after development. Note that, although the figure shows one heat treatment module 21, the coating and developing apparatus 2 is provided with multiple heat treatment modules 21, and different heat treatment modules 21 are used depending on the application. A known configuration can be used for the heat treatment module 21.

Furthermore, the coating and developing apparatus 2 is provided with first to fifth imaging modules 31 ₁ to 31 ₅ (hereinafter, sometimes collectively referred to as "imaging modules 31"). The imaging modules 31 can use the imaging results for wafer inspection, but in this embodiment, as will be described later, the imaging results are used to estimate feature quantities of each layer (each film) of a film stack on the wafer W.

The first imaging module 31 ₁ is used to capture an image of the wafer W before the lower layer film formation process by the lower layer film formation module 11 .
The second imaging module 31 ₂ is used to image the wafer W after the lower layer film formation process and before the intermediate layer film formation process by the intermediate layer film formation module 12 .
The third imaging module ₃₁₃ is used to capture an image of the wafer W after the intermediate layer film forming process and before the resist film forming process by the resist film forming module 13 .
The fourth imaging module ₃₁₄ is used to capture an image of the wafer W after the resist film forming process and before the exposure process.
The fifth imaging module ₃₁₅ is used to capture an image of the wafer W after the development process.

The first imaging module _31-1 has a casing 200, as shown in Figs. 5 and 6. A mounting table 201 on which a wafer W is placed is provided inside the casing 200. The mounting table 201 can be rotated and stopped freely by a rotation drive unit 202 such as a motor. A guide rail 203 is provided on the bottom surface of the casing 200, and extends from one end side (the negative X-direction side in Fig. 6) to the other end side (the positive X-direction side in Fig. 6) inside the casing 200. The mounting table 201 and the rotation drive unit 202 are provided on the guide rail 203, and can be moved along the guide rail 203 by a drive device 204.

An imaging unit 210 is provided on the side of the other end of the casing 200 (the positive X-direction side in FIG. 6). The imaging unit 210 uses, for example, a line sensor camera as a camera.

A half mirror 211 is provided near the center of the top of the casing 200. The half mirror 211 is provided in a position facing the imaging unit 210, with the mirror surface tilted 45 degrees upward toward the imaging unit 210 from a state in which the mirror surface faces vertically downward. An illumination unit 212 is provided above the half mirror 211 as a light source. The half mirror 211 and the illumination unit 212 are fixed to the upper surface inside the casing 100. Illumination from the illumination unit 212 passes through the half mirror 211 and is illuminated downward. Therefore, light reflected by an object below the illumination unit 212 is further reflected by the half mirror 211 and taken in by the imaging unit 210. That is, the imaging unit 210 can capture an image of an object in the area illuminated by the illumination unit 212.

The first imaging module ₃₁₁ moves the wafer W in one direction (X direction in FIG. 6 ) along the guide rail, and captures an image of the surface of the wafer W by scanning the surface with a line sensor camera of the imaging unit 210 having a long imaging field of view in a direction approximately perpendicular to the one direction.

The configurations of the second to fifth imaging modules 31 ₂ to 31 ₅ are substantially the same as the configuration of the first imaging module 31 ₁ described above.

As shown in FIG. 1 , the coating and developing apparatus 2 is provided with a control unit 41 .
The control unit 41 is, for example, a computer equipped with a CPU, a memory, and the like, and has a program storage unit (not shown). This program storage unit stores programs and the like for controlling the operation of the drive systems of the above-mentioned various modules and the transfer device (not shown), and for performing various processes on the wafer W. The above programs may be recorded in a computer-readable storage medium and installed from the storage medium into the control unit 41. A part or all of the programs may be realized by dedicated hardware (circuit board).

The control unit 41 has a memory unit 41a, an image generation unit 41b, and an estimation unit 41c. These will be described later.

The etching device 3 has an LTO film etching module 51, a TiN film etching module 52, and an oxide film etching module 53. These modules 51 to 53 are, for example, plasma-type dry etching modules.

The LTO film etching module 51 etches the LTO film F3 using the laminated film on the wafer W formed by the coating and developing apparatus 2 as a mask. As a result, as shown in Figures 4 and 7 (A), the resist pattern P1 is transferred to the LTO film F3, and an LTO film pattern P2 is formed.

The TiN film etching module 52 etches the TiN film F2 using the LTO film pattern P2 formed by the LTO film etching module 51 as a mask. As a result, as shown in Figures 7(A) and 7(B), the LTO film pattern P2 is transferred to the TiN film F2, and a TiN film pattern P3 is formed.

The oxide film etching module 53 etches the oxide film F1 using the TiN film pattern P3 formed by the TiN film etching module 52 as a mask. As a result, the TiN film pattern P3 is transferred to the oxide film F1, as shown in Figures 7(B) and 7(C).

As shown in FIG. 1, the processing system 1 further includes an overall control device 4 .
The overall control device 4 is, for example, a computer equipped with a CPU, memory, etc., and has a program storage unit (not shown). This program storage unit stores a program for creating a correlation model, which will be described later, etc. The above program may be recorded in a non-transitory computer-readable storage medium and installed from the storage medium into the overall control device 4. A part or all of the program may be realized by dedicated hardware (circuit board).
The overall control device 4 has a storage unit 61 , a model creation unit 62 , an acquisition unit 63 , a processing condition determination unit 64 , and a processing condition correction unit 65 .

Here, we will explain the memory unit 41a, image generation unit 41b, and estimation unit 41c of the control unit 41, and the memory unit 61, model creation unit 62, acquisition unit 63, processing condition determination unit 64, and processing condition correction unit 65 of the overall control device 4.

The memory unit 41a of the control unit 41 stores various information. For example, the memory unit 41a stores an estimation model (described below) created by the model creation unit 62 of the overall control device 4.

The image generating unit 41b generates an image of the wafer W based on the imaging result of the wafer W by the imaging unit 210 of the imaging module 31. For example, the image generating unit 41b divides the wafer W in the imaging result of the imaging unit 210 into 437 regions, and calculates the average value of the pixel values of R (red), G (green), and B (blue) in each region. Then, the image generating unit 41b creates a table that associates the coordinates of each region with the average value of the pixel values, i.e., the average value of the RGB data, for each of the above regions. In other words, the image generating unit 41b generates information that aggregates pixels at each position on the wafer surface (on the two-dimensional coordinate system). In addition, the image generating unit 41b calibrates the table to match the optical system in the imaging module 31. From the calibrated table, an image Im as shown in FIG. 8 can be generated. Hereinafter, the above-mentioned table acquired in the above-mentioned manner from the imaging result of the imaging unit 210 is referred to as a "captured image".

The image generating unit 41b generates a captured image of the wafer after processing related to each layer of the laminated film on the wafer W. The processing related to the layer is, for example, a forming process of the layer (such as a forming process of an intermediate layer film) or a developing process of the layer (such as a developing process of a resist film).
The captured images generated by the image generating unit 41b are basically stored for each wafer W in the storage unit 41a.

The estimation unit 41c estimates the feature amount of the mth layer (m is an integer of 1 or more) formed on the wafer W by the processing system 1 based on the pixel values in the captured image of the wafer W after the processing of the mth layer. This estimation is performed for each region constituting the captured image of the wafer W. For example, when the wafer W is divided into 437 regions as described above, the feature amount of the mth layer is estimated for each of the 437 regions in the captured image of the wafer W after the processing of the mth layer based on the pixel values of the region. The feature amount of the mth layer is, for example, a feature related to the shape of the mth layer, and specifically, the thickness of the mth layer, the line width of the mth layer, and other dimensions. The in-plane distribution of the feature amount is obtained by combining the estimation result of the feature amount for each region and the position information of each region. Specifically, the estimation unit 41c estimates the in-plane distribution of the film thickness of the mth layer (distribution of thick and thin parts) and the in-plane distribution of the line width of the mth layer (distribution of thick and thin parts).
The estimation unit 41c estimates the feature amount for each region of all layers constituting the laminated film on the wafer W, for example.

When estimating the feature quantity of the outermost layer (i.e., the nth layer) of a laminate film consisting of n (n is an integer of 2 or more) layers, the estimation unit 41c acquires estimated feature quantities for at least the layers up to the n-1th layer for each region. Then, the estimation unit 41c estimates the feature quantity of the nth layer of the processed wafer for each region based on the acquisition results of the estimated feature quantities, pixel values in the captured image of the processed wafer W relating to the nth layer, an estimation model (described below) created in advance, and the like. The estimation model is created in advance using a wafer W for model creation (hereinafter, a preparation wafer W). The estimation model can be, for example,
(X) feature amounts for each of the layers up to the (n-1)th layer formed on the wafer (W) and pixel values in a captured image of the wafer (W) after processing for the nth layer;
(Y) a feature amount of the n-th layer of the wafer W after the above processing; and
This is a model showing the correlation between

The feature amounts estimated by the estimation unit 41c (hereinafter referred to as "estimated feature amounts") are stored for each wafer W in the memory unit 41a.

The storage unit 61 of the overall control device 4 stores various information. For example, the storage unit 61 stores information used when the model creation unit 62 creates the above-mentioned estimation model.

The model creation unit 62 creates the above-mentioned estimation model in advance for each type of film (layer) feature amount. For example, the model creation unit 62 specifically creates an estimation model in advance for each of the thickness of the underlayer film, the thickness of the intermediate layer film, the thickness of the resist film, and the line width of the resist pattern. The details of this creation method will be described later.
The estimation model created by the model creation unit 62 is stored in the storage unit 61, and is also sent to the coating and developing apparatus 2 and stored in the storage unit 41a.

The acquisition unit 63 acquires information used for determining process conditions in the process condition determination unit 64 and for correcting process conditions in the process condition correction unit 65. Specifically, the acquisition unit 63 acquires from the coating and developing apparatus 2 the feature amounts (in-plane distribution) of each of a plurality of layers including the outermost layer of the laminated film on the wafer W, which are estimated based on the captured image by the estimation unit 41c of the coating and developing apparatus 2. For example, the acquisition unit 63 acquires the in-plane distribution of the estimated feature amounts from the coating and developing apparatus 2 for each of all layers of the laminated film on the wafer W.

The processing condition determination unit 64 determines processing conditions for downstream processes based on the results acquired by the acquisition unit 63, i.e., based on the estimated feature quantities for each layer of the laminated film formed on the wafer W. Specifically, the processing condition determination unit 64 determines the etching processing conditions in the etching device 3 for the wafer W on which the laminated film is formed, based on the estimated feature quantities for each layer of the laminated film formed on the wafer W.

The process condition correction unit 65 corrects the process conditions of the film formation process and development process for the layers constituting the laminated film on the wafer W based on the results acquired by the acquisition unit 63, i.e., based on the estimated feature quantities for each layer of the laminated film formed on the wafer W.

Next, we will explain an example of how to create an estimation model.

(1. Initial State Imaging Step)
When creating an estimation model, first, an image of the preparation wafer W before various films such as an underlayer film are formed, i.e., in an initial state, is captured in the coating and developing apparatus 2, and the captured image is generated.
Specifically, for example, the surface of the preparation wafer W in an initial state is imaged by the imaging unit 210 of the first imaging module _31-1 . Then, the image generating unit 41b generates an image of the preparation wafer W in the initial state (hereinafter, sometimes referred to as an "initial state image") based on the imaging result by the imaging unit 210. The generated image is sent to the overall control device 4 and stored in the storage unit 61 for each wafer W.
The preparation wafer W is, for example, a production wafer used in mass production of semiconductor devices, that is, when forming resist patterns on a mass production basis, and has a pattern formed on the wafer surface in the same manner as in FIG.

(2. Lower layer film formation process)
After the initial state imaging step, an underlayer film is formed on the preparation wafer W. Specifically, an SOC film is formed on the preparation wafer W under predetermined processing conditions by the underlayer film forming module 11. The preparation wafer W is heat-treated under predetermined processing conditions by the heat treatment module 21 for the SOC film.

(3. Imaging process after forming underlayer film)
Next, an image of the preparation wafer W on which the underlayer film is formed is captured, and a captured image of the preparation wafer W is generated.
Specifically, for example, the surface of the preparation wafer W after the formation of the SOC film as the underlayer film is imaged by the imaging unit 210 of the second imaging module _312. Then, the image generating unit 41b generates an image of the preparation wafer W after the formation of the underlayer film (hereinafter, sometimes referred to as an "image captured after the formation of the underlayer film") based on the imaging result by the imaging unit 210. The generated image is sent to the overall control device 4 and stored in the memory unit 61 for each wafer W.

(4. Underlayer Film Thickness Measurement Process)
Next, the thickness of the underlayer film formed on the preparation wafer W is measured by a film thickness measuring device (not shown) provided outside the processing system 1 .
At this time, for example, the preparation wafer W is divided into 437 regions, the same as the number of divided regions in the captured image, and the film thickness of the underlying film on each region is measured.
The measurement results are input to the overall control device 4 and stored in the storage unit 61 for each wafer W. As the film thickness measuring device, for example, a film thickness meter using a reflection spectroscopy method or the like is used.

(5. Intermediate layer film formation process)
After the film thickness measurement process of the lower layer film, the preparation wafer W is returned to the processing system 1, and an intermediate layer film is formed on the lower layer film of the preparation wafer W. Specifically, the intermediate layer film forming module 12 An SOG film is formed on the underlying film of the preparation wafer W under predetermined processing conditions, and then the preparation wafer W is heat-treated under the predetermined processing conditions by the heat treatment module 21 for the SOG film.

(6. Imaging process after intermediate layer film formation)
Next, an image of the preparation wafer W on which the intermediate layer film is formed is captured, and an image of the preparation wafer W is generated.
Specifically, for example, the surface of the preparation wafer W after the formation of an SOG film as an intermediate layer film is imaged by the imaging unit 210 of the third imaging module _313. Then, the image generating unit 41b generates an image of the preparation wafer W after the formation of the intermediate layer film (hereinafter, sometimes referred to as an "image captured after the formation of the intermediate layer film") based on the imaging result by the imaging unit 210. The generated image is sent to the overall control device 4 and stored in the memory unit 61 for each wafer W.

(7. Intermediate layer film thickness measurement process)
Next, the thickness of the intermediate film formed on the preparation wafer W is measured by a film thickness measuring device (not shown) provided outside the processing system 1, similar to the film thickness measuring process of the lower film.
The measurement results of the thickness of the intermediate layer film are input to the overall controller 4 and stored for each wafer W in the memory unit 61 .

(8. Resist film forming process)
After the film thickness measurement process of the intermediate layer film, the preparation wafer W is returned to the processing system 1, and a resist film is formed on the intermediate layer film of the preparation wafer W. Specifically, a resist film is formed on the intermediate layer film of the preparation wafer W under predetermined processing conditions by the resist film forming module 13, and then the PAB processing is performed on the preparation wafer W under predetermined processing conditions by the heat treatment module 21 for the PAB processing.

(9. Imaging process after resist film formation)
Next, an image of the preparation wafer W on which the resist film is formed is captured, and a captured image of the preparation wafer W is generated.
Specifically, for example, the surface of the preparation wafer W after the resist film has been formed is imaged by the imaging unit 210 of the fourth imaging module _314. Then, the image generating unit 41b generates an image of the preparation wafer W after the resist film has been formed (hereinafter, may be referred to as an "image after the resist film has been formed") based on the imaging result by the imaging unit 210. The generated image is sent to the overall control device 4 and stored in the memory unit 61 for each wafer W.

(10. Resist Film Thickness Measurement Process)
Next, the thickness of the resist film formed on the preparation wafer W is measured by a film thickness measuring device (not shown) provided outside the processing system 1, similar to the film thickness measuring process of the underlayer film.
The measurement results of the thickness of the resist film are input to the overall controller 4 and stored for each wafer W in the memory unit 61 .

(11. Exposure process)
After the resist film thickness measurement process, an exposure process is performed on the preparation wafer W in an exposure device integrally connected to the coating and developing apparatus 2. As a result, the resist film on the preparation wafer W is exposed to light in a predetermined pattern.

(12. PEB process)
Thereafter, the preparation wafer W is subjected to a PEB process by the heat treatment module 21 for the PEB process under predetermined process conditions.

(13. Development process)
Next, a development process is performed on the preparation wafer W. Specifically, the development process is performed by the development module 14 under predetermined processing conditions, and a resist pattern is formed on the preparation wafer W.

(14. Post-Pattern Formation Imaging Process)
Next, an image of the preparation wafer W on which the resist pattern is formed is captured, and a captured image of the preparation wafer W is generated.
Specifically, for example, the surface of the preparation wafer W after the resist pattern has been formed is imaged by the imaging unit 210 of the fifth imaging module _315. Then, the image generating section 41b generates an image of the preparation wafer W after the resist pattern has been formed (hereinafter, may be referred to as a "post-pattern-formation image") based on the imaging result by the imaging unit 210. The generated image is sent to the overall control device 4 and stored in the memory section 61 for each wafer W.

(15. Resist Pattern Line Width Measurement Process)
Next, the line width of the resist pattern formed on the preparation wafer W is measured by a line width measuring device (not shown) provided outside the processing system 1 .
At this time, for example, the preparation wafer W is divided into 437 regions, the same as the number of divided regions in the captured image, and in each region, the line width of the resist pattern on that region is measured.
The measurement results are input to the overall control device 4 and stored in the storage unit 61 for each wafer W. As the line width measuring device, for example, a SEM (Scanning Electron Microscope) is used.

The above steps 1. Initial state imaging step to 15. Resist pattern line width actual measurement step are performed for each of the multiple preparation wafers W. The processing conditions may be intentionally made different between the preparation wafers W so that the thickness of each film on the preparation wafer W and the line width of the resist pattern differ between the preparation wafers W. In other words, in order to create an estimation model, the preparation wafers W may be processed under multiple processing conditions that differ from one another for each layer.

(16. Process for creating an estimation model of the thickness of the underlayer film)
Then, an estimated model of the thickness of the underlayer film is created based on the initial state image, the measurement results of the thickness of the underlayer film formed on the preparation wafer W by a film thickness measuring device, and the image taken after the underlayer film is formed.
Specifically, for example, the model creation unit 62 of the overall control device 4 creates an estimation model of the film thickness of the lower layer film, which shows the correlation between the following information (A1) to (A3), from the following information (a1) to (a3):

(a1) pixel values in an image captured in an initial state of each of the 437 regions of the preparation wafer W; (a2) pixel values in an image captured after formation of an underlayer film of each of the 437 regions of the preparation wafer W; (a3) measurement results of the thickness of the underlayer film by a film thickness gauge of each of the 437 regions of the preparation wafer W.

(A1) Pixel value in a captured image of the wafer W in an initial state. (A2) Pixel value in a captured image of the wafer W after the underlayer film is formed. (A3) Thickness of the underlayer film on the wafer W.

In addition, in cases where the production wafers are bare wafers, an estimation model of the thickness of the underlayer film showing the correlation between (A2) to (A3) above may be created from the information in (a2) to (a3) above. In this case, the initial state image is not required to create the estimation model.

(Step of creating an estimation model of the thickness of the intermediate layer film)
In addition, an estimation model for the thickness of the intermediate layer film is created based on the measurement results of the thickness of the intermediate layer film and the thickness of the underlayer film formed on the preparation wafer W by a film thickness measuring device and an image taken after the intermediate layer film is formed.
Specifically, for example, the model creation unit 62 of the overall control device 4 creates an estimation model of the thickness of the intermediate layer film, which shows the correlation between the following (B1) to (B3), from the following information (b1) to (b3) for each of the above-mentioned 437 regions of the preparation wafer W.

(b1) Measurement result of thickness of the underlayer film by a film thickness gauge. (b2) Pixel value in an image captured after forming the intermediate layer film. (b3) Measurement result of thickness of the intermediate layer film by a film thickness gauge.

(B1) Thickness of the underlayer film (B2) Pixel value in the captured image of the wafer W after the intermediate layer film is formed (B3) Thickness of the intermediate layer film

(Process for creating an estimation model of resist film thickness)
Furthermore, an estimation model of the thickness of the resist film is created based on the measurement results of the thickness of the resist film, the thickness of the intermediate layer film, and the thickness of the underlayer film formed on the preparation wafer W by a film thickness measuring device, and on the image captured after the resist film is formed.
Specifically, for example, the model creation unit 62 of the overall control device 4 creates an estimation model of the film thickness of the underlying film, which shows the correlation between the following (C1) to (C4), from the following information (c1) to (c4) for each of the above-mentioned 437 regions of the preparation wafer W.

(c1) Measurement result of thickness of underlayer film by film thickness gauge. (c2) Measurement result of thickness of intermediate layer film by film thickness gauge. (c3) Pixel value in image captured after resist film formation. (c4) Measurement result of thickness of resist film by film thickness gauge.

(C1) Thickness of the underlayer film (C2) Thickness of the intermediate layer film (C3) Pixel value in the captured image of the wafer W after the resist layer film is formed (C4) Thickness of the resist film

(Process for creating an estimation model of the line width of a resist pattern)
Furthermore, an estimated model of the line width of the resist pattern formed on the preparation wafer W is created based on the measurement results of the line width of the resist pattern formed on the preparation wafer W by a line width measuring device, the measurement results of the thickness of the resist film, the thickness of the intermediate layer film, and the thickness of the underlayer film formed on the preparation wafer W by a film thickness measuring device, and the image captured after the pattern is formed.
Specifically, for example, the model creation unit 62 of the overall control device 4 creates an estimated model of the line width of the resist pattern, which shows the correlation among the following (D1) to (D5), from the following information (d1) to (d5) for each of the above-mentioned 437 regions of the preparation wafer W.

(d1) Measurement result of the thickness of the underlayer film by a film thickness gauge; (d2) Measurement result of the thickness of the intermediate layer film by a film thickness gauge; (d3) Measurement result of the thickness of the resist film by a film thickness gauge; (d4) Pixel value in the image captured after pattern formation; (d5) Measurement result of the line width of the resist pattern by a line width gauge.

(D1) Thickness of the underlayer film (D2) Thickness of the intermediate layer film (D3) Thickness of the resist film (D4) Pixel value in the captured image of the wafer W after the resist pattern is formed (D5) Line width of the resist pattern

In this manner, each estimation model is created in advance before mass-production processing is performed in the processing system 1. Each estimation model created in advance is sent to the coating and developing apparatus 2 and stored in the memory unit 41a.

Next, we will explain the processing during mass production in the processing system 1. Figure 9 is a flowchart that explains an example of the processing during mass production in the processing system 1.

During mass production in the processing system 1, for example, as shown in FIG. 9, a process of stacking a film on a wafer W and forming a resist pattern (step S1) and a process of generating an image of the wafer W (step S2) are performed in parallel.
Specifically, the wafer W undergoes the same processes as the above-mentioned 1. initial state imaging process, 2. underlayer film forming process, 3. underlayer film formation post-imaging process, 5. intermediate layer film forming process, 6. intermediate layer film formation post-imaging process, 8. resist film forming process, 9 resist film formation post-imaging process, 11. exposure process, 12. PEB process, 13. development process, and 14. pattern formation post-imaging process. As a result, the underlayer film, intermediate layer film, and resist film are stacked on the wafer W, and then the resist film is developed to form a resist pattern. Furthermore, the image generating unit 41b generates an image of the wafer W in the initial state, an image of the wafer W after the underlayer film is formed, an image of the wafer W after the intermediate layer film is formed, an image of the wafer W after the resist film is formed, and an image of the wafer W after the resist pattern is formed. The generated images are stored in the memory unit 41a for each wafer W.

During mass production, for example, a process of estimating the thickness of the underlayer film (step S3), a process of estimating the thickness of the second and subsequent layers (intermediate layer and resist film) (step S4), and a process of estimating the line width of the resist pattern (step S5) are performed. Each estimation result is stored for each wafer W in the memory unit 41a.

In the process of estimating the thickness of the underlayer film in step S3, for example, the estimation unit 41c estimates the thickness of the underlayer film based on the captured image of the wafer W in the initial state, the captured image of the wafer W after the underlayer film has been formed, and the estimation model of the thickness of the underlayer film stored in the memory unit 41a. Specifically, for each of the above-mentioned 437 regions of the wafer W, the thickness of the underlayer film is estimated based on the pixel values in the captured image of the wafer W in the initial state, the pixel values in the captured image of the wafer W after the underlayer film has been formed, and the estimation model of the thickness of the underlayer film. That is, the in-plane distribution of the thickness of the underlayer film is estimated. Note that if the initial state captured image is not used when creating the estimation model of the thickness of the underlayer film, the pixel values of the captured image of the wafer W in the initial state are not used to estimate the thickness of the underlayer film.

In the process of estimating the thickness of the second and subsequent layers (intermediate layer and resist film) in step S4, for example, the estimation unit 41c first acquires from the memory unit 41a the in-plane distribution of the estimated thickness for the layer located below the outermost layer of the laminate film whose film thickness is to be estimated. When estimating the thickness of the intermediate layer film, for example, the in-plane distribution of the estimated thickness of the lower layer film is acquired from the memory unit 41a, and when estimating the thickness of the resist film, the in-plane distribution of the estimated thicknesses of the lower layer film and intermediate layer film is acquired from the memory unit 41a.
Then, the estimation unit 41c estimates the thickness of the outermost layer based on the estimated thickness acquisition result, an image of the wafer W on which the outermost layer of the laminated film to be estimated is formed, and an estimation model corresponding to the outermost layer.
For example, the thickness of the intermediate layer film is estimated based on the in-plane distribution of the estimated thickness of the underlayer film, the captured image of the wafer W after the intermediate layer film is formed, and the estimation model of the thickness of the intermediate layer film. Specifically, for each of the above-mentioned 437 regions of the wafer W, the thickness of the intermediate layer film is estimated based on the estimated thickness of the underlayer film, the pixel value in the captured image of the wafer W after the intermediate layer film is formed, and the estimation model of the thickness of the intermediate layer film. That is, the in-plane distribution of the thickness of the intermediate layer film is estimated. Also, the thickness of the resist film is estimated based on the in-plane distribution of the estimated thickness of the underlayer film and the intermediate layer film, the captured image of the wafer W after the resist film is formed, and the estimation model of the thickness of the resist film. Specifically, for each of the above-mentioned 437 regions of the wafer W, the thickness of the resist film is estimated based on the estimated thickness of the underlayer film and the intermediate layer film, the pixel value in the captured image of the wafer W after the resist film is formed, and the estimation model of the thickness of the resist film. That is, the in-plane distribution of the thickness of the resist film is estimated.

In the process of estimating the line width of the resist pattern in step S5, for example, first, the estimation unit 41c acquires from the memory unit 41a the in-plane distribution of the estimated thickness for each layer including the outermost layer of the laminated film on the wafer W before development. Specifically, the in-plane distribution of the estimated thicknesses of the underlayer film, the intermediate layer film, and the resist film (before development) is acquired from the memory unit 41a.
Then, the estimation unit 41c estimates the line width based on the in-plane distribution of the estimated thicknesses of the underlayer film, the intermediate layer film, and the resist film acquired, the captured image of the wafer W after the resist pattern is formed, and the estimated model of the line width of the resist pattern. Specifically, for each of the above-mentioned 437 regions of the wafer W, the line width of the resist pattern is estimated based on the estimated thicknesses of the underlayer film, the intermediate layer film, and the resist film, the pixel value in the captured image of the wafer W after the resist pattern is formed, and the estimated model of the line width of the resist pattern. That is, the in-plane distribution of the line width of the resist pattern is estimated.

When the estimation of each characteristic amount is completed, a step of determining etching processing conditions (step S6) is performed.
In this process, for example, first, the acquisition unit 63 acquires from the coating and developing apparatus 2 the in-plane distribution of the estimated line width of the resist pattern formed on the wafer W by the coating and developing apparatus 2 and the in-plane distribution of the estimated thickness of the intermediate layer film.
Then, the process condition determination unit 64 determines the etching process conditions for the etching device 3 based on the information acquired by the acquisition unit 63. For example, when the estimated line width of the resist pattern acquired by the acquisition unit 63 falls within a desired range over the entire surface of the wafer W, and the estimated thickness of the intermediate layer film acquired by the acquisition unit 63 is thinner than the desired thickness only on the outer periphery of the wafer, the process condition determination unit 64 determines the etching process conditions as follows. That is, In this case, the process condition determination unit 64 determines, that is, adjusts, the etching process conditions of the LTO film etching module 51 so that the etching amount per unit time in the LTO film etching module 51 is reduced only on the outer periphery of the wafer. The etching process conditions to be adjusted include the flow rate of the process gas used in etching, the temperature of the wafer, and the like. The adjusted etching process conditions are sent to a control unit (not shown) of the etching device 3.

Then, an etching process (step S7) is performed by the etching device 3.
In this step, etching by the LTO film etching module 51, etching by the TiN film etching module 52, and etching by the oxide film etching module 53 are performed in sequence under the control of a control unit (not shown) of the etcher 3. If the etching process conditions have been adjusted in step S6, the etching in the etcher 3 is performed under the adjusted etching process conditions.

Furthermore, a step of correcting the processing conditions in the coating and developing apparatus 2 (step S8) is performed.
In this process, for example, first, the acquisition unit 63 acquires the in-plane distribution of the estimated thickness of the resist film, the in-plane distribution of the estimated thickness of the intermediate layer film, and the in-plane distribution of the estimated thickness of the underlayer film formed on the wafer W by the coating and developing apparatus 2.
Then, the processing condition correction unit 65 corrects the processing conditions in the coating and developing apparatus 2 based on the results acquired by the acquisition unit 63. For example, when the laminated film consisting of the underlayer film, the intermediate layer film, and the resist film has a characteristic film thickness profile as a whole (for example, a profile in which the film thickness increases toward the center of the substrate or a profile in which the film thickness increases toward the outer periphery of the substrate), the processing condition correction unit 65 performs the correction as follows. That is, in this case, the processing condition correction unit 65 identifies a film having a film thickness profile similar to the characteristic film thickness profile among the underlayer film, the intermediate layer film, and the resist film based on the results acquired by the acquisition unit 63. The processing condition correction unit 65 corrects the processing conditions for the identified film, for example, the heat treatment conditions in the heat treatment module 21 for the film.

Each of the above steps is performed for each wafer W.

In the above, the information acquired by the acquisition unit 63 from the coating and developing apparatus 2 and used for determination by the processing condition determination unit 64 and correction by the processing condition correction unit 65 is information on the feature amount of each layer itself (specifically, its in-plane distribution). The information acquired by the acquisition unit 63 may be information indicating the feature amount of each layer, and for example, instead of or in addition to information on the feature amount itself (specifically, its in-plane distribution), information on pixel values in the captured image of the wafer W that correlate with the feature amount (specifically, its in-plane distribution) may be used.

As described above, the processing system 1 according to the present embodiment includes the coating and developing apparatus 2 and the like as a semiconductor manufacturing apparatus, and the imaging module 31. The processing system 1 also includes an image generating unit 41b that generates an image of each layer constituting the laminated film on the wafer W based on the imaging result of the imaging module 31 of the wafer W after processing of the layer. The processing system 1 also includes an acquisition unit 63 that acquires information indicating feature amounts estimated based on the captured images for each of a plurality of layers including the outermost layer of the laminated film on the wafer W. That is, in the present embodiment, the acquisition unit 63 acquires the results of processing performed on the wafer W for layers other than the outermost layer. Therefore, based on the acquisition result of the acquisition unit 63, it is possible to more appropriately set processing conditions for the wafer W having the laminated film, such as etching processing conditions, and to more appropriately correct the processing conditions in the coating and developing apparatus 2.
Furthermore, in this embodiment, since a captured image of the wafer W is used to estimate the feature quantities, the results of the processing performed on the wafer W can be obtained for layers other than the outermost layer without compromising throughput, compared to the case where the feature quantities are actually measured using a film thickness measuring instrument, a line width measuring instrument, or the like.

Furthermore, in this embodiment, the acquisition unit 63 acquires information indicating feature amounts estimated based on the captured images for each of a plurality of layers, including the outermost layer, of the laminated film on the wafer W, and the process condition correction unit 65 corrects the process conditions in the coating and developing apparatus 2 based on the acquired results. Therefore, the process condition correction unit 65 is able to grasp the feature amounts not only for the outermost layer but also for the lower layers of the laminated film, compare the states of each layer with each other, and comprehensively view the state, appropriately selecting the process for correcting the process conditions and determining the amount of correction.

In addition, in this embodiment, the configurations of the imaging modules 31 used to acquire each captured image are substantially identical to each other. Therefore, even without calibration for each imaging module 31, similar captured images can be obtained from the same subject, making it easy to estimate features based on the captured images.

Furthermore, in this embodiment, the imaging module 31 is provided separately for each layer constituting the laminated film formed on the wafer W, specifically, for each process related to that layer. Furthermore, each imaging module 31 has the same type of light source and camera, that is, the same type of imaging optical system. By capturing images of the surface of each layer using the same type of imaging optical system, the performance differences (e.g., accuracy and reproducibility) of the imaging results at each timing can be reduced and made uniform, and reliability can be maintained when the same model, i.e., correlation information, is applied.

In this embodiment, imaging of one layer constituting the laminated film on the wafer W by the imaging module 31 is performed in a time that does not exceed the time required for the exposure process. Specifically, the imaging is performed in a time that does not exceed the time from when the wafer W is loaded into an exposure device (not shown) to when the wafer W is unloaded from the exposure device after the exposure process is completed. This prevents the imaging from lengthening the time between the exposure process and the next exposure process, thereby preventing a decrease in throughput due to the imaging.

In this embodiment, the model creation unit 62, the acquisition unit 63, and the processing condition determination unit 64 are provided in the same control device. Alternatively, the model creation unit 62, the acquisition unit 63, and the processing condition determination unit 64 may be provided in separate control devices. In this case, when the information acquired by the acquisition unit 63 from the coating and developing apparatus 2 is information on pixel values in the captured image of the wafer W that correlates with the feature amount of each layer (specifically, its in-plane distribution), the acquisition unit 63 may also acquire correlation information indicating the correlation between the feature amount and the pixel value, i.e., an estimation model. In this way, for example, when the information acquired by the acquisition unit 63 from the coating and developing apparatus 2 is the in-plane distribution of the pixel values, when the pixel value shows an abnormal value, it is possible to determine whether the cause is a malfunction of the imaging module 31 or an inaccurate estimation model.

Second Embodiment
FIG. 10 is a diagram illustrating a schematic configuration of a substrate processing system according to the second embodiment.
A processing system 1 a as a substrate processing system according to this embodiment includes a coating/developing apparatus 2 a, an etching apparatus 3, an overall control apparatus 4, and in addition, a coating apparatus 5, as shown in the figure.

The coating and developing apparatus 2a omits the underlayer film formation module 11 of the coating and developing apparatus 2 in the first embodiment. The omitted underlayer film formation module 11 is provided in the coating apparatus 5. Therefore, the processing system 1a includes the coating and developing apparatus 2a as a semiconductor manufacturing apparatus having an intermediate layer film formation module 12 as a spin coating module, a resist film formation module 13, and a development module 14, and the coating apparatus 5 having the underlayer film formation module 11 as a spin coating module. In other words, the processing system 1a includes multiple semiconductor manufacturing apparatuses having spin coating modules.

Furthermore, in the coating and developing apparatus 2a, the second imaging module ₃₁₂ of the coating and developing apparatus 2 in the first embodiment is omitted.
Meanwhile, the coating apparatus 5 is provided with a first imaging module _71-1 and a second imaging module _71-2 (hereinafter, sometimes collectively referred to as imaging modules 71). The configuration of the imaging module 71 is substantially the same as that of the imaging module 31 of the coating and developing apparatus 2a. Having substantially the same configuration of the imaging modules means that similar imaging results are obtained when the same object is imaged.
The first imaging module 71 ₁ is used to capture an image of the wafer W before the underlayer film formation process by the underlayer film formation module 11 in the coating apparatus 5 .
The second imaging module ₇₁₂ is used to capture an image of the wafer W after the above-mentioned lower layer film forming process.

Furthermore, the coating device 5 has a heat treatment module 21 for heat treatment after formation of the SOC film F4 as the underlayer film.

Furthermore, the coating device 5 is provided with a control unit 81 .
The control unit 81 is, for example, a computer equipped with a CPU, a memory, and the like, and has a program storage unit (not shown). This program storage unit stores programs and the like for controlling the operation of a drive system such as various modules and a transfer device (not shown) to perform various processes on the wafer W. The above programs may be recorded in a computer-readable storage medium and installed from the storage medium into the control unit 81. A part or all of the programs may be realized by dedicated hardware (circuit board).

The control unit 81 includes a storage unit 81a, an image generating unit 81b, and an estimating unit 81c.
The storage unit 81a stores various types of information, such as an estimated model of the thickness of the lower layer film that is created in advance by the model creation unit 62 of the overall control device 4.

The image generating unit 81b generates an image of the wafer W based on the imaging result of the wafer W by the imaging unit 210 of the imaging module 71. Specifically, an image of the wafer W in an initial state and an image of the wafer W after the underlayer film is formed are generated.
The captured images generated by the image generating unit 81b are basically stored for each wafer W in the storage unit 81a.

The estimation unit 81c estimates the thickness of the underlayer film formed by the coating device 5 for each of the above-mentioned 437 regions of the wafer W, based on pixel values in a captured image of the wafer W in an initial state, pixel values in a captured image of the wafer W after the underlayer film has been formed, and a pre-generated estimation model of the thickness of the underlayer film. That is, the estimation unit 81c estimates the in-plane distribution of the thickness of the underlayer film formed by the coating device 5. The method of creating the estimation model is the same as in the first embodiment.
The feature amount estimated by the estimation unit 81c is stored for each wafer W in the storage unit 81a.

In addition, in this embodiment, when the estimation unit 41c of the coating and developing apparatus 2a estimates the in-plane distribution of the thickness of the intermediate layer, the in-plane distribution of the estimated thickness of the underlayer film used in the estimation is obtained, for example, from the coating apparatus 5. When the estimation unit 41c of the coating and developing apparatus 2a estimates the thickness of the resist film or the resist pattern, the in-plane distribution of the estimated thickness of the underlayer film used in the estimation is similarly obtained, for example, from the coating apparatus 5.

Furthermore, in this embodiment, when determining the etching processing conditions, if the in-plane distribution of the estimated thickness of the underlayer film is required, information on the in-plane distribution of the estimated thickness is acquired by the acquisition unit 63, for example, from the coating device 5.
In this embodiment, when the processing conditions in the coating and developing apparatus 2a or the coating apparatus 5 are corrected by the processing condition correction unit 65, if the in-plane distribution of the estimated thickness of the underlayer film is required, information on the in-plane distribution of the estimated thickness is similarly acquired by the acquisition unit 63, for example, from the coating apparatus 5.

Third Embodiment
FIG. 11 is a diagram illustrating a schematic configuration of a substrate processing system according to the third embodiment.
As shown in the figure, a processing system 1b as a substrate processing system in this embodiment includes a coating and developing apparatus 2, an etching apparatus 3, and an overall control apparatus 4, as well as film forming apparatuses 6a and 6b, imaging apparatuses 7a, 7b, 7c, and 7d, and a polishing apparatus 8.

The film forming apparatuses 6a, 6b, and 6c form the single layers that make up the laminated film by a deposition method such as CVD or ALD. The film forming apparatus 6a forms, for example, the TiN film F2 of FIG. 2 on the wafer W, and the film forming apparatus 6b forms, for example, the LTO film F3 of FIG. 2 on the wafer W. The film forming apparatus 6c forms, for example, a Cu film as a metal wiring layer on the wafer W in the state shown in FIG. 7(C) after etching by the etching apparatus 3.

The imaging devices 7a, 7b, 7c, and 7d each have an imaging module 91a, 91b, 91c, and 91 having substantially the same configuration as the imaging module 31, and are separate from semiconductor manufacturing equipment such as the film forming devices 6a, 6b, and 6c and the coating and developing device 2.
The imaging module 91a is used to capture an image of the wafer W before it is carried into the film forming apparatus 6a, that is, before the TiN film forming process is performed.
The imaging module 91b is used to capture an image of the wafer W after the TiN film formation process by the film formation device 6a and before the wafer W is loaded into the film formation device 6b.
The imaging module 91c is used to capture an image of the wafer W after the LTO film formation process by the film forming device 6b.
The imaging module 91d is used to capture an image of the wafer W after the Cu film formation process by the film formation device 6c.

Furthermore, the imaging devices 7b to 7d are provided with control units 101 to 103, respectively.
The control units 101, 102, and 103 have memory units 101a, 102a, and 103a similar to the memory units 41a and 81a of the control units 41 and 81, image generation units 101b, 102b, and 103b similar to the image generation units 41b and 81b, and estimation units 101c, 102c, and 103c similar to the estimation units 41c and 81c.

As with the estimation units 41c and 81c in the first and second embodiments, the estimation unit 101c estimates the thickness of the TiN film formed by the film forming device 6a, for example, for each of the above-mentioned 437 regions of the wafer W, from pixel values in a captured image of the wafer W before the TiN film formation process, pixel values in a captured image of the wafer W after the TiN film formation process, and a previously generated estimation model of the thickness of the TiN film. That is, the estimation unit 101c estimates the in-plane distribution of the thickness of the TiN film formed by the film forming device 6a.
Similarly, the estimation unit 102c estimates the thickness of the LTO film formed by the film forming apparatus 6b, for example, for each of the above-mentioned 437 regions of the wafer W, from the estimated thickness of the TIN film, the pixel values in the captured image of the wafer W after the LTO film has been formed, and a previously generated estimated model of the thickness of the LTO film.
Similarly, the estimation unit 103c estimates the thickness of the Cu film formed by the film forming apparatus 6c, for example, for each of the above-mentioned 437 regions of the wafer W, from pixel values in an image of the wafer W before the Cu film formation process and pixel values in an image of the wafer W after the Cu film formation process.
The method of creating the estimation models used in the estimation units 101c, 102c, and 103c is similar to the estimation model for the thickness of the lower layer film and the estimation model for the thickness of the intermediate layer film in the first embodiment.

The polishing device 8 removes unnecessary films by polishing the wafer W. For example, the polishing device 8 removes unnecessary portions of the Cu layer formed by the film forming device 6c.

In this embodiment, the acquisition unit 63 of the overall control device 4 also acquires information indicating the estimated thickness of the TiN film and information indicating the estimated thickness of the Cu film on the wafer W to be processed from the imaging devices 7b and 7c.
Then, the processing condition determination unit 64 determines the polishing processing conditions in the polishing apparatus 8 based on the information indicating the estimated thickness of the TiN film and the information indicating the estimated thickness of the Cu film of the processing target wafer W acquired by the acquisition unit 63. The polishing processing conditions include, for example, the polishing pressure and the polishing trajectory of the polishing pad.
For example, if the estimated thickness of the Cu film is uniform across the wafer and the estimated thickness of the TiN film only at the wafer edge is greater than the desired thickness, the Cu layer is likely to be scraped off at the wafer edge, so if the polishing pressure or polishing time is made uniform across the wafer, the thickness of the Cu layer after polishing will not be uniform across the wafer. Therefore, in the above case, the process condition determination unit 64 may, for example, set a high polishing pressure for the wafer center or adjust the polishing trajectory so that the polishing time at the wafer center is longer.
In this embodiment, the polishing process can be performed more appropriately.

In addition, in processing system 1b, an apparatus that estimates the characteristics of a processed wafer W may transmit the following information (A) and (B) to an apparatus that performs a similar estimation for a process downstream of the estimation target of the apparatus (for example, imaging apparatus 7b to imaging apparatus 7c, and imaging apparatus 7c to coating and developing apparatus 2).
(A) Correlation information, i.e., an estimation model, indicating the in-plane distribution of pixel values in the captured image of the wafer W used in the apparatus and the correlation between the pixel values and the above-mentioned feature. (B) The in-plane distribution of pixel values and the estimation model used in each apparatus that performs similar estimation for processing upstream of the estimation target of the apparatus. Furthermore, the in-plane distribution of pixel values in the captured image of the wafer W and the estimation model may be stored in association with the corresponding layer.

In this embodiment, the wafer W is imaged by imaging devices 7b to 7d after processing in the film forming devices 6a to 6c, and the captured image based on the image capture results is used to estimate the processing results in the film forming devices 6a to 6c. Similarly, the wafer W may be imaged by imaging devices after processing in the etching device 3 or polishing device 8, and the captured image based on the image capture results may be used to estimate the processing results in the etching device 3 or polishing device 8. The processing results in the etching device 3 are, for example, dimensions such as the line width of the pattern after etching, and the processing results in the polishing device 8 are, for example, the amount of Cu layer polished off.

In the above example, when estimating the feature amount for each region of the second and subsequent layers on the wafer W, the film thickness in each region of each layer was used as the feature amount of each layer on the wafer W before processing for the film to be estimated. However, the feature amount of each layer is not limited to this, and may be, for example, the in-plane average thickness of each layer.

In the above, when estimating the features of a laminated film on a wafer W formed by a semiconductor manufacturing apparatus having a spin coating module (coating and developing apparatus 2, 2a), only information indicating the estimated features of a layer processed by a semiconductor manufacturing apparatus having a spin coating module (coating and developing apparatus 2, 2a, coating apparatus 5) was used. However, when estimating the features of a laminated film on a wafer W formed by a semiconductor manufacturing apparatus having a spin coating module (coating and developing apparatus 2, 2a, coating apparatus 5), information indicating the estimated features of a layer formed by a CVD method or an ALD method in a process prior to the semiconductor manufacturing apparatus may be used. Information indicating the estimated features of a layer etched in a process prior to the semiconductor manufacturing apparatus may also be used.

In the above example, the processing condition determination unit 64 adjusts the processing conditions within the surface of the wafer W. However, in cases where the estimation results of the feature quantities differ between wafers or lots, the processing condition determination unit 64 may adjust the processing conditions for each wafer W or for each lot.
Similarly, in cases where the estimation results of the feature quantities differ between wafers or lots, the process condition correction unit 65 may correct the process conditions for each wafer W or each lot.

In the above example, when estimating the feature amount of the second or subsequent layer film on the wafer W, the captured image of the wafer W before the processing for the film is not used, but may be used. For example, when estimating the thickness of the resist film, not only the captured image of the wafer W after the resist film is formed, but also the captured image of the wafer W before the resist film is formed, i.e., after the intermediate layer film is formed, may be used, and further, the captured image of the wafer W after the lower layer film is formed, the captured image of the wafer W in the initial state, etc. may be used. For example, when estimating the line width of the resist pattern, not only the captured image of the wafer W after the resist pattern is formed, but also the captured image of the wafer W before the resist pattern is formed, i.e., after the resist film is formed, may be used, and further, the captured image of the wafer W after the intermediate layer film is formed, the captured image of the wafer W after the lower layer film is formed, the captured image of the wafer W in the initial state, etc. may be used. Furthermore, in the third embodiment, the captured image of the wafer W after the LTO film is formed and the captured image of the wafer W after the TiN film is formed may be used to estimate the thickness of the resist film and the line width of the resist pattern.
This makes it possible to estimate the feature quantity that more accurately reflects the past processing state.

In the figure, the overall control device 4 is separate from the semiconductor manufacturing equipment such as the coating and developing apparatus 2 and the imaging devices 7a to 7d. However, some or all of the functions of the overall control device 4 may be incorporated in the semiconductor manufacturing equipment such as the coating and developing apparatus 2 and the imaging devices 7a to 7d.
Furthermore, the functions of the image generating section and the estimation section provided in the coating and developing apparatus 2, the imaging devices 7b to 7d, etc. may be incorporated in the overall control device 4, etc.

The embodiments disclosed herein should be considered in all respects as illustrative and not restrictive. The above-described embodiments may be omitted, substituted, or modified in various ways without departing from the scope and spirit of the appended claims.

Note that the following configurations also fall within the technical scope of the present disclosure.
(1) generating an image of the substrate after processing for each layer constituting a laminate film on the substrate;
and acquiring information indicating feature amounts estimated based on the captured image for each of a plurality of layers including an outermost layer of a laminated film on the substrate.
According to the above (1), it becomes possible to appropriately set processing conditions for a substrate having a laminated film.

(2) The substrate processing method described in (1), wherein the information indicating the feature is at least one of information on the feature itself and information on pixel values in the captured image that correlate with the feature.

(3) the information indicating the feature amount includes information on a pixel value in the captured image that is correlated with the feature amount,
The substrate processing method includes:
The substrate processing method according to (3), further comprising the step of acquiring correlation information indicating a correlation between the feature amount and the pixel value.

(4) The substrate processing method according to any one of (1) to (3), further comprising a step of determining processing conditions for a substrate on which a laminated film is formed, based on the results of the step of acquiring information indicating the characteristic amount.

(5) The substrate processing method according to (4), wherein the processing performed on the substrate on which the laminated film is formed is an etching process.

(6) The substrate processing method according to (4) or (5), in which the processing performed on the substrate on which the laminated film is formed is a polishing process.

(7) The substrate processing method according to any one of (1) to (6), further comprising a step of correcting processing conditions for layers constituting a laminated film on a substrate based on the results of the step of acquiring information indicating the characteristic amount.

(8) The substrate processing method according to any one of (1) to (7), wherein the laminated film is formed using multiple semiconductor manufacturing devices.

(9) The substrate processing method according to (8), wherein the plurality of semiconductor manufacturing apparatuses include a plurality of semiconductor manufacturing apparatuses each having a spin coating module that applies a processing liquid to a substrate by a spin coating method.

(10) The substrate processing method according to (8) or (9), wherein the plurality of semiconductor manufacturing devices include a semiconductor manufacturing device having a spin coating module that forms the single layers constituting the laminated film by a spin coating method, and a film forming device that forms the single layers constituting the laminated film by a deposition method.

(11) The method further includes a step of imaging, with an imaging module, a surface of the substrate after processing of each layer constituting a laminated film on the substrate and in a state in which no other layer is formed on the layer;
The substrate processing method according to any one of (1) to (10), wherein all of the imaging modules have approximately the same configuration.

(12) The imaging module is provided individually for each layer of the laminated film,
The substrate processing method according to (11), wherein each of the imaging modules captures images using the same type of light source and camera.

(13) taking an image of the surface of the substrate after processing of each layer constituting the laminated film on the substrate and before another layer is formed thereon, using an imaging module;
and performing an exposure process on any of the layers constituting the laminated film on the substrate using an exposure device.
The substrate processing method according to any one of (1) to (10), wherein the imaging of one layer constituting a laminated film on a substrate is performed in a time period not exceeding the time from when the substrate is carried into the exposure device to when the substrate is carried out of the exposure device after the exposure processing is completed.

(14) A semiconductor manufacturing device;
An imaging module;
an image generating unit that acquires an image of each layer constituting a laminated film on a substrate based on an image capturing result of the substrate after processing related to the layer by the imaging module;
and an acquisition unit that acquires information indicating a feature amount estimated based on the captured image for each of a plurality of layers including an outermost layer of a laminated film on the substrate.

(15) The substrate processing system according to (14), which has an imaging module for each process related to a layer constituting a laminated film on a substrate.

(16) The substrate processing system described in (14) or (15), wherein at least some of the imaging modules are provided in an apparatus separate from the semiconductor manufacturing apparatus.

Reference Signs List 1, 1a, 1b, 1c Processing system 2, 2a Coating and developing apparatus 3 Etching apparatus 5 Coating apparatus 6a, 6b Film forming apparatus 8 Polishing apparatus 31, 71, 91a, 91b, 91c, 9d Imaging module 41b, 101b, 102b, 103b Image generating unit W Wafer

Claims (16)

generating an image of the substrate after processing for each layer constituting a laminate film on the substrate;
and acquiring information indicating feature amounts estimated based on the captured image for each of a plurality of layers including an outermost layer of a laminated film on the substrate. The substrate processing method according to claim 1, wherein the information indicating the feature is at least one of information on the feature itself and information on pixel values in the captured image that correlate with the feature. the information indicating the feature amount includes information on pixel values in the captured image that are correlated with the feature amount,
The substrate processing method includes:
The substrate processing method according to claim 2 , further comprising the step of acquiring correlation information indicating a correlation between the feature amount and the pixel value. The substrate processing method according to any one of claims 1 to 3, further comprising a step of determining processing conditions for a substrate on which a laminated film is formed, based on the results of the step of acquiring information indicating the characteristic amount. The substrate processing method according to claim 4, wherein the processing performed on the substrate on which the laminated film is formed is an etching process. The substrate processing method according to claim 4 or 5, wherein the processing for the substrate on which the laminated film is formed is a polishing processing. The substrate processing method according to any one of claims 1 to 6, further comprising a step of correcting processing conditions for layers constituting a laminated film on a substrate based on the results of the step of acquiring information indicating the characteristic amount. The substrate processing method according to any one of claims 1 to 7, wherein the laminated film is formed using multiple semiconductor manufacturing equipment. The substrate processing method according to claim 8, wherein the plurality of semiconductor manufacturing devices includes a plurality of semiconductor manufacturing devices having a spin coating module that applies a processing liquid to a substrate by a spin coating method. The substrate processing method according to claim 8 or 9, wherein the plurality of semiconductor manufacturing devices include a semiconductor manufacturing device having a spin coating module that forms the single layers constituting the laminated film by a spin coating method, and a film forming device that forms the single layers constituting the laminated film by a deposition method. The method further includes a step of imaging, with an imaging module, a surface of the substrate after processing of each layer constituting the laminated film on the substrate and in a state where no other layer is formed on the layer;
The substrate processing method according to any one of claims 1 to 10, wherein all of the imaging modules have substantially the same configuration. the imaging module is provided for each layer of the laminated film,
The substrate processing method according to claim 11 , wherein each of the imaging modules captures images using the same type of light source and camera. A step of imaging a surface of the substrate after processing of each layer constituting a laminated film on the substrate and in a state where no other layer is formed on the layer, using an imaging module;
and performing an exposure process on any of the layers constituting the laminated film on the substrate using an exposure device.
The substrate processing method according to any one of claims 1 to 10, wherein the imaging of one layer constituting a laminated film on a substrate is performed in a time period not exceeding the time from when the substrate is carried into the exposure device to when the substrate is carried out of the exposure device after the exposure process is completed. A semiconductor manufacturing device,
An imaging module;
an image generating unit that acquires an image of each layer constituting a laminated film on a substrate based on an image capturing result of the substrate after processing related to the layer by the imaging module;
and an acquisition unit that acquires information indicating a feature amount estimated based on the captured image for each of a plurality of layers including an outermost layer of a laminated film on the substrate. The substrate processing system according to claim 14, comprising an imaging module for each process related to a layer constituting a laminated film on a substrate. 16. The substrate processing system according to claim 14, wherein at least a part of the imaging modules is provided in an apparatus separate from the semiconductor manufacturing apparatus.

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