CN113075867A - Substrate processing method and substrate processing system - Google Patents

Substrate processing method and substrate processing system Download PDF

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Publication number
CN113075867A
CN113075867A CN202011436803.3A CN202011436803A CN113075867A CN 113075867 A CN113075867 A CN 113075867A CN 202011436803 A CN202011436803 A CN 202011436803A CN 113075867 A CN113075867 A CN 113075867A
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film
substrate
wafer
unit
layer
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榎本正志
中村泰之
鹤田丰久
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Tokyo Electron Ltd
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Tokyo Electron Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/30—Imagewise removal using liquid means
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
    • G01B11/00—Measuring arrangements characterised by the use of optical techniques
    • G01B11/02—Measuring arrangements characterised by the use of optical techniques for measuring length, width or thickness
    • G01B11/06—Measuring arrangements characterised by the use of optical techniques for measuring length, width or thickness for measuring thickness ; e.g. of sheet material
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G06T7/0002—Inspection of images, e.g. flaw detection
    • G06T7/0004—Industrial image inspection
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G06T7/60—Analysis of geometric attributes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/6715—Apparatus for applying a liquid, a resin, an ink or the like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
    • G01B2210/00—Aspects not specifically covered by any group under G01B, e.g. of wheel alignment, caliper-like sensors
    • G01B2210/56—Measuring geometric parameters of semiconductor structures, e.g. profile, critical dimensions or trench depth
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2207/00—Indexing scheme for image analysis or image enhancement
    • G06T2207/30—Subject of image; Context of image processing
    • G06T2207/30108—Industrial image inspection
    • G06T2207/30148—Semiconductor; IC; Wafer

Abstract

The invention provides a substrate processing method and a substrate processing system. The substrate processing method of the present invention comprises: a step of generating a captured image of the substrate after processing relating to each layer of the laminated film on the substrate; and acquiring information indicating the feature amount estimated based on the captured image for each of a plurality of layers including the outermost layer of the laminated film on the substrate. The present invention can appropriately set the processing conditions for a substrate having a laminated film.

Description

Substrate processing method and substrate processing system
Technical Field
The invention relates to a substrate processing method and a substrate processing system.
Background
Patent document 1 discloses a processing system including a decompression processing apparatus, a configuration determination apparatus, and a system control apparatus. The reduced-pressure processing apparatus performs etching processing on the wafer using the resist pattern as a mask. The structure discriminating apparatus measures the size of the pattern structure on the wafer surface before the etching process using scatterometry (scatterometry). The system control device stores data relating to the processing conditions during the etching process and the amount of removal of the pattern structure on the wafer surface by the etching process. The system controller sets the processing conditions during the etching process based on the measurement result of the dimension of the pattern structure on the wafer surface and the correlation data so that the pattern structure on the wafer surface after the etching process has a desired dimension.
Documents of the prior art
Patent document
Patent document 1: japanese patent laid-open publication No. 2011-86965
Disclosure of Invention
Technical problem to be solved by the invention
The technique of the present invention can appropriately set the processing conditions and the like for the substrate having the laminated film.
Technical solution for solving technical problem
One embodiment of the present invention is a substrate processing method including: a step of generating a captured image of the substrate after processing relating to each layer of the laminated film on the substrate; and acquiring information indicating the feature amount estimated based on the captured image for each of a plurality of layers including the outermost layer of the laminated film on the substrate.
Effects of the invention
According to the present invention, the processing conditions and the like for the substrate having the laminated film can be appropriately set.
Drawings
Fig. 1 is a diagram schematically showing the schematic configuration of a substrate processing system according to a first embodiment.
Fig. 2 is a view schematically showing a wafer to be processed.
Fig. 3 is a view schematically showing a film formed on a wafer to be processed by a coating and developing apparatus.
Fig. 4 is a diagram schematically showing a resist pattern formed on a wafer to be processed by a coating and developing apparatus.
Fig. 5 is a longitudinal sectional view schematically showing a schematic configuration of an image pickup unit included in the coating and developing apparatus.
Fig. 6 is a cross-sectional view schematically showing the schematic configuration of an imaging unit provided in the coating and developing apparatus.
Fig. 7 is a diagram schematically showing states of wafers after various etchings by an etching apparatus provided in a substrate processing system.
Fig. 8 is a diagram for explaining a captured image of a wafer.
Fig. 9 is a flowchart illustrating an example of processing in mass production in the substrate processing system of fig. 1.
Fig. 10 is a diagram schematically showing the schematic configuration of a substrate processing system according to a second embodiment.
Fig. 11 is a diagram schematically showing the schematic configuration of a substrate processing system according to a third embodiment.
Description of the reference numerals
1. 1a, 1b, 1c processing system
2. 2a coating and developing apparatus
3 etching apparatus
5 coating device
6a, 6b film forming apparatus
8 grinding device
31. 71, 91a, 91b, 91c, 9d photographing unit
41b, 101b, 102b, 103b image generating unit
W wafer.
Detailed Description
In a manufacturing process of a semiconductor device or the like, a predetermined process is performed to form a resist pattern on a semiconductor wafer (hereinafter, sometimes referred to as a "wafer"). The predetermined process includes, for example, a resist coating process for supplying a resist solution onto a wafer to form a resist film, an exposure process for exposing the resist film to a predetermined pattern, a PEB process for promoting a chemical reaction in the resist film after the exposure, a development process for developing the resist film after the exposure, and the like. After the resist pattern is formed, etching is performed using the resist pattern as a mask. In addition, when forming a resist pattern, a film other than a resist film, such as a base film of the resist film, is formed on a wafer to form a laminated film.
However, since the shape of the resist pattern affects etching using the resist pattern as a mask, conventionally, the dimension of the pattern structure on the wafer surface is evaluated before the etching process, and the process conditions for the etching process are set based on the evaluation result.
For example, in the processing system disclosed in patent document 1, the dimension of the pattern structure on the wafer surface before the etching process is measured using the scatterometry. In the processing system, the correlation data between the processing conditions during the etching process and the amount of removal of the pattern structure on the wafer surface by the etching process is obtained in advance. Then, based on the measurement result of the dimension of the pattern structure on the wafer surface and the above-mentioned correlation data, the processing conditions at the time of the etching process are set so that the pattern structure on the wafer surface after the etching process has a desired dimension.
However, when a laminated film including a resist film is formed on a film to be etched of a wafer, the thickness of a film other than the resist film and the like have an influence in an etching process using a resist pattern as a mask. Specifically, for example, in the case where an underlying film is formed in addition to a resist film, the thickness of the underlying film affects the processing result of etching using the resist pattern as a mask.
Therefore, the technique of the present invention can appropriately set the processing conditions for the substrate having the laminated film.
Next, a substrate processing method and a substrate processing system according to the present embodiment will be described with reference to the drawings. In the present specification and the drawings, elements having substantially the same functional configuration are denoted by the same reference numerals, and redundant description thereof is omitted.
(first embodiment)
Fig. 1 is a diagram schematically showing the schematic configuration of a substrate processing system according to a first embodiment. Fig. 2 is a view schematically showing a wafer to be processed. Fig. 3 is a view schematically showing a film formed on a wafer to be processed by a coating and developing apparatus. Fig. 4 is a diagram schematically showing a resist pattern formed on a wafer to be processed by a coating and developing apparatus. Fig. 5 and 6 are a longitudinal sectional view and a cross sectional view schematically showing the schematic configuration of an imaging unit included in the coating and developing apparatus, respectively. Fig. 7 is a diagram schematically showing states of wafers after various kinds of etching by the etching apparatus in the substrate processing system. Fig. 8 is a diagram for explaining a captured image described later.
As shown in fig. 1, a processing system 1 as a substrate processing system includes a coating and developing apparatus 2 and an etching apparatus 3 as semiconductor manufacturing apparatuses. Although not shown, the coating and developing apparatus 2 and the etching apparatus 3 are provided with a cassette station and a wafer transfer mechanism. The cassette station is used for carrying in and out a cassette containing a plurality of wafers. Further, the wafer transfer mechanism is used for wafer transfer between a wafer cassette station and various units (modules), wafer transfer between various units, and the like.
The coating and developing apparatus 2 forms a laminated film including a resist film on a wafer or develops the exposed resist film. In the following description, as shown in fig. 2, the wafer W to be processed which is carried into the coating and developing apparatus 2 is formed by laminating an oxide film F1, a TiN film F2, and a Low Temperature Oxidation (LTO) film F3 in this order from the bottom on a base wafer W1, and patterning the LTO film F3 to form an LTO pattern.
The coating and developing apparatus 2 has a lower layer film forming unit 11, an intermediate layer film forming unit 12, a resist film forming unit 13, and a developing unit 14 to laminate a film on the wafer W (specifically, for example, on the LTO film F3), or to process the laminated film that has been formed. The units 11 to 14 are spin coating units for applying the treatment liquid to the wafer W by spin coating. In the spin coating method, a processing liquid is discharged onto the wafer W from, for example, a coating nozzle (not shown), and the wafer W is rotated to spread the processing liquid on the surface of the wafer W. The lower layer film forming unit 11, the intermediate layer film forming unit 12, the resist film forming unit 13, and the developing unit 14 can use known structures.
The lower layer film forming unit 11 applies a lower layer film material as a processing liquid to the wafer W to form a lower layer film as a base film of a resist film. Specifically, as shown in fig. 3, for example, the lower layer film forming unit 11 forms an SOC (spin on carbon) film F4 as a lower layer film on the LTO film F3(LTO pattern) of the wafer W.
The intermediate layer film forming unit 12 applies an intermediate layer film forming material as a processing liquid to the wafer W to form an intermediate layer film as a base film of a resist film. Specifically, the intermediate layer film forming unit 12 forms an SOG (spin on glass) film F5 as an intermediate layer film on the SOC film F4 film of the wafer W, for example, as shown in fig. 3.
The resist film forming unit 13 applies a resist solution as a processing solution to the wafer W to form a resist film. Specifically, the resist film forming unit 13 forms a resist film F6 on the SOG film F5 of the wafer W, for example, as shown in fig. 3.
The developing unit 14 applies a developing solution as a processing solution to the wafer W to develop the wafer W. Specifically, the developing unit 14 develops the resist film F6 exposed by an exposure device (not shown) integrally connected to the coating and developing device 2, for example, to form a resist pattern P1 on the wafer W as shown in fig. 4.
As shown in fig. 1, the coating and developing apparatus 2 includes a heat treatment unit 21, and the heat treatment unit 21 performs a heat treatment on the wafer W using a hot plate on which the wafer W can be placed. The heat treatment unit 21 is used, for example, after the SOC film F4 is formed, after the SOG film F5 is formed, after the resist film F6 is formed, before exposure, before development after exposure, and after development. In the figure, the number of the heat treatment units 21 is one, but a plurality of heat treatment units 21 are provided in the coating and developing apparatus 2, and different heat treatment units 21 are used depending on the application. The heat treatment unit 21 can have a known structure.
The coating and developing apparatus 2 is provided with first to fifth imaging units 311～315(hereinafter, collectively referred to as "photographing unit 31".). The imaging unit 31 can use the imaging result for wafer inspection, but as will be described later, in the present embodiment, the imaging result is used to estimate the feature amount of each layer (each film) of the laminated film on the wafer W.
First photographing unit 311For photographing the wafer W before the lower layer film formation processing by the lower layer film formation unit 11.
Second photographing unit 312For imaging the wafer W after the lower layer film formation process and before the intermediate layer film formation process by the intermediate layer film formation unit 12.
Third photographing unit 313For imaging the wafer W before the resist film formation process by the resist film formation unit 13 after the above-described intermediate layer film formation process.
Fourth photographing unit 314For imaging the wafer W after the resist film formation process and before the exposure process.
Fifth photographing unit 315For photographing the wafer W after the development processing.
As shown in fig. 5 and 6, the first photographing unit 311Having a housing 200. A stage 201 on which a wafer W can be placed is provided in the housing 200. The table 201 is rotatable and stoppable by a rotation driving unit 202 such as a motor. A guide rail 203 extending from one end side (negative X-direction side in fig. 6) to the other end side (positive X-direction side in fig. 6) in the housing 200 is provided on the bottom surface of the housing 200. The table 201 and the rotation driving unit 202 are provided on a guide rail 203, and are movable along the guide rail 203 by a driving device 204.
An imaging mechanism 210 is provided on the side surface of the other end side (the positive X-direction side in fig. 6) in the housing 200. The imaging mechanism 210 uses a line sensor camera as a camera, for example.
A half mirror (half-mirror)211 is provided near the center of the upper portion of the housing 200. The half mirror 211 is provided at a position facing the imaging mechanism 210 in a state inclined upward by 45 degrees from a state where the mirror surface faces vertically downward toward the imaging mechanism 210. An illumination mechanism 212 as a light source is provided above the half mirror 211. The half mirror 211 and the illumination mechanism 212 are fixed to the upper surface inside the housing 100. Illumination light from the illumination mechanism 212 is irradiated downward by the half mirror 211. Therefore, light reflected by an object located below the illumination mechanism 212 is further reflected by the half mirror 211, and enters the photographing mechanism 210. That is, the imaging mechanism 210 can image an object in the irradiation area of the illumination mechanism 212.
First photographing unit 311The wafer W is moved in one direction (X direction in fig. 6) along the guide rail, and the surface of the wafer W is imaged by a line sensor camera of the imaging mechanism 210 having a long imaging field in a direction substantially perpendicular to the one direction.
In addition, the second to fifth photographing units 312～315And the first photographing unit 31 described above1The structure of (a) is substantially the same.
As shown in fig. 1, the coating and developing apparatus 2 is provided with a control unit 41.
The control unit 41 is a computer having a CPU, a memory, and the like, and has a program storage unit (not shown). The program storage unit stores programs and the like for controlling the operations of the drive systems of the various units, the transport device (not shown), and the like described above to perform various processes on the wafer W. The program may be recorded in a computer-readable storage medium, and installed from the storage medium to the control unit 41. Part or all of the program may be implemented by dedicated hardware (circuit board).
The control unit 41 includes a storage unit 41a, an image generation unit 41b, and an estimation unit 41 c. This is explained later.
The etching apparatus 3 includes an LTO film etching unit 51, a TiN film etching unit 52, and an oxide film etching unit 53. The units 51 to 53 are, for example, plasma dry etching units.
The LTO film etching unit 51 performs etching of the LTO film F3 using the laminated film on the wafer W formed by the coating and developing apparatus 2 as a mask. Thereby, as shown in fig. 4 and fig. 7 (a), the resist pattern P1 is transferred to the LTO film F3, forming a LTO film pattern P2.
The TiN film etching unit 52 performs etching of the TiN film F2 using the pattern P2 of the LTO film formed by the LTO film etching unit 51 as a mask. Thereby, as shown in fig. 7 (a) and 7 (B), the pattern P2 of the LTO film was transferred to the TiN film F2, forming a pattern P3 of the TiN film.
The oxide film etching means 53 performs etching of the oxide film F1 using the TiN film pattern P3 formed by the TiN film etching means 52 as a mask. Thereby, as shown in fig. 7 (B) and 7 (C), the pattern P3 of the TiN film was transferred to the oxide film F1.
As shown in fig. 1, the processing system 1 also has an overall control device 4.
The overall control device 4 is a computer having a CPU, a memory, and the like, for example, and has a program storage unit (not shown). The program storage unit stores a program for generating a correlation model described later. The program may be recorded in a non-transitory computer-readable storage medium, and installed from the storage medium to the overall control device 4. Part or all of the program may be implemented by dedicated hardware (circuit board).
The overall control device 4 includes a storage unit 61, a model generation unit 62, an acquisition unit 63, a processing condition determination unit 64, and a processing condition correction unit 65.
Here, the storage unit 41a, the image generation unit 41b, and the estimation unit 41c of the control unit 41, and the storage unit 61, the model generation unit 62, the acquisition unit 63, the processing condition determination unit 64, and the processing condition correction unit 65 of the overall control device 4 will be described.
The storage unit 41a of the control unit 41 stores various information. The storage unit 41a stores an estimation model, which will be described later, generated by the model generation unit 62 of the overall control device 4, for example.
The image generator 41b generates a captured image of the wafer W based on the result of imaging of the wafer W by the imaging mechanism 210 of the imaging unit 31. For example, the image generator 41B divides the wafer W in the imaging result of the imaging mechanism 210 into 437 regions, and calculates the average value of the pixel values of R (red), G (green), and B (blue) in each region. Then, the image generating unit 41b generates a table in which the coordinates of each region are associated with the average value of the RGB data, which is the average value of the pixel values, for each region. Then, the image generator 41b makes the table correspond to the optical system or the like in the imaging unit 31 and performs correction. From the corrected table, the image Im shown in fig. 8 can be generated. Hereinafter, the above table acquired as described above from the imaging result by the imaging means 210 will be referred to as "captured image".
The image generating unit 41b generates a captured image of the wafer after the process for each layer of the laminated film on the wafer W. The process related to the layer includes, for example, a process for forming the layer (e.g., a process for forming an interlayer film), and a process for developing the layer (e.g., a process for developing a resist film).
The captured image generated by the image generator 41b is basically stored in the storage 41a for each wafer W.
The estimation unit 41c estimates the feature value of the m-th layer (m is an integer equal to or greater than 1) formed on the wafer W in the processing system 1, based on the pixel value or the like in the captured image of the wafer W after the processing relating to the m-th layer. This estimation is performed for each region constituting the captured image of the wafer W. For example, as described above, when the wafer W is divided into 437 regions, the feature amount of the mth layer is estimated based on the pixel value and the like of each of the 437 regions in the captured image of the processed wafer W relating to the mth layer. The characteristic amount of the m-th layer is, for example, a characteristic related to the shape of the m-th layer, specifically, a size such as a thickness of the m-th layer or a line width of the m-th layer. When the in-plane distribution of the feature amount is acquired by associating the estimation result of the feature amount for each region with the position information of each region, the estimation unit 41c specifically estimates the in-plane distribution of the film thickness of the m-th layer (distribution of thick portions and thin portions) and the in-plane distribution of the line width of the m-th layer (distribution of thick portions and thin portions).
The estimation unit 41c estimates the characteristic amount for all layers constituting the laminated film on the wafer W, for example.
When estimating the characteristic amount of the outermost layer (i.e., the nth layer) of the laminated film including n (n is an integer of 2 or more) layers, the estimating unit 41c acquires the estimated characteristic amount for each of at least the (n-1) th layer for each region. Then, the estimation unit 41c estimates the feature value of the n-th layer of the processed wafer W for each region based on the acquisition result of the feature value estimated as described above, the pixel value in the captured image of the processed wafer W for the n-th layer, an estimation model to be described later generated in advance, and the like. The estimation model is generated in advance using a wafer W for model generation (hereinafter, a preparation wafer W). The estimation model is, for example, a model showing a correlation between (X) and (Y), where (X) is a feature value of each layer from (n-1) to (n-1) on the wafer W and a pixel value in a processed captured image of the wafer W relating to the n-th layer, and (Y) is a feature value of the n-th layer of the wafer W after the processing.
The feature amount estimated by the estimation unit 41c (hereinafter sometimes referred to as "estimated feature amount") is stored in the storage unit 41a for each wafer W.
The storage unit 61 of the overall control device 4 stores various kinds of information. The storage unit 61 stores information used when the model generation unit 62 generates the estimation model described above, for example.
The model generation unit 62 generates the estimation model described above in advance for each type of characteristic amount of the film (layer). For example, the model generation unit 62 specifically generates an estimation model in advance for each of the underlayer film thickness, the interlayer film thickness, the resist film thickness, and the resist pattern line width. Details of the generation method will be described later.
The estimation model generated by the model generation unit 62 is stored in the storage unit 61, and is transmitted to the coating and developing apparatus 2 and stored in the storage unit 41 a.
The acquisition unit 63 acquires information for determining the processing conditions by the processing condition determination unit 64 and for correcting the processing conditions by the processing condition correction unit 65. Specifically, the acquiring unit 63 acquires, from the coating and developing apparatus 2, the characteristic amount (in-plane distribution) of each of the plurality of layers including the outermost layer of the laminated film on the wafer W, which is estimated by the estimating unit 41c of the coating and developing apparatus 2 based on the captured image. For example, the acquiring unit 63 acquires the in-plane distribution of the estimated characteristic amount from the coating and developing apparatus 2 for each of all layers of the laminated film on the wafer W.
The processing condition determining unit 64 determines the processing conditions in the downstream process based on the acquisition result of the acquiring unit 63, that is, the estimated characteristic amount of each layer of the laminated film formed on the wafer W. Specifically, the processing condition determining unit 64 determines the etching processing conditions for the wafer W on which the laminated film is formed in the etching apparatus 3, based on the estimated characteristic amount of each layer of the laminated film formed on the wafer W.
The process condition correcting unit 65 corrects the process conditions of the film formation process and the development process with respect to the layers constituting the laminated film on the wafer W based on the acquisition result of the acquiring unit 63, that is, based on the estimated feature value of each layer of the laminated film formed on the wafer W.
Next, an example of a method for generating an estimation model will be described.
(1. initial imaging step)
When the estimation model is generated, first, the coating and developing apparatus 2 takes an image of the prepared wafer W in an initial state before various films such as an underlayer film are formed, and generates an image of the taken image.
Specifically, for example, the first photographing unit 311The imaging mechanism 210 (a) images the surface of the preparation wafer W in the initial state. Then, the image generator 41b generates an initial captured image of the prepared wafer W (hereinafter, sometimes referred to as "initial captured image") based on the imaging result of the imaging mechanism 210. The generated captured image is transmitted to the overall control device 4, and is stored in the storage unit 61 for each wafer W.
The prepared wafer W is a production wafer used for mass production of semiconductor devices, for example, when a resist pattern is formed in a mass production place, and a pattern is formed on the wafer surface in the same manner as in fig. 2.
(2. lower layer film formation step)
After the initial state imaging step, an underlayer film is formed on the preparation wafer W. Specifically, the SOC film is formed on the preliminary wafer W by the lower layer film forming unit 11 under a predetermined process condition, and then the preliminary wafer W is subjected to a heat treatment under a predetermined process condition by the heat treatment unit 21 for SOC film.
(3. imaging Process after formation of lower layer film)
Next, the prepared wafer W on which the underlayer film is formed is photographed, and a photographed image of the prepared wafer W is generated.
Specifically, for example, the second photographing unit 312The imaging mechanism 210 (a) images the surface of the prepared wafer W after the SOC film as the lower layer film is formed. Then, the image generator 41b generates an image of the prepared wafer W after the lower layer film is formed (hereinafter, may be referred to as "lower layer film formed image") based on the imaging result of the imaging mechanism 210. The generated captured image is transmitted to the overall control device 4, and is stored in the storage unit 61 for each wafer W.
(4 actual measurement Process for film thickness of underlayer film)
Next, the thickness of the underlayer film formed on the preparation wafer W is measured by a film thickness measuring instrument (not shown) provided outside the processing system 1.
At this time, for example, the preparation wafer W is divided into 437 regions equal to the number of divided regions of the captured image, and the film thickness of the underlayer film on each region is measured.
The measurement results are input to the overall controller 4 and stored in the storage unit 61 for each wafer W. As the film thickness measuring instrument, for example, a film thickness meter using a reflection spectroscopy method or the like can be used.
(5. intermediate layer film formation step)
After the actual measurement step of the thickness of the underlayer film, the prepared wafer W is returned to the processing system 1, and an underlayer film is formed on the underlayer film of the prepared wafer W. Specifically, the SOG film is formed on the lower layer film of the preliminary wafer W under predetermined process conditions by the intermediate layer film forming unit 12, and then heat treatment is performed on the preliminary wafer W under predetermined process conditions by the heat treatment unit 21 for the SOG film.
(6. imaging step after formation of interlayer film)
Next, the prepared wafer W on which the interlayer film is formed is photographed, and a photographed image of the prepared wafer W is generated.
In particular, the method of manufacturing a semiconductor device,for example, by the third photographing unit 313The imaging mechanism 210 (a) images the surface of the prepared wafer W after the SOG film as the intermediate layer film is formed. Then, the image generating unit 41b generates an image of the prepared wafer W after the formation of the intermediate layer film (hereinafter, may be referred to as "an image taken after the formation of the intermediate layer film") based on the imaging result of the imaging mechanism 210. The generated captured image is transmitted to the overall control device 4, and is stored in the storage unit 61 for each wafer W.
(7 actual measurement Process for film thickness of intermediate layer film)
Next, the thickness of the intermediate layer film formed on the preparation wafer W is measured by a film thickness measuring instrument (not shown) provided outside the processing system 1, in the same manner as in the actual film thickness measuring step of the intermediate layer film.
The measurement results of the thickness of the interlayer film are input to the overall controller 4 and stored in the storage unit 61 for each wafer W.
(8 resist film formation step)
After the actual measurement step of the thickness of the interlayer film, the prepared wafer W is returned to the processing system 1, and a resist film is formed on the interlayer film of the prepared wafer W. Specifically, after a resist film is formed on the intermediate layer film of the preliminary wafer W under predetermined process conditions by the resist film forming unit 13, the preliminary wafer W is subjected to the PAB process under predetermined process conditions by the heat treatment unit 21 for PAB process.
(9. post-resist-film-formation imaging step)
Next, the prepared wafer W on which the resist film is formed is photographed, and a photographed image of the prepared wafer W is generated.
Specifically, for example, the fourth photographing unit 314The imaging mechanism 210 (a) images the surface of the prepared wafer W after the resist film is formed. Then, the image generating unit 41b generates a captured image of the prepared wafer W after the resist film formation (hereinafter, may be referred to as "captured image after resist film formation") based on the imaging result of the imaging mechanism 210. The generated captured image is transmitted to the overall control device 4, and is stored in the storage unit 61 for each wafer W.
(10. actual measurement Process for film thickness of resist film)
Next, the thickness of the resist film formed on the preparation wafer W is measured by a film thickness measuring instrument (not shown) provided outside the processing system 1, in the same manner as in the actual film thickness measuring step of the underlayer film.
The measurement result of the thickness of the resist film is input to the overall control device 4 and stored in the storage unit 61 for each wafer W.
(11. Exposure step)
After the actual measurement step of the resist film thickness, the exposure process for the preparation wafer W is performed in an exposure apparatus integrally connected to the coating and developing apparatus 2. Thereby, the resist film on the wafer W is prepared to be exposed to a predetermined pattern.
(12.PEB Process)
Thereafter, the prepared wafer W is subjected to PEB processing under predetermined processing conditions by the heat treatment unit 21 for PEB processing.
(13. developing step)
Subsequently, the preparatory wafer W is subjected to a developing process. Specifically, a developing process is performed under predetermined process conditions by the developing unit 14, and a resist pattern is formed on the wafer W.
(14. post-pattern formation imaging step)
Next, the prepared wafer W on which the resist pattern is formed is photographed, and a photographed image of the prepared wafer W is generated.
Specifically, for example, the fifth photographing unit 315The imaging mechanism 210 (a) images the surface of the preparation wafer W after the resist pattern is formed. Then, the image generator 41b generates a captured image of the prepared wafer W after the resist pattern formation (hereinafter, may be referred to as a "post-pattern formation captured image") based on the imaging result of the imaging mechanism 210. The generated captured image is transmitted to the overall control device 4, and is stored in the storage unit 61 for each wafer W.
(15 actual line width measurement step of resist Pattern)
Next, the line width of the resist pattern formed on the preparation wafer W is measured by a line width measuring instrument (not shown) provided outside the processing system 1.
At this time, for example, the preparation wafer W is divided into 437 regions equal to the number of divided regions of the captured image, and the line width of the resist pattern in each region is measured.
The measurement results are input to the overall controller 4 and stored in the storage unit 61 for each wafer W. Further, as the line width measuring instrument, for example, SEM (Scanning Electron Microscope) can be used.
The processes from the above 1 initial state imaging process to 15 actual line width measurement process of the resist pattern are performed on each of the plurality of prepared wafers W. The process conditions may be intentionally varied between the prepared wafers W so that the thickness of each film on the prepared wafer W and the line width of the resist pattern may be varied between the prepared wafers W. That is, the prepared wafer W may be processed under a plurality of processing conditions different for each layer to generate the estimation model.
(16. calculation model creation step of underlayer film thickness)
Then, an estimation model of the thickness of the lower layer film is generated based on the initial state captured image, the measurement result of the thickness of the lower layer film formed on the prepared wafer W by the film thickness measuring instrument, and the captured image after the formation of the lower layer film.
Specifically, for example, the model generation unit 62 of the overall controller 4 generates an estimation model of the underlayer film thickness indicating the correlation between the following (a1) to (A3) based on the following information (a1) to (A3).
(a1) Preparation of pixel values in the initial-state captured image of each of the 437 regions of the wafer W
(a2) The pixel values in the captured image after formation of the lower layer film for each of the 437 regions of the wafer W were prepared
(a3) The measurement results of the thickness of the lower layer film measured by the film thickness measuring instrument for each of the 437 regions of the wafer W were prepared
(A1) Pixel value in the captured image of the wafer W in the initial state
(A2) Pixel value in the captured image of the wafer W after formation of the lower layer film
(A3) Thickness of underlayer film on wafer W
In the case where the production wafer is a bare wafer, etc., an estimation model of the film thickness of the underlayer film, which represents the correlation between the above (a2) to (A3), may be generated from the information of the above (a2) to (A3). In this case, the initial-state captured image is not necessary when the estimation model is generated.
(Process for generating estimation model of intermediate layer film thickness)
An estimation model of the thickness of the intermediate layer film is generated based on the measurement results of the thickness of the intermediate layer film and the thickness of the lower layer film formed on the prepared wafer W measured by the film thickness measuring instrument and the captured image after the formation of the intermediate layer film.
Specifically, for example, the model generation unit 62 of the overall controller 4 generates an estimation model of the film thickness of the interlayer film indicating the correlation between the following (B1) to (B3) from the information of the following (B1) to (B3) for each of the 437 regions of the prepared wafer W.
(b1) Measurement result of thickness of underlayer film measured by film thickness measuring instrument
(b2) Taking a pixel value in an image after formation of an interlayer film
(b3) Measurement result of thickness of intermediate layer film measured by film thickness measuring instrument
(B1) Thickness of underlayer film
(B2) Pixel value in the captured image of the wafer W after formation of the interlayer film
(B3) Thickness of interlayer film
(step of generating estimation model of thickness of resist film)
Further, an estimation model of the thickness of the resist film is generated based on the measurement results of the thickness of the resist film formed on the preparation wafer W, the thickness of the intermediate layer film, and the thickness of the underlayer film measured by the film thickness measuring instrument, and the captured image after the resist film is formed.
Specifically, for example, the model generation unit 62 of the overall controller 4 generates an estimation model of the film thickness of the underlayer film, which indicates the correlation between the following (C1) to (C4), from the following information (C1) to (C4) for each of the 437 regions of the prepared wafer W.
(c1) Measurement result of thickness of underlayer film measured by film thickness measuring instrument
(c2) Measurement result of thickness of intermediate layer film measured by film thickness measuring instrument
(c3) Pixel value in captured image after resist film formation
(c4) Measurement result of thickness of resist film measured by film thickness measurer
(C1) Thickness of underlayer film
(C2) Thickness of interlayer film
(C3) Pixel value in the captured image of the wafer W after formation of the resist layer film
(C4) Thickness of resist film
(estimation model creation step of line Width of resist Pattern)
Further, an estimation model of the line width of the resist pattern is generated based on the measurement result of the line width of the resist pattern formed on the preparation wafer W measured by the line width measuring instrument, the thickness of the resist film formed on the preparation wafer W measured by the film thickness measuring instrument, the measurement results of the thickness of the intermediate layer film and the thickness of the underlayer film, and the captured image after pattern formation.
Specifically, for example, the model generation unit 62 of the overall controller 4 generates an estimated model of the line width of the resist pattern indicating the correlation between the following (D1) to (D5) from the information of the following (D1) to (D5) for each of the 437 areas of the prepared wafer W.
(d1) Measurement result of thickness of underlayer film measured by film thickness measuring instrument
(d2) Measurement result of thickness of intermediate layer film measured by film thickness measuring instrument
(d3) Measurement result of thickness of resist film measured by film thickness measurer
(d4) Pixel values in a captured image after pattern formation
(d5) Measurement result of line width of resist pattern measured by line width measurer
(D1) Thickness of underlayer film
(D2) Thickness of interlayer film
(D3) Thickness of resist film
(D4) Pixel value in the captured image of the wafer W after resist pattern formation
(D5) Line width of resist pattern
As described above, each estimation model is generated in advance before the process is performed in the production area in the processing system 1. Each estimation model generated in advance is transmitted to the coating and developing apparatus 2 and stored in the storage unit 41 a.
Next, a process in mass production in the processing system 1 will be described. Fig. 9 is a flowchart illustrating an example of processing in mass production in the processing system 1.
In mass production in the processing system 1, for example, as shown in fig. 9, a step of forming a resist pattern by laminating a film on the wafer W (step S1) and a step of generating a captured image of the wafer W (step S2) are performed in parallel.
Specifically, the wafer W is subjected to the same processes as those in the above-described 1 initial state imaging step, 2 lower layer film formation step, 3 lower layer film formation post-imaging step, 5 intermediate layer film formation step, 6 intermediate layer film formation post-imaging step, 8 resist film formation step, 9 resist film formation post-imaging step, 11 exposure step, 12 PEB step, 13 development step, and 14 pattern formation post-imaging step. In this way, after the underlayer film, the interlayer film, and the resist film are laminated on the wafer W, the resist film is developed to form a resist pattern. Then, the image generator 41b generates an image of the wafer W in an initial state, an image of the wafer W after the lower layer film formation, an image of the wafer W after the intermediate layer film formation, an image of the wafer W after the resist film formation, and an image of the wafer W after the resist pattern formation. The generated captured image is stored in the storage unit 41a for each wafer W.
In addition, in mass production, for example, a step of estimating the thickness of the underlayer film (step S3), a step of estimating the thickness of the layers subsequent to the second layer (intermediate layer and resist film) (step S4), and a step of estimating the line width of the resist pattern (step S5) are performed. The respective estimation results are stored in the storage unit 41a for each wafer W.
In the step of estimating the thickness of the underlayer film in step S3, the estimation unit 41c estimates the thickness of the underlayer film, for example, based on the captured image of the wafer W in the initial state, the captured image of the wafer W after the underlayer film is formed, and the estimation model of the thickness of the underlayer film stored in the storage unit 41 a. Specifically, the thickness of the lower layer film is estimated for each of the 437 regions of the wafer W based on the pixel values in the captured image of the wafer W in the initial state, the pixel values in the captured image of the wafer W after the lower layer film is formed, and the estimation model of the thickness of the lower layer film. That is, the in-plane distribution of the thickness of the underlayer film is estimated. In addition, when the initial captured image is not used in generating the model for estimating the film thickness of the underlayer film, the pixel value of the captured image of the wafer W in the initial state is not used in estimating the film thickness of the underlayer film.
In the step of estimating the thicknesses of the layers subsequent to the second layer (intermediate layer and resist film) in step S4, for example, first, the estimating unit 41c acquires the in-plane distribution of the estimated thickness from the storage unit 41a for the layer located below the outermost layer of the laminated film to be estimated of the film thickness. When the thickness of the intermediate layer film is estimated, for example, the in-plane distribution of the estimated thickness of the lower layer film is acquired from the storage unit 41a, and when the thickness of the resist film is estimated, the in-plane distribution of the estimated thicknesses of the lower layer film and the intermediate layer film is acquired from the storage unit 41 a.
Then, the estimation unit 41c estimates the thickness of the outermost layer of the laminate film to be estimated, based on the acquisition result of the estimated thickness, the captured image of the wafer W on which the outermost layer of the laminate film is formed, and the estimation model corresponding to the outermost layer.
For example, the thickness of the intermediate layer film is estimated based on an in-plane distribution of the estimated thickness of the lower layer film, a captured image of the wafer W after the formation of the intermediate layer film, and an estimation model of the thickness of the intermediate layer film. Specifically, the thickness of the interlayer film is estimated for each of the 437 regions of the wafer W based on the estimated thickness of the underlayer film, the pixel values in the captured image of the wafer W after the formation of the interlayer film, and the estimated model of the interlayer film. That is, the in-plane distribution of the thickness of the interlayer film was estimated. The thickness of the resist film is estimated based on the in-plane distribution of the estimated thicknesses of the lower layer film and the intermediate layer film, the captured image of the wafer W after the resist film formation, and the estimated model of the thickness of the resist film. Specifically, the thickness of the resist film is estimated for each of the 437 regions of the wafer W based on the estimated thicknesses of the lower layer film and the intermediate layer film, the pixel values in the captured image of the wafer W after the formation of the resist layer film, and the estimated model of the thickness of the resist film. That is, the in-plane distribution of the thickness of the resist film was estimated.
In the step of estimating the line width of the resist pattern as the step S5, for example, first, the estimating unit 41c acquires the in-plane distribution of the estimated thickness from the storage unit 41a for each layer including the outermost layer of the laminated film on the wafer W before development. Specifically, the estimated thicknesses of the underlayer film, the interlayer film, and the resist film (before development) are acquired from the storage unit 41 a.
Then, the estimation unit 41c estimates the line width based on the acquired in-plane distribution of the estimated thicknesses of the underlayer film, the interlayer film, and the resist film, the captured image of the wafer W after the formation of the resist pattern, and the estimation model of the line width of the resist pattern. Specifically, the line width of the resist pattern can be estimated by estimating an estimation model of the estimated thicknesses of the underlayer film, the interlayer film, and the resist film, the pixel value in the captured image of the wafer W after the formation of the resist pattern, and the line width of the resist pattern for each of the 437 regions of the wafer W. That is, the in-plane distribution of the line width of the resist pattern is estimated.
When the estimation of each feature amount is completed, a step of determining etching process conditions is performed (step S6).
In this step, for example, first, the acquisition unit 63 acquires, from the coating and developing apparatus 2, an in-plane distribution of the estimated line width of the resist pattern formed on the wafer W by the coating and developing apparatus 2 and an in-plane distribution of the estimated thickness of the intermediate layer film.
Then, the processing condition determining section 64 determines the etching processing conditions of the etching apparatus 3 based on the information acquired by the acquiring section 63. For example, when the estimated line width of the resist pattern acquired by the acquisition unit 63 falls within a desired range in all regions of the surface of the wafer W and the estimated thickness of the interlayer film acquired by the acquisition unit 63 is smaller than a desired thickness only in the outer periphery of the wafer, the process condition determination unit 64 determines the etching process conditions as follows. That is, in this case, the process condition determining unit 64 determines (i.e., adjusts) the etching process conditions of the LTO film etching unit 51 such that the etching amount per unit time in the LTO film etching unit 51 becomes smaller only at the wafer periphery. The etching process conditions to be adjusted are the flow rate of the process gas used for etching, the temperature of the wafer, and the like. The adjusted etching process conditions are sent to a control unit (not shown) of the etching apparatus 3.
Next, the etching process is performed by the etching apparatus 3 (step S7).
In this step, etching by the LTO film etching means 51, etching by the TiN film etching means 52, and etching by the oxide film etching means 53 are sequentially performed under the control of a control unit (not shown) of the etching apparatus 3. When the etching process conditions are adjusted in step S6, etching is performed in the etching apparatus 3 under the adjusted etching process conditions.
Further, a process of correcting the process conditions in the coating and developing apparatus 2 is performed (step S8).
In this step, for example, first, the acquisition unit 63 acquires the in-plane distribution of the estimated thickness of the resist film formed on the wafer W by the coating and developing apparatus 2, the in-plane distribution of the estimated thickness of the intermediate layer film, and the in-plane distribution of the estimated thickness of the lower layer film.
Then, the process condition correction unit 65 corrects the process conditions in the coating and developing apparatus 2 based on the result acquired by the acquisition unit 63. For example, when the entire multilayer film including the underlayer film, the interlayer film, and the resist film has a characteristic film thickness distribution (for example, a distribution in which the film thickness increases toward the center of the substrate or a distribution in which the film thickness increases toward the outer periphery of the substrate), the process condition correction unit 65 corrects the film thickness distribution as follows. In other words, in this case, the process condition correction unit 65 specifies the film having the same film thickness distribution as the characteristic film thickness distribution, among the underlayer film, the interlayer film, and the resist film, based on the result acquired by the acquisition unit 63. The processing condition correction unit 65 corrects the processing condition relating to the determined film, for example, the processing condition in the heat processing unit 21 for the film.
The above steps are performed for each wafer W.
Note that, in the above description, the information acquired from the coating and developing apparatus 2 by the acquisition unit 63 used for the determination by the process condition determination unit 64 and the correction by the process condition correction unit 65 is information of the feature amount itself (specifically, the in-plane distribution thereof) of each layer. The information acquired by the acquisition unit 63 may be information indicating the feature value of each layer, and for example, information on the pixel value in the captured image of the wafer W (specifically, the in-plane distribution thereof) related to the feature value may be used instead of or in addition to the information on the feature value itself (specifically, the in-plane distribution thereof).
As described above, the processing system 1 of the present embodiment includes the coating and developing apparatus 2 and the like as the semiconductor manufacturing apparatus and the imaging unit 31. The processing system 1 further includes an image generating unit 41b, and the image generating unit 41b generates a captured image of each layer constituting the laminated film on the wafer W based on the result of imaging by the imaging unit 31 of the wafer W after the processing relating to the layer. The processing system 1 further includes an acquisition unit 63, and the acquisition unit 63 acquires information indicating a feature amount estimated based on the captured image for each of a plurality of layers including the outermost layer of the laminated film on the wafer W. That is, in the present embodiment, the acquiring unit 63 also acquires the processing result applied to the wafer W for the layer other than the outermost layer. Therefore, based on the acquisition result of the acquisition unit 63, it is possible to more appropriately set the processing conditions for processing the wafer W having the laminated film, such as the etching processing conditions, or to more appropriately correct the processing conditions in the coating and developing apparatus 2.
In the present embodiment, since the captured image of the wafer W is used for the estimation of the feature amount, the processing result applied to the wafer W can be obtained for the layer other than the outermost layer without losing throughput (throughput) as compared with the case where the feature amount is actually measured using a film thickness measuring instrument, a line width measuring instrument, or the like.
In the present embodiment, the acquisition unit 63 acquires information indicating the feature amount estimated based on the captured image for each of the plurality of layers including the outermost layer of the laminated film on the wafer W, and the processing condition correction unit 65 corrects the processing conditions in the coating and developing apparatus 2 based on the acquisition result. Therefore, the process condition correction unit 65 can grasp the feature values not only for the surface layer but also for the lower layer in the stack, and comprehensively examine the states of the respective layers by comparing them with each other, thereby appropriately selecting the process of correcting the process conditions and determining the correction amount thereof.
In the present embodiment, the imaging units 31 for acquiring the respective captured images have substantially the same configuration. Therefore, the same captured image can be acquired from the same subject without performing correction for each imaging unit 31, and therefore, estimation of the feature amount based on the captured image and the like can be easily performed.
In the present embodiment, the imaging unit 31 is provided individually for each layer constituting the laminated film formed on the wafer W, specifically, for each process related to the layer. Also, the photographing units 31 each have the same kind of light source and camera, i.e., have the same kind of photographing optical system. By performing imaging of the surface of each layer using the same type of imaging optical system, it is possible to reduce and equalize variations in performance (for example, accuracy and reproducibility) of the imaging result at each time, and it is possible to ensure reliability when the same model, that is, the related information is used.
In the present embodiment, the imaging unit 31 performs imaging of one layer constituting the laminated film on the wafer W for a time not exceeding the time required for the exposure process. Specifically, the imaging is performed within a time period not exceeding a time period from when the wafer W is loaded into the exposure apparatus (not shown) to when the wafer W is loaded out of the exposure apparatus after the exposure process is completed. Accordingly, the time between the exposure process and the next exposure process is not increased by the imaging, and thus the throughput can be prevented from being reduced by the imaging.
In the present embodiment, the model generation unit 62 is provided in the same control device as the acquisition unit 63 and the processing condition determination unit 64. Instead, the model generation unit 62 may be provided in a different control device from the acquisition unit 63 and the processing condition determination unit 64. In this case, when the information acquired by the acquisition unit 63 from the coating and developing apparatus 2 is information on the pixel values (specifically, the in-plane distribution thereof) in the captured image of the wafer W relating to the feature amount of each layer, the acquisition unit 63 acquires the estimation model together with the correlation information indicating the correlation between the feature amount and the pixel value. Thus, for example, when the information acquired by the acquisition unit 63 from the coating and developing device 2 is the in-plane distribution of the pixel values, if the pixel values indicate abnormal values, it is possible to determine whether the cause of the abnormal values is caused by a defect in the imaging unit 31 or whether the estimation model is incorrect.
(second embodiment)
Fig. 10 is a diagram schematically showing the schematic configuration of a substrate processing system according to a second embodiment.
As shown in the drawing, the processing system 1a as the substrate processing system of the present embodiment is provided with a coating apparatus 5 in addition to a coating and developing apparatus 2a, an etching apparatus 3, and an overall control apparatus 4.
The coating and developing apparatus 2a omits the lower layer film forming unit 11 of the coating and developing apparatus 2 in the first embodiment. The omitted lower layer film forming unit 11 is provided in the coating apparatus 5. Thus, the processing system 1a comprises: a coating and developing apparatus 2a as a semiconductor manufacturing apparatus having an intermediate layer film forming unit 12, a resist film forming unit 13, and a developing unit 14 as spin coating units; and a coating apparatus 5 having a lower layer film forming unit 11 as a spin coating unit. That is, the processing system 1a includes a plurality of semiconductor manufacturing apparatuses having spin coating units.
In the coating and developing apparatus 2a, the second imaging unit 31 of the coating and developing apparatus 2 according to the first embodiment is omitted2。
On the other hand, the coating device 5 is provided with a first paddlePickup unit 711And a second photographing unit 712(hereinafter, collectively referred to as an imaging unit 71.). The imaging unit 71 has substantially the same configuration as the imaging unit 31 of the coating and developing apparatus 2 a. The substantially same configuration of the imaging means that the same imaging result can be obtained when the same subject is imaged.
First photographing unit 711The imaging device is used for imaging the wafer W before the lower layer film formation process by the lower layer film formation unit 11 in the coating apparatus 5.
Second photographing unit 712The lower layer film formation processing is performed on the wafer W.
The coating apparatus 5 further includes a heat treatment unit 21 for performing heat treatment after the formation of the SOC film F4 as the lower layer film.
The coating device 5 is provided with a control unit 81.
The control unit 81 is a computer having a CPU, a memory, and the like, for example, and has a program storage unit (not shown). The program storage unit stores programs and the like for controlling operations of drive systems of various units, a transport device (not shown), and the like to perform various processes on the wafer W. The program may be stored in a computer-readable storage medium, and installed from the storage medium to the control unit 81. Part or all of the program may be implemented by dedicated hardware (circuit board).
The control unit 81 includes a storage unit 81a, an image generation unit 81b, and an estimation unit 81 c.
The storage section 81a stores various information. The storage unit 81a stores, for example, an estimation model of the thickness of the underlayer film, which is generated in advance by the model generation unit 62 of the overall control device 4.
The image generator 81b generates a captured image of the wafer W based on the result of imaging of the wafer W by the imaging mechanism 210 of the imaging unit 71. Specifically, a captured image of the wafer W in an initial state and a captured image of the wafer W after the lower layer film is formed are generated.
The captured image generated by the image generator 81b is basically stored in the storage 81a for each wafer W.
The estimation unit 81c estimates the thickness of the lower layer film formed by the coating device 5, for each of the 437 regions of the wafer W, based on the pixel values in the captured image of the wafer W in the initial state, the pixel values in the captured image of the wafer W after the lower layer film is formed, and a previously generated estimation model of the thickness of the lower layer film. That is, the estimating unit 81c estimates the in-plane distribution of the thickness of the underlayer film formed by the coating apparatus 5. The above-described estimation model generation method is the same as that of the first embodiment.
The feature amount estimated by the estimation unit 81c is stored in the storage unit 81a for each wafer W.
In the present embodiment, when the estimation unit 41c of the coating and developing device 2a estimates the in-plane distribution of the thickness of the intermediate layer, the in-plane distribution of the estimated thickness of the lower layer film used for the estimation is acquired from, for example, the coating device 5. When the thickness of the resist film and the resist pattern are estimated by the estimation unit 41c of the coating and developing apparatus 2a, the in-plane distribution of the estimated thickness of the lower layer film used for the estimation is obtained from, for example, the coating apparatus 5 in the same manner.
In the present embodiment, when the in-plane distribution of the estimated thickness of the underlayer film is required when the etching process conditions are determined, the information on the in-plane distribution of the estimated thickness is acquired by the acquisition unit 63 from, for example, the coating apparatus 5.
In the present embodiment, when the correction of the process conditions in the coating and developing device 2a and the coating device 5 by the process condition correction unit 65 requires the in-plane distribution of the estimated thickness of the underlayer coating, the acquisition unit 63 acquires information on the in-plane distribution of the estimated thickness from, for example, the coating device 5.
(third embodiment)
Fig. 11 is a diagram schematically showing the schematic configuration of a substrate processing system according to a third embodiment.
As shown in the figure, the processing system 1b as the substrate processing system of the present embodiment includes film forming apparatuses 6a, 6b, and 6c, image pickup apparatuses 7a, 7b, 7c, and 7d, and a polishing apparatus 8 in addition to the coating and developing apparatus 2, the etching apparatus 3, and the overall control apparatus 4.
The film forming apparatuses 6a, 6b, and 6c form individual layers constituting the laminated film by a vapor deposition method such as a CVD method or an ALD method. The film forming apparatus 6a forms the TiN film F2 shown in FIG. 2 on the wafer W, for example, and the film forming apparatus 6b forms the LTO film F3 shown in FIG. 2 on the wafer W, for example. The film formation apparatus 6C forms a Cu film as a metal wiring layer on the wafer W in the state shown in fig. 7 (C) after etching by the etching apparatus 3, for example.
The imaging devices 7a, 7b, 7c, and 7d have imaging units 91a, 91b, 91c, and 91 having substantially the same configurations as the imaging unit 31, respectively, and the film forming devices 6a, 6b, and 6c, the coating and developing device 2, and other semiconductor manufacturing devices are provided separately.
The imaging unit 91a is used for imaging the wafer W before being carried into the film formation apparatus 6a, i.e., before the TiN film formation process.
The imaging unit 91b is used for imaging the wafer W after the TiN film formation process by the film formation apparatus 6a and before the wafer W is sent to the film formation apparatus 6 b.
The imaging unit 91c is used for imaging the wafer W after the LTO film formation process by the film formation device 6 b.
The imaging unit 91d is used for imaging the wafer W after the Cu film formation process by the film formation apparatus 6 c.
The imaging devices 7b to 7d are provided with control units 101 to 103, respectively.
The control units 101, 102, 103 have storage units 101a, 102a, 103a similar to the storage units 41a, 81a of the control units 41, 81, image generation units 101b, 102b, 103b similar to the image generation units 41b, 81b, and estimation units 101c, 102c, 103c similar to the estimation units 41c, 81 c.
As in the estimating units 41c and 81c of the first and second embodiments, the estimating unit 101c estimates the thickness of the TiN film formed by the film forming apparatus 6a, for example, for each of the 437 regions of the wafer W, based on the pixel values in the captured image of the wafer W before the TiN film formation process, the pixel values in the captured image of the wafer W after the TiN film formation, and a previously generated model for estimating the thickness of the TiN film. That is, the estimating unit 101c estimates the in-plane distribution of the thickness of the TiN film formed by the film forming apparatus 6 a.
Similarly, the estimating unit 102c estimates the thickness of the LTO film formed by the film forming apparatus 6b, for example, for each of the 437 regions of the wafer W, based on the estimated thickness of the TiN film, the pixel value in the captured image of the wafer W after LTO film formation, and a previously generated estimation model of the thickness of the LTO film.
Similarly, the estimation unit 103c estimates the thickness of the Cu film formed by the film formation device 6c, for example, for each of the 437 regions of the wafer W, based on the pixel values in the captured image of the wafer W before the Cu film formation process, the pixel values in the captured image of the wafer W after the Cu film formation, and the like.
The method of generating the estimation model used in the estimation units 101c, 102c, and 103c is the same as the estimation model of the thickness of the underlayer film and the estimation model of the thickness of the interlayer film in the first embodiment.
The polishing apparatus 8 is an apparatus for polishing the wafer W to remove an unnecessary film. For example, the polishing apparatus 8 removes an unnecessary portion of the Cu layer formed by the film formation apparatus 6 c.
In the present embodiment, the acquiring unit 63 of the overall controller 4 also acquires information indicating the estimated thickness of the TiN film and information indicating the estimated thickness of the Cu film of the wafer W to be processed from the imaging devices 7b and 7 c.
Then, the processing condition determining unit 64 determines the polishing processing conditions in the polishing apparatus 8 based on the information indicating the estimated thickness of the TiN film and the information indicating the estimated thickness of the Cu film of the wafer W to be processed, which are acquired by the acquiring unit 63. The polishing conditions include, for example, a polishing pressure, a polishing track of a polishing disk, and the like.
For example, when the estimated thickness of the Cu film is the same in the wafer plane and the estimated thickness of the TiN film is larger than the desired thickness only at the wafer peripheral edge, the Cu layer is easily removed at the wafer peripheral edge, and therefore, when the polishing pressure and the polishing time are made the same in the wafer plane, the thickness of the Cu layer after polishing becomes different in the wafer plane. Therefore, in the above case, the processing condition determining unit 64 sets a large polishing pressure at the wafer center, or adjusts the polishing trajectory so that the polishing time at the wafer center is increased, for example.
In the present embodiment, the polishing treatment can be appropriately performed.
In the processing system 1B, the apparatus for estimating the characteristic amount of the processed wafer W may transmit the following information (a) and (B) to an apparatus for estimating the characteristic amount of the processed wafer W similarly to the process downstream of the apparatus to be estimated (for example, the imaging apparatus 7B may transmit the information to the imaging apparatus 7c, or the imaging apparatus 7c may transmit the information to the coating and developing apparatus 2).
(A) The estimation model is information on the in-plane distribution of pixel values in the captured image of the wafer W used in the apparatus and on the correlation between the pixel values and the feature values
(B) Comparing the in-plane distribution of the pixel values used in the same estimation device with the estimation model for the process of the device on the upstream side of the estimation object
Then, the in-plane distribution of the pixel values in the captured image of the wafer W and the above estimation model are stored in association with the corresponding layer.
In the present embodiment, after the processes of the film formation devices 6a to 6c, the wafers W are imaged by the imaging devices 7b to 7d, and the process results of the film formation devices 6a to 6c are estimated using the images obtained based on the imaging results. Similarly, after the processing by the etching apparatus 3 and the polishing apparatus 8, the wafer W is imaged by the imaging apparatus, and the processing result by the etching apparatus 3 and the processing result by the polishing apparatus 8 are estimated using the imaging image based on the imaging result. The processing result of the etching device 3 is, for example, the size of the line width of the pattern after etching, and the processing result of the polishing device 8 is, for example, the polishing amount of the Cu layer.
In the above example, when the feature values are estimated for each of the second and subsequent layers on the wafer W, the film thicknesses in the respective regions of the respective layers are used as the feature values of the respective layers on the wafer W before the processing related to the film to be estimated. However, the characteristic amount of each layer is not limited to this, and for example, the thickness of each layer may be averaged in the plane.
In the above description, when estimating the characteristic amount of the laminated film on the wafer W formed by the semiconductor manufacturing apparatus (the coating and developing apparatuses 2 and 2a) having the spin coating unit, only the information indicating the estimated characteristic amount of the layer processed by the semiconductor manufacturing apparatus (the coating and developing apparatuses 2 and 2a and the coating apparatus 5) having the spin coating unit is used. However, when estimating the characteristic amount of the laminated film on the wafer W formed by the semiconductor manufacturing apparatus (the coating and developing apparatuses 2 and 2a, and the coating apparatus 5) having the spin coating unit, information indicating the estimated characteristic amount of the layer formed by the CVD method or the ALD method in the previous step of the semiconductor manufacturing apparatus may be used. In addition, information indicating the estimated characteristic amount of the layer etched in the step before the semiconductor manufacturing apparatus may be used.
In the above example, the processing condition determining unit 64 adjusts the processing conditions within the surface of the wafer W. However, when the estimation result of the feature amount differs between wafers or between lots, the processing condition determination unit 64 may adjust the processing conditions for each wafer W or for each lot.
Similarly, when the estimation result of the feature amount differs between wafers W or between lots, the processing condition correction unit 65 may correct the processing condition for each wafer W or for each lot.
In the above example, the captured image of the wafer W before the process related to the film is not used when the feature value is estimated for the film of the second layer or later on the wafer W, but the captured image of the wafer W before the process related to the film may be used. For example, when the thickness of the resist film is estimated, not only the captured image of the wafer W after the resist film formation, but also the captured image of the wafer W before the resist film formation, that is, after the intermediate layer film formation, the captured image of the wafer W after the lower layer film formation, the captured image of the wafer W in an initial state, and the like may be used. For example, when the line width of the resist pattern is estimated, not only the captured image of the wafer W after the resist pattern is formed, but also the captured image of the wafer W before the resist pattern is formed, that is, after the resist film is formed, the captured image of the wafer W after the intermediate layer film is formed, the captured image of the wafer W after the lower layer film is formed, the captured image of the wafer W in an initial state, and the like may be used. In the third embodiment, for the estimation of the thickness of the resist film and the line width of the resist pattern, the photographed image of the wafer W after the LTO film formation and the photographed image of the wafer W after the TiN film formation may be used.
This enables estimation of a feature amount that more accurately reflects the past processing state.
In the figure, the overall control device 4 is provided separately from the semiconductor manufacturing apparatus such as the coating and developing apparatus 2 and the imaging devices 7a to 7 d. However, a part or all of the functions of the overall control device 4 may be incorporated in a semiconductor manufacturing apparatus such as the coating and developing apparatus 2, the image pickup devices 7a to 7d, and the like.
The functions of the image generating unit and the estimating unit provided in the coating and developing apparatus 2, the imaging devices 7b to 7d, and the like may be incorporated in the overall control apparatus 4 and the like.
The embodiments disclosed herein are illustrative in all respects and should not be considered restrictive. The above-described embodiments may be omitted, replaced, or changed in various ways without departing from the scope and spirit of the appended claims.
The following configurations also fall within the technical scope of the present invention.
(1) A method of processing a substrate, comprising:
a step of generating a captured image of the substrate after processing relating to each layer of the laminated film on the substrate; and
and acquiring information indicating the characteristic amount estimated based on the captured image for each of a plurality of layers including the outermost layer of the laminated film on the substrate.
According to the above (1), the processing conditions for the substrate having the laminated film and the like can be appropriately set.
(2) In the substrate processing method described in (1), the information indicating the feature amount is at least one of information of the feature amount itself and information of a pixel value in the captured image related to the feature amount.
(3) In the substrate processing method according to the above (2),
the information indicating the feature amount includes information of a pixel value in the captured image related to the feature amount,
the substrate processing method further includes a step of acquiring correlation information indicating a correlation between the characteristic amount and the pixel value.
(4) The method for treating a substrate according to any one of (1) to (3) above,
the method includes a step of determining conditions for processing the substrate on which the laminated film is formed, based on the acquisition result in the step of acquiring the information indicating the characteristic amount.
(5) In the substrate processing method according to the above (4),
the process for the substrate on which the laminated film is formed is an etching process.
(6) In the substrate processing method according to the above (4) or (5),
the treatment of the substrate on which the laminated film is formed is a polishing treatment.
(7) The method for treating a substrate according to any one of (1) to (6) above,
includes a step of correcting the conditions of the processing relating to the layer constituting the laminated film on the substrate based on the acquisition result in the step of acquiring the information representing the characteristic amount.
(8) The method for treating a substrate according to any one of (1) to (7) above,
the laminated film is formed using a plurality of semiconductor manufacturing apparatuses.
(9) In the substrate processing method described in the above (8),
the plurality of semiconductor manufacturing apparatuses include a plurality of semiconductor manufacturing apparatuses having spin coating units for applying a processing liquid to a substrate by a spin coating method.
(10) The method for processing a substrate according to the above (8) or (9),
the plurality of semiconductor manufacturing apparatuses include:
a semiconductor manufacturing apparatus having a spin coating unit for forming a single layer constituting the laminated film by a spin coating method; and
and a film forming device for forming the single layer of the laminated film by a vapor deposition method.
(11) The method for treating a substrate according to any one of (1) to (10) above,
further comprising a step of imaging, with an imaging unit, a surface of the substrate in a state where no other layer is formed on each layer constituting the laminated film on the substrate after the treatment related to the layer,
the above-described photographing units all have substantially the same structure.
(12) The method for processing a substrate according to item (11) above,
the imaging unit is provided separately for each layer of the laminated film,
the shooting units respectively use the same type of light source and camera to shoot.
(13) The substrate processing method according to any one of the above (1) to (10), further comprising:
a step of imaging, with an imaging unit, a surface of the substrate in a state where no other layer is formed on each layer constituting the laminated film on the substrate after the treatment related to the layer; and
a step of subjecting any one of the layers constituting the laminated film on the substrate to exposure treatment by an exposure device,
the imaging of one layer of the laminated film on the substrate is performed for a time not exceeding a time from when the substrate is fed into the exposure apparatus to when the substrate is fed out from the exposure apparatus after the exposure process is completed.
(14) A substrate processing system, comprising:
a semiconductor manufacturing apparatus;
a shooting unit;
an image generating unit that acquires a captured image of each layer constituting a laminated film on a substrate based on a result of imaging of the substrate after processing relating to the layer by the imaging unit; and
and an acquisition unit that acquires information indicating a feature amount estimated based on the captured image, for each of a plurality of layers including an outermost layer of the laminated film on the substrate.
(15) In the substrate processing system described in the above (14),
the above-described imaging unit is provided for each process related to the layer constituting the laminated film on the substrate.
(16) In the substrate processing system according to the above (14) or (15),
at least a part of the imaging unit is provided in a separate apparatus from the semiconductor manufacturing apparatus.

Claims (16)

1. A method of processing a substrate, comprising:
a step of generating a captured image of the substrate after processing relating to each layer of the laminated film on the substrate; and
and acquiring information indicating a feature amount estimated based on the captured image for each of a plurality of layers including an outermost layer of the laminated film on the substrate.
2. The substrate processing method according to claim 1, wherein:
the information indicating the feature amount is at least one of information of the feature amount itself and information of a pixel value in the captured image related to the feature amount.
3. The substrate processing method according to claim 2, wherein:
the information representing the feature amount includes information of a pixel value in the captured image relating to the feature amount,
the substrate processing method further includes a step of acquiring correlation information representing a correlation of the feature quantity with the pixel value.
4. The substrate processing method according to claim 1, wherein:
the method includes a step of determining conditions for processing the substrate on which the laminated film is formed, based on the acquisition result in the step of acquiring information indicating the characteristic amount.
5. The substrate processing method according to claim 4, wherein:
the process for the substrate on which the laminated film is formed is an etching process.
6. The substrate processing method according to claim 4 or 5, wherein:
the treatment of the substrate on which the laminated film is formed is a polishing treatment.
7. The substrate processing method according to any one of claims 1 to 5, wherein:
includes a step of correcting the conditions of processing relating to the layers constituting the laminated film on the substrate based on the acquisition result in the step of acquiring information representing the characteristic amount.
8. The substrate processing method according to any one of claims 1 to 5, wherein:
the laminated film is formed using a plurality of semiconductor manufacturing apparatuses.
9. The substrate processing method according to claim 8, wherein:
the plurality of semiconductor manufacturing apparatuses include a plurality of semiconductor manufacturing apparatuses having spin coating units that apply a processing liquid to a substrate by a spin coating method.
10. The substrate processing method according to claim 8, wherein:
the plurality of semiconductor manufacturing apparatuses includes:
a semiconductor manufacturing apparatus having a spin coating unit that forms a single layer constituting the laminated film by a spin coating method; and
and a film forming device for forming the single layer of the laminated film by a vapor deposition method.
11. The substrate processing method according to any one of claims 1 to 5, wherein:
further comprising a step of imaging, with an imaging unit, a surface of the substrate in a state where no other layer is formed on each layer constituting the laminated film on the substrate after the treatment related to the layer,
the photographing units all have substantially the same structure.
12. The substrate processing method of claim 11, further comprising:
the photographing unit is separately provided for each layer of the laminated film,
the photographing units respectively use the same kind of light source and camera to perform photographing.
13. The substrate processing method according to any one of claims 1 to 5, further comprising:
a step of imaging, with an imaging unit, a surface of the substrate in a state where no other layer is formed on each layer constituting the laminated film on the substrate after the treatment related to the layer; and
a step of subjecting any one of the layers constituting the laminated film on the substrate to exposure treatment by an exposure device,
the imaging of one layer of the laminated film on the substrate is performed for a time not exceeding a time from when the substrate is fed into the exposure apparatus to when the substrate is fed out from the exposure apparatus after the exposure process is completed.
14. A substrate processing system, comprising:
a semiconductor manufacturing apparatus;
a shooting unit;
an image generating unit that acquires a captured image of each layer constituting a laminated film on a substrate, based on a result of imaging of the substrate after processing relating to the layer by the imaging unit; and
and an acquisition unit that acquires information indicating a feature amount estimated based on the captured image for each of a plurality of layers including an outermost layer of the laminated film on the substrate.
15. The substrate processing system of claim 14, wherein:
the imaging unit is provided for each process related to a layer constituting the laminated film on the substrate.
16. The substrate processing system of claim 14 or 15, wherein:
at least a part of the imaging unit is provided in a separate device from the semiconductor manufacturing apparatus.
CN202011436803.3A 2019-12-17 2020-12-10 Substrate processing method and substrate processing system Pending CN113075867A (en)

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