JP7510123B2 - Semiconductor Device - Google Patents

Description

The present invention relates to a semiconductor device that is useful for power devices, etc.

As a next-generation switching element capable of realizing high voltage resistance, low loss, and high heat resistance, semiconductor devices using gallium oxide (Ga ₂ O ₃ ) with a large band gap have been attracting attention, and are expected to be applied to power semiconductor devices such as inverters. In addition, due to the wide band gap, a wide range of applications as light receiving and emitting devices such as LEDs and sensors are also expected. In particular, according to Non-Patent Document 1, α-Ga ₂ O ₃ and the like having a corundum structure among gallium oxides can control the band gap by forming a mixed crystal with indium and aluminum, respectively or in combination, and constitutes an extremely attractive material system as an InAlGaO-based semiconductor. Here, InAlGaO-based semiconductors refer to In _x Al _y Ga _{zo 3} (0≦X≦2, 0≦Y≦2, 0≦Z≦2, X+Y+Z=1.5-2.5) (Patent Document 9, etc.), and can be viewed as the same material system containing gallium oxide.

However, since the most stable phase of gallium oxide is the β-gallium structure, it is difficult to form a crystalline film with the corundum structure, which is a metastable phase, unless a special film formation method is used. For example, the crystal growth conditions are often restricted in heteroepitaxial growth, etc., which tends to result in a high dislocation density. Furthermore, many challenges remain, not only in the formation of crystalline films with a corundum structure, but also in improving the film formation rate and crystal quality, suppressing cracks and abnormal growth, suppressing twins, and preventing substrate cracking due to warping. Under these circumstances, several studies are currently being conducted on the formation of crystalline semiconductors with a corundum structure.

Patent Document 1 describes a method for producing an oxide crystal thin film by mist CVD using gallium or indium bromide or iodide. Patent Documents 2 to 4 describe a multilayer structure in which a semiconductor layer having a corundum crystal structure and an insulating film having a corundum crystal structure are laminated on a base substrate having a corundum crystal structure. In addition, as in Patent Documents 5 to 7, film formation by mist CVD using an ELO substrate or void formation is also considered.
Patent Document 8 describes that a gallium oxide film having a corundum structure is formed by halide vapor phase epitaxy (HVPE) using at least a gallium raw material and an oxygen raw material. Patent Documents 10 and 11 describe that a PSS substrate is used to perform ELO crystal growth, and a crystal film having a surface area of 9 μm ² or more and a transition density of 5×10 ⁶ cm ⁻² is obtained. However, gallium oxide has a problem with heat dissipation, and in order to solve the problem of heat dissipation, for example, it is necessary to thin the film thickness of gallium oxide to 30 μm or less, but there is a problem that the polishing process becomes complicated and the cost increases, and there is also a problem that the adhesion between the electrode and the semiconductor layer is not good in the first place. In addition, the series resistance in the case of a vertical device was not fully satisfactory. Therefore, in order to fully utilize the performance of gallium oxide as a power device, it is desirable to obtain a gallium oxide film having even better crystal quality, and a new semiconductor device has been awaited.
It should be noted that Patent Documents 1 to 11 are all publications related to patents or patent applications filed by the present applicants, and are currently under investigation.

Patent No. 5397794 Patent No. 5343224 Patent No. 5397795 JP 2014-72533 A JP 2016-100592 A JP 2016-98166 A JP 2016-100593 A JP 2016-155714 A International Publication No. 2014/050793 US Publication No. 2019/0057865 JP 2019-034883 A

Kentaro Kaneko, "Growth and properties of corundum-structured gallium oxide alloy thin films", Doctoral dissertation, Kyoto University, March 2013

The object of the present invention is to provide a semiconductor device with excellent semiconductor characteristics such as voltage resistance.

As a result of intensive research into achieving the above object, the inventors discovered that by performing ELO under specific conditions, a semiconductor device with excellent breakdown voltage and other properties can be easily obtained, and that such a semiconductor device can solve all of the above-mentioned conventional problems at once.

After obtaining the above findings, the inventors conducted further research and completed the present invention.

That is, the present invention relates to the following inventions.
A vertical semiconductor device including an insulating substrate, a dielectric film, and a semiconductor layer, wherein the dielectric film and the semiconductor layer are stacked on the insulating substrate, and the insulating substrate is a crystalline substrate having the same crystal structure as the semiconductor layer.
The semiconductor device as described above, wherein the semiconductor layer is a laterally grown layer.
The semiconductor device, wherein the semiconductor layer includes a first semiconductor region and a second semiconductor region, the first semiconductor region is in contact with the dielectric, and the second semiconductor region includes more dislocations than the first semiconductor region.
The semiconductor device as described above, wherein the semiconductor layer has a thickness of 1 μm or more.
The semiconductor device as described above, wherein the semiconductor layer has a corundum structure.
The semiconductor device, wherein the dielectric film extends in the c-axis direction.
The semiconductor device as described above, wherein the semiconductor layer contains at least gallium.
The semiconductor device as described above, wherein the dielectric film is a gate insulating film.
A vertical semiconductor device including an insulating substrate, a dielectric film, a first semiconductor layer, and a second semiconductor layer, wherein the dielectric film, the first semiconductor layer, and the second semiconductor layer are stacked on the insulating substrate, and the insulating substrate is a crystalline substrate having the same crystal structure as the first semiconductor layer.
The semiconductor device as described above, wherein the first semiconductor layer has a crystal structure including a c-axis, and the dielectric film extends in the c-axis direction.
The semiconductor device, characterized in that the first semiconductor layer includes a first semiconductor region and a second semiconductor region, the second semiconductor layer includes a first semiconductor region and a second semiconductor region, the first semiconductor region of the first semiconductor layer is joined to the dielectric film, and the first semiconductor region in the first semiconductor layer has fewer dislocations than the second semiconductor region.
The semiconductor device as described above, wherein the dielectric film is a gate insulating film.
The semiconductor device is a MOSFET.
The semiconductor device is a power device.
A semiconductor system including the semiconductor device.

The semiconductor device of the present invention has excellent semiconductor properties such as voltage resistance.

1A to 1C are schematic diagrams illustrating a part of a preferred manufacturing process for the semiconductor device of the present invention. FIG. 1 is a diagram illustrating a halide vapor phase epitaxy (HVPE) apparatus preferably used in the present invention. FIG. 2 is a schematic diagram showing one embodiment of a concave-convex portion formed on the surface of a substrate suitably used in the present invention. FIG. 1 is a diagram illustrating a mist CVD apparatus preferably used in the present invention. FIG. 1 is a diagram illustrating a preferred example of a power supply system. FIG. 1 is a diagram illustrating a preferred example of a system device. FIG. 1 is a diagram illustrating a preferred example of a power supply circuit diagram of a power supply device. 1A and 1B are diagrams illustrating a preferred example of a semiconductor device bonded to a lead frame, a circuit board, or a heat dissipation board. FIG. 2 is a diagram showing a schematic diagram of a preferred example of a power card. 1 shows a TEM image in an embodiment of the present invention. As an embodiment of the present invention, a main part of an example of a semiconductor device is shown. As an embodiment of the present invention, a main part of an example of a semiconductor device is shown.

The semiconductor device of the present invention is a vertical semiconductor device including an insulating substrate (hereinafter also referred to as a "crystal substrate" or "crystal growth substrate"), a dielectric film, and a semiconductor layer, and is characterized in that the dielectric film and the semiconductor layer are laminated on the insulating substrate, and the insulating substrate is a crystal substrate having the same crystal structure as the semiconductor layer. To obtain such a semiconductor device, for example, a method is preferably used in which an ELO mask extending in the c-axis direction of an insulating substrate having a corundum structure is formed on the insulating substrate, and the ELO mask is grown laterally to form a semiconductor layer made of a crystal film. Note that the "vertical semiconductor device" is also called a vertical device, and refers to a semiconductor device in which the direction of current flow is vertical. In addition, "extending in the c-axis direction" may mean that the entire ELO mask extends in the c-axis direction, or that a part of the ELO mask extends in the c-axis direction. In addition, the "c-axis direction" is not particularly limited as long as it is a direction perpendicular to the c-plane in this embodiment. Examples of the crystal structure including the c-axis include a corundum structure. By adopting such a structure, in the present invention, a semiconductor device having a good bonding state at the interface with the semiconductor layer, good crystallinity of the channel layer, and excellent semiconductor characteristics can be obtained. As one embodiment of the present invention, it is preferable that the electrode is used as the ELO mask, and the electrode is a Schottky electrode. It is also preferable that the gate insulating film is used as the ELO mask, and the gate insulating film is formed on the crystal substrate so as to cover the gate electrode. It is also preferable that the thickness of the semiconductor layer is 1 μm or more. It is also preferable that the semiconductor layer includes a dislocation-free semiconductor region having a cross-sectional area of 1 ^μm2 or more. The semiconductor layer may include mixed dislocations. It is also preferable that the semiconductor layer has a corundum structure, and it is also preferable that the semiconductor layer includes at least gallium. Examples of the above-mentioned preferable semiconductor devices include the semiconductor device shown in FIG. 11 or FIG. 12. According to such a semiconductor device, a better interface can be formed, and semiconductor characteristics such as a better channel layer or drift layer can be exhibited. More specifically, FIG. 11 is a diagram showing a main part of a MOSFET, and the MOSFET in FIG. 11 includes at least a substrate 11, an electrode (gate electrode) 14, a dielectric film (gate insulating film) 15, a semiconductor layer (channel layer) 18, an n-type semiconductor layer 18a, and an n+ type semiconductor layer 18b. In the present invention, by using a gate insulating film as an ELO mask, the channel layer can be preferably made a dislocation-free layer, and more excellent semiconductor characteristics can be exhibited. FIG. 12 is a diagram showing a main part of an SBD, and the SBD in FIG. 12 includes at least a substrate 11, an electrode (Schottky electrode) 14, a semi-insulating layer 16, and an n-type semiconductor layer 18a. The substrate 11 is an insulating substrate, and a through-hole electrode (not shown) continuing to the Schottky electrode is provided. In the present invention, by using the Schottky electrode material in the ELO mask as a Schottky electrode, not only can the Schottky junction be improved, but also, preferably, the drift layer near the Schottky interface can be made into a dislocation-free layer, thereby enabling more excellent semiconductor characteristics to be exhibited.

The semiconductor device of the present invention is a vertical device, but since it has an insulating substrate, it is preferable to provide a through hole using a conventional method such as laser drilling, drilling, punching, or laser, and then form a through-hole electrode using a conventional method such as wet plating or mist CVD. Such an insulating substrate with a through-hole electrode is also included in the present invention.

The dielectric film is not particularly limited and may be a known dielectric film. The dielectric constant of the dielectric film is not particularly limited, but it is preferable that the dielectric constant is 5 or less. The "dielectric constant" is the ratio of the dielectric constant of the film to the dielectric constant of a vacuum. Examples of the dielectric film include oxide films, phosphorus oxide films, and nitride films, but in the present invention, it is preferable that the dielectric film is a film containing Si. A suitable example of the film containing Si is a silicon oxide film. Examples of the silicon oxide film include SiO ₂ film, phosphorus-added SiO ₂ (PSG) film, boron-added SiO ₂ film, phosphorus-boron-added SiO ₂ film (BPSG film), SiOC film, and SiOF film. The means for forming the dielectric film is not particularly limited, but examples include CVD, atmospheric CVD, plasma CVD, mist CVD, and thermal oxidation. In the present invention, it is preferable that the means for forming the dielectric film is mist CVD or atmospheric CVD. In addition, the thickness of the dielectric film is not particularly limited, but it is preferable that at least a part of the insulator film has a thickness of 1 μm or more. According to the present invention, even when such a thick dielectric film is laminated on the semiconductor layer, it is possible to more suitably obtain a film free from crystal defects due to stress concentration in the semiconductor layer.

The semiconductor layer (hereinafter, simply referred to as "oxide semiconductor film" or "semiconductor film") is preferably an oxide having a corundum structure. In the present invention, the oxide preferably contains one or more metals selected from Group 9 (e.g., cobalt, rhodium, or iridium) and Group 13 (e.g., aluminum, gallium, or indium) of the periodic table, more preferably contains at least one metal selected from aluminum, indium, gallium, and iridium, even more preferably contains at least gallium or iridium, and most preferably contains at least gallium. In the present invention, it is more preferable that the main surface of the oxide semiconductor film is an m-plane, since this can further suppress the diffusion of oxygen and the like and further improve the electrical characteristics. In addition, the oxide semiconductor film may have an off-axis angle. In the present invention, the oxide is preferably α-Ga ₂ O ₃ or a mixed crystal thereof. The term "main component" means that the oxide is preferably contained in an atomic ratio of 50% or more, more preferably 70% or more, and even more preferably 90% or more of the total components of the semiconductor layer, and may be 100%. The thickness of the semiconductor layer is not particularly limited and may be 1 μm or less or 1 μm or more, but in the present invention, it is preferably 1 μm or more, and more preferably 10 μm or more. The surface area of the semiconductor film is not particularly limited, but may be 1 mm ² or more or 1 mm ² or less, but is preferably 10 mm ² to 300 cm ² , and more preferably 100 mm ² to 100 cm ^2. The semiconductor film is preferably a single crystal film, but may be a polycrystalline film or a crystalline film containing polycrystals.

The semiconductor layer preferably contains a dopant. The dopant is not particularly limited and may be a known one. Examples of the dopant include n-type dopants such as tin, germanium, silicon, titanium, zirconium, vanadium, or niobium, or p-type dopants such as magnesium, calcium, or zinc. In the present invention, the semiconductor layer preferably contains an n-type dopant, and is more preferably an n-type oxide semiconductor layer. In the present invention, the n-type dopant is preferably Sn, Ge, or Si. The content of the dopant in the composition of the semiconductor layer is preferably 0.00001 atomic % or more, more preferably 0.00001 atomic % to 20 atomic %, and most preferably 0.00001 atomic % to 10 atomic %. More specifically, the dopant concentration may be generally about 1×10 ¹⁶ /cm ³ to 1×10 ²² /cm ³ , or may be a low concentration of, for example, about 1×10 ¹⁷ /cm ³ or less. According to one aspect of the present invention, the dopant may be contained at a high concentration of about 1×10 ²⁰ /cm ³ or more. The concentration of fixed charges in the semiconductor layer is not particularly limited, but in the present invention, it is preferable that the concentration is 1×10 ¹⁷ /cm ³ or less, because this allows a depletion layer to be formed well in the semiconductor layer.

The semiconductor layer may be formed using known techniques. Examples of techniques for forming the semiconductor layer include CVD, MOCVD, MOVPE, mist CVD, mist epitaxy, MBE, HVPE, pulse growth, and ALD.

Hereinafter, an example of a method for manufacturing the semiconductor device will be described, in which the semiconductor layer (hereinafter also referred to as the "crystal growth layer" or "crystal film") is formed using the HVPE method.

As one embodiment of the HVPE method, for example, a metal source containing a metal is gasified to form a metal-containing source gas using the HVPE apparatus shown in FIG. 2, and then the metal-containing source gas and the oxygen-containing source gas are supplied to a substrate in a reaction chamber to form a film. A crystal substrate having an ELO mask made of, for example, the electrode on its surface is used, and a reactive gas is supplied to the substrate, and the film is formed under the flow of the reactive gas.

(Metal Source)
The metal source is not particularly limited as long as it contains a metal and can be gasified, and may be a metal element or a metal compound. Examples of the metal include one or more metals selected from gallium, aluminum, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt, and iridium. In the present invention, the metal is preferably one or more metals selected from gallium, aluminum, and indium, more preferably gallium, and the metal source is most preferably gallium element. The metal source may be gas, liquid, or solid, but in the present invention, for example, when gallium is used as the metal, the metal source is preferably liquid.

The gasification means is not particularly limited and may be a known means as long as it does not impede the object of the present invention. In the present invention, the gasification means is preferably carried out by halogenating the metal source. The halogenating agent used for the halogenation is not particularly limited and may be a known halogenating agent as long as it can halogenate the metal source. Examples of the halogenating agent include halogen and hydrogen halide. Examples of the halogen include fluorine, chlorine, bromine, and iodine. Examples of the hydrogen halide include hydrogen fluoride, hydrogen chloride, hydrogen bromide, and hydrogen iodide. In the present invention, it is preferable to use hydrogen halide for the halogenation, and more preferably hydrogen chloride. In the present invention, it is preferable to carry out the gasification by supplying a halogen or hydrogen halide as a halogenating agent to the metal source and reacting the metal source with the halogen or hydrogen halide at a temperature higher than the vaporization temperature of the metal halide to form a metal halide. The halogenation reaction temperature is not particularly limited, but in the present invention, for example, when the metal source metal is gallium and the halogenating agent is HCl, the temperature is preferably 900°C or less, more preferably 700°C or less, and most preferably 400°C to 700°C. The metal-containing source gas is not particularly limited as long as it is a gas containing the metal source metal. Examples of the metal-containing source gas include halides of the metal (fluorides, chlorides, bromides, iodides, etc.).

In an embodiment of the present invention, a metal source containing a metal is gasified to obtain a metal-containing source gas, and then the metal-containing source gas and the oxygen-containing source gas are supplied onto the substrate in the reaction chamber. In another embodiment of the present invention, a reactive gas is supplied onto the substrate. Examples of the oxygen-containing source gas include _O2 gas, _CO2 gas, NO gas, _NO2 gas, _N2O gas, _H2O gas, and _O3 gas. In the present invention, the oxygen-containing source gas is preferably one or more gases selected from the group consisting of _O2 , _H2O , and _N2O , and more preferably contains _O2 . In one embodiment, the oxygen-containing source gas may contain _CO2 . The reactive gas is usually a gas with a different reactivity from the metal-containing source gas and the oxygen-containing source gas, and does not include an inert gas. The reactive gas is not particularly limited, but may be, for example, an etching gas. The etching gas is not particularly limited as long as it does not hinder the object of the present invention, and may be a known etching gas. In the present invention, the reactive gas is preferably a halogen gas (e.g., fluorine gas, chlorine gas, bromine gas, or iodine gas), a hydrogen halide gas (e.g., hydrofluoric acid gas, hydrochloric acid gas, hydrogen bromide gas, hydrogen iodide gas), hydrogen gas, or a mixed gas of two or more of these, and preferably contains a hydrogen halide gas, and most preferably contains hydrogen chloride. The metal-containing source gas, the oxygen-containing source gas, and the reactive gas may contain a carrier gas. Examples of the carrier gas include inert gases such as nitrogen and argon. The partial pressure of the metal-containing source gas is not particularly limited, but in the present invention, it is preferably 0.5 Pa to 1 kPa, and more preferably 5 Pa to 0.5 kPa. The partial pressure of the oxygen-containing source gas is not particularly limited, but in the present invention, it is preferably 0.5 times to 100 times the partial pressure of the metal-containing source gas, and more preferably 1 time to 20 times. The partial pressure of the reactive gas is not particularly limited, but in an embodiment of the present invention, it is preferably 0.1 to 5 times, and more preferably 0.2 to 3 times, the partial pressure of the metal-containing source gas.

In the embodiment of the present invention, it is also preferable to supply a dopant-containing source gas to the substrate. The dopant-containing source gas is not particularly limited as long as it contains a dopant. The dopant is also not particularly limited, but in the present invention, the dopant preferably contains one or more elements selected from germanium, silicon, titanium, zirconium, vanadium, niobium and tin, more preferably contains germanium, silicon or tin, and most preferably contains germanium. By using the dopant-containing source gas in this way, the conductivity of the obtained film can be easily controlled. The dopant-containing source gas preferably contains the dopant in the form of a compound (e.g., a halide, an oxide, etc.), more preferably in the form of a halide. The partial pressure of the dopant-containing source gas is not particularly limited, but in the present invention, it is preferably 1×10 ⁻⁷ to 0.1 times, and more preferably 2.5×10 ⁻⁶ to 7.5×10 ⁻² times, the partial pressure of the metal-containing source gas. Note that in the present invention, it is preferable to supply the dopant-containing source gas onto the substrate together with the reactive gas.

(Crystal Substrate)
In the present invention, the substrate is preferably a crystalline substrate. The crystalline substrate is an insulating substrate, and is not particularly limited as long as it is a substrate containing a crystalline substance as a main component, and may be a known substrate. It may be a single crystal substrate or a polycrystalline substrate. The crystalline substrate may be, for example, a substrate containing a crystalline substance having a corundum structure as a main component. The "main component" refers to a substrate containing the crystalline substance in a composition ratio of 50% or more, preferably 70% or more, and more preferably 90% or more.

Examples of substrates containing crystals having the corundum structure as a main component include sapphire substrates and undoped α-type gallium oxide substrates.

In an embodiment of the present invention, the crystal substrate is preferably a sapphire substrate. Examples of the sapphire substrate include an m-plane sapphire substrate and an a-plane sapphire substrate. In the present invention, the sapphire substrate is preferably an m-plane sapphire substrate. The sapphire substrate may have an off-angle. The off-angle is not particularly limited, but is preferably 0° to 15°. The thickness of the crystal substrate is not particularly limited, but is preferably 50 to 2000 μm, and more preferably 200 to 800 μm. The area of the crystal substrate is not particularly limited, but is preferably 15 cm ² or more, and more preferably 100 cm ² or more.

In one embodiment of the present invention, the crystal substrate preferably includes an ELO mask made of the dielectric film. By using such a dielectric film, the present invention can use it as a gate insulating film. In this case, the ELO mask usually includes a gate electrode. Examples of the electrode material of the gate electrode include the following electrode materials. By covering the gate electrode with the ELO mask, a semiconductor device having a channel layer with higher crystal quality, particularly a MOSFET, can be easily obtained. The constituent material of the ELO mask is not particularly limited and may be a known mask material. It may be an insulating material, a conductive material, or a semiconductor material. The constituent material may be amorphous, single crystal, or polycrystal. Examples of the constituent material of the convex portion include oxides, nitrides, or carbides of Si, Ge, Ti, Zr, Hf, Ta, Sn, etc., carbon, diamond, metal, and mixtures thereof. More specifically, examples of the material include a Si-containing compound containing SiO ₂ , SiN, or polycrystalline silicon as a main component, and a metal having a melting point higher than the crystal growth temperature of the crystalline oxide semiconductor (e.g., a noble metal such as platinum, gold, silver, palladium, rhodium, iridium, or ruthenium). The content of the constituent material is preferably 50% or more, more preferably 70% or more, and most preferably 90% or more in terms of composition ratio in the convex portion. The gate insulating film is not particularly limited as long as it does not impede the object of the present invention, and may be a known gate insulating film. Suitable examples of the gate insulating film include oxide films such as SiO ₂ , Si ₃ N ₄ , Al ₂ O ₃ , GaO, AlGaO, InAlGaO, AlInZnGaO ₄ , AlN, Hf ₂ O ₃ , SiN, SiON, MgO, GdO, and oxide films containing at least phosphorus.

The means for forming the ELO mask may be known means, such as known patterning processing means such as photolithography, electron beam lithography, laser patterning, and subsequent etching (e.g., dry etching or wet etching). The pitch interval of the pattern shape is not particularly limited, but in an embodiment of the present invention, it is preferably 100 μm or less, more preferably 0.5 μm to 50 μm, and most preferably 0.5 μm to 10 μm.

In one embodiment of the present invention, the crystal substrate preferably includes an ELO mask made of the electrode. The material of the ELO mask is not particularly limited, but is usually an electrode material. The electrode material is not particularly limited to the type of electrode as long as it has conductivity, but in the present invention, it is preferable to use the electrode material as an ohmic electrode and a Schottky electrode. The electrode material may be a known metal. The metal is preferably at least one metal selected from Groups 4 to 11 of the periodic table. Examples of metals in Group 4 of the periodic table include titanium (Ti), zirconium (Zr), and hafnium (Hf). Examples of metals in Group 5 of the periodic table include vanadium (V), niobium (Nb), and tantalum (Ta). Examples of metals in Group 6 of the periodic table include chromium (Cr), molybdenum (Mo), and tungsten (W). Examples of metals in Group 7 of the periodic table include manganese (Mn), technetium (Tc), and rhenium (Re). Examples of metals in Group 8 of the periodic table include iron (Fe), ruthenium (Ru), and osmium (Os). Examples of metals in Group 9 of the periodic table include cobalt (Co), rhodium (Rh), and iridium (Ir). Examples of metals in Group 10 of the periodic table include nickel (Ni), palladium (Pd), and platinum (Pt). Examples of metals in Group 11 of the periodic table include copper (Cu), silver (Ag), and gold (Au). The thickness of each of the metal layers is not particularly limited, but is preferably 0.1 nm to 10 μm, more preferably 5 nm to 500 nm, and most preferably 10 nm to 200 nm.

The electrode forming means is not particularly limited and may be a known means. Specific examples of the forming means include a dry method and a wet method. Examples of dry methods include sputtering, vacuum deposition, and CVD. Examples of wet methods include screen printing and die coating.

Below, an example of an embodiment of a crystal growth substrate (crystal substrate) suitable for use in the present invention is described with reference to the drawings.

3 shows an embodiment of the convex portion made of the ELO mask provided on the crystal growth surface of the crystal substrate preferably used in the present invention. The crystal substrate including the ELO mask in FIG. 3 is formed of a crystal substrate 1 and a convex portion 2a on the crystal growth surface 1a. The convex portion 2a is striped with respect to the crystal growth surface 1a and extends in the c-axis direction. The striped convex portions 2a are periodically arranged on the crystal growth surface 1a of the crystal substrate 1. The convex portions 2a are made of a silicon-containing compound such as _SiO2 , and can be formed by covering the gate electrode using a known means such as photolithography after the gate electrode is formed.

The width, height, and spacing of the protrusions are not particularly limited, but in the present invention, each is, for example, within the range of about 10 nm to about 1 mm, preferably about 10 nm to about 300 μm, and more preferably about 10 nm to about 10 μm.

In an embodiment of the present invention, a buffer layer including a stress relaxation layer or the like may be provided on the crystal substrate. In addition, in an embodiment of the present invention, the substrate may have the ELO mask on a part or all of the surface via the buffer layer, or may have the buffer layer via the ELO mask. The means for forming the buffer layer is not particularly limited and may be a known means. Examples of the forming means include a spray method, a mist CVD method, a HVPE method, an MBE method, a MOCVD method, and a sputtering method. A preferred embodiment for forming the buffer layer by a mist CVD method will be described in more detail below.

The buffer layer can be preferably formed, for example, by using a mist CVD apparatus as shown in FIG. 4 to atomize or turn the raw material solution into droplets (atomization process), transporting the resulting atomized droplets to the substrate using a carrier gas (transport process), and then thermally reacting the atomized droplets on a part or the entire surface of the substrate (buffer layer formation process). Note that in the present invention, the crystal growth layer can also be formed in a similar manner.

(Atomization process)
In the atomization step, the raw solution is atomized to obtain the atomized droplets. The atomization means for the raw solution is not particularly limited as long as it can atomize the raw solution, and may be a known means, but in the embodiment of the present invention, an atomization means using ultrasonic waves is preferable. The atomized droplets obtained using ultrasonic waves are preferable because they have an initial velocity of zero and float in the air, and are not sprayed like a spray, but are mist that floats in space and can be transported as a gas, so there is no damage due to collision energy, which is very suitable. The droplet size of the atomized droplets is not particularly limited, and may be droplets of about several mm, but is preferably 50 μm or less, and more preferably 0.1 to 10 μm.

(raw material solution)
The raw material solution is not particularly limited as long as it can be atomized and the buffer layer can be obtained by mist CVD. Examples of the raw material solution include an organic metal complex (e.g., acetylacetonate complex, etc.) of the atomization metal and an aqueous solution of a halide (e.g., fluoride, chloride, bromide, or iodide, etc.). The atomization metal is not particularly limited, and examples of such atomization metal include one or more metals selected from aluminum, gallium, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt, and iridium. In the present invention, the atomization metal preferably contains at least gallium, indium, or aluminum, and more preferably contains at least gallium. The content of the atomization metal in the raw material solution is not particularly limited as long as it does not hinder the object of the present invention, but is preferably 0.001 mol% to 50 mol%, and more preferably 0.01 mol% to 50 mol%.

It is also preferable that the raw material solution contains a dopant. By including a dopant in the raw material solution, the conductivity of the buffer layer can be easily controlled without ion implantation or the like and without destroying the crystal structure. In the present invention, the dopant is preferably tin, germanium, or silicon, more preferably tin or germanium, and most preferably tin. The concentration of the dopant may usually be about 1×10 ¹⁶ /cm ³ to 1×10 ²² /cm ³ , or the dopant concentration may be a low concentration of, for example, about 1×10 ¹⁷ /cm ³ or less, or the dopant may be contained at a high concentration of about 1×10 ²⁰ /cm ³ or more.

The solvent of the raw material solution is not particularly limited, and may be an inorganic solvent such as water, an organic solvent such as alcohol, or a mixed solvent of an inorganic solvent and an organic solvent. In the present invention, the solvent preferably contains water, more preferably water or a mixed solvent of water and alcohol, and most preferably water. More specifically, examples of the water include pure water, ultrapure water, tap water, well water, mineral water, hot spring water, spring water, fresh water, and seawater, but in the present invention, ultrapure water is preferred.

(Transportation process)
In the transport step, the atomized droplets are transported into the film-forming chamber by a carrier gas. The carrier gas is not particularly limited as long as it does not impede the object of the present invention, and suitable examples include oxygen, ozone, inert gas such as nitrogen or argon, or reducing gas such as hydrogen gas or forming gas. The type of carrier gas may be one type, but may be two or more types, and a dilution gas with a reduced flow rate (for example, a 10-fold dilution gas, etc.) may be further used as a second carrier gas. The supply point of the carrier gas may be not only one but also two or more. The flow rate of the carrier gas is not particularly limited, but is preferably 0.01 to 20 L/min, and more preferably 1 to 10 L/min. In the case of a dilution gas, the flow rate of the dilution gas is preferably 0.001 to 2 L/min, and more preferably 0.1 to 1 L/min.

(Buffer layer forming process)
In the buffer layer forming process, the atomized droplets are thermally reacted in a film forming chamber to form the buffer layer on the substrate. The thermal reaction may be performed as long as the atomized droplets react with heat, and the reaction conditions are not particularly limited as long as the object of the present invention is not hindered. In this process, the thermal reaction is usually performed at a temperature equal to or higher than the evaporation temperature of the solvent, but is preferably not too high (for example, 1000°C) or lower, more preferably 650°C or lower, and most preferably 400°C to 650°C. In addition, the thermal reaction may be performed under any atmosphere, such as a vacuum, a non-oxygen atmosphere, a reducing gas atmosphere, or an oxygen atmosphere, as long as the object of the present invention is not hindered. In addition, the thermal reaction may be performed under any condition, such as atmospheric pressure, pressurized pressure, or reduced pressure, but in the present invention, it is preferable to perform the thermal reaction under atmospheric pressure. The thickness of the buffer layer can be set by adjusting the formation time.

After forming the buffer layer as described above, the crystal growth layer is formed on the buffer layer by the method described above, which can further reduce defects such as tilt in the crystal growth layer and improve the film quality.

In addition, the buffer layer is not particularly limited, but in the present invention, it is preferable that it contains a metal oxide as a main component. Examples of the metal oxide include metal oxides containing one or more metals selected from aluminum, gallium, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt, and iridium. In the present invention, it is preferable that the metal oxide contains one or more elements selected from indium, aluminum, and gallium, more preferably contains at least indium and/or gallium, and most preferably contains at least gallium. As one embodiment of the present invention, the buffer layer may contain a metal oxide as a main component, and the metal oxide contained in the buffer layer may contain gallium and a smaller amount of aluminum than gallium. By using a buffer layer containing a smaller amount of aluminum than gallium, not only can crystal growth be improved, but also good high-temperature growth can be achieved. As one embodiment of the present invention, the buffer layer may contain a superlattice structure. By using a buffer layer containing a superlattice structure, not only can good crystal growth be achieved, but it is also easier to suppress warping during crystal growth. Here, the term "main component" means that the metal oxide is preferably contained in an atomic ratio of 50% or more, more preferably 70% or more, and even more preferably 90% or more of the total components of the buffer layer, and may be 100%. The crystal structure of the crystalline oxide semiconductor is not particularly limited, but in the present invention, it is preferably a corundum structure. In addition, the first lateral crystal growth layer and the buffer layer may each have the same or different main components as long as the object of the present invention is not hindered, but in the present invention, it is preferable that they are the same.

In the embodiment of the present invention, a metal-containing source gas, an oxygen-containing source gas, a reactive gas, and optionally a dopant-containing source gas are supplied onto the substrate on which the buffer layer may be provided, and a film is formed under the flow of the reactive gas. In the present invention, it is preferable that the film is formed on a heated substrate. The film formation temperature is not particularly limited as long as it does not impede the object of the present invention, but is preferably 900°C or less, more preferably 700°C or less, and most preferably 400°C to 700°C. In addition, the film formation may be performed under any atmosphere, such as a vacuum, a non-vacuum, a reducing gas atmosphere, an inert gas atmosphere, or an oxidizing gas atmosphere, as long as it does not impede the object of the present invention, and may be performed under any condition, such as normal pressure, atmospheric pressure, pressurized pressure, or reduced pressure, but in the embodiment of the present invention, it is preferable that the film is formed under normal pressure or atmospheric pressure. The film thickness can be set by adjusting the film formation time.

The crystal growth layer usually contains a crystalline metal oxide as a main component. Examples of the crystalline metal oxide include metal oxides containing one or more metals selected from aluminum, gallium, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt, and iridium. In the present invention, the crystalline metal oxide preferably contains one or more elements selected from indium, aluminum, and gallium, more preferably contains at least indium and/or gallium, and is most preferably crystalline gallium oxide or a mixed crystal thereof. In the crystal growth layer in the embodiment of the present invention, the term "main component" means that the crystalline metal oxide is preferably contained in an atomic ratio of 50% or more, more preferably 70% or more, and even more preferably 90% or more of the total components of the first lateral crystal growth layer, and may be 100%. In the embodiment of the present invention, a crystal growth film having a corundum structure can be obtained by forming the film using a substrate having a corundum structure as the substrate. The crystalline metal oxide may be single crystal or polycrystalline, but in the embodiment of the present invention, it is preferably single crystal. The upper limit of the thickness of the first lateral crystal growth layer is not particularly limited, but is, for example, 100 μm, and the lower limit of the thickness of the crystal growth layer is not particularly limited, but is preferably 1 μm, more preferably 10 μm, and most preferably 20 μm. In the present invention, the thickness of the first lateral crystal growth layer is preferably 3 μm to 100 μm, more preferably 10 μm to 100 μm, and most preferably 20 μm to 100 μm.

The preferred manufacturing method of the present invention will be described in more detail below with reference to the drawings.

An ELO mask extending in the c-axis direction is formed on the surface of the crystal growth substrate. It is preferable to use a sapphire substrate for the crystal growth substrate. In the present invention, it is preferable to use a sapphire substrate having an m-plane or an a-plane as the main surface as the sapphire substrate. FIG. 1(a) shows a sapphire substrate 1. As shown in FIG. 1(b), an ELO mask 5 is formed on the crystal growth surface of the sapphire substrate 1. The ELO mask 5 is not particularly limited as long as it extends in the c-axis direction, but has a stripe shape with respect to the crystal growth surface. A crystal growth layer is formed using the crystal growth substrate of FIG. 1(b), and a laminated structure of FIG. 1(c) is obtained. In the laminated structure (c), a crystal growth layer 8 is formed on a sapphire substrate 1 having an ELO mask 5 on its surface, and the region corresponding to the channel layer or drift layer is, for example, a dislocation-free region, and excellent semiconductor characteristics can be expressed.

In the present invention, it is also preferable that the ELO mask includes a Schottky electrode. By using the Schottky electrode as the ELO mask, a semiconductor device, particularly an SBD, having a better quality drift layer and Schottky interface can be easily obtained. In addition, examples of the electrode material in the electrode including the Schottky electrode include metals or alloys of two or more of the above metals, metal oxide conductive films such as tin oxide, zinc oxide, rhenium oxide, indium oxide, indium tin oxide (ITO), and indium zinc oxide (IZO), organic conductive compounds such as polyaniline, polythiophene, and polypyrrole, and mixtures thereof, but in the present invention, metals are preferred. As the metal, preferably, at least one metal selected from Groups 4 to 10 of the periodic table can be used. Examples of metals in Group 4 of the periodic table include titanium (Ti), zirconium (Zr), and hafnium (Hf). Examples of metals in Group 5 of the periodic table include vanadium (V), niobium (Nb), and tantalum (Ta). Examples of metals in Group 6 of the periodic table include chromium (Cr), molybdenum (Mo), and tungsten (W). Examples of metals in Group 7 of the periodic table include manganese (Mn), technetium (Tc), and rhenium (Re). Examples of metals in Group 8 of the periodic table include iron (Fe), ruthenium (Ru), and osmium (Os). Examples of metals in Group 9 of the periodic table include cobalt (Co), rhodium (Rh), and iridium (Ir). Examples of metals in Group 10 of the periodic table include nickel (Ni), palladium (Pd), and platinum (Pt). The method of forming the electrodes is not particularly limited, and they can be formed on the substrate according to a method appropriately selected from among wet methods such as printing, spraying, and coating, physical methods such as vacuum deposition, sputtering, and ion plating, and chemical methods such as CVD and plasma CVD, taking into consideration their suitability with the material.

The laminated structure can be particularly suitably used in semiconductor devices that include at least an electrode and a semiconductor layer, and is particularly useful in power devices. Examples of the semiconductor device include MOSFETs, transistors such as MIS and HEMTs, TFTs, Schottky barrier diodes that use semiconductor-metal junctions, PN or PIN diodes combined with other P layers, and light-emitting and receiving elements.

In addition to the above, the semiconductor device of the present invention is preferably used as a semiconductor device by bonding to a lead frame, a circuit board, or a heat dissipation substrate using a bonding member based on a conventional method, and is particularly preferably used as a power module, an inverter, or a converter, and further preferably used in a semiconductor system using a power supply device, etc. FIG. 8 shows a preferred example of the semiconductor device bonded to a lead frame, a circuit board, or a heat dissipation substrate. In the semiconductor device of FIG. 8, both sides of a semiconductor element 500 are bonded to a lead frame, a circuit board, or a heat dissipation substrate 502 by solder 501, respectively. By configuring in this way, a semiconductor device with excellent heat dissipation properties can be obtained. In the present invention, it is preferable that the periphery of the bonding member such as solder is sealed with resin.

The power supply device can be fabricated from the semiconductor device or as a power supply device including the semiconductor device by connecting to a wiring pattern or the like using a known method. FIG. 5 shows a power supply system 170 using a plurality of the power supplies 171 and 172 and a control circuit 173. As shown in FIG. 6, the power supply system can be used in a system device 180 by combining an electronic circuit 181 and a power supply system 182. An example of a power supply circuit diagram of a power supply device is shown in FIG. 7. FIG. 7 shows a power supply circuit of a power supply device consisting of a power circuit and a control circuit, in which a DC voltage is switched at high frequency by an inverter 192 (composed of MOSFETs A to D) to convert it to AC, then insulated and transformed by a transformer 193, rectified by a rectifier MOSFET 194, smoothed by a DCL 195 (smoothing coils L1, L2) and a capacitor, and a DC voltage is output. At this time, a voltage comparator 197 compares the output voltage with a reference voltage, and a PWM control circuit 196 controls the inverter 192 and the rectifier MOSFET 194 so as to obtain the desired output voltage.

In the present invention, the semiconductor device is preferably a power card, and includes a cooler and an insulating member. More preferably, the cooler is provided on both sides of the semiconductor layer via at least the insulating member, and most preferably, a heat dissipation layer is provided on both sides of the semiconductor layer, and the cooler is provided on the outside of the heat dissipation layer via at least the insulating member. Figure 9 shows a power card that is one of the preferred embodiments of the present invention. The power card in Figure 9 is a double-sided cooling type power card 201, and includes a refrigerant tube 202, a spacer 203, an insulating plate (insulating spacer) 208, a sealing resin part 209, a semiconductor chip 301a, a metal heat transfer plate (protruding terminal part) 302b, a heat sink and electrode 303, a metal heat transfer plate (protruding terminal part) 303b, a solder layer 304, a control electrode terminal 305, and a bonding wire 308. The thickness direction cross section of the refrigerant tube 202 has many flow paths 222 partitioned by many partition walls 221 extending in the flow path direction at a predetermined interval from each other. Such a suitable power card can achieve better heat dissipation and achieve higher reliability.

The semiconductor chip 301a is joined to the inner main surface of the metal heat transfer plate 302b with a solder layer 304, and the metal heat transfer plate (protruding terminal portion) 302b is joined to the remaining main surface of the semiconductor chip 301a with a solder layer 304, so that the collector electrode surface and emitter electrode surface of the IGBT are connected to the anode electrode surface and cathode electrode surface of the flywheel diode in a so-called inverse parallel manner. Examples of materials for the metal heat transfer plates (protruding terminal portions) 302b and 303b include Mo and W. The metal heat transfer plates (protruding terminal portions) 302b and 303b have a thickness difference that absorbs the thickness difference of the semiconductor chip 301a, and as a result, the outer surfaces of the metal heat transfer plates 302b and 303b are flat.

The resin sealing portion 209 is made of, for example, epoxy resin, and is molded to cover the side surfaces of the metal heat transfer plates 302b and 303b, and the semiconductor chip 301a is molded with the resin sealing portion 209. However, the outer main surfaces, i.e., the contact heat receiving surfaces, of the metal heat transfer plates 302b and 303b are completely exposed. The metal heat transfer plates (protruding terminal portions) 302b and 303b protrude from the resin sealing portion 209 to the right in FIG. 9, and the control electrode terminal 305, which is a so-called lead frame terminal, connects the gate (control) electrode surface of the semiconductor chip 301a on which an IGBT is formed, for example, to the control electrode terminal 305.

The insulating plate 208, which is an insulating spacer, is made of, for example, an aluminum nitride film, but may be other insulating films. The insulating plate 208 completely covers and adheres to the metal heat transfer plates 302b and 303b, but the insulating plate 208 and the metal heat transfer plates 302b and 303b may simply be in contact with each other, or may be coated with a good heat transfer material such as silicon grease, or may be joined by various methods. An insulating layer may also be formed by ceramic spraying, or the insulating plate 208 may be joined to the metal heat transfer plate, or may be joined or formed on the refrigerant tube.

The refrigerant tubes 202 are made by cutting a plate material formed by drawing or extrusion of an aluminum alloy to the required length. The thickness direction cross section of the refrigerant tubes 202 has many flow paths 222 partitioned by many partition walls 221 extending in the flow path direction at a predetermined interval from each other. The spacer 203 may be, for example, a soft metal plate such as a solder alloy, or may be a film formed by coating or the like on the contact surface of the metal heat transfer plates 302b and 303b. The surface of this soft spacer 203 easily deforms and adapts to the minute unevenness and warping of the insulating plate 208 and the minute unevenness and warping of the refrigerant tubes 202, reducing the thermal resistance. In addition, a known good thermal conductive grease may be applied to the surface of the spacer 203, or the spacer 203 may be omitted.

(Example)
1. Fabrication of a semiconductor device An m-plane sapphire substrate is used as a crystal growth substrate, and an ELO mask extending in the c-axis direction is formed in a stripe shape on the surface. FIG. 1(a) shows a sapphire substrate 1. As shown in FIG. 1(b), an ELO mask 5 having a stripe pattern is formed on the crystal growth surface of the sapphire substrate 1. Using the crystal growth substrate of FIG. 1(b), a crystal growth layer made of α-Ga ₂ O ₃ is formed by mist CVD to obtain a laminated structure of FIG. 1(c). In the laminated structure (c), a crystal growth layer 8 is formed on a sapphire substrate 1 having an ELO mask 5 on its surface. After obtaining the laminated structure (c), electrodes and the like are formed by known means to obtain a semiconductor device. The semiconductor device thus obtained has excellent adhesion between the ELO mask and the crystal growth layer (semiconductor layer), and a good quality crystal region is formed in the channel layer, so that the semiconductor device has excellent semiconductor properties.

2. Evaluation The semiconductor device obtained in 1 above was observed using a TEM. The results are shown in Fig. 10. Fig. 10 shows that there are no gaps between the ELO mask and the crystal growth layer (semiconductor layer), and that the adhesion is excellent. Fig. 10 also shows that a good quality crystal region is formed on the ELO mask.

The semiconductor device of the present invention can be used in a wide range of fields, including semiconductors (e.g., compound semiconductor electronic devices), electronic and electrical equipment components, optical and electrophotographic devices, and industrial materials, but is particularly useful in power devices.

1. Substrate (sapphire substrate)
1a Substrate surface (crystal growth surface)
2a Convex portion 5 Mask (on substrate)
8 Crystal growth layer (semiconductor layer)
REFERENCE SIGNS LIST 11 Substrate 14 Electrode 15 Dielectric film 16 Semi-insulating layer 18 Semiconductor layer 18a n-type semiconductor layer 18b n+ type semiconductor layer 19 Mist CVD apparatus 20 Sample to be deposited 21 Sample stage 22a Carrier gas source 22b Carrier gas (dilution) source 23a Flow rate control valve 23b Flow rate control valve 24 Mist source 24a Source solution 24b Mist 25 Container 25a Water 26 Ultrasonic transducer 27 Deposition chamber 28 Heater 50 Halide vapor phase epitaxy (HVPE) apparatus 51 Reaction chamber 52a Heater 52b Heater 53a Halogen-containing source gas supply source 53b Metal-containing source gas supply pipe 54a Reactive gas supply source 54b Reactive gas supply pipe 55a Oxygen-containing source gas supply source 55b Oxygen-containing source gas supply pipe 56 Substrate holder 57 Metal source 58 Protective sheet 59 Gas exhaust section 170 Power supply system 171 Power supply device 172 Power supply device 173 Control circuit 180 System device 181 Electronic circuit 182 Power supply system 192 Inverter 193 Transformer 194 Rectification MOSFET
195 DCL
196 PWM control circuit 197 Voltage comparator 201 Double-sided cooled power card 202 Refrigerant tube 203 Spacer 208 Insulating plate (insulating spacer)
209 Sealing resin portion 221 Partition wall 222 Flow path 301a Semiconductor chip 302b Metal heat transfer plate (protruding terminal portion)
303 Heat sink and electrode 303b Metal heat transfer plate (protruding terminal portion)
304 solder layer 305 control electrode terminal 308 bonding wire 500 semiconductor element 501 solder 502 lead frame, circuit board or heat dissipation board

Claims (13)

A vertical semiconductor device including an insulating substrate, a dielectric film, and a semiconductor layer, the dielectric film and the semiconductor layer being stacked on the insulating substrate, the insulating substrate being a crystalline substrate having the same crystal structure as the semiconductor layer, and the dielectric film extending in a c-axis direction . A vertical semiconductor device including an insulating substrate, a dielectric film, and a semiconductor layer, the dielectric film and the semiconductor layer being stacked on the insulating substrate, the insulating substrate being a crystalline substrate having the same crystal structure as the semiconductor layer, and the dielectric film being a gate insulating film. 3. The semiconductor device according to claim 1, wherein the semiconductor layer is a laterally grown layer. 4. The semiconductor device according to claim 1, wherein the semiconductor layer includes a first semiconductor region and a second semiconductor region, the first semiconductor region is in contact with the dielectric film, and the second semiconductor region includes more dislocations than the first semiconductor region. The semiconductor device according to any one of claims 1 to 4, wherein the thickness of the semiconductor layer is 1 μm or more. The semiconductor device according to any one of claims 1 to 5, wherein the semiconductor layer has a corundum structure. The semiconductor device according to any one of claims 1 to 6, wherein the semiconductor layer contains at least gallium. A vertical semiconductor device including an insulating substrate, a dielectric film, a first semiconductor layer, and a second semiconductor layer, wherein the dielectric film, the first semiconductor layer, and the second semiconductor layer are stacked on the insulating substrate, the insulating substrate is a crystal substrate having the same crystal structure as the first semiconductor layer, the first semiconductor layer has a crystal structure including a c-axis, and the dielectric film extends in the c-axis direction . A vertical semiconductor device including an insulating substrate, a dielectric film, a first semiconductor layer, and a second semiconductor layer, wherein the dielectric film, the first semiconductor layer, and the second semiconductor layer are stacked on the insulating substrate, the insulating substrate is a crystalline substrate having the same crystal structure as the first semiconductor layer, and the dielectric film is a gate insulating film. 10. The semiconductor device according to claim 8, wherein the first semiconductor layer includes a first semiconductor region and a second semiconductor region, the second semiconductor layer includes a first semiconductor region and a second semiconductor region, the first semiconductor region of the first semiconductor layer is joined to the dielectric film, and the first semiconductor region has fewer dislocations in the first semiconductor layer than the second semiconductor region. The semiconductor device according to any one of claims 1 to 10 , which is a MOSFET. The semiconductor device according to any one of claims 1 to 11 , which is a power device. A semiconductor system comprising a semiconductor device, the semiconductor device being the semiconductor device according to any one of claims 1 to 12 .