JP7503369B2 - Inverter Device - Google Patents

Description

The present invention relates to an inverter device.

Conventionally, inverter devices connected to AC power systems are equipped with an anti-islanding function to ensure that the device is disconnected from the AC power system in the event of a power outage in the AC power system.

As an example of related prior art, see Patent Document 1 by the applicant of the present application.

In addition, Non-Patent Document 1, which defines new interconnection regulations for PCS [power conditioning systems] for PV [photovoltaic] systems, proposes a frequency feedback function and a step injection function as common technologies for active islanding detection.

The frequency feedback function injects reactive power based on fluctuations in the operating frequency of the PCS, promoting fluctuations in the operating frequency. When the PCS transitions to an islanding state, if there is an imbalance between the PCS output and the consumer load, unintended fluctuations will occur in the PCS operating frequency. In this case, if reactive power is injected using the frequency feedback function, it is possible to promote fluctuations in the operating frequency, making it possible to capture these fluctuations and detect islanding of the PCS.

The step injection function is a function that performs reactive power injection in a stepped manner when harmonic distortion in the PCS output increases suddenly, forcibly varying the operating frequency of the PCS. In an area where the PCS output and consumer load are balanced, the operating frequency of the PCS is likely to stabilize even if the PCS transitions to an islanding operation state. For this reason, it is desirable to have the above-mentioned step injection function as a security technology for ensuring islanding detection.

Patent No. 6200196

Japan Electrical Manufacturers' Association standard JEM1498 (established on August 27, 2012, revised on December 15, 2017)

However, with the above-mentioned conventional technology, if the amount of reactive power injected becomes smaller than expected even when the PCS transitions to an islanding state, there is a risk that the detection of the islanding state of the PCS may be delayed.

In view of the above problems, the present invention aims to provide an inverter device that can more reliably detect isolated operation and stop operation.

The inverter device disclosed in this specification is an inverter device that includes a power conversion unit that converts DC power to AC power and connects it to an AC power system, monitors the system frequency to detect islanding, promotes a frequency change in the system frequency by injecting reactive power according to the deviation of the system frequency, forcibly causes a deviation in the system frequency by stepwise injecting the reactive power when a sudden increase in harmonic distortion is detected, determines whether islanding is possible, and if it is determined that islanding is possible, executes processing to stop the output of the power conversion unit.

The inverter device according to the present invention makes it possible to provide an inverter device that can more reliably detect isolated operation and stop operation.

FIG. 1 is a block diagram showing a configuration example of an inverter device according to an embodiment of the present invention; FIG. 1 is a diagram for explaining how to distort PWM data Dp'. FIG. 1 is a diagram showing a first example of an apparent waveform of PWM data Dp′. FIG. 11 is a diagram showing a second example of an apparent waveform of PWM data Dp′. FIG. 13 is a diagram showing a third example of an apparent waveform of PWM data Dp′. FIG. 4 is a diagram showing a fourth example of an apparent waveform of PWM data Dp′. FIG. 13 is a diagram showing an example of fluctuations in inverter output frequency. FIG. 1 shows an example of a positive feedback loop used to control an inverter output frequency. Overall block diagram of standard active islanding system Diagram showing the system frequency (period) measurement algorithm Frequency deviation calculation diagram Image of updating moving average value Frequency deviation - reactive power characteristics FIG. 1 is a diagram for explaining a first condition (fundamental voltage fluctuation) for generating step injection. FIG. 1 is a diagram for explaining the second condition for occurrence of step injection (harmonic voltage fluctuations); Block diagram showing an example of application to an inverter device FIG. 1 is an overall block diagram showing a first configuration example of a PCS to which an isolated operation possibility determination processing unit is added; Image of reactive power array that stores calculated reactive power values A table of the assumed reactive power change amount stored in the assumed reactive power change amount calculation unit shown in FIG. 17 A graph showing the relationship between the g-rate value and the expected reactive power change Overall block diagram showing a third configuration example of a PCS to which an isolated operation possibility determination processing unit is added 22 is a graph for explaining an example of calculation of an assumed output current in the assumed output current calculation unit shown in FIG.

<Inverter device>
1 is a block diagram showing a configuration example of an inverter device. The inverter device 1 includes an inverter main circuit 4 that converts DC power input from a DC power source 2 into AC power and supplies it to a load 3, a voltage detector 5 that detects a load supply voltage Vo supplied to the load 3, a zero-cross detection circuit 6 that creates an output synchronization signal Vs based on the load supply voltage Vo, a current detector 7 that detects an output current Io of an AC output (hereinafter referred to as inverter output) of the inverter main circuit 4, an A/D converter 8 that A/D converts the output current Io, a DSP [digital signal processor] 9 that controls the inverter main circuit 4 with PWM [pulse width modulation] based on the output current Io and the output synchronization signal Vs, a voltage abnormality detection circuit 10 that detects a voltage abnormality of the load supply voltage Vo supplied to the load 3, a timer/counter circuit 11 that creates a gate pulse signal Gp' based on the PWM data output by the DSP 9, and a gate drive circuit 12 that controls switching of a switching element (not shown) of the inverter main circuit 4 based on the gate pulse signal Gp'. A filter 15, which is made up of a reactor 13 and a capacitor 14, is provided between the inverter main circuit 4 and the load 3 to remove high frequency components from the inverter output.

The load 3 is supplied with AC power from the AC power system 16 via a circuit breaker 17 and a pole transformer 18, separately from the inverter device 1, and the inverter device 1 is operated in connection with the AC power system 16.

The DSP 9 includes a current reference waveform memory 19 in which current reference waveform data Wb is stored, a multiplication unit 20 that sequentially reads out the current reference waveform data Wb from the current reference waveform memory 19 and multiplies it by the output command signal Vc to create a current reference signal Ic, an error signal creation unit 21 that calculates the error between the output current Io and the current reference signal Ic to create a current error signal e, an error waveform pattern integration circuit 22 that integrates the waveform pattern of the current error signal e with the period of the output synchronization signal Vs as one interval, a PWM processing circuit 23 that pulse-width modulates the integral data e' output from the error waveform pattern integration circuit 22 to create PWM data Dp, a PWM memory 24 that stores the PWM data Dp, and a zero-crossing period detection processing circuit 25 that calculates the frequency of the load supply voltage Vo, outputs a frequency abnormality signal Fe indicating a frequency abnormality of the load supply voltage Vo, and further outputs a read address designation signal C.

Next, the operation of the inverter device 1 will be explained step by step. The output current Io of the inverter output detected by the current detector 7 is A/D converted by the A/D converter 8 and then input to the error signal creation unit 21.

Meanwhile, the load supply voltage Vo detected by the voltage detector 5 is input to the zero-cross detection circuit 6. The zero-cross detection circuit 6 creates an output synchronization signal Vs based on the input load supply voltage Vo and outputs it to the current reference waveform memory 19. The current reference waveform memory 19 reads out the stored current reference waveform data Wb in synchronization with the input output synchronization signal Vs and outputs it to the multiplication unit 20. The multiplication unit 20 multiplies the input current reference waveform data Wb by the output command signal Vc to create a current reference signal Ic, which is output to the error signal creation unit 21.

The error signal creation unit 21, to which the output current Io and the current reference signal Ic are input, creates a current error signal e, which is the error between the output current Io and the current reference signal Ic, and outputs it to the error waveform pattern integration circuit 22. The error waveform pattern integration circuit 22 receives the output synchronization signal Vs from the zero-cross detection circuit 6, and integrates the waveform pattern of the current error signal e, with the period of the output synchronization signal Vs being one interval. The integration data e' created in this way is stored in the error waveform pattern integration circuit 22 for use in the integration calculation at the next sampling time, and is also output to the PWM processing circuit 23.

The PWM processing circuit 23 pulse-width modulates the input integral data e' to create PWM data Dp, which is stored in the PWM memory 24. The PWM memory 24 outputs the PWM data Dp' distorted by the address specification signal C to the timer/counter circuit 11 for each sampling, while synchronizing with the output synchronization signal Vs input from the zero-cross detection circuit 6.

The timer/counter circuit 11 creates a gate pulse signal Gp' based on the PWM data Dp' created by the DSP 9 in the above-mentioned procedure, and outputs it to the gate drive circuit 12. The gate drive circuit 12 controls the switching of the switching element (not shown) of the inverter main circuit 4 based on the input gate pulse signal Gp', thereby driving the inverter main circuit 4.

When the inverter device 1 enters an isolated operation state due to a power outage or the like in the AC power system 16, the inverter device 1 detects the isolated operation state and stops the inverter output as follows. That is, when the inverter device 1 enters an isolated operation state in a state in which the reactive power supplied by the inverter device 1 does not match the reactive power required by the load 3, the frequency of the load supply voltage Vo (which is equal to the inverter output in an isolated operation state) fluctuates from the rated frequency (50/60 Hz), and the voltage value of the load supply voltage Vo also fluctuates accordingly. Therefore, the voltage abnormality detection circuit 10 detects whether there is an abnormality in the load supply voltage Vo, and if an overvoltage abnormality or undervoltage abnormality occurs in the load supply voltage Vo, a voltage abnormality signal Ve is output to the gate drive circuit 12. In addition, the zero-cross period detection processing circuit 25 detects the frequency of the load supply voltage Vo, and further compares the detected frequency of the load supply voltage Vo with the rated frequency f0 to calculate the deviation between the two, and if the calculated deviation exceeds a predetermined threshold, a frequency abnormality signal Fe is output to the gate drive circuit 12.

When the gate drive circuit 12 receives the voltage abnormality signal Ve or frequency abnormality signal Fe, it determines that the inverter device 1 is in an isolated operation state and stops switching control of the inverter main circuit 4, causing the inverter main circuit 4 to stop inverter output.

Next, the characteristic operation of the inverter device 1 will be described. When the inverter device 1 is in an isolated operation state with the reactive power supplied by the inverter device 1 almost equal to the reactive power required by the load 3 (the power factor of the load impedance is close to 1), the frequency of the load supply voltage Vo hardly fluctuates. Therefore, the voltage abnormality detection circuit 10 and the zero-cross period detection processing circuit 25 cannot detect an abnormality in the load supply voltage Vo. Therefore, in the inverter device 1, the following distortion is applied to the PWM data Dp' output by the PWM memory 24, so that the frequency of the load supply voltage Vo in the isolated operation state is fluctuated regardless of the power factor of the load impedance, thereby reliably detecting the isolated operation state of the inverter device 1. The application of the distortion will be described in detail below.

The inverter device 1 is characterized by the configuration of the zero-cross period detection processing circuit 25, which distorts the inverter output. That is, the zero-cross period detection processing circuit 25 outputs a read address designation signal C to the PWM memory 24.

The read address specification signal C that the zero-cross period detection processing circuit 25 gives to the PWM memory 24 is a signal that specifies the following. That is, as shown in FIG. 2, when the PWM data Dp is read from the PWM memory 24, the read address specification signal C distorts the PWM data Dp by changing the increase rate (g-rate) of the read counter (g-count) for each zero-cross period.

That is, if the read address of the PWM data Dp is m and the time change of the PWM data Dp retrieved from the PWM memory 24 is Y(n), then the read address designation signal C is expressed as follows:
m = int (g-rate × g-count) ... (1)
g-count = n mod N ... (2)
Y(n)=Dpm... (3)
These are addressing signals.

The PWM data Dp' read from the PWM memory 24 based on the read address designation signal C set in this way is input to the timer/counter circuit 11. The timer/counter circuit 11 then creates a gate pulse signal Gp' based on this PWM data Dp' and outputs it to the gate drive circuit 12. The gate drive circuit 12 controls the switching of the inverter main circuit 4 using the input gate pulse signal Gp'.

Here, if g-rate>1, as shown in Figure 3, the inverter output waveform is distorted so that the output is zero for a certain period β ending at the zero crossing point, and the apparent period T3 of the PWM data Dp' becomes shorter than the period T0 of the rated frequency f0. When the inverter output is created based on this PWM data Dp', the detection timing of the zero crossing point becomes earlier by the period β, and as a result, the frequency of the inverter output increases above the rated frequency f0.

On the other hand, when g-rate < 1, as shown in Figure 4, the inverter output waveform is given a distortion that outputs an arbitrary offset to the descending waveform path from the crest to the zero crossing point, and the apparent period T4 of the PWM data Dp' becomes longer than the period T0 of the rated frequency f0. When the inverter output is created based on this PWM data Dp', the apparent period T4 becomes longer, and the timing of detecting the zero crossing point becomes delayed by the amount of the increase in the apparent period T4, resulting in the frequency of the inverter output falling below the rated frequency f0.

Since such frequency fluctuations occur even if the power factor of the load impedance is approximately 1, the zero-cross period detection processing circuit 25 or the voltage change associated with the frequency fluctuations is detected by the voltage abnormality detection circuit 10, so that the isolated operation state of the inverter device 1 can be reliably detected.

In addition to the methods shown in Figures 3 and 4, the inverter output waveform may be distorted by the inverter device 1 in such a way that the output level is zero for a predetermined period γ on both sides of the zero crossing point, as shown in Figure 5. In this way, the apparent period TT of the PWM data Dp' becomes shorter than the period T0 of the rated frequency f0, and the frequency of the inverter output (load supply voltage Vo) fluctuates from the rated frequency f0.

Furthermore, as shown in FIG. 6, a distortion may be added to the inverter output waveform such that the zero crossing point outputs an arbitrary offset on both wave height peak sides. In this way, the apparent period T6 of the PWM data Dp' becomes longer than the period T0 of the rated frequency f0, and as a result, the frequency of the inverter output fluctuates from the rated frequency f0.

In order to impart the distortion shown in Figures 5 and 6 to the inverter output waveform, the function that specifies the read address in the read address specification signal C can be changed. Note that in Figures 3 to 6, the solid lines show the apparent output waveform with PWM data Dp', and the dotted lines show the output waveform at the rated frequency f0.

The frequency of the inverter output when the inverter device 1 is operating independently is also affected by the type of load 3 to which the inverter device 1 is connected. When the load 3 is an inductive load, the inverter output frequency during independent operation increases, and when the load 3 is a capacitive load, the inverter output frequency during independent operation decreases. Therefore, in cases where the frequency fluctuation caused by distorting the inverter output waveform and the frequency fluctuation caused by the load 3 are equal in absolute value and the directions of the fluctuations are opposite, the frequency fluctuation caused by the distortion and the frequency fluctuation caused by the load 3 may cancel each other out, making it difficult for frequency fluctuation to occur.

In contrast, as described above, in the inverter device 1, the inverter output frequency can be increased or decreased relative to the rated frequency f0 depending on how the increase rate (g-rate) of the read counter (g-count) is set. Therefore, in the inverter device 1, as shown in FIG. 7, a period M1 in which a first distortion (see FIG. 3) is applied, in which the inverter output frequency increases by a predetermined fluctuation width Δf, and a period M2 in which a second distortion (see FIG. 4) is applied, in which the inverter output frequency decreases by a predetermined fluctuation width Δf, are set alternately. Therefore, even if the frequency fluctuation effect caused by the application of the distortion and the frequency fluctuation effect caused by the load 3 cancel each other out in a certain period M1 (M2), they will no longer cancel each other out in the next period M2 (M1), so the inverter output frequency will definitely fluctuate. Therefore, the isolated operation state of the inverter device 1 will be detected reliably regardless of the power balance with the load 3.

In addition, in the inverter device 1, a distortion-free period M3 in which the rated frequency f0 is maintained is provided between the period M1 in which the first distortion is applied and the period M2 in which the second distortion is applied. As a result, in the normal operating state of the inverter device 1, i.e., in the state in which it is connected to the AC power system 16 and operating at the rated frequency f0, distortion is unlikely to occur in the load supply voltage Vo.

For example, seven periods of the inverter output frequency are appropriate for the periods M1 and M2 during which the first and second distortions are applied, and three periods of the inverter output frequency are appropriate for the period M3 during which no distortion is applied, and the fluctuation range Δf is, for example, ±0.2 Hz. However, these values are merely examples, and it goes without saying that the fluctuation range Δf of each period M1, M2, M3 may be other values.

Furthermore, the inverter device 1 controls the inverter output with a positive feedback loop as shown in FIG. 8. In FIG. 8, the horizontal axis indicates the output frequency Fin of the load supply voltage Vo detected by the zero-crossing period detection processing circuit 25 (corresponding to the frequency of the inverter output when the inverter device 1 is operating alone), and the vertical axis indicates the apparent frequency Fout in the PWM data Dp'. As can be seen from this figure, the inverter device 1 (specifically, the zero-crossing period detection processing circuit 25) divides the load supply voltage Vo into a dead zone K, which is a predetermined frequency period (for example, a period of ±0.2 Hz is appropriate, but is not limited to this period) that sandwiches the rated frequency f0, a +-side abnormal frequency region L+, which is a frequency region higher than the dead zone K, and a --side abnormal frequency region L-, which is a frequency region lower than the dead zone K.

In the dead zone K, as shown in FIG. 7, a period M1 in which a first distortion (see FIG. 3) that increases the inverter output frequency is applied, a period M3 in which no distortion is applied, and a period M2 in which a second distortion (see FIG. 4) that decreases the inverter output frequency are set in sequence and alternately. In the abnormal frequency region L+, the inverter is controlled by creating PWM data Dp' in a positive feedback loop in which the apparent frequency Fout in the PWM data Dp' formed based on the frequency Fin of the load supply voltage Vo is higher than the frequency Fin of the load supply voltage Vo. Furthermore, in the abnormal frequency region L-, the inverter is controlled by creating PWM data Dp' in a positive feedback loop in which the apparent frequency Fout in the PWM data Dp' formed based on the frequency Fin is lower than the frequency Fin of the load supply voltage Vo. This type of control can be achieved by changing the function that specifies the read address using the read address specification signal C through feedback control based on the load supply voltage Vo.

By carrying out the above-mentioned control, the frequency of the load supply voltage Vo will rapidly fluctuate when the inverter device 1 is operating alone. That is, when the inverter device 1 is operating alone, the power factor of the load impedance is almost 1. Even if the load supply voltage Vo does not leave the dead zone K in the conventional case, the inverter output is first given a first distortion and a second distortion, so that the load supply voltage Vo leaves the dead zone K and moves to the abnormal frequency ranges L+ and L-. If the load supply voltage Vo moves to the abnormal frequency ranges L+ and L-, the frequency fluctuation will be accelerated by frequency control in a positive feedback loop. Therefore, if the inverter device 1 starts operating alone, it will be detected promptly by the zero-cross period detection processing circuit 25 and the voltage abnormality detection circuit 10.

Furthermore, as shown in FIG. 8, in the inverter device 1, if the frequency of the load supply voltage Vo stays in the abnormal frequency range L+, L-, the slope of the positive feedback loop is changed so that the amount of change in the frequency Fout relative to the frequency Fin increases. That is, in the zero-cross period detection processing circuit 25, the period during which the frequency Fin is in the abnormal frequency range L+, L- is measured, and if the frequency Fin does not exceed a preset period (for example, a period of five periods of Fin is appropriate, but is not limited to this period), control is performed based on the positive feedback loop P1 with a relatively small slope, while if the frequency Fin exceeds the preset period, control is performed based on the positive feedback loop P2 with a relatively large slope. This allows the frequency fluctuation of the frequency Fin that has moved into the abnormal frequency range L+, L- to be further accelerated, and if the inverter device 1 starts operating alone, it will be detected more quickly by the zero-cross period detection processing circuit 25 and the voltage abnormality detection circuit 10.

Also, as mentioned above, depending on whether the load 3 is an inductive load or a capacitive load, the frequency of the load supply voltage Vo may fluctuate due to the action of the load 3, and the frequency fluctuation due to the load 3 and the frequency fluctuation due to the application of distortion may cancel each other out. If this happens, the frequency fluctuation speed of the load supply voltage Vo may slow down, which is inconvenient. However, as shown in FIG. 8, since two positive feedback loops P1 and P2 are switched, even if the frequency fluctuation speed slows down in the control of the positive feedback loop P1 with a relatively small slope because the frequency fluctuation due to the load 3 and the frequency fluctuation due to the application of distortion cancel each other out, by switching to the positive feedback loop P2 with a relatively large slope, this offset relationship is eliminated, and the frequency will fluctuate significantly.
<Standard active islanding detection method>
The islanding detection method for distributed power sources explained so far is a method that provides a frequency bias that acts as an active signal for injecting reactive power steadily, to encourage deviation of the operating frequency during islanding, and detects islanding by frequency shift operation. However, in an environment where multiple distributed power sources are installed, there is a technical drawback in that the active signals from the distributed power sources interfere with each other and cancel each other out. To solve this drawback, a standard active islanding detection method that is compatible with centralized grid connection is known, and its outline is as follows. It has two characteristic functions: a function to calculate the reactive power to be injected from the deviation of the grid frequency and encourage a frequency shift (frequency feedback function), and a function to intentionally cause a frequency change when the output power of the distributed power source and the power consumption of the grid load are in balance (reactive power step injection function). It has features such as high-speed detection of islanding, no unnecessary operation, no mutual interference with other methods, and small impact on the grid by active signals. This type of islanding detection method is called the "standard active islanding detection method (frequency feedback method with step injection)" and its contents will be explained in detail.

Figure 9 is an overall block diagram of a power conditioner (hereinafter, sometimes referred to as a PCS [power conditioning system]) that employs the above-mentioned active islanding method. The PCS 100 of this configuration example has a system frequency measurement unit 110, a frequency feedback unit (reactive power injection unit) 120, a reactive power step injection unit 130, an islanding detection unit 140, a current control processing unit 150, and an inverter unit 160.

The system frequency measurement unit 110 is a control unit that measures the system frequency used to calculate the frequency deviation, and includes a frequency detection circuit 111, a frequency measurement processing unit 112, and a phase difference measurement synchronization processing unit 113. Figure 10 shows the algorithm for measuring the system frequency (period).

The frequency detection circuit 111 generates a square wave signal synchronized with the system voltage and outputs it to the frequency measurement processing unit 112 (see the upper part of Figure 10). The frequency detection circuit 111 is implemented as a hardware unit.

The frequency measurement processing unit 112 monitors the square wave signal input from the frequency detection circuit 111 and measures period data (frequency data) of the system voltage (see the middle part of FIG. 10). More specifically, the frequency measurement processing unit 112 obtains the difference between the median value when counting from the falling edge to the rising edge of the square wave signal and the median value when counting from the next falling edge to the rising edge as period data (frequency data). The frequency measurement processing unit 112 has a resolution sufficient for measuring the system frequency (e.g., 2.5 MHz or more (400 ns or less)). The frequency measurement processing unit 112 is implemented as a software unit.

The phase difference measurement synchronization processing unit 113 synchronizes the period data (frequency data) measured by the frequency measurement processing unit 112 with the rising edge of the square wave signal (see the lower part of Figure 10). The phase difference measurement synchronization processing unit 113 is implemented as a software unit.

The frequency feedback unit 120 is a control unit that calculates the reactive power to be injected from the frequency deviation (periodic deviation) of the system frequency calculated by moving average processing to promote a frequency shift, and includes a first moving average calculation unit 121, a second moving average calculation unit 122, a frequency deviation calculation unit 123, a reactive power injection amount calculation unit 124, and an addition unit 125.

The first moving average calculation unit 121 calculates the first moving average value (corresponding to the most recent period) of the system frequency (system period). The first moving average calculation unit 121 is implemented as a software unit.

The second moving average calculation unit 122 calculates the second moving average value (corresponding to the past period) of the system frequency (system period). The second moving average calculation unit 122 is implemented as a software unit.

The frequency deviation calculation unit 123 calculates the frequency deviation (periodic deviation) of the system frequency from the difference between the first moving average value and the second moving average value. The frequency deviation calculation unit 123 is implemented as a software unit.

Figure 11 is an image diagram of frequency deviation calculation, and Figure 12 is an image diagram of moving average value update. The periodic data used to calculate the frequency deviation is updated every period of the system voltage. The moving average value used to calculate the frequency deviation is updated every time t1 (e.g., t1 = 5 ms), and the frequency deviation calculation itself is also performed every time t1. Note that time t1 is a uniform value regardless of the frequency (50 Hz/60 Hz) of the AC power system PW. As the first moving average value (most recent period), a moving average value for time t2 (e.g., t2 = 40 ms) is used, with the acquisition timing of the most recent period as the end point. On the other hand, as the second moving average value (past period), a moving average value for time t4 (e.g., t4 = 320 ms) is used, with the timing going back by time t3 (e.g., t3 = 200 ms) from the acquisition timing of the most recent period as the end point.

The reactive power injection amount calculation unit 124 calculates the reactive power to be injected according to the frequency deviation (periodic deviation) calculated by the frequency deviation calculation unit 123. The reactive power injection amount calculation unit 124 is implemented as a software unit.

Figure 13 is a diagram showing frequency deviation-reactive power characteristics. As shown in this figure, the reactive power injection amount calculation unit 124 changes the gain of the reactive power calculation when the frequency deviation is ±f [Hz] (for example, f = 0.01 Hz (±4.0 μs @ 50 Hz, ±2.8 μs @ 60 Hz)). The upper and lower limits of the reactive power to be injected are set to ±A [p.u.] (for example, A = 0.25 p.u.). Here, p.u. [per unit] is a symbol used to express the ratio to a reference value (rated capacity) in the unit method. For example, if the reference value (rated capacity) is 4 kW, ±0.25 p.u. = ±1 kW (±1 Var for reactive power).

The adder 125 adds the reactive power injection amount calculated by the reactive power injection amount calculation unit 124 and the step injection amount of reactive power calculated by the step injection amount calculation unit 136 described later, and transmits the sum to the current control processing unit 150. The adder 125 is implemented as a software unit.

The reactive power step injection unit 130 is a control unit that injects reactive power in a step manner to promote a frequency shift under conditions in which the output power of the PCS 100 and the power consumption of the load device are balanced and the deviation of the system frequency is small during isolated operation of the distributed power source, and includes a fundamental wave voltage measurement circuit 131, a harmonic voltage measurement circuit 132, a fundamental wave voltage calculation unit 133, a harmonic voltage calculation unit 134, a step injection occurrence condition determination unit 135, and a step injection amount calculation unit 136.

The fundamental wave voltage measurement circuit 131 measures the fundamental wave component contained in the output current of the PCS 100 as a fundamental wave voltage. The fundamental wave voltage measurement circuit 131 is implemented as a hardware unit.

The harmonic voltage measurement circuit 132 measures the harmonic components contained in the output current of the PCS 100 as harmonic voltages. The harmonic voltage measurement circuit 132 is implemented as a hardware unit.

The fundamental wave voltage calculation unit 133 calculates the amount of change in the fundamental wave voltage. The fundamental wave voltage calculation unit 133 is implemented as a software unit.

The harmonic voltage calculation unit 134 calculates the amount of change in the harmonic voltage. Second to seventh or higher harmonics are used to calculate the harmonic voltage. The discrete Fourier analysis described below may also be used to calculate the harmonic voltage. The harmonic voltage calculation unit 134 is implemented as a software unit.

なお、上式中の変数について、ｎはサンプリング点（Ｎ個）（ｎ＝０，１，２，…，Ｎ－１）、ｆ１は基本周波数（ｆ１＝１／（ＮＴ）＝ｆｓ／Ｎ）、ｆｓはサンプリング周波数、Ｔはサンプリング間隔（Ｔ＝１／ｆｓ）、ｋは高調波の時数（ｋ＝０，１，２，…，Ｎ／２）、Ａ［ｋ］はｋ次余弦の振幅、Ｂ［ｋ］はｋ次正弦の振幅、Ｈａｒｍ［ｋ］はｋ次高調波電圧（ピーク電圧）をそれぞれ示している。

In the above equation, n denotes the sampling points (N points) (n=0, 1, 2, ..., N-1), f1 denotes the fundamental frequency (f1=1/(NT)=fs/N), fs denotes the sampling frequency, T denotes the sampling interval (T=1/fs), k denotes the number of hours of the harmonic (k=0, 1, 2, ..., N/2), A[k] denotes the amplitude of the kth cosine, B[k] denotes the amplitude of the kth sine, and Harm[k] denotes the kth harmonic voltage (peak voltage).

The step injection occurrence condition determination unit 135 determines whether or not the step injection occurrence condition is satisfied according to the outputs of the fundamental wave voltage calculation unit 133 and the harmonic voltage calculation unit 134. More specifically, the step injection occurrence condition determination unit 135 determines that the need for step injection has arisen when the frequency deviation is within a predetermined minute range (for example, within ±0.01 Hz) and the amount of change in the fundamental wave voltage or the harmonic voltage satisfies a predetermined condition. The fundamental wave voltage and the harmonic voltage are one of the variables other than the system frequency that occurs when islanding occurs. The step injection occurrence condition determination unit 133 is implemented as a software unit.

Figure 14 is a diagram for explaining the first condition for step injection (fundamental voltage fluctuation). In this figure, Mi indicates the fundamental voltage i cycles ago, and Mavr indicates the average value of three values from three cycles ago to five cycles ago. The fundamental voltage calculation unit 133 calculates the amount of change in the fundamental voltage (Mk-Mavr) (where k = 0 to 5), and the step injection occurrence condition determination unit 135 determines that a fluctuation in the fundamental voltage has occurred when each amount of change satisfies a predetermined conditional formula.

Figure 15 is a diagram for explaining the second condition for the occurrence of step injection (harmonic voltage fluctuation). In this figure, Ni indicates the effective value THD [total harmonic distortion] of the second to seventh harmonic voltages i cycles ago, and Navr indicates the average value of the three values from three cycles ago to five cycles ago. The harmonic voltage calculation unit 134 calculates the amount of change in the harmonic voltage (Nk-Navr) (where k = 0 to 5), and the step injection occurrence condition determination unit 135 determines that a harmonic voltage fluctuation has occurred when each amount of change satisfies a predetermined conditional formula.

The step injection amount calculation unit 136 calculates the step injection amount of reactive power according to the judgment result of the step injection occurrence condition judgment unit 135. The injection time is set to a predetermined number of cycles or less (e.g., 3 cycles or less). A predetermined upper limit value (e.g., 0.1 pu) is set for the injection amount. The reactive power is injected in a direction that delays the current phase (direction that lowers the frequency) as viewed from the PCS 100. The step injection of reactive power is performed within half a cycle of the system frequency (period) after the aforementioned conditions are satisfied. The step injection amount calculation unit 136 is implemented as a software unit.

The islanding operation detection unit 140 is a control unit that determines whether or not an islanding operation has occurred based on changes in the system frequency, and includes an active islanding operation detection unit 141 and a passive islanding operation detection unit 142.

The current control processing unit 150 performs synchronization processing based on the output of the system frequency measurement unit 110, while controlling the current of the inverter unit 160 so as to inject appropriate reactive power. Note that, as a specific method for injecting reactive power, for example, the current control of the inverter unit 160 may be performed as described above with reference to Figures 1 to 8.

The inverter unit 160 is a power conversion unit that converts DC power supplied from a DC power source (e.g., a PV panel) into AC power and connects it to the AC power system PW.

Note that Figure 9 shows an example in which the above components are divided into a hardware section (other than the CPU) and a software section (CPU), but the division boundary is not limited to this.

A PCS100 that employs such an active islanding detection method can quickly shut down a PCS100 that has fallen into an islanding state without delay (for example, within 0.2 seconds after the occurrence of islanding).

In addition, with PCS100, the CPU interrupt time (the interval between target waveforms) can be changed based on the past system frequency (system cycle), making it possible to relatively reduce the amount of distortion even if the system frequency (cycle) changes.

The above-mentioned active islanding detection method makes it possible to create an environment in which safety requirements can be met without the islanding detection functions of each PCS interfering with each other, even when multiple photovoltaic power generation systems are connected to a common commercial power grid, thereby making it possible to smoothly promote the introduction of photovoltaic power generation systems to homes, etc.

<Application Examples>
16 is a block diagram showing an example in which the above-mentioned active islanding detection method is applied to a PCS (inverter device). In this application example, a consumer H is equipped with a photovoltaic power generation system X and a load device Y. The photovoltaic power generation system X is an example of a distributed power source, and includes a PCSX1 and a PV panel X2.

PCSX1 is an example of an inverter device, and in addition to including a grid-connected inverter unit X11, it also includes an islanding prevention function unit X12 and an islanding prevention assistance unit X13 as means for implementing a standard active islanding detection method.

The grid-connected inverter unit X11 converts the DC power supplied from the PV panel X2 into AC power and connects it to the AC power grid PW.

The islanding prevention function unit X12 is a function block that detects islanding operation from changes in the system frequency and system voltage and stops the system-connected inverter unit X11. For example, this corresponds to the islanding detection unit 140 in FIG. 9.

The islanding prevention aid unit X13 is a functional block that controls the grid-connected inverter unit X11 to aid in the islanding prevention function. More specifically, the islanding prevention aid unit X13 is a functional block that detects the grid frequency and feedback-controls the operating frequency of the grid-connected inverter unit X11 in a direction that aids in the change in frequency, and corresponds to, for example, the grid frequency measurement unit 110, the frequency feedback unit (reactive power injection unit) 120, the reactive power step injection unit 130, and the current control processing unit 150 in FIG. 9.

In this way, with the PCSX1 of this application example, it is possible to stop the PCSX1 that has fallen into an isolated operation state quickly and without delay.

<Inverter output stop function when islanding is possible>
Here, in the configuration of PCS 100, even if the value of g-rate is the same, the output current frequency is less likely to change in an isolated operation state compared to a grid-connected state compared to normal operation, and therefore, the detection of isolated operation by inverter unit 160 may be delayed.

To explain in detail, for example, when g-rate>1, the inverter output voltage has a period T3=T0/g-rate as shown in FIG. 3. In this case, if the system is connected to the grid, the system voltage is stable regardless of the inverter output voltage, so the inverter output current is output according to the difference between the inverter output voltage and the system voltage. On the other hand, if the system is in an isolated operation state, the system is disconnected from the grid voltage, so the inverter output voltage is supplied to the load as is, and the inverter output current is the same as the current used by the load for the inverter output voltage. In other words, if the grid voltage frequency before the calculation of g-rate is F0, the output voltage frequency F0' when g-rate distortion is applied during isolated operation is F0'=F0/g-rate, and the inverter output current is output with the frequency F0' as described above, without changing the current for each phase of the grid voltage up to that point (however, the output current when changed by g-rate during isolated operation does not necessarily match the output voltage (reactive power does not become 0).). This is because, when multiple units including other PCSs occur simultaneously, the isolated operation may be in a somewhat stable state, although it is not as stable as the grid voltage.

Therefore, even if the same PWM data Dp' is created and output using the same g-rate in the grid-connected state and the isolated operation state, different currents will be output. In fact, when the same g-rate is used, the frequency of the inverter output current changes more greatly when the inverter is grid-connected than when the inverter is in isolated operation. Therefore, during isolated operation, the output current frequency does not change as expected when the inverter is grid-connected, and as a result, the inverter output voltage frequency changes more slowly than expected. This makes it longer than expected to wait for the active isolated operation detection unit 141, which detects the voltage frequency change and stops the inverter unit 160, to start working after the occurrence of isolated operation. As a result, it is possible that the detection of isolated operation will be delayed and the dangerous state will continue for a long time.

Therefore, in order to prevent such a delay in detecting isolated operation, it is preferable to execute an isolated operation possibility determination process to determine whether or not isolated operation is possible, and if it is determined that isolated operation is possible, execute a process (stop process) to stop the output of the inverter unit 160.

In the following, an example of a configuration in which an isolated operation possibility determination processing unit is added to the PCS 100 will be described, but it is also possible to add an isolated operation possibility determination processing unit to the inverter device 1 shown in Figure 1.

<Operation of islanding operation possibility determination process>
(First Configuration Example)
17 is an overall block diagram showing a first configuration example of a PCS to which an isolated operation possibility determination processing unit 170 is added. This PCS 101 determines the presence or absence of an isolated operation possibility based on whether the output reactive power is smaller than expected. Specifically, the PCS 101 calculates the reactive power output by its own device in software, and if the expected reactive power is not being output, determines that there is a possibility of isolated operation and executes a process to stop the output from the inverter unit 160.

As shown in this figure, the PCS 101 further includes an isolated operation possibility determination processing unit 170. The isolated operation possibility determination processing unit 170 includes a first reactive power calculation unit 171, a second reactive power calculation unit 172, a third reactive power calculation unit 173, a reactive power deviation calculation unit 174, an expected reactive power change amount calculation unit 175, and an isolated operation possibility determination unit 176. Each unit of the isolated operation possibility determination processing unit 170 is implemented as a software unit.

よって、 The first reactive power calculation unit 171 calculates the reactive power output by the inverter unit 160. Specifically, the first reactive power calculation unit 171 detects the inverter output current (I) and the system voltage (V) by high-speed (e.g., 38 kHz) interrupt processing that calculates a switching duty ratio based on, for example, the inverter output current and the inverter target current. Using these detected values, the first reactive power calculation unit 171 calculates the reactive power (var) for a half cycle or one cycle by the following calculation. Note that the period for calculating the reactive power is not particularly limited.

Therefore,

第１無効電力算出部１７１は、上記演算によって求めた無効電力の算出値を第２無効電力算出部１７２および第３無効電力算出部１７３へ出力する。

The first reactive power calculation unit 171 outputs the calculated value of reactive power obtained by the above calculation to the second reactive power calculation unit 172 and the third reactive power calculation unit 173 .

The second reactive power calculation unit 172 calculates the average value of reactive power (most recent period reactive power) for the most recent period (e.g., 40 ms period) based on the calculated reactive power value input from the first reactive power calculation unit 171. The third reactive power calculation unit 173 calculates the average value of reactive power (past period reactive power) for a certain period (e.g., 320 ms period) from a short time ago (e.g., 200 ms ago) based on the calculated reactive power value input from the first reactive power calculation unit 171.

Figure 18 is an image diagram of a reactive power array that stores the calculated reactive power values input from the first reactive power calculation unit 171. The calculated reactive power values for each cycle or half cycle input from the first reactive power calculation unit 171 are stored in a memory or the like for a certain period (e.g., 520 ms). As shown in this figure, the calculated reactive power value for each cycle is stored over a period of, for example, 28 cycles. Note that the calculated reactive power value may be stored every half cycle, or every 5 ms as in the frequency deviation calculation for frequency feedback shown in Figure 11.

Based on the reactive power array thus stored, the second reactive power calculation unit 172 calculates, for example, the average value of the reactive power for the most recent two cycles (most recent cycle reactive power). The third reactive power calculation unit 173 calculates, for example, the average value of the reactive power for the period from 12 cycles before to 27 cycles before the acquisition timing of the most recent cycle (past cycle reactive power).

The second reactive power calculation unit 172 may use only the reactive power of the most recent cycle as the most recent cycle reactive power. The third reactive power calculation unit 173 calculates the average value of a period ending at least 200 ms before the acquisition timing of the most recent cycle as the past cycle reactive power. This makes it possible to detect islanding within 200 ms.

The second reactive power calculation unit 172 outputs the calculated most recent cycle reactive power to the reactive power deviation calculation unit 174. The third reactive power calculation unit 173 also outputs the calculated past cycle reactive power to the reactive power deviation calculation unit 174.

The reactive power deviation calculation unit 174 calculates the reactive power deviation based on the most recent cycle reactive power input from the second reactive power calculation unit 172 and the past cycle reactive power input from the third reactive power calculation unit 173. Specifically, the reactive power deviation calculation unit 174 calculates the reactive power deviation by calculating the difference between the most recent cycle reactive power and the past cycle reactive power (reactive power deviation = most recent cycle reactive power - past cycle reactive power). The reactive power deviation calculation unit 174 outputs the calculated reactive power deviation to the islanding operation possibility determination unit 176.

The expected reactive power change amount calculation unit 175 calculates the expected reactive power change amount (the reactive power value (amount of change) that is expected to change by when operating in a grid-connected state) based on the g-rate value and at least one parameter related to the current output active power of the PCS 101 (e.g., output active power, output command signal, output current effective value, output current peak value, etc.).

As an example, a method for calculating the expected reactive power change amount based on the g-rate value and the output active power is described below. In this case, the output active power "W" shown in [Equation 2] above is also used.

Figure 19 is an example of a table showing the g-rate values stored by the expected reactive power change calculation unit 175 and the relationship between the output active power and the expected reactive power change. In this figure, the values in the table indicate the expected reactive power conversion amount [Var].

The expected reactive power change calculation unit 175 stores a table of expected reactive power changes based on the g-rate value and output active power as shown in this figure, and may calculate the expected reactive power change based on this table.

Alternatively, the expected reactive power change calculation unit 175 may calculate the expected reactive power change using a formula between the numerical value of g-rate, the output active power, and the expected reactive power change.

20 is a graph showing the relationship between the value of g-rate and the expected reactive power change. As shown in this figure, the expected reactive power change calculation unit 175 may calculate the expected reactive power change by the following calculation.
Expected reactive power change = ((g-rate - 1) x 10 x output active power) [Var]
For example, when the output effective power is 5500 W and g-rate = 1.025,
Expected reactive power change amount = ((1.025 - 1) x 10 x 5500) = 1100 [Var]
(1100 Var is equivalent to 0.25 pu of rated power 5500 WPCS).

In this way, by calculating the expected reactive power change from a table of the expected reactive power change based on the g-rate value and the output active power, or by calculating the g-rate value, the output active power, and the expected reactive power change, it is possible to determine the possibility of islanding at any time.

The expected reactive power change amount calculation unit 175 calculates the expected reactive power conversion amount using, for example, the above table or the above calculation, and outputs it to the isolated operation possibility determination unit 176.

The expected reactive power change calculation unit 175 may calculate the expected reactive power change using the output command signal, the output current effective value, or the output current peak value instead of the output active power. By using these parameters, it is possible to omit the calculation of the output active power described above.

The isolated operation possibility determination unit 176 determines whether or not isolated operation is possible based on the reactive power deviation and the expected reactive power change amount. For example, if the difference between the reactive power deviation and the expected reactive power change amount exceeds a predetermined threshold value (reactive power deviation - expected reactive power change amount > threshold value), the isolated operation possibility determination unit 176 determines that isolated operation is possible. Note that a threshold value may be set for the absolute value of the difference. Also, the above-mentioned predetermined threshold value may be set to a different value for the deviation on the positive side and the deviation on the negative side.

In addition, it is possible to prevent erroneous judgments by determining whether islanding is possible only when the g-rate reaches a limit value that is set so that the reactive power injected during interconnected operation is close to, for example, 0.25 pu. In addition, it is possible to prevent erroneous judgments by determining that islanding is possible when the threshold is exceeded a set number of times in succession. Furthermore, it is possible to prevent erroneous judgments by designing the threshold with a margin.

As a specific numerical example to prevent erroneous judgment, when the active power is output at 5,500 W, if the g-rate is at the limit value and the reactive power deviation is below 140 var for four consecutive half cycles, it is judged that there is a possibility of islanding.

The isolated operation possibility determination unit 176 outputs the result of determining whether or not isolated operation is possible to the current control processing unit 150.

The current control processing unit 150 executes processing to stop the output from the inverter unit 160 based on the result of the determination of the possibility of isolated operation output from the isolated operation possibility determination unit 176. For example, if it is determined that there is a possibility of isolated operation, the current control processing unit 150 stops the operation of the inverter unit 160 (output stop processing).

Alternatively, when the current control processing unit 150 determines that there is a possibility of islanding, it relaxes the criteria for active islanding detection in the active islanding detection unit 141, making it easier to stop the output of the inverter unit 160 (criterion relaxation processing).

For example, the active islanding detection unit 141 actively detects islanding when the frequency fluctuates in the same direction for five or more consecutive cycles (judgment cycles) and the most recent frequency fluctuates by 1.2 Hz or more compared to the frequency several cycles ago, as the judgment criterion for normal active islanding detection judgment. Therefore, when the islanding possibility judgment unit 176 judges that there is a possibility of islanding, the threshold value (judgment threshold) of the judgment criterion for active islanding detection is relaxed so that islanding is actively detected when, for example, the frequency fluctuates in the same direction for three or more consecutive cycles and the most recent frequency fluctuates by 0.7 Hz or more compared to the frequency several cycles ago. This makes it possible to stop the output of the inverter unit 160 at a higher speed than when normal active islanding detection is performed.

In addition to relaxing the judgment criteria, when the isolated operation possibility judgment unit 176 judges that there is an isolated operation possibility judgment, the judgment criteria may be switched to a different one (judgment criteria switching process). For example, whether the frequency has fluctuated several times in the same direction may not be included in the judgment, and active isolated operation detection judgment may be performed only based on whether the most recent frequency has fluctuated by more than a certain threshold (e.g., 0.7 Hz) compared to the frequency several cycles ago. Alternatively, a completely different threshold may be used, such as using a judgment criterion of whether the voltage harmonics have fluctuated by more than a judgment threshold (e.g., 2 V).

Furthermore, regarding the amount by which the threshold is relaxed, it is possible to prevent malfunctions in the islanding detection by determining the amount of relaxation according to the difference between the deviation in reactive power and the expected amount of reactive power change. For example, if the difference between the deviation in reactive power and the expected amount of reactive power conversion is very large, the threshold can be relaxed significantly, and if the difference is small, the threshold can be relaxed only slightly, thereby preventing malfunctions. The numerical value of the amount by which the threshold is relaxed may be calculated linearly, or may be based on a table.

In this way, by executing a process to stop the output of the inverter unit 160 when it is determined that there is a possibility of islanding, it is possible to more reliably detect islanding and stop the operation of the PCS 101.

(Second Configuration Example)
In the above-mentioned first configuration example, the deviation of reactive power is calculated to execute the islanding possibility determination process, but the islanding possibility determination process may be executed using the reactive power itself instead of the deviation of reactive power. That is, when the difference between the calculated reactive power and the assumed reactive power exceeds a predetermined threshold, it may be determined that there is a possibility of islanding.

In this case, the expected reactive power is calculated from the output current and g-rate, and compared with the actually calculated reactive power to determine the possibility of islanding.

If the configuration determines the possibility of islanding based on the difference between the reactive power calculated in this way and the expected reactive power, the possibility of islanding can be determined without using the saved past reactive power array, making it unnecessary to save the past reactive power array.

(Third Configuration Example)
21 is an overall block diagram showing a third configuration example of a PCS equipped with an islanding operation possibility determination processing unit 170. This PCS 102 determines the presence or absence of islanding operation possibility based on whether the output current is different from the assumption, and executes a process to stop the output from the inverter unit 160 when it is determined that there is an islanding operation possibility. That is, the PCS 102 differs from the above-mentioned PCS 101, which determines the presence or absence of islanding operation possibility based on reactive power, in that it determines the presence or absence of islanding operation possibility based on the output current. As shown in this figure, the islanding operation possibility determination processing unit 170 of the PCS 102 includes an assumed output current calculation unit 177 and an islanding operation possibility determination unit 176.

The expected output current calculation unit 177 calculates the expected output current (the value that is approximately expected to be output when the output current is in a grid-connected state) for a certain point in time or period within one cycle or half cycle in a cycle where g-rate ≠ 1, and for the time from the grid voltage zero crossing point and the PWM data Dp'.

Figure 22 is a graph for explaining an example of calculation of the expected output current in the expected output current calculation unit 177. As shown in this figure, the current is different at a point with the same distance from the voltage zero crossing during grid connection (1002 in Figure 22) and during islanding operation (1003 in Figure 22). Therefore, the expected output current calculation unit 177 has a table of the expected output current that stores both each point from the voltage zero crossing and the magnitude of the output current, and can calculate the expected reactive power conversion amount using this table. Alternatively, the expected output current calculation unit 177 may calculate a numerical value by calculation. The expected output current calculation unit 177 outputs the calculated expected output current to the islanding operation possibility determination unit 176.

In the PCS 102, the islanding operation possibility determination unit 176 determines whether or not there is a possibility of islanding operation based on the output current and the assumed output current output from the assumed output current calculation unit 177. For example, if the difference between the output current and the assumed output current exceeds a predetermined threshold (output current - assumed output current > threshold), the islanding operation possibility determination unit 176 determines that there is a possibility of islanding operation.

In this way, by determining whether or not islanding is possible based on the output current, it is possible to increase the processing speed without the need to perform the reactive power calculations described in the first configuration example above. Note that the above-mentioned method for preventing erroneous determination is effective even in this case.

(Fourth Configuration Example)
The islanding possibility determination processing unit 170 may further superimpose harmonic distortion on the PWM data Dp' when the determination is made in the above-mentioned first to third configuration examples. In that case, if the amount of harmonic distortion superimposed is smaller than the amount of harmonic distortion superimposed on the output current expected, it is determined that there is a possibility of islanding. Note that the superimposition process of harmonic distortion may be performed independently regardless of the above-mentioned first to third configuration examples.

<Other Modifications>
In addition to the above-described embodiment, the configuration of the present invention can be modified in various ways without departing from the spirit of the invention. In other words, the above-described embodiment should be considered to be illustrative in all respects and not restrictive, and the technical scope of the present invention is indicated by the claims, not the description of the above-described embodiment, and should be understood to include all modifications that fall within the meaning and scope of the claims.

[Software implementation example]
The control block (CPU) of the PCS described above may be realized by a logic circuit (hardware) formed in an integrated circuit (IC chip) or the like, or may be realized by software.

In the latter case, the PCS is equipped with a computer that executes the instructions of a program, which is software that realizes each function. This computer is equipped with, for example, at least one processor (control device) and at least one computer-readable recording medium that stores the program. The object of the present invention is achieved by the processor reading the program from the recording medium and executing it in the computer. The processor can be, for example, a CPU (Central Processing Unit). The recording medium can be a "non-transient tangible medium," such as a ROM (Read Only Memory), as well as a tape, a disk, a card, a semiconductor memory, a programmable logic circuit, etc. The computer can also be equipped with a RAM (Random Access Memory) that expands the program. The program can be supplied to the computer via any transmission medium (such as a communication network or broadcast waves) that can transmit the program. One aspect of the present invention can also be realized in the form of a data signal embedded in a carrier wave, in which the program is embodied by electronic transmission.

(summary)
The inverter device according to aspect 1 of the present invention includes a power conversion unit that converts DC power into AC power and connects it to an AC power system, monitors the system frequency to detect islanding, and promotes a frequency change in the system frequency by injecting reactive power according to a deviation of the system frequency, and when a sudden increase in harmonic distortion is detected, forcibly causes a deviation in the system frequency by injecting the reactive power in a stepwise manner, determines whether or not islanding is possible, and if it is determined that islanding is possible, executes a stop process to stop the output of the power conversion unit.

The above configuration makes it possible to provide an inverter device that can more reliably detect isolated operation and stop operation.

In the inverter device according to aspect 2 of the present invention, in the above aspect 1, the reactive power or the deviation of the reactive power output from the power conversion unit may be calculated, and if the difference between the calculated reactive power or the deviation of the reactive power and the expected amount of change in the reactive power or the reactive power exceeds a predetermined threshold, it may be determined that there is a possibility of isolated operation.

In the inverter device according to aspect 3 of the present invention, in the above aspect 2, the expected reactive power or the amount of change in the reactive power may be calculated from the output current of the power conversion unit and the increase rate of a read counter of PWM data that controls the power conversion unit.

In the inverter device according to aspect 4 of the present invention, as in aspect 1 above, the output current output from the power conversion unit may be measured, and if the difference between the measured output current and the expected output current output from the power conversion unit exceeds a predetermined threshold, it may be determined that there is a possibility of isolated operation.

In the inverter device according to aspect 5 of the present invention, in any one of aspects 1 to 4 above, the stop process may be an output stop process that stops the output of the power conversion unit.

In the inverter device according to aspect 6 of the present invention, in any of aspects 1 to 4 above, the stop process may be a criterion relaxation process that relaxes the criteria for active islanding detection.

In the inverter device according to aspect 7 of the present invention, in the above aspect 6, the judgment criterion may be to perform active islanding detection when the deviation of the grid frequency exceeds a predetermined judgment threshold, and the judgment criterion relaxation process may be a process of reducing the judgment threshold.

In the inverter device according to aspect 8 of the present invention, in the above aspect 6 or 7, the judgment criterion may be to perform active islanding detection when the deviation of the grid frequency exceeds a predetermined judgment threshold continuously for a predetermined judgment period or more, and the judgment criterion relaxation process may be a process of shortening the period of the judgment period.

In the inverter device according to aspect 9 of the present invention, in the above aspect 7, the amount by which the judgment threshold is reduced may be calculated based on the difference between the reactive power or the deviation of the reactive power and the expected amount of change in the reactive power or the reactive power.

In the inverter device according to aspect 10 of the present invention, in any of aspects 1 to 4 above, the stop process may be a criterion switching process that switches the criterion for active islanding detection to another criterion.

In the inverter device according to aspect 11 of the present invention, in the above aspect 10, the judgment criteria switching process may be a process of switching the judgment criteria so as to perform active islanding detection when the voltage harmonics exceed a threshold value.

The distributed power supply system according to aspect 12 of the present invention includes a DC power supply, an inverter device according to any one of aspects 1 to 11 above that converts DC power input from the DC power supply into AC power and connects the DC power to an AC power grid, and a load that operates by receiving the supply of AC power.

The above configuration makes it possible to provide a distributed power system that can more reliably detect islanding and stop the operation of the inverter device.

In the distributed power supply system according to aspect 13 of the present invention, in aspect 12 above, the DC power supply may be a PV module.

The inverter device according to each aspect of the present invention may be realized by a computer. In this case, the control program for the inverter device, which causes the computer to operate as each unit (software element) of the inverter device, thereby realizing the inverter device on the computer, and the computer-readable recording medium on which the control program is recorded, also fall within the scope of the present invention.

Reference Signs List 1 Inverter device 2 DC power supply 3 Load 4 Inverter main circuit 5 Voltage detector 6 Zero-cross detection circuit 7 Current detector 8 A/D converter 9 DSP
REFERENCE SIGNS LIST 10 Abnormal voltage detection circuit 11 Timer/counter circuit 12 Gate drive circuit 13 Reactor 14 Capacitor 15 Filter 16 AC power system 17 Circuit breaker 18 Pole transformer 19 Current reference waveform memory 20 Multiplication unit 21 Error signal creation unit 22 Error waveform pattern integration circuit 23 PWM processing circuit 24 PWM memory 25 Zero-cross period detection processing circuit 100 PCS (power conditioner)
101 PCS (power conditioner)
102 PCS (power conditioner)
110 System frequency measurement unit 111 Frequency detection circuit 112 Frequency measurement processing unit 113 Phase difference measurement synchronization processing unit 120 Frequency feedback unit (reactive power injection unit)
121 First moving average calculation unit 122 Second moving average calculation unit 123 Frequency deviation calculation unit 124 Reactive power injection amount calculation unit 125 Addition unit 130 Reactive power step injection unit 131 Fundamental wave voltage measurement circuit 132 Harmonic voltage measurement circuit 133 Fundamental wave voltage calculation unit 134 Harmonic voltage calculation unit 135 Step injection occurrence condition determination unit 136 Step injection amount calculation unit 140 Islanding operation detection unit 141 Active islanding operation detection unit 142 Passive islanding operation detection unit 150 Current control processing unit 160 Inverter unit (power conversion unit)
170 Islanding operation possibility determination processing unit PW AC power system X Photovoltaic power generation system (distributed power source)
X1 PCS (inverter device)
X2 PV panel X11 Grid-connected inverter unit X12 Islanding operation prevention function unit X13 Islanding operation prevention assistance unit Y Load device H Consumer

Claims (11)

An inverter device including a power conversion unit that converts DC power into AC power and connects the power to an AC power system,
A reactive power injection process for injecting reactive power into an output of the power conversion unit;
a first isolated operation detection process for detecting an isolated operation of the inverter device based on a change in a system frequency caused by the injection of the reactive power;
After the reactive power injection process, (A) a reactive power deviation, which is a difference between reactive power in a recent cycle and reactive power in a past cycle, or reactive power output from the power conversion unit, calculated based on a system voltage and an output current of the power conversion unit, or (B) a second isolated operation detection process for determining whether or not there is a possibility of isolated operation of the inverter device, based on the output current of the power conversion unit , is executed;
the inverter device executing a stop process for stopping an output of the power conversion unit when the second isolated operation detection process determines that there is a possibility of the inverter device being in isolated operation. When determining whether or not there is a possibility of the inverter device operating independently based on (A),
The second isolated operation detection process includes :
2. The inverter device according to claim 1, wherein, when a difference between the calculated reactive power and a reactive power assumed when the inverter device is operated in a grid-connected state, or a difference between the calculated reactive power deviation and a change in reactive power assumed when the inverter device is operated in a grid-connected state, exceeds a predetermined threshold value, it is determined that there is a possibility of isolated operation. The reactive power injection process adjusts the reactive power output from the power conversion unit by distorting the output waveform by changing an increment rate of a counter that specifies an address for reading PWM data from a data string of PWM data that defines an output waveform of the power conversion unit;
The inverter device according to claim 2 , wherein the second isolated operation detection process calculates the expected reactive power or the amount of change in the reactive power from an effective output power of the power conversion unit and the rate of increase. When determining whether or not there is a possibility of the inverter device operating independently based on (B),
The inverter device according to claim 1, wherein the second isolated operation detection process determines that there is a possibility of isolated operation when a difference between the output current and an output current output from the power conversion unit expected when the inverter device is operated in a grid-connected state exceeds a predetermined threshold value. The inverter device according to claim 1 , wherein the stop process is an output stop process for stopping an output of the power conversion unit. The inverter device according to claim 1 , wherein the stop process is a criterion relaxing process that relaxes a criterion for the first isolated-operation detection process. the determination criterion is to detect an islanding operation when a deviation of a system frequency, which is a difference between the system frequency in a recent cycle and the system frequency in a past cycle, exceeds a predetermined determination threshold value;
The inverter device according to claim 6 , wherein the determination criterion relaxing process is a process of reducing the determination threshold value. the determination criterion is to detect an islanding operation when a deviation of a system frequency, which is a difference between the system frequency in a recent cycle and the system frequency in a past cycle, exceeds a predetermined determination threshold value for a predetermined determination period or more consecutively,
8. The inverter device according to claim 6, wherein the determination criterion relaxing process is a process for shortening a period of the determination cycle. 8. The inverter device according to claim 7, wherein an amount by which the judgment threshold is reduced is calculated based on a difference between the reactive power output from the power conversion unit and the reactive power assumed when the inverter device is operated in a grid-connected state, or based on a difference between a reactive power deviation, which is a difference between the reactive power in a most recent cycle and the reactive power in a past cycle output from the power conversion unit, and an amount of change in the reactive power assumed when the inverter device is operated in a grid-connected state. The inverter device according to claim 1 , wherein the stop process is a criterion switching process for switching a criterion of the first isolated-operation detection process to another criterion. The inverter device according to claim 10, wherein the judgment criterion switching process is a process of switching the judgment criterion so that the first isolated operation detection process detects an isolated operation when a voltage harmonics contained in the system voltage exceeds a predetermined judgment threshold.

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