JP7494526B2 - MEMORY ALLOCATION METHOD AND PROCESSING APPARATUS - Patent application - Google Patents

Description

The present invention relates to a memory allocation method and processing device for executing a data flow graph.

Conventionally, various methods and devices have been used to execute data flow graphs (see, for example, Patent Document 1).

JP 2019-71120 A

When executing a dataflow graph, memory allocation must be performed to allocate memory space for the buffers required to execute the nodes.

The object of the present invention is to provide a memory allocation method and processing device that can achieve appropriate memory allocation.

The first embodiment of the present invention is a memory allocation method for executing a data flow graph, comprising: a first allocation step of allocating an input buffer from one direction side and an output buffer from the reverse direction side in a specified shared area of a memory area at a specified stage of the data flow graph; and a second allocation step of allocating an input buffer from the reverse direction side in the specified shared area and an output buffer from the one direction side at a stage next to the specified stage of the data flow graph.

The second embodiment of the present invention is a processing device (10) for executing a data flow graph, comprising a memory (12) having a memory area, an arithmetic unit (14) for executing nodes of the data flow graph and performing input/output to the memory area, and a memory allocation device (16) for allocating an input buffer from one direction side and an output buffer from the reverse direction side in a specified shared area of the memory area at a specified stage of the data flow graph, and allocating an input buffer from the reverse direction side in the specified shared area at a stage next to the specified stage, and allocating an output buffer from the one direction side in the specified shared area.

The present invention makes it possible to achieve appropriate memory allocation.

FIG. 1 is a block diagram showing a processing device according to an embodiment of the present invention. FIG. 2 is a schematic diagram showing a data flow graph according to an embodiment of the present invention. 2 is a flow diagram illustrating a memory allocation method according to an embodiment of the present invention. 1 is a schematic diagram showing a memory allocation method according to an embodiment of the present invention;

One embodiment of the present invention will be described with reference to Figures 1 to 4.

A processing apparatus 10 according to the present embodiment will be outlined with reference to FIG.
As shown in Fig. 1, a processing device 10 is mounted on an embedded system and executes a data flow graph. In the processing device 10, a memory 12 has a memory area. An arithmetic unit 14 executes nodes of the data flow graph and executes input/output to the memory area of the memory 12. A memory allocation unit 16 allocates an input buffer from one direction side and an output buffer from the reverse direction side in a predetermined shared area in the memory area of the memory 12 at a predetermined stage of the data flow graph, and allocates an input buffer from the reverse direction side of the shared area at the next stage of the predetermined stage and allocates an output buffer from the one direction side. The memory allocation unit 16 also allocates a shared buffer to be used across all stages of the data flow graph to a predetermined common area in the memory area of the memory 12.

The processing method of this embodiment will be described with reference to Figures 2 to 4.

The data flow graph of this embodiment will be described with reference to FIG.
The data flow graph of this embodiment is a forward data flow graph with no backtracking. The data flow graph is divided into stages that are executed simultaneously. In each stage, a node is executed for input from an input buffer, and output is made to an output buffer.

In this embodiment, as shown in FIG. 2, the data flow graph is divided into stages 1 to 3. In stage 1, nodes n1 and n2 are executed for input from input buffer b1, and output is provided to output buffers b2 and b3, respectively. In stage 2, node n3 is executed for input from input buffers b2 and b3, and output is provided to output buffer b4. In stage 3, node n4 is executed for input from input buffers b3 and b4, and output is provided to output buffer b5. Here, buffer b3 is a common buffer used across stages 1 to 3.

The memory allocation method of this embodiment will be described with reference to FIG. 3 and FIG.
In the memory allocation method of this embodiment, when a graph program of a data flow graph is compiled, the division of the stages of the data flow graph and the allocation of memory in the memory area are statically performed.

Each memory element in the memory area is assigned an address in sequence, and the beginning and end of the address are called the upper and lower sides, respectively.

In the memory area, a shared area is secured that is used for each stage of the dataflow graph, and a common area is secured that is used across all stages. Then, at a specific stage of the dataflow graph, an input buffer is assigned from one side of the shared area of the memory area, and an output buffer is assigned from the opposite side, and at the stage following the specific stage, an input buffer is assigned from the opposite side of the shared area, and an output buffer is assigned from the one side. A common buffer that is used across all stages is also assigned to the common area of the memory area.

The shared and common memory areas are allocated sizes that will not cause memory shortages during execution of the graph program of the dataflow graph. In other words, the size required for the shared area is the maximum total size of the total sizes of the input/output buffers required at each stage. The size required for the common area is the total size of all the common buffers.

In this embodiment, as shown in Figures 3 and 4, in stage 1 (S1) of the data flow graph, in the shared area R of the memory area, an input buffer b1 is allocated from the upper side, which is one direction, and an output buffer b2 is allocated from the lower side, which is the opposite direction. In addition, a common buffer b3 is allocated as an output buffer to the common area S of the memory area. As described above, in stage 1 of the data flow graph, nodes n1 and n2 are each executed in response to input from input buffer b1, and output is made to output buffers b2 and b3, respectively.

In stage 2 (S2), in the shared area R of the memory area, input buffer b2 is allocated from the lower side, which is the opposite direction side, and output buffer b4 is allocated from the upper side, which is the one-way side. In addition, common buffer b3 is allocated as an input buffer to the common area S of the memory area. As described above, in stage 2, node n3 is executed in response to inputs from input buffers b2 and b3, and output is made to output buffer b4.

In stage 3 (S3), in the shared area R of the memory area, input buffer b4 is allocated from the upper side, which is one direction, and output buffer b5 is allocated from the lower side, which is the opposite direction. In addition, common buffer b3 is allocated as an input buffer to the common area S of the memory area. As described above, in stage 3, node n4 is executed in response to inputs from input buffers b3 and b4, and output is made to output buffer b5.

The size required for the shared region R of the memory area is the total size of the input buffer b1 and the output buffer b2 in stage 1, the total size of the input buffer b2 and the output buffer b4 in stage 2, and the total size of the input buffer b4 and the output buffer b5 in stage 3. Here, since the total size of stage 3 is the maximum total size, the size required for the shared region R of the memory area is the total size of the input buffer b4 and the output buffer b5, which is the total size of stage 3. Also, the size required for the common region R of the memory area is the size of the common buffer b3.

The memory allocation device and method of this embodiment provide the following advantages:

In this embodiment, a shared area is reserved in the memory area, and at a specified stage of the data flow graph, an input buffer is allocated from one side of the shared area and an output buffer is allocated from the opposite side, and at the next stage after the specified stage, an input buffer is allocated from the opposite side of the shared area and an output buffer is allocated from the one side. The size required for the shared area is the maximum total size of the total sizes of the input/output buffers required at each stage.

To use a memory area as a buffer, a continuous memory area corresponding to the buffer is required. In a memory allocation method in which a memory area is reserved each time a buffer is required to execute each node of the dataflow graph and the memory area is released each time the buffer is no longer required, if the size of the buffer required to execute each node is different, this leads to memory area fragmentation, which generates memory areas that cannot be used as buffers. In this case, it is necessary to stop the graph program and organize the memory area to eliminate the fragmentation, which is particularly unsuitable for embedded systems. In addition, if a memory area of a constant size is always reserved regardless of the size of the buffer required to execute each node of the dataflow graph, it is possible to avoid memory area fragmentation, but memory utilization efficiency will decrease.

In contrast, in the present embodiment described above, fragmentation of memory space does not occur in principle, and memory usage is more efficient than when a fixed size memory space is always reserved to execute each node in the data flow graph.

In addition, in a memory allocation where the shared memory area is simply divided in half and an input buffer and an output buffer are alternately assigned to the memory area on one side and an output buffer and an input buffer to the memory area on the opposite side for each stage, the size required for the shared area is twice the maximum total size of the total size of the input buffers or the total size of the output buffers required for each stage.

In contrast, in the embodiment described above, the size required for the shared area is merely the maximum total size of the total sizes of the input/output buffers required at each stage, resulting in high memory utilization efficiency.

Furthermore, in this embodiment, when the graph program of the data flow graph is compiled, the division of the stages of the data flow graph and the allocation of memory in the memory area are performed statically, so that memory shortages do not occur during execution of the graph program. Note that when the graph program of the data flow graph is executed, the division of the stages of the data flow graph and the allocation of memory in the memory area may be performed dynamically.

10: Processing device 12: Memory 14: Arithmetic unit 16: Memory allocation device

Claims (4)

1. A memory allocation method for executing a data flow graph executed by a memory allocation apparatus , comprising:
A step of reserving a predetermined number of consecutive memory elements as a predetermined shared area in a memory area consisting of a plurality of memory elements to which addresses are sequentially assigned;
a first allocation step of allocating input buffers to a plurality of consecutive memory elements from one address direction side in the predetermined shared area and allocating output buffers to a plurality of consecutive memory elements from an opposite address direction side in the predetermined shared area in a predetermined stage of the data flow graph;
a second allocation step of allocating input buffers to a plurality of consecutive memory elements from a reverse direction side of the address in the predetermined shared area and allocating output buffers to a plurality of consecutive memory elements from one direction side of the address in a stage next to the predetermined stage of the data flow graph;
1. A memory allocation method comprising: reserving, as a predetermined common area, a predetermined number of consecutive memory elements in the memory area, which are different from the memory elements in which the predetermined shared area is set;
an additional allocation step of allocating a common buffer to the predetermined common area, the common buffer being used across multiple stages of the data flow graph ;
2. The memory allocation method of claim 1, further comprising: dividing the stages of the data flow graph and allocating memory in the memory area when compiling a graph program of the data flow graph;
2. The memory allocation method according to claim 1. A processing device (10) for executing a data flow graph, comprising:
a memory (12) having a memory area made up of a plurality of memory elements to which addresses are sequentially assigned ;
an arithmetic unit (14) for executing nodes of the data flow graph and performing input/output to the memory region;
a memory allocation device (16) that reserves a predetermined number of consecutive memory elements in the memory area as a predetermined shared area, and in a predetermined stage of the data flow graph, assigns an input buffer to a plurality of consecutive memory elements in the predetermined shared area from one address direction and assigns an output buffer to a plurality of consecutive memory elements in the opposite address direction, and in a stage next to the predetermined stage, assigns an input buffer to a plurality of consecutive memory elements in the predetermined shared area from the opposite address direction and assigns an output buffer to a plurality of consecutive memory elements in the predetermined shared area from the one address direction;
A processing device comprising:

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