JP4409568B2 - Band control program and multiprocessor system - Google Patents

Description

  The present invention relates to a bandwidth control program and a multiprocessor system for controlling a memory bandwidth in which each of a plurality of processor elements can access a memory.

  Recently, computer hardware (hereinafter referred to as a multiprocessor system) that has a plurality of processor elements (PE) and that the PEs share and use, for example, one memory unit (hereinafter simply referred to as memory). Is written).

  On such a multiprocessor system, an operating system (hereinafter referred to as OS) operates on at least one PE.

  The OS includes a scheduler. The scheduler executes a process of assigning a number of tasks generated by the OS itself or user applications to each PE. As a result, the entire multiprocessor system operates. Here, a task is a processing unit to be executed by each PE.

  Usually, since the number of tasks to be executed is larger than the number of PEs, it is necessary to perform scheduling such that the execution time of PEs is divided and assigned to each task. Further, the plurality of tasks include, for example, a task that should be completed relatively quickly, a task whose execution may be delayed, or an intermediate task between them. Of the multiple tasks, execute many PEs for tasks that should be completed early, use less PEs for tasks that may be delayed in execution, or intermediate for those intermediate tasks Scheduling that gives the PE execution time is desirable.

  Therefore, a priority value (processing priority) is set for each of the plurality of tasks. For example, the smaller the value of the priority value, the more PE execution time is given. For example, in the case where the priority value is either 0 or 1, a task with a priority value of 0 is executed with more PE execution time than a task with a priority value of 1. Hereinafter, a task with a higher PE execution time (for example, a priority value of 0) is a task with a higher priority value, and a task with a lower PE execution time (for example, a priority value of 1) is a task with a lower priority value. Called.

  Each of the PEs operates with a large execution time for a task with a high priority value and with a short execution time for a task with a low priority value, for example, among the tasks assigned to the PE.

For example, a technique for managing the quality of service to each resource requesting device is disclosed (for example, using a fixed priority order and not knowing the relationship between the resource requesting devices other than the priority order) (for example, (See Patent Document 1).
JP 2004-5589 A

  However, even when the PE execution time is assigned according to the priority value for each task as described above, the efficiency of the entire system cannot be improved by simply increasing or decreasing the PE execution time. There are factors. One of the factors is a processing delay during memory access.

  In a hardware configuration in which a plurality of PEs access the same memory as described above, a significant processing delay may occur due to contention between the memory accesses of the PEs. For example, when memory accesses are concentrated from PEs that are executing tasks with low priority values, the memory accesses of PEs that are executing tasks with high priority values are slowed down. As a result, an inefficient state in which substantial processing corresponding to the execution time of the PE given to each task cannot be performed occurs.

  Therefore, there is hardware that can set a limit value (maximum value) or a guaranteed value (minimum value) of the bandwidth at which each PE can access a memory (or bus), for example. On such hardware, when a PE executes a task with a low priority value, the OS narrowly limits the bandwidth with which the PE can access the memory. Conversely, when a PE executes a task with a high priority value, the OS guarantees a wide bandwidth for the PE to access the memory, and does not limit it. Thereby, it is possible to avoid an inefficient state due to competition of memory access from each PE.

  However, when the memory bandwidth is set for each PE according to the task (priority value) at the time of task execution, when there are multiple tasks whose priority value is not the lowest, it is appropriate for each PE that executes each task. Discriminating a large bandwidth requires a very complicated process. In other words, when each PE starts executing a task, the bandwidth for each PE in the entire system and the priority value of the task executed by each PE are determined, and the bandwidth that allows each PE to access the memory is determined. However, if necessary, it is necessary to change the bandwidth of another PE. Performing such complicated processing itself naturally consumes the execution time of the PE, and further, the bandwidth of each PE needs to be adjusted each time the priority value of the task executed by each PE changes. For this reason, there is a possibility that the execution efficiency of the task of the entire system is lowered.

  On the other hand, there is hardware that can manage a memory bandwidth by grouping a plurality of PEs. This is used for the purpose of virtually dividing the memory when, for example, one piece of hardware is virtually divided into a plurality of computers.

  An object of the present invention is to provide a bandwidth control program and a multiprocessor system that can set a memory bandwidth of each PE at high speed and easily by grouping a plurality of PEs.

  According to one aspect of the present invention, a plurality of processor elements, a memory accessed to each of the plurality of processor elements, and a memory bandwidth that each of the plurality of processor elements can access the memory are limited. In a multiprocessor system including a memory controller, a bandwidth control program executed by at least one of the plurality of processor elements is provided. The bandwidth control program sets, in the memory controller, a memory bandwidth for each processor element group to which each of the plurality of processor elements belongs, and a task to be executed. Assigning the task to one of the plurality of processor elements to execute the generated task, and causing the assigned processor element to execute the generated task. Determining a processor element group to which the assigned processor element should belong according to an operating condition or an operating state of the generated task; and to the assigned processor element to belong to the determined processor element group, The processor set in the memory controller. In memory bandwidth element group and a step of executing the generation task.

  According to the present invention, the memory bandwidth of each PE can be set quickly and easily by grouping a plurality of PEs.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram showing a hardware configuration of a multiprocessor system according to this embodiment.

  The multiprocessor system of FIG. 1 mainly includes a plurality of processor elements (processor elements) 10, a memory controller 20, a memory 30, an I / O controller 40, and an external storage device 50. Hereinafter, the processor element is simply expressed as PE.

  Each of the plurality of PEs 10 is, for example, a main processor or a sub processor provided for controlling the operation of the multiprocessor system. The plurality of PEs 10 include PE (0), PE (1), PE (2), and PE (3). The plurality of PEs 10 execute various application programs such as an operating system (hereinafter referred to as OS) 51 and a user application program stored in the external storage device 50, for example. The plurality of PEs 10 are connected to the memory 30 via a memory controller 20 that performs memory access control. The plurality of PEs 10 share and use one memory 30, for example.

  The memory controller 20 includes a bandwidth control unit 21. The bandwidth control unit 21 sets a limit value (maximum value) or guaranteed value (minimum value) of the bandwidth that allows each PE to access the memory 30. In addition, the memory controller 20 groups each of the plurality of PEs 10 and manages the memory bandwidth.

  The plurality of PEs 10 are connected to, for example, the external storage device 50 or other devices via an I / O controller 40 that controls exchanges with various devices.

  The external storage device 50 stores an OS 51 executed by a plurality of PEs 10. The OS 51 is a program for integrated management of, for example, allocation of hardware resources and software resources of a multiprocessor system. Further, the OS 51 operates on at least one PE, for example, PE (0) among the plurality of PEs 10.

  Here, for example, by executing the OS 51 on at least one of the plurality of PEs 10, processing such as allocation of hardware resources and software resources of the multiprocessor system is executed. However, in the following description, it is assumed that the OS 51 performs various processes in order to avoid complexity.

  For example, the OS 51 executes a process of assigning a task to be executed (processed) to a plurality of PEs 10 to one of the PEs 10. Many of these tasks occur depending on the OS 51 and user applications. Each of the generated tasks is assigned to each of the plurality of PEs 10 by the OS 51. For each task, for example, operating conditions are predetermined. A task has, for example, an execution priority (Priority) value indicating a priority at which the task is executed as a predetermined operation condition. The smaller the execution priority value, the higher the execution priority value (priority). For example, when the execution priority value is 0, the execution priority value is the highest. Further, the OS 51 controls the memory bandwidth set by the bandwidth controller 21 of the memory controller 20 described above.

  The plurality of PEs 10, the memory controller 20, the memory 30, the I / O controller 40, the external storage device 50, and the like are connected via a bus, for example.

  Next, FIG. 2 is a block diagram mainly showing a functional configuration of the OS 51 shown in FIG. The OS 51 includes a bandwidth setting unit 511, a scheduler 512, and a group setting unit 513. These units 511 to 513 are realized by executing the OS 51 in which at least one PE among the plurality of PEs 10 illustrated in FIG. 1 is stored in the external storage device 50. The OS 51 can be stored in advance in a computer-readable storage medium and distributed.

  Further, the external storage device 50 shown in FIG. 1 stores a group / bandwidth table 52, a group / priority table 53, and a task table 54.

  The band setting unit 511, for example, according to a value input by the user, group identification information for identifying each of a plurality of PE groups to which each of the plurality of PEs 10 belongs, and PEs belonging to the PE group indicated by the group identification information. Bandwidth information indicating the memory bandwidth accessible to the memory 30 is associated and registered in the group / bandwidth table 52. The bandwidth setting unit 511 refers to the group / band table 52 and sets the memory bandwidth for each PE group in the memory controller 20 (the bandwidth control unit 21 thereof). The group / bandwidth table 52 may have a configuration in which group identification information and bandwidth information are registered in advance as system settings.

  In the group priority table 53, an execution priority value indicating the priority at which each of the tasks described above is executed and group identification information indicating the PE group to which the PE executing the task belongs are stored in advance.

  In the task table 54, for example, generated tasks (information relating to) are registered. In the task table 54, for example, an execution priority value is stored in association with each task.

  For example, the scheduler 512 executes processing for creating the task table 54 when the OS 51 is activated. When a task occurs, the scheduler 512 registers the task in the task table 54. The scheduler 512 executes processing for assigning the task registered in the task table 54 to each PE. As a result, the scheduler 512 attempts to execute a plurality of tasks using a plurality of PEs 10. For example, the scheduler 512 divides the execution time of PEs and assigns them to tasks. For example, the scheduler 512 allocates a large amount of execution time to a task having a high execution priority value, and allocates a small execution time to a task having a low execution priority value.

  In addition, the scheduler 512 performs a task with a memory bandwidth indicated by the bandwidth information held in the group / bandwidth table 52 in association with the group identification information for a PE in which group identification information to be described later is set. Let it run. That is, the scheduler 512 causes each PE to execute a task with the memory bandwidth for each PE group set in the memory controller 20.

  The scheduler 512 assigns a task to each PE by adding the task registered in the task table 54 to the task queue (not shown) of each PE. When a task is assigned to each PE, the identifier of the PE that executes the task is registered in the task table 54 in association with the task. The scheduler 512 adds tasks to the task queue of each PE in descending order of execution priority, for example. This task queue is stored in the external storage device 50.

  Each of the plurality of PEs 10 operates (processes) with reference to its own task queue, for example, giving a large execution time to a task with a high execution priority and a low execution time to a task with a low execution priority.

  The scheduler 512 includes a group determination unit 514. The group determination unit 514 determines a PE group to which each PE should belong according to, for example, an operation condition of a task executed by each PE. The group determination unit 514 refers to the group / priority table 53 and the task table 54 and determines the PE group of each PE from the execution priority value of the task executed by each PE. The group determination unit 514 acquires the execution priority value held in the task table 54 in association with the task executed by each PE. The group determination unit 514 determines the PE group indicated by the group identification information held in the group / priority table 53 in association with the acquired execution priority value as a PE group to which each PE belongs.

  The group setting unit 513 sets group identification information (PE group number) indicating the PE group of each PE determined by the group determination unit 514 in the PE group register of each PE. The PE group register is a storage area that exists in each PE and sets group identification information (identifier) of a PE group to which each PE belongs.

  Each PE executes a task with the memory bandwidth of the PE group indicated by the group identification information set in the memory controller 30 by the bandwidth setting unit 511 by setting the group identification information in the PE group register of each PE. To do.

  Next, a processing procedure in which the bandwidth setting unit 511 of the OS 51 creates (registers) the group / bandwidth table 52 will be described with reference to the flowchart of FIG. This process is executed, for example, when the system starts operating or when the operation mode is changed.

  First, the bandwidth setting unit 511 receives, for example, an input of the number of PE groups input by the user (step S1). Here, it is assumed that the number of PE groups input by the user is N (N is an integer of 2 or more).

  Next, the bandwidth setting unit 511 sets “0” as an initial value of the group n (n = 0, 1, 2,..., N−1), for example (step S2).

  The bandwidth setting unit 511 receives, for example, an input of the memory bandwidth for accessing the memory by the PE belonging to the PE group n input by the user (step S3). Here, it is assumed that the memory bandwidth input by the user is Bn%. Bn is assumed to be 1 to 100%.

  The bandwidth setting unit 511 registers (sets) the group identification information indicating the PE group n and the bandwidth information indicating the memory bandwidth Bn input in step S3 in the group / band table 52 on the external storage device 50 (step). S4). Here, group identification information indicating PE group 0 and bandwidth information indicating memory bandwidth B0 are registered in association with each other.

  The bandwidth setting unit 511 adds 1 to the value of the PE group n (step S5). The bandwidth control unit 511 determines whether or not the value of the PE group n is N−1 (step S6). If the bandwidth control unit 511 determines that the value of the PE group n is not N−1 (NO in step S6), the bandwidth control unit 511 returns to step S3 and sets the memory bandwidth for all the PE groups input in step S1. The process is repeated until registration (determination is made as PE group n = N−1 in step S6). In this case, the process returns to step S3, and the process of registering the memory bandwidth B1 of the PE group 1 in the group / bandwidth table 52 is executed.

  For example, the memory bandwidth registered for each PE group is registered such that the total is 100%.

  On the other hand, when it is determined in step S6 that the value of the PE group n is N-1, the process of creating the group / band table 52 is terminated.

  Since the initial value of the PE group is 0 as described above, when processing up to PE group N-1 as described above, the number of PE groups registered in the group / band table 52 is actually N It becomes.

  FIG. 4 shows an example of the data structure of the group / band table 52 created (registered) by the band setting unit 511.

  As shown in FIG. 4, the group / bandwidth table 52 holds group identification information indicating a PE group and memory bandwidth information set for the PE group in association with each other. In the example of FIG. 4, the memory bandwidth B0 indicated by the memory bandwidth information held in association with the group identification information “0” indicating the PE group 0 is “90%”. The memory bandwidth B1 indicated by the memory bandwidth information held in association with the group identification information “1” indicating the PE group 1 is “10%”. In this example, 2 (PE group 0 and PE group 1) is input as the number of PE groups by the user. The total memory bandwidth associated with the group identification information “0” and “1” is 100%.

  Next, a processing procedure in which the bandwidth setting unit 511 sets the memory bandwidth for each PE group in the memory controller 20 will be described with reference to the flowchart of FIG. The processing for setting the memory bandwidth for each PE group is executed when the scheduler of the OS 51 is activated, for example.

  First, the bandwidth setting unit 511 reads the group / bandwidth table 52 from the external storage device 50 (step S11).

  Next, the bandwidth setting unit 511 sets “0” as an initial value of the PE group n (n = 0, 1, 2,..., N), for example (step S2).

  The bandwidth setting unit 511 refers to the group / bandwidth table 52 and sets the memory bandwidth B0 of the PE group 0 in the memory controller 20 (step S13). The bandwidth setting unit 511 sets the memory bandwidth B0 indicated by the memory bandwidth information held in the group / bandwidth table 52 in association with the group identification information indicating the PE group 0.

  The bandwidth setting unit 511 adds 1 to the value of the PE group n (step S14). The bandwidth control unit 511 determines whether or not the value of the PE group n is N−1 (step S15). If the bandwidth control unit 511 determines that the value of the PE group n is not N−1 (NO in step S15), the bandwidth control unit 511 returns to step S13 and applies to all the PE groups held in the group / bandwidth table 52. The process is repeated until the memory bandwidth is set. In this case, the process returns to step S3, and the process of setting the memory bandwidth B1 of the group 1 in the memory controller 20 is executed.

  On the other hand, if it is determined in step S15 that the value of PE group n is N-1, the process of setting the PE group memory bandwidth is terminated, and the process of creating the initial task table and task queue is executed. . As a result, processing (task dispatch) for allocating a plurality of tasks held in the task table 54 to each PE is executed.

  FIG. 6 shows an example of the data structure of the group / priority table 53.

  As shown in FIG. 6, the group priority table 53 holds execution priority values and group identification information. It is assumed that the number of stages of the execution priority value is 2 (execution priority value 0 or 1) and the number of PE groups is 2 (PE group 0 or 1). In the example of FIG. 6, group identification information “0” indicating PE group 0 is held in association with the execution priority value “0”. Further, group identification information “1” indicating PE group 1 is held in association with the execution priority value “1”. The execution priority value and group identification information held in the group priority table 53 are determined in advance, for example, when the system operation is started or when the operation mode is changed.

  FIG. 7 shows an example of the data structure of the task table 54 and the task queue of each PE. As shown in FIG. 7, the task table 54 holds the execution priority value of the task for each task. The task table 54 holds PE identification information indicating the PE to which the task is assigned by the scheduler 512 for each task.

  In the example of FIG. 7, tasks A to C and tasks 1 to 10 are held in the task table 54. The execution priority value of tasks A to C is 0, and the execution priority value of tasks 1 to 10 is 1. It is assumed that the execution priority value is higher in priority than 0 (processing priority). That is, each PE operates with a large execution time for tasks A to C and operates with a small execution time for tasks 1 to 10.

  Further, tasks assigned by the scheduler 512 are registered in the task queue of each PE for each execution priority. A plurality of tasks registered in the task queue of each PE are processed by each PE in the order of registration, for example.

  As shown in FIG. 7, task A is assigned to the task queue of PE (0) as a task with an execution priority value “0”. In addition, tasks 3 and 7 are registered in the task queue of PE (0) as tasks having an execution priority value “1”.

  Similarly, task B is assigned to the task queue of PE (1) as a task with an execution priority value “0”. In addition, tasks 4 and 8 are registered in the task queue of PE (1) as tasks having an execution priority value “1”.

  Similarly, task C is assigned to the task queue of PE (2) as a task with an execution priority value “0”. In addition, tasks 5 and 9 are registered in the task queue of PE (2) as tasks having an execution priority value “1”.

  Similarly, tasks 1, 2, 6, and 10 are registered in the task queue of PE (3) as tasks having an execution priority value “1”.

  A plurality of tasks held in the task table 54 are assigned to each PE in descending order of execution priority value, for example.

  Also, the task table 54 of FIG. 7 shows PE identification information indicating each PE to which each task is assigned as described above for each task. Here, the PE identification information indicating PE (0) is “0”, the PE identification information indicating PE (1) is “1”, the PE identification information indicating PE (2) is “2”, and PE (3). The indicated PE identification information is “3”.

  Next, a processing procedure for setting a PE group to which the PE belongs when each PE executes a task will be described with reference to a flowchart of FIG. Here, processing when PE (0) executes task A will be described. The same applies to other PEs, and the same applies to the execution of other tasks. Moreover, it demonstrates using FIG.4, FIG.6 and FIG.7 as needed.

  First, when the PE (0) executes the task A, the group determination unit 514 of the scheduler 512 refers to the task table 54 shown in FIG. Here, “0”) is acquired (step S21).

  Next, the group determination unit 514 refers to the group / priority table 53 and determines a PE group from the acquired execution priority value (step S22). The group determining unit 514 determines the PE group indicated by the group identification information held in the group / priority table 53 in association with the acquired execution priority value as the PE group to which PE (0) should belong. For example, the group determination unit 514 stores the group identification information “0” in association with the execution priority value “0” in the group priority table 53 illustrated in FIG. It is determined that it is PE group 0.

  The group setting unit 513 sets the PE group number (group identification information) of the PE group determined by the group determination unit 514 in the PE group register of PE (0) (step S23). In this case, “0” is set in the PE group register of PE (0).

  When “0” is set in the PE group register of PE (0), PE (0) is associated with the group identification information “0” and is indicated by the band information held in the group / band table 52. Task A is executed with bandwidth. In the example of the group / bandwidth table 52 shown in FIG. 4, PE (0) can process task A with a memory bandwidth of 90%.

  FIG. 9 shows a flow of processing in which PE (0) to PE (3) execute a plurality of assigned tasks in real time t. A plurality of tasks are assigned to PE (0) to PE (3) as shown in FIG. As shown in FIG. 9, PE (0) to PE (2) have tasks (0-3) with an execution priority value “0” compared to tasks (tasks 3-5, 7-9) with an execution priority value “1”. The execution time of tasks A to C) is increased, and the number of executions is increased. In addition, since all the tasks to be executed (tasks 1, 2, 6, and 10) have the execution priority value “1”, PE (3) executes each task uniformly with the execution time and the number of executions. .

  10 shows that the PE group to which each of PE (0) to PE (3) belongs when the real time t shown in FIG. 9 is t0 and each of the PE (0) to PE (3) can access the memory 30. The memory bandwidth relationship is shown.

  In the example of FIG. 9, at the actual time t0, PE (0) is executing the task 3 with the execution priority value “1”. PE (1) executes task 4 with an execution priority value “1”, PE (2) executes task 5 with an execution priority value “1”, and PE (3) executes task 2 with an execution priority value “1”. is doing. That is, PE (0) to PE (3) are all executing tasks with the execution priority value “1”.

In this case, as shown in FIG. 10, the PE group to which each of PE (0) to PE (3) should belong is PE group 1. Therefore, group identification information (G) “1” is set in each PE group register of PE (0) to PE (3). Thus, in the example of FIG. 10, PE (0) to PE (3) have the memory bandwidth indicated by the bandwidth information stored in the group / bandwidth table 52 in association with the group identification information “1”. The memory 30 can be accessed. That is, in the example of the group / band table 52 shown in FIG. 4, PE (0) to PE (3) can access the memory 30 with a memory bandwidth of 10%.
Here, it is assumed that the real time t shown in FIG. 9 has elapsed from t0 to t1. In this case, the task executed in PE (2) is switched from task 5 to task C. Also, the task executed in PE (3) is switched from task 2 to task 6.

  With reference to the flowchart of FIG. 11, for example, a processing procedure for setting a PE group to which PE (2) should belong when a task executed in PE (2) is switched from task 5 to task C will be described. In addition, it demonstrates using FIG.4, FIG6 and FIG.7 as needed.

  First, it is assumed that a task switching interrupt by task C occurs while PE (2) is executing task 5 (step S31).

  When a task switching interrupt occurs, stop (end) processing of task 5 (previous task) currently being executed by PE (2) is executed (step S32).

  Next, the group determining unit 514 obtains an execution priority value held in the task table 54 in association with task A (new task) executed next to task 5 by PE (2) (step S33). . In the case of the task table 54 illustrated in FIG. 7, the group determination unit 514 acquires the execution priority value “0”.

  The group determination unit 514 refers to the group priority table 53 and determines a PE group from the acquired execution priority value (step S34). For example, the group determination unit 514 holds the group identification information “0” in association with the execution priority value “0” in the group priority table 53 shown in FIG. The group is determined to be PE group 0.

  The group setting unit 513 sets the PE group number (group identification information) of the PE group determined by the group determination unit 514 in the PE group register of PE (2) (step S35). In this case, “0” is set in the PE group register of PE (2).

  As a result, when PE (2) is executing task 5, the group identification information is set in the PE group register of PE (2) for which group identification information “1” has been set. Information “0” is set. Thus, the group identification information of the PE group register can be set (rewritten) according to the priority value of the task executed by each PE.

  When “0” is set in the PE group register of PE (2), PE (2) is associated with the group identification information “0” and the memory band indicated by the band information held in the group / band table 52 Task C is executed with the width. In the example of the group / bandwidth table 52 shown in FIG. 4, PE (2) can process task C with a memory bandwidth of 90%.

  When group identification information “0” is set in the PE group register of PE (2), a process for resuming (starting up) the execution of task C (new task) is executed (step S36). Here, for example, context restoration processing of the task after switching (task C) is executed. Specifically, for example, the task execution state (program address, general-purpose register value, etc.) stored in the main memory is set in the PE. This prepares for the PE to execute the task after switching.

  Note that the processing from step S32 to S36 described above is task switching processing. When the task switching process is completed, the interrupt process is completed (step S37). When the interrupt process is completed, PE (2) executes the switched task (here, task C) with the given bandwidth (here, memory bandwidth 90%).

  When the real time t shown in FIG. 9 has elapsed from t0 to t1, the task executed in PE (3) is switched from task 2 to task 6. Also in this case, the group identification information of the PE group register of PE (3) is set similarly. In this case, since the execution priority values of task 2 and task 6 are both “1”, the group identification information set in the PE group register of PE (3) does not change as a result.

  12 shows that the PE group to which each of PE (0) to PE (3) when the real time t shown in FIG. 9 is t1 and each of the PE (0) to PE (3) can access the memory 30. The memory bandwidth relationship is shown.

  In the example of FIG. 9, at the actual time t1, PE (0) is executing the task 3 with the execution priority value “1”. PE (1) executes task 4 with an execution priority value “1”, PE (2) executes task C with an execution priority value “0”, and PE (3) executes task 6 with an execution priority value “1”. is doing.

  In this case, as shown in FIG. 12, the PE group to which each of PE (0), PE (1), and PE (3) belongs is determined to be PE group 1. The PE group to which PE (2) should belong is determined to be PE group 0. Therefore, group identification information “1” is set in each PE group register of PE (0), PE (1), and PE (3). Further, group identification information “0” is set in the PE group register of PE (2). Thus, in the example of FIG. 12, PE (0), PE (1), and PE (3) are indicated by the bandwidth information held in the group / bandwidth table 52 in association with the group identification information “1”. It becomes possible to access the memory 30 with a memory bandwidth to be increased. The PE (2) can access the memory 30 with the memory bandwidth indicated by the bandwidth information stored in the group / bandwidth table 52 in association with the group identification information “0”. That is, in the example of the group / band table 52 shown in FIG. 4, PE (0), PE (1) and PE (3) have a memory bandwidth of 10% and PE (2) has a memory bandwidth of 90%. Accessible.

  13 shows that the PE group to which each of PE (0) to PE (3) when the real time t shown in FIG. 9 is t2 and each of the PE (0) to PE (3) can access the memory 30. The memory bandwidth relationship is shown. When a task switching interrupt occurs in each PE, the group identification information of the PE group register of each PE is set by the processing as shown in FIG.

  In the example of FIG. 9, at the actual time t2, PE (0) is executing the task A with the execution priority value “0”. PE (1) executes task B with an execution priority value “0”, PE (2) executes task C with an execution priority value “0”, and PE (3) executes task 10 with an execution priority value “1”. is doing.

  In this case, as shown in FIG. 13, the PE group to which each of PE (0) to PE (2) should belong is determined to be PE group 0. Further, the PE group to which PE (3) should belong is determined to be PE group 1. Therefore, group identification information “0” is set in each PE group register of PE (0) to PE (2). Also, group identification information “1” is set in the PE group register of PE (3). Accordingly, in the example of FIG. 13, PE (0) to PE (2) can access the memory 30 with a memory bandwidth of 90% and PE (3) with a memory bandwidth of 10%.

  FIG. 14 shows that the PE group to which each of PE (0) to PE (3) when the real time t shown in FIG. 9 is t3 and each of the PE (0) to PE (3) can access the memory 30. The memory bandwidth relationship is shown.

  In the example of FIG. 9, at the actual time t3, PE (0) is executing the task A with the execution priority value “0”. PE (1) executes task B with an execution priority value “0”, PE (2) executes task 9 with an execution priority value “1”, and PE (3) executes task 10 with an execution priority value “1”. is doing.

  In this case, as shown in FIG. 14, the PE group to which each of PE (0) and PE (1) should belong is determined to be PE group 0. The PE group to which PE (2) and PE (3) should belong is determined to be PE group 1. Therefore, group identification information “0” is set in each PE group register of PE (0) PE (1). Also, group identification information “1” is set in the PE group registers of PE (2) and PE (3). Thus, in the example of FIG. 14, PE (0) and PE (1) can access the memory 30 with a memory bandwidth of 90%, and PE (2) and PE (3) with a memory bandwidth of 10%.

  As described above, in the present embodiment, when a plurality of PEs 10 are grouped, when a task is executed, group identification is performed in the PE group register of the PE that executes the task according to the execution priority value of the task. The memory bandwidth of each PE can be set with a simple procedure of setting information. In addition, since the memory bandwidth is set in the memory controller for each group, the PE executing a task with a high execution priority does not compete with the PE executing a male task with a low execution priority for access to the memory 30. Can perform tasks.

  In the above-described embodiment, the band control unit 21 has been described as being included in the memory controller 20, but may be configured as an independent hardware module.

  In the above-described embodiment, the bandwidth control unit 21 is described as controlling the memory bandwidth. However, for example, the bandwidth control unit 21 is included in the bus controller, and the bandwidth control unit 21 includes each PE and each bandwidth. The bus bandwidth between the memories 30 may be controlled.

[Modification]
Next, a modification of this embodiment will be described. In this modification, an operation state is set in advance for each of the plurality of tasks. In addition to the execution priority value described in the present embodiment, each task has an access priority (Access Priority) value indicating the frequency of access to the memory 30 as the operation state of the task. The smaller the access priority value, the higher the access priority value (access frequency). For example, when the access priority value is 0, the access priority value is the highest.

  The group determination unit 514 of the scheduler 512 determines the PE group to which the PE belongs to from the execution priority value and the access priority value of the task executed by each PE.

  In this modification, unlike the present embodiment, it is assumed that the number of PE groups is set to 3 for convenience. Further, in this modification, since the PE group is directly determined from the execution priority value and the access priority value, the group priority table 53 does not exist unlike the present embodiment.

  FIG. 15 shows an example of the data structure of the group / band table 52 of this modification. As shown in FIG. 15, the group / bandwidth table 52 holds group identification information and memory bandwidth information indicating PE groups in association with each other. In the example of FIG. 15, the memory bandwidth B0 indicated by the memory bandwidth information held in association with the group identification information “0” indicating the PE group 0 is “60%”. The memory bandwidth B1 indicated by the memory bandwidth information held in association with the group identification information “1” indicating the PE group 1 is “30%”. The memory bandwidth B2 indicated by the memory bandwidth information held in association with the group identification information “2” indicating the PE group 2 is “10%”.

  FIG. 16 shows an example of the data structure of the task table 54 of this modification. As shown in FIG. 16, the task table 54 holds an execution priority value and an access priority value for each task. The task table 54 holds PE identification information indicating the PE to which the task is assigned by the scheduler 512 for each task. Since each task held in the task table 54 and the execution priority value associated with the task are the same as those in the task table 54 shown in FIG. 7, detailed description thereof will be omitted. Each task is assigned to each PE as in FIG.

  In the example of FIG. 16, the access priority values of tasks A, B, and 1 to 4 are 0, and the access priority values of tasks C and 5 to 10 are 1. It is assumed that the access priority value of 0 is higher than 1 and the access frequency to the memory 30 is higher.

  Further, when the PE group is determined from the task execution priority value and the access priority value, the task table 54 stores group identification information indicating the determined PE group for each task. Details of processing for determining the PE group from the execution priority value and the access priority value will be described later.

  Next, a processing procedure for setting a PE group to which the PE belongs when each PE executes a task will be described with reference to FIG.

  First, when the PE executes a task, the group determination unit 514 of the scheduler 512 refers to the task table 54 and acquires the execution priority value and the access priority value held in association with the task (step S41). ).

  Next, the group determination unit 514 determines (calculates) a PE group to which the PE executing the task should belong based on the acquired execution priority value and access priority value (step S42).

  Here, a specific example of processing for determining the PE group from the combination of the execution priority value and the access priority value will be described. As described above, it is assumed that the execution priority value is 0 when the priority is highest, and the access priority value is 0 when the frequency of accessing the memory 30 is highest. Further, the larger the execution priority value, the lower the execution priority value, and the same applies to the access priority value.

  Hereinafter, the execution priority value held in the task table 54 in association with the task is P, the access priority value is A, the maximum execution priority value (lowest priority) is Pmax, and the maximum access priority value (access) Let Amax be the lowest frequency. A group number (group identification information) indicating the PE group to be determined is denoted as G or G (P, A). In the PE group, the PE group indicated by the PE group number 0 has the widest memory bandwidth, and the PE group indicated by the maximum PE group number Gmax has the narrowest memory bandwidth.

  First, a first specific example (addition method) will be described. The first specific example is characterized in that G is determined by multiplying P and A after multiplying them by a predetermined coefficient. As an example of the general formula, G = αP + βA (α and β are positive real numbers determined in advance). The simplest simple addition method using this equation is G = P + A.

  Specifically, for example, when Gmax = 2 and Pmax = Amax = 1 (the number of groups is 3 and the number of priority value stages is 2), for example, a task with a high processing priority and a high access frequency to the memory 30 By setting P = 0 and A = 0, the PE group number of the PE group to which the PE executing the task should belong is G (0, 0) = 0, and the PE has the widest bandwidth. Assigned to PE group 0.

  Similarly, G (0, 1) = 1, G (1, 0) = 1, and G (1, 1) = 2. In this manner, PEs belonging to the PE group with G = 0 can execute the task without depriving the bandwidth of other PEs that execute tasks with low P or A. The PE belonging to the PE group with G = 2 executes the task without disturbing the bandwidth of the PE belonging to the PE group with G = 1.

  The simple addition method as described above can also be applied to multi-level grouping such as Gmax = 4, Pmax = Amax = 2 (5 groups, each having 3 priority levels).

  Further, when the number of stages of the execution priority value and the access priority value is different, or when the number of stages of the execution priority value and the access priority value is larger than the number of groups, for example, G = (P / Pmax + A / Amax) × This can be dealt with by using a normalized addition method such as Gmax / 2.

  Further, in particular, when it is desired to further weight the execution priority value and the access priority value due to system requirements or the like, it is possible to appropriately cope with such as multiplying the normalized addition method P or A by a weighting factor.

  For example, when G (P, A) is less than 0 or exceeds Gmax according to the above-described calculation formula, it is set to 0 or Gmax, respectively. For example, when G (P, A) includes a decimal part according to a calculation formula, it is determined as appropriate whether the decimal part is rounded down or rounded up.

  According to the addition method as described above, a task having the highest execution priority value (execution priority value is 0) and the highest access priority value (access priority value is 0) executes a task having an execution priority value lower than that task. The PE is executed without disturbing the memory bandwidth. In addition, there is an advantage that the memory bandwidth can be distributed in a well-balanced manner for a task whose execution priority value or access priority value is not the highest.

  Next, a second specific example (execution priority separation method) will be described. In the second specific example, G (P) is such that a PE that executes a task with a higher P always has a wider memory bandwidth or is assigned to the same PE group for a PE that executes a task with a lower P. , A) is determined.

  Specifically, for example, when Gmax = 3 and Pmax = Amax = 1 (the number of groups is 4 and the number of priority value stages is 2), G (0, 0) = 0, G (0, 1 ) = 1, G (1, 0) = 2, G (1, 1) = 3. Such a linear arrangement can be expressed by a calculation formula, but the execution priority separation method does not necessarily have to be arranged in a linear form. For example, when Gmax = 2 and Pmax = Amax = 1, an arrangement such as G (0, 0) = 0, G (0, 1) = 1, G (1, 0) = G (1, 1) = 2, etc. It does not matter.

  According to such an execution priority separation method, it can be ensured that the execution of a task having P is not disturbed by the execution of a task having a lower execution priority value such as P + 1. Furthermore, since a task group having the same P can be subdivided by different A, it is possible to reduce the use of a useless memory bandwidth when a task with a high P and a low A is executed.

  It should be noted that when Pmax is larger than Gmax, a method of grouping consecutive Pmax values together can be implemented as an extension of the execution priority separation method. For example, when Gmax = 2, Pmax = 3, and Amax = 1, G (0, 0) = 0, G (0, 1) = 1, G (1, 0) = 2, G (1, 1) = 2, G (2, 0) = 2, G (2, 1) = 2, etc. can be considered.

  In any of the above-described methods, when tasks with different execution priority values or access priority values exist in the same PE group, a longer PE execution time is given to the higher execution priority value or access priority value. The methods may be applied simultaneously.

  The group determination unit 514 determines the PE group to which the PE executing the task should belong based on the above-described method. The determined PE group is registered in the task table 54 in association with each task.

  Next, the group setting unit 513 sets the PE group number (group identification information) of the PE group determined by the group determination unit 514 in the PE group register (step S43).

  FIG. 18 shows a flow of processing for executing a plurality of tasks to which PE (0) to PE (3) are assigned in real time t. A plurality of tasks are assigned to PE (0) to PE (3) as shown in FIG. Note that the execution time of each task is determined in accordance with, for example, the execution priority value and is the same as that described above with reference to FIG.

  In FIG. 19, the PE group to which each of PE (0) to PE (3) when the real time t shown in FIG. 18 is t0 and each of the PE (0) to PE (3) can access the memory 30. The memory bandwidth relationship is shown.

  In the example of FIG. 18, PE (0) belongs to PE group 1 because it executes task 3 at real time t0. Note that this PE group is determined by the simple addition method from the execution priority value and the access priority value for each task in the task table 54 shown in FIG. Also, PE (1) is executing task 4 and therefore belongs to PE group 1. PE (2) belongs to PE group 1 because task C is executed. PE (3) belongs to PE group 2 because task 6 is being executed. Further, the group number of the PE group to which each PE belongs is set in the PE group register of each PE.

  In this case, as shown in FIG. 19, PE (0) to PE (2) are memory bandwidths indicated by the bandwidth information held in the group / band table 52 in association with the group number (identification information) 1. The memory 30 can be accessed by the width. Also, PE (3) can access the memory 30 with the memory bandwidth indicated by the bandwidth information held in the group / bandwidth table 52 in association with the group number 2. That is, in the example of the group / band table 52 shown in FIG. 15, PE (0) to PE (2) can access the memory 30 with a memory bandwidth of 30%. PE (3) can access the memory 30 with a memory bandwidth of 10%.

  In FIG. 20, the PE group to which each of PE (0) to PE (3) when the real time t shown in FIG. 18 is t1 and each of the PE (0) to PE (3) can access the memory 30. The memory bandwidth relationship is shown. When the task executed by each PE is switched, the PE group number of the PE group to which each PE executing the new task belongs is set in the PE group register of the PE, as in the above-described embodiment. Processing is executed.

  In the example of FIG. 18, PE (0) belongs to PE group 0 because it executes task A at real time t1. PE (1) is executing task B and therefore belongs to PE group 0. PE (2) belongs to PE group 1 because task C is executed. PE (3) belongs to PE group 2 because task 6 is being executed. Further, the group number of the PE group to which each PE belongs is set in the PE group register of each PE.

  In this case, as shown in FIG. 20, PE (0) and PE (1) are stored in the memory 30 with the memory bandwidth indicated by the bandwidth information held in the group / bandwidth table 52 in association with the group number 0. Can be accessed. The PE (2) can access the memory 30 with the memory bandwidth indicated by the bandwidth information stored in the group / bandwidth table 52 in association with the group number 1. Also, PE (3) can access the memory 30 with the memory bandwidth indicated by the bandwidth information held in the group / bandwidth table 52 in association with the group number 2. That is, in the example of the group / band table 52 shown in FIG. 15, PE (0) and PE (1) can access the memory 30 with a memory bandwidth of 60%. PE (2) can access the memory 30 with a memory bandwidth of 30%. PE (3) can access the memory 30 with a memory bandwidth of 10%.

  As described above, in this modification, when a task is executed by grouping a plurality of PEs 10, the PE group of the PE that executes the task according to the execution priority value and the access priority value of the task The memory bandwidth of each PE can be set with a simple procedure of setting group identification information (number) in the register.

  In the above-described embodiment, since the PE group is determined based on only the execution priority value, the PE that executes a task that has a high execution priority value but does not access the memory 30 very frequently, and the execution priority value is Since a PE that executes a task that is high and frequently accesses the memory 30 may belong to the same PE group, the execution time may be longer. However, in this modification, since the PE group is determined based on the execution priority value and the access priority value, the PE that executes a task having both a high execution priority value and an access priority value has an execution priority value that is the access priority value in the other world. Belongs to a PE group different from the PE that executes the lower task. Thereby, the inefficient state which may generate | occur | produce in this embodiment as mentioned above can be avoided.

  In the above-described embodiment, the configuration for determining the PE group to which the PE executing the task belongs using only the execution priority value of each task has been described. Similarly, each task described in the present modification is described. The PE group to which the PE executing the task should belong may be determined using only the access priority value. In this case, the access priority value and the group identification information may be held in the group priority table 53 described above.

  The present invention is not limited to the above-described embodiment or modification as it is, and can be embodied by modifying the constituent elements without departing from the spirit of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment or the modification. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, you may combine suitably the component covering embodiment or a modification.

1 is a block diagram showing a hardware configuration of a multiprocessor system according to an embodiment of the present invention. The block diagram which mainly shows the function structure of OS51 shown in FIG. 5 is a flowchart showing a processing procedure for creating a group / bandwidth table 52 by the bandwidth setting unit 511 of the OS 51. The figure which shows an example of the data structure of the group and the band table 52 produced by the band setting part 511. 5 is a flowchart showing a processing procedure in which a bandwidth setting unit 511 sets a memory bandwidth for each PE group in the memory controller 20. 6 is a diagram showing an example of a data structure of a group priority table 53. FIG. The figure which shows an example of the data structure of the task table 54 and a task queue. The flowchart which shows the process sequence which sets PE group which the said PE should belong when each PE performs a task. The figure which shows the flow of a process which performs the some task to which PE (0) -PE (3) was allocated in real time t. The PE group to which each of PE (0) to PE (3) when the real time t shown in FIG. 9 is t0 and the memory bandwidth to which each of the PE (0) to PE (3) can access the memory 30 are shown. The figure which shows a relationship. The flowchart which shows the process sequence which sets PE group to which PE (2) should belong when the task performed by PE (2) is switched from the task 5 to the task C. The PE group to which each of PE (0) to PE (3) when the real time t shown in FIG. 9 is t1 and the memory bandwidth to which each of the PE (0) to PE (3) can access the memory 30 are shown. The figure which shows a relationship. The PE group to which each of PE (0) to PE (3) when the real time t shown in FIG. 9 is t2 and the memory bandwidth to which each of the PE (0) to PE (3) can access the memory 30 are shown. The figure which shows a relationship. The PE group to which each of PE (0) to PE (3) when the real time t shown in FIG. 9 is t2 and the memory bandwidth to which each of the PE (0) to PE (3) can access the memory 30 are shown. The figure which shows a relationship. The figure which shows an example of the data structure of the group and the band table 52 of the modification of this embodiment. The figure which shows an example of the data structure of the task table. The flowchart which shows the process sequence which sets PE group which the said PE should belong when each PE performs a task. The figure which shows the flow of a process which performs the some task to which PE (0) -PE (3) was allocated in real time t. The PE group to which each of PE (0) to PE (3) belongs when the real time t shown in FIG. 18 is t0 and the memory bandwidth to which each of the PE (0) to PE (3) can access the memory 30 are shown. The figure which shows a relationship. The PE group to which each of PE (0) to PE (3) when the real time t shown in FIG. 18 is t1 and the memory bandwidth to which each of the PE (0) to PE (3) can access the memory 30 are shown. The figure which shows a relationship.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Plural PE (processor element), 20 ... Memory controller, 21 ... Band control part, 30 ... Memory, 40 ... I / O controller, 50 ... External storage device, 51 ... OS (operating system), 52 ... Group Band table 53, group priority table, 54 task table, 511 band setting unit, 512 scheduler, 513 group setting unit, 514 group determining unit.

Claims (5)

In a multiprocessor system comprising a plurality of processor elements, a memory, and a memory controller that limits a memory bandwidth in which each of the plurality of processor elements can access the memory, at least of the plurality of processor elements A bandwidth control program executed by one processor element,
In the one processor element,
Setting a memory bandwidth for each processor element group to which each of the plurality of processor elements belongs to the memory controller;
Assigning the task to one of the plurality of processor elements to cause the generated task to be executed when a task to be executed occurs;
Determining a processor element group to which the assigned processor element should belong, in accordance with an operating condition or an operating state of the generated task, when causing the assigned processor element to execute the generated task; ,
Causing the assigned processor element to belong to the determined processor element group to execute the generated task with the memory bandwidth of the processor element group set in the memory controller. Bandwidth control program. The multiprocessor system corresponds to an execution priority value indicating a priority at which each of a plurality of tasks generated in the multiprocessor system is executed and the group identification information indicating a processor element group to which the processor element executing the task belongs. Group priority holding means to hold in advance,
When a task to be executed is generated, a predetermined execution priority value indicating the priority of execution of the generated task is associated with the task as an operation condition of the task and stored in the task holding unit. Further causing the one processor element to perform a holding step;
The determining step includes:
Obtaining an execution priority value held in the task holding means in association with the generated task when the assigned processor element executes the generated task;
Determining a processor element group indicated by the group identification information held in the group priority holding means in association with the acquired execution priority value as a processor element group to which the assigned processor element belongs. The bandwidth control program according to claim 1, further comprising: The multiprocessor system includes an access priority value indicating a frequency of access to the memory when each of a plurality of tasks generated in the multiprocessor system is executed, and a processor element group to which a processor element executing the task belongs. Group priority holding means for previously holding the group identification information in association with each other,
When the task to be executed occurs, a predetermined access priority value indicating the frequency of access to the memory when the generated task is executed is set as the task operating state in the task. Causing the one processor element to further execute a step of associating and holding the task in the task holding unit;
The determining step includes:
Obtaining an access priority value held in the task holding means in association with the generated task when the assigned processor element executes the generated task;
Determining a processor element group indicated by group identification information held in the group priority holding means in association with the acquired access priority value as a processor element group to which the assigned processor element should belong; The bandwidth control program according to claim 1, comprising: When the task to be executed occurs, a predetermined execution priority value indicating the priority of the generated task to be executed and the predetermined memory to the memory when the predetermined task is executed Causing the one processor element to further execute a step of holding an access priority value indicating an access frequency in a task holding unit in association with the task,
In the determining step, when the assigned processor element executes the generated task, the execution priority value and the access priority value held in the task holding unit in association with the generated task are set. The bandwidth control program according to claim 1, wherein a processor element group to which the allocated processor element should belong is determined based on. Multiple processor elements;
Memory accessed by each of the plurality of processor elements;
A memory controller that limits a memory bandwidth at which each of the plurality of processor elements can access the memory;
Setting means for setting, in the memory controller, a memory bandwidth for each processor element group to which each of the plurality of processor elements belongs;
Assigning means for assigning the task to one of the plurality of processor elements in order to cause the generated task to be executed when a task to be executed occurs;
When causing the processor element to which the generated task is assigned by the assigning means to execute the generated task, the assigned processor element belongs according to an operation condition or an operation state of the generated task. A determination means for determining a processor element group to be
Execution for causing the assigned processor element to belong to the processor element group determined by the determining means to execute the generated task with the memory bandwidth of the processor element group set in the memory controller by the setting means. And a multiprocessor system.

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