JP7472522B2 - Semiconductor Integrated Circuit - Google Patents

Semiconductor Integrated Circuit Download PDF

Info

Publication number
JP7472522B2
JP7472522B2 JP2020022332A JP2020022332A JP7472522B2 JP 7472522 B2 JP7472522 B2 JP 7472522B2 JP 2020022332 A JP2020022332 A JP 2020022332A JP 2020022332 A JP2020022332 A JP 2020022332A JP 7472522 B2 JP7472522 B2 JP 7472522B2
Authority
JP
Japan
Prior art keywords
region
semiconductor integrated
integrated circuit
well region
conversion element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2020022332A
Other languages
Japanese (ja)
Other versions
JP2020174173A (en
Inventor
将晴 山路
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to US16/813,104 priority Critical patent/US11562995B2/en
Priority to CN202010167105.1A priority patent/CN111834358A/en
Publication of JP2020174173A publication Critical patent/JP2020174173A/en
Application granted granted Critical
Publication of JP7472522B2 publication Critical patent/JP7472522B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

本発明は、半導体集積回路に関し、特に電力用の半導体集積回路に関する。 The present invention relates to semiconductor integrated circuits, and in particular to power semiconductor integrated circuits.

主に低容量のインバータでは、電力変換用ブリッジ回路等を構成している電力用スイッチング素子を高耐圧集積回路（ＨＶＩＣ）により駆動・制御している。ＨＶＩＣは、入力端子からの入力信号に応じて、電力用スイッチング素子のゲートをオン・オフして駆動する駆動信号を出力端子から出力する。例えば電力変換用ブリッジ回路では、ＨＶＩＣからの駆動信号を受けた高電位側の電力用スイッチング素子と低電位側の電力用スイッチング素子がそれぞれ動作することで電力変換を行う。 In low-capacity inverters, the power switching elements that make up the power conversion bridge circuit are driven and controlled by a high-voltage integrated circuit (HVIC). The HVIC outputs a drive signal from its output terminal that drives the gates of the power switching elements by turning them on and off in response to the input signal from the input terminal. For example, in a power conversion bridge circuit, power conversion is performed by operating the high-potential side power switching element and the low-potential side power switching element, which receive a drive signal from the HVIC.

ＨＶＩＣでは、高電位側回路領域（ハイサイド回路領域）と低電位側回路領域（ローサイド回路領域）の間を高耐圧接合終端構造（ＨＶＪＴ）により電気的に分離している。また、ハイサイド回路領域とローサイド回路領域の間の信号伝達を行うために、レベルシフタを設ける。 In an HVIC, the high-side circuit area and the low-side circuit area are electrically isolated by a high-voltage junction termination structure (HVJT). In addition, a level shifter is provided to transmit signals between the high-side circuit area and the low-side circuit area.

ＨＶＪＴとレベルシフタの構成に関して、ＨＶＪＴの一部をレベルシフタとして利用した構造が知られている。この構造は、ＨＶＪＴ上を横切る高電位配線を必要としないため、信頼性が高い。また、ＨＶＪＴとレベルシフタを個別に形成した構造に比べて、レベルシフタの面積分だけチップサイズを縮小できる。この構造を実現するためには、ハイサイド回路領域の内部回路とレベルシフタとを電気的に分離する必要がある。 Regarding the configuration of HVJT and level shifter, a structure is known in which part of the HVJT is used as a level shifter. This structure is highly reliable because it does not require high-potential wiring that crosses the HVJT. Also, compared to a structure in which the HVJT and level shifter are formed separately, the chip size can be reduced by the area of the level shifter. To realize this structure, it is necessary to electrically isolate the internal circuitry in the high-side circuit area from the level shifter.

特許文献１の図４には、レベルシフタとハイサイド回路領域とをｐ型のスリット領域で分割することにより、ハイサイド回路領域の内部回路とレベルシフタとを電気的に分離した構造が記載されている。また、特許文献１の図２には、ハイサイド回路領域の４辺をｐ型の分離領域で囲むことにより、ハイサイド回路領域の内部回路とレベルシフタとを電気的に分離した構造が記載されている。 Figure 4 of Patent Document 1 describes a structure in which the level shifter and high-side circuit region are divided by a p-type slit region, thereby electrically isolating the internal circuitry of the high-side circuit region from the level shifter. Also, Figure 2 of Patent Document 1 describes a structure in which the internal circuitry of the high-side circuit region and the level shifter are electrically isolated by surrounding the four sides of the high-side circuit region with p-type isolation regions.

特許文献２の図３には、ハイサイド回路領域の３辺をｐ型のスリット領域で囲むことにより、ハイサイド回路領域の内部回路とレベルシフタとを電気的に分離した構造が記載されている。ｐ型のスリット領域の無いハイサイド回路領域の１辺はハイサイド回路領域の最高電位に固定し、この最高電位と、レベルシフタを構成する高耐圧ｎ型ＭＯＳＦＥＴのドレインとの間の寄生抵抗をレベルシフト抵抗として用いている。 Figure 3 of Patent Document 2 describes a structure in which the internal circuitry of the high-side circuit region and the level shifter are electrically isolated by surrounding three sides of the high-side circuit region with p-type slit regions. One side of the high-side circuit region that does not have a p-type slit region is fixed to the highest potential of the high-side circuit region, and the parasitic resistance between this highest potential and the drain of the high-voltage n-type MOSFET that constitutes the level shifter is used as the level shift resistance.

特許文献３の図４には、ＨＶＪＴの一部をトレンチで分割することにより、ハイサイド回路領域の内部回路とレベルシフタとを電気的に分離した構造が記載されている。 Figure 4 of Patent Document 3 shows a structure in which the internal circuitry of the high-side circuit area and the level shifter are electrically isolated by dividing part of the HVJT with a trench.

特許文献１～３では、ＨＶＪＴとレベルシフタとでドリフト領域の長さ（ドリフト長）を揃えており、オフ耐圧も等しい。オフ耐圧が等しいと、静電気放電（ＥＳＤ）サージ等が高電位側の電源端子に入力された場合、ＨＶＪＴとレベルシフタが同時にアバランシェ状態に陥るため、ＨＶＪＴとレベルシフタに略均一にアバランシェ電流が流れる。そのため、局所的な電流集中を起こしにくい。しかし、高耐圧ｎ型ＭＯＳＦＥＴ等のレベルシフタではアバランシェ電流により寄生ｎｐｎバイポーラトランジスタがオンし、寄生動作が誘発されるため、ｐｎ接合ダイオードであるＨＶＪＴに比べて破壊しやすい。なお、レベルシフト抵抗を調整することでレベルシフタに流れるアバランシェ電流を制限し、この破壊耐量のアンバランスを解消する方法もあるが、その場合、レベルシフト抵抗を必要以上に大きくする必要があるため、設計上の制限を受けることになる。 In Patent Documents 1 to 3, the length of the drift region (drift length) is the same for the HVJT and the level shifter, and the off-state breakdown voltage is also the same. If the off-state breakdown voltage is the same, when an electrostatic discharge (ESD) surge or the like is input to the high-potential power supply terminal, the HVJT and the level shifter simultaneously enter an avalanche state, and the avalanche current flows approximately uniformly through the HVJT and the level shifter. This makes it difficult for localized current concentration to occur. However, in a level shifter such as a high-voltage n-type MOSFET, the avalanche current turns on the parasitic npn bipolar transistor, inducing parasitic operation, making it more likely to break down than the HVJT, which is a pn junction diode. There is also a method of adjusting the level shift resistor to limit the avalanche current flowing through the level shifter and eliminate this imbalance in breakdown breakdown resistance, but in that case, the level shift resistor needs to be larger than necessary, which imposes design limitations.

また、特許文献４の図６には、ＨＶＪＴのドリフト長よりもレベルシフタのドリフト長を長くすることで、レベルシフタにおけるＥＳＤ破壊耐量を向上させた構造が記載されている。この構造では、レベルシフタのドリフト領域がハイサイド回路領域側に突出するため、ハイサイド回路の有効配置面積が減少してしまう。これとは逆に、特許文献４の図７に示すように、レベルシフタのドリフト領域を接地（ＧＮＤ）領域である外周側へ突出させた構造にした場合には、チップ面積が増大してしまう。 Furthermore, FIG. 6 of Patent Document 4 describes a structure in which the drift length of the level shifter is made longer than the drift length of the HVJT, thereby improving the ESD breakdown resistance of the level shifter. In this structure, the drift region of the level shifter protrudes into the high-side circuit region, reducing the effective layout area of the high-side circuit. Conversely, as shown in FIG. 7 of Patent Document 4, if the drift region of the level shifter is made to protrude toward the outer periphery, which is the ground (GND) region, the chip area will increase.

特開平９－２８３７１６号公報Japanese Patent Application Laid-Open No. 9-283716 特開２０１５－１７３２５５Patent Publication 2015-173255 特開２００５－１２３５１２号公報JP 2005-123512 A 国際公開第２０１７／０８６０６９号International Publication No. 2017/086069

上記問題に鑑み、本発明は、ＨＶＪＴの一部をレベルシフタとして利用するＨＶＩＣにおいて、チップ面積の増大を抑制しつつ、ＥＳＤ耐量を向上させることができる半導体集積回路を提供することを目的とする。 In view of the above problems, the present invention aims to provide a semiconductor integrated circuit that can improve ESD tolerance while suppressing an increase in chip area in an HVIC that uses part of the HVJT as a level shifter.

本発明の一態様は、高電位側回路領域と、その高電位側回路領域を囲む高耐圧接合終端構造と、その高耐圧接合終端構造を介して高電位側回路領域を囲む低電位側回路領域が同一半導体チップに集積化された半導体集積回路であって、（ａ）高電位側回路領域に配置された第１導電型の中央ウェル領域と、（ｂ）中央ウェル領域の下端に埋め込まれた第１導電型の埋込層と、（ｃ）中央ウェル領域の周囲を囲む高耐圧接合終端構造の位置に配置された、第１導電型の環状のドリフト領域と、（ｄ）ドリフト領域の周囲を囲む第２導電型の環状ウェル領域と、（ｅ）低電位側回路領域と高電位側回路領域との間で信号を伝達するレベルシフト回路に含まれるレベル変換素子の担体供給領域であって、環状ウェル領域に配置された第１導電型の担体供給領域と、（ｆ）レベル変換素子の担体受領領域であって、ドリフト領域もしくは中央ウェル領域に配置された、ドリフト領域もしくは中央ウェル領域よりも高不純物濃度で第１導電型の担体受領領域と、（ｇ）ドリフト領域もしくは中央ウェル領域に、担体受領領域と離して配置された、ドリフト領域もしくは中央ウェル領域よりも高不純物濃度で第１導電型の第１コンタクト領域とを備え、第１コンタクト領域が形成される領域における環状ウェル領域と埋込層との第１距離の内の最小値は、担体受領領域が形成される領域における環状ウェル領域と埋込層との第２距離の内の最小値よりも短いことを特徴とする半導体集積回路であることを要旨とする。 One aspect of the present invention is a semiconductor integrated circuit in which a high-potential side circuit region, a high-voltage junction termination structure surrounding the high-potential side circuit region, and a low-potential side circuit region surrounding the high-potential side circuit region via the high-voltage junction termination structure are integrated on the same semiconductor chip, the semiconductor integrated circuit comprising: (a) a first-conductivity type central well region disposed in the high-potential side circuit region; (b) a first-conductivity type buried layer buried in the lower end of the central well region; (c) a first-conductivity type annular drift region disposed at the position of the high-voltage junction termination structure surrounding the periphery of the central well region; (d) a second-conductivity type annular well region surrounding the periphery of the drift region; and (e) a carrier supply region for a level conversion element included in a level shift circuit that transmits a signal between the low-potential side circuit region and the high-potential side circuit region, the annular well region being a first conductive type buried layer disposed in the high-potential side circuit region; The gist of the semiconductor integrated circuit is that it comprises: (a) a carrier supply region of a first conductivity type arranged in the well region; (f) a carrier receiving region of the level conversion element, which is arranged in the drift region or the central well region and has a first conductivity type with a higher impurity concentration than the drift region or the central well region; and (g) a first contact region of the first conductivity type and has a higher impurity concentration than the drift region or the central well region and is arranged in the drift region or the central well region away from the carrier receiving region, and the minimum value of the first distance between the annular well region and the buried layer in the region where the first contact region is formed is shorter than the minimum value of the second distance between the annular well region and the buried layer in the region where the carrier receiving region is formed.

本発明の他の態様は、高電位側回路領域と、その高電位側回路領域を囲む高耐圧接合終端構造と、その高耐圧接合終端構造を介して高電位側回路領域を囲む低電位側回路領域が同一半導体チップに集積化された半導体集積回路であって、（ａ）高電位側回路領域に配置された第１導電型の中央ウェル領域と、（ｂ）中央ウェル領域の下端に埋め込まれた第１導電型の埋込層と、（ｃ）中央ウェル領域の周囲を囲む高耐圧接合終端構造の位置に配置された、第１導電型の環状のドリフト領域と、（ｄ）ドリフト領域の周囲を囲む第２導電型の環状ウェル領域と、（ｅ）ドリフト領域に配置された第２導電型のベース領域と、（ｆ）低電位側回路領域と高電位側回路領域との間で信号を伝達するレベルシフト回路に含まれるレベル変換素子の担体供給領域であって、ベース領域に配置された第１導電型の担体供給領域と、（ｇ）レベル変換素子の担体受領領域であって、ドリフト領域もしくは中央ウェル領域に配置された、ドリフト領域もしくは中央ウェル領域よりも高不純物濃度で第１導電型の担体受領領域と、（ｈ）ドリフト領域もしくは中央ウェル領域に、担体受領領域と離して配置された、ドリフト領域もしくは中央ウェル領域よりも高不純物濃度で第１導電型の第１コンタクト領域とを備え、第１コンタクト領域が形成される領域における環状ウェル領域と埋込層との第１距離の内の最小値は、担体受領領域が形成される領域における環状ウェル領域と埋込層との第２距離の内の最小値よりも短いことを特徴とする半導体集積回路であることを要旨とする。 Another aspect of the present invention is a semiconductor integrated circuit in which a high potential side circuit region, a high voltage junction termination structure surrounding the high potential side circuit region, and a low potential side circuit region surrounding the high potential side circuit region via the high voltage junction termination structure are integrated on the same semiconductor chip, the semiconductor integrated circuit including: (a) a first conductivity type central well region arranged in the high potential side circuit region; (b) a first conductivity type buried layer buried in a lower end of the central well region; (c) a first conductivity type annular drift region arranged at the position of the high voltage junction termination structure surrounding the periphery of the central well region; (d) a second conductivity type annular well region surrounding the periphery of the drift region; (e) a second conductivity type base region arranged in the drift region; and (f) a level conversion element included in a level shift circuit that transmits a signal between the low potential side circuit region and the high potential side circuit region. The gist of the present invention is a semiconductor integrated circuit comprising: (a) a carrier supply region of a level conversion element, the carrier supply region being a first conductivity type arranged in a base region; (b) a carrier receiving region of the level conversion element, the carrier receiving region being arranged in the drift region or the central well region and having a first conductivity type with a higher impurity concentration than the drift region or the central well region; and (c) a first contact region of the first conductivity type and having a higher impurity concentration than the drift region or the central well region, the first contact region being arranged in the drift region or the central well region and separated from the carrier receiving region, the minimum value of a first distance between the annular well region and the buried layer in the region where the first contact region is formed is shorter than a minimum value of a second distance between the annular well region and the buried layer in the region where the carrier receiving region is formed.

本発明によれば、ＨＶＪＴの一部をレベルシフタとして利用するＨＶＩＣにおいて、チップ面積の増大を抑制しつつ、ＥＳＤ耐量を向上させることができる半導体集積回路を提供することができる。 The present invention provides a semiconductor integrated circuit that can improve ESD tolerance while suppressing an increase in chip area in an HVIC that uses part of an HVJT as a level shifter.

実施形態に係る半導体集積回路の一例を示す回路図である。1 is a circuit diagram showing an example of a semiconductor integrated circuit according to an embodiment; 実施形態に係る半導体集積回路の一例を示す平面図である。1 is a plan view illustrating an example of a semiconductor integrated circuit according to an embodiment. 図２のＡ－Ａ´方向から見た断面図である。3 is a cross-sectional view taken along the line AA' of FIG. 2. 図２のＢ－Ｂ´方向から見た断面図である。3 is a cross-sectional view taken along the line BB' of FIG. 2. 実施形態に係る半導体集積回路の８５０Ｖ印加時の電界強度シミュレーション結果を示すグラフである。11 is a graph showing the results of an electric field strength simulation when 850 V is applied to the semiconductor integrated circuit according to the embodiment. 実施形態に係る半導体集積回路の１０００Ｖ印加時の電界強度シミュレーション結果を示すグラフである。11 is a graph showing the results of an electric field strength simulation when 1000 V is applied to the semiconductor integrated circuit according to the embodiment. 実施形態に係る半導体集積回路の耐圧シミュレーション結果を示すグラフである。11 is a graph showing a result of a breakdown voltage simulation of the semiconductor integrated circuit according to the embodiment. 第１比較例に係る半導体集積回路を示す平面図である。FIG. 1 is a plan view showing a semiconductor integrated circuit according to a first comparative example. 第２比較例に係る半導体集積回路を示す平面図である。FIG. 11 is a plan view showing a semiconductor integrated circuit according to a second comparative example. 第３比較例に係る半導体集積回路を示す平面図である。FIG. 13 is a plan view showing a semiconductor integrated circuit according to a third comparative example. 第１変形例に係る半導体集積回路の一例を示す平面図である。FIG. 11 is a plan view showing an example of a semiconductor integrated circuit according to a first modification; 図１１のＡ－Ａ´方向から見た断面図である。12 is a cross-sectional view taken along the line AA' of FIG. 11. 図１１のＢ－Ｂ´方向から見た断面図である。12 is a cross-sectional view taken along the line BB' of FIG. 11. 第２変形例に係る半導体集積回路の、図１１のＡ－Ａ´方向から見た断面図に対応する断面図である。12 is a cross-sectional view of a semiconductor integrated circuit according to a second modification, the cross-sectional view corresponding to the cross-sectional view taken along the line AA' in FIG. 11. 第２変形例に係る半導体集積回路の、図１１のＢ－Ｂ´方向から見た断面図に対応する断面図である。12 is a cross-sectional view of a semiconductor integrated circuit according to a second modification, the cross-sectional view corresponding to the cross-sectional view taken along the line BB' in FIG. 11. 第３変形例に係る半導体集積回路の、図１１のＡ－Ａ´方向から見た断面図に対応する断面図である。12 is a cross-sectional view of a semiconductor integrated circuit according to a third modified example, the cross-sectional view corresponding to the cross-sectional view taken along the line AA' in FIG. 11. 第３変形例に係る半導体集積回路の、図１１のＢ－Ｂ´方向から見た断面図に対応する断面図である。12 is a cross-sectional view of a semiconductor integrated circuit according to a third modified example, the cross-sectional view corresponding to the cross-sectional view taken along the line BB' in FIG. 11. 第４変形例に係る半導体集積回路の一例を示す平面図である。FIG. 13 is a plan view showing an example of a semiconductor integrated circuit according to a fourth modification. 第５変形例に係る半導体集積回路の一例を示す平面図である。FIG. 13 is a plan view showing an example of a semiconductor integrated circuit according to a fifth modification. 第６変形例に係る半導体集積回路の一例を示す平面図である。FIG. 13 is a plan view showing an example of a semiconductor integrated circuit according to a sixth modification. 図２０のＡ－Ａ´方向から見た断面図である。21 is a cross-sectional view taken along the line AA' of FIG. 20. 図２０のＢ－Ｂ´方向から見た断面図である。21 is a cross-sectional view taken along the line BB' of FIG. 20. 第７変形例に係る半導体集積回路の一例を示す平面図である。FIG. 13 is a plan view showing an example of a semiconductor integrated circuit according to a seventh modification. 第７変形例に係る半導体集積回路の埋込層の曲率半径と耐圧の関係を示すグラフである。13 is a graph showing the relationship between the radius of curvature of a buried layer and the breakdown voltage of a semiconductor integrated circuit according to a seventh modification. 第７変形例に係る半導体集積回路の一例を示す他の平面図である。FIG. 23 is another plan view showing an example of a semiconductor integrated circuit according to the seventh modification. 第８変形例に係る半導体集積回路の一例を示す平面図である。FIG. 13 is a plan view showing an example of a semiconductor integrated circuit according to an eighth modification. 図２６のＡ－Ａ´方向から見た断面図である。27 is a cross-sectional view taken along the line AA' of FIG. 26. 図２６のＢ－Ｂ´方向から見た断面図である。27 is a cross-sectional view taken along the line BB' of FIG. 26.

以下、図面を参照して、本発明の実施形態及び各変形例を説明する。図面の記載において、同一又は類似の部分には同一又は類似の符号を付し、重複する説明を省略する。但し、図面は模式的なものであり、厚みと平面寸法との関係、各層の厚みの比率等は実際のものとは異なる場合がある。また、図面相互間においても寸法の関係や比率が異なる部分が含まれ得る。また、以下に示す実施形態は、本発明の技術的思想を具体化するための装置や方法を例示するものであって、本発明の技術的思想は、構成部品の材質、形状、構造、配置等を下記のものに特定するものでない。 The following describes the embodiments and variations of the present invention with reference to the drawings. In the description of the drawings, identical or similar parts are given the same or similar reference numerals, and duplicate explanations are omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of thickness of each layer, etc. may differ from the actual ones. Furthermore, the drawings may include parts with different dimensional relationships and ratios. Furthermore, the embodiments shown below are examples of devices and methods for embodying the technical idea of the present invention, and the technical idea of the present invention does not specify the materials, shapes, structures, arrangements, etc. of the components as described below.

本明細書において、「担体供給領域」とは、電界効果トランジスタ（ＦＥＴ）や静電誘導トランジスタ（ＳＩＴ）のソース領域、絶縁ゲート型バイポーラトランジスタ（ＩＧＢＴ）のエミッタ領域等の主電流を構成する多数キャリアを供給する半導体領域を意味する。また、静電誘導（ＳＩ）サイリスタやゲートターンオフ（ＧＴＯ）サイリスタにおいてはアノード領域が担体供給領域となる。また、「担体受領領域」とは、ＦＥＴやＳＩＴにおのドレイン領域、ＩＧＢＴのコレクタ領域等の主電流を構成する多数キャリアを受領する半導体領域を意味する。ＳＩサイリスタやＧＴＯサイリスタにおいてはカソード領域が担体受領領域として機能する。 In this specification, "carrier supply region" refers to a semiconductor region that supplies majority carriers that make up the main current, such as the source region of a field effect transistor (FET) or static induction transistor (SIT), or the emitter region of an insulated gate bipolar transistor (IGBT). In addition, in a static induction (SI) thyristor or gate turn-off (GTO) thyristor, the anode region serves as the carrier supply region. In addition, "carrier receiving region" refers to a semiconductor region that receives majority carriers that make up the main current, such as the drain region of a FET or SIT, or the collector region of an IGBT. In an SI thyristor or GTO thyristor, the cathode region functions as the carrier receiving region.

また、「制御電極」とは、ＦＥＴ、ＳＩＴ、ＩＧＢＴ、ＳＩサイリスタやＧＴＯサイリスタのゲート電極を意味し、上記担体供給領域と担体受領領域の間を流れる主電流の流れを制御する機能を有する。 The term "control electrode" refers to the gate electrode of a FET, SIT, IGBT, SI thyristor, or GTO thyristor, and has the function of controlling the flow of the main current between the carrier supply region and the carrier receiving region.

また、以下の説明における上下等の方向の定義は、単に説明の便宜上の定義であって、本発明の技術的思想を限定するものではない。例えば、対象を９０°回転して観察すれば上下は左右に変換して読まれ、１８０°回転して観察すれば上下は反転して読まれることは勿論である。 In addition, the definitions of up and down and other directions in the following explanation are merely for the convenience of explanation and do not limit the technical ideas of the present invention. For example, if an object is rotated 90 degrees and observed, up and down are converted into left and right and read, and of course, if it is rotated 180 degrees and observed, up and down are read inverted.

また、以下の説明では、第１導電型がｎ型、第２導電型がｐ型の場合について例示的に説明する。しかし、導電型を逆の関係に選択して、第１導電型をｐ型、第２導電型をｎ型としても構わない。また「ｎ」や「ｐ」に付す「＋」や「－」は、「＋」及び「－」が付記されていない半導体領域に比して、それぞれ相対的に不純物濃度が高い又は低い半導体領域であることを意味する。ただし同じ「ｎ」と「ｎ」とが付された半導体領域であっても、それぞれの半導体領域の不純物濃度が厳密に同じであることを意味するものではない。更に、以下の説明で「第１導電型」及び「第２導電型」の限定を加えた部材や領域は、特に明示の限定がなくても半導体材料からなる部材や領域を意味していることは、技術的にも論理的にも自明である。 In the following description, the first conductivity type is n-type and the second conductivity type is p-type. However, the conductivity types may be reversed, with the first conductivity type being p-type and the second conductivity type being n-type. The "+" and "-" affixed to "n" and "p" respectively indicate that the semiconductor region has a relatively high or low impurity concentration compared to the semiconductor region without the "+" and "-" affixed. However, even if the semiconductor region has the same "n" and "n" affixed, it does not mean that the impurity concentration of each semiconductor region is strictly the same. Furthermore, it is technically and logically self-evident that the members and regions to which the "first conductivity type" and "second conductivity type" are limited in the following description mean members and regions made of semiconductor material even without any explicit limitation.

（実施形態）
本発明の実施形態に係る半導体集積回路５０は、図１に示すように、駆動対象が例えば電力変換用ブリッジ回路の場合、ブリッジ回路の一相分である電力変換部６０を駆動するＨＶＩＣである。電力変換部６０は、高電位側スイッチング素子Ｓ１と、低電位側スイッチング素子Ｓ２とを直列に接続して出力回路を構成している。 (Embodiment)
1, when the object to be driven is, for example, a bridge circuit for power conversion, a semiconductor integrated circuit 50 according to an embodiment of the present invention is an HVIC that drives a power conversion unit 60 that is one phase of the bridge circuit. The power conversion unit 60 has an output circuit formed by connecting a high-potential side switching element S1 and a low-potential side switching element S2 in series.

図１においては、高電位側スイッチング素子Ｓ１及び低電位側スイッチング素子Ｓ２がそれぞれＩＧＢＴである場合を例示しているが、高電位側スイッチング素子Ｓ１及び低電位側スイッチング素子Ｓ２はＩＧＢＴに限定されるものではなく、ＭＯＳＦＥＴ等の他の電力用スイッチング素子でも構わない。図１では高電位側スイッチング素子Ｓ１には還流ダイオードＦＷＤ１が並列に逆接続され、低電位側スイッチング素子Ｓ２には、還流ダイオードＦＷＤ２が並列に逆接続された等価回路表示がされている。例えば、高電位側スイッチング素子Ｓ１と還流ダイオードＦＷＤ１が１つの半導体チップ（半導体基板）に、低電位側スイッチング素子Ｓ２と還流ダイオードＦＷＤ２が他の半導体チップに、それぞれ集積された２つの逆導通ＩＧＢＴの構成でも構わない。 In FIG. 1, the high-side switching element S1 and the low-side switching element S2 are each an IGBT, but the high-side switching element S1 and the low-side switching element S2 are not limited to IGBTs and may be other power switching elements such as MOSFETs. In FIG. 1, an equivalent circuit is shown in which a freewheel diode FWD1 is connected in parallel in reverse to the high-side switching element S1, and a freewheel diode FWD2 is connected in parallel in reverse to the low-side switching element S2. For example, a configuration of two reverse-conducting IGBTs may be used in which the high-side switching element S1 and the freewheel diode FWD1 are integrated on one semiconductor chip (semiconductor substrate), and the low-side switching element S2 and the freewheel diode FWD2 are integrated on another semiconductor chip.

高電位側スイッチング素子Ｓ１及び低電位側スイッチング素子Ｓ２は、正極側である高圧の主電源ＶＤＣと、主電源ＶＤＣに対する負極側となる接地電位（ＧＮＤ電位）との間に直列で接続されてハーフブリッジ回路を構成している。高電位側スイッチング素子Ｓ１の高電位側端子（コレクタ端子）が主電源ＶＤＣに接続され、低電位側スイッチング素子Ｓ２の低電位側端子（エミッタ端子）がＧＮＤ電位に接続されている。高電位側スイッチング素子Ｓ１の低電位側端子（エミッタ端子）と低電位側スイッチング素子Ｓ２の高電位側端子（コレクタ端子）の間の接続点６１は、電力変換用ブリッジ回路の一相分である電力変換部６０の出力点である。接続点６１にはモータ等の負荷６７が接続され、基準電位端子ＶＳにおけるＶＳ電位が負荷６７に供給される。 The high-potential side switching element S1 and the low-potential side switching element S2 are connected in series between the high-voltage main power supply VDC, which is the positive side, and the ground potential (GND potential), which is the negative side of the main power supply VDC, to form a half-bridge circuit. The high-potential side terminal (collector terminal) of the high-potential side switching element S1 is connected to the main power supply VDC, and the low-potential side terminal (emitter terminal) of the low-potential side switching element S2 is connected to the GND potential. A connection point 61 between the low-potential side terminal (emitter terminal) of the high-potential side switching element S1 and the high-potential side terminal (collector terminal) of the low-potential side switching element S2 is the output point of the power conversion unit 60, which is one phase of the power conversion bridge circuit. A load 67 such as a motor is connected to the connection point 61, and the VS potential at the reference potential terminal VS is supplied to the load 67.

実施形態に係る半導体集積回路５０は、入力端子ＩＮからの入力信号に応じて、高電位側スイッチング素子Ｓ１のゲートをオン・オフして駆動する駆動信号を出力端子ＯＵＴから出力する。実施形態に係る半導体集積回路５０は、低電位側回路（ローサイド回路）４１、レベルシフト回路４２及び高電位側回路（ハイサイド回路）４３を少なくとも回路の一部として含む。ローサイド回路４１、レベルシフト回路４２及びハイサイド回路４３は、例えば単一の半導体チップ上にモノリシックに集積してもよい。或いは、ローサイド回路４１、レベルシフト回路４２及びハイサイド回路４３を構成する素子を２以上の半導体チップに分けてハイブリッドに集積してもよい。 The semiconductor integrated circuit 50 according to the embodiment outputs a drive signal from the output terminal OUT to drive the gate of the high-potential side switching element S1 by turning it on and off in response to an input signal from the input terminal IN. The semiconductor integrated circuit 50 according to the embodiment includes a low-potential side circuit (low-side circuit) 41, a level shift circuit 42, and a high-potential side circuit (high-side circuit) 43 as at least a part of the circuit. The low-side circuit 41, the level shift circuit 42, and the high-side circuit 43 may be monolithically integrated on a single semiconductor chip, for example. Alternatively, the elements constituting the low-side circuit 41, the level shift circuit 42, and the high-side circuit 43 may be integrated in a hybrid manner by dividing them into two or more semiconductor chips.

ローサイド回路４１は、接地電位端子ＧＮＤに印加されるＧＮＤ電位（第１電位）を基準電位とし、低電位側電源端子ＶＣＣに印加されるＶＣＣ電位を電源電位として動作する。ローサイド回路４１は、入力端子ＩＮからの入力信号に応じて、ローサイドレベルのオン・オフ信号を生成し、レベルシフト回路４２に出力する。ローサイド回路４１は、図示を省略するが、例えばｎＭＯＳトランジスタとｐＭＯＳトランジスタのＣＭＯＳ回路を備える。 The low-side circuit 41 operates with the GND potential (first potential) applied to the ground potential terminal GND as the reference potential and the VCC potential applied to the low potential side power supply terminal VCC as the power supply potential. The low-side circuit 41 generates a low-side level on/off signal in response to an input signal from the input terminal IN and outputs it to the level shift circuit 42. Although not shown in the figure, the low-side circuit 41 includes, for example, a CMOS circuit of nMOS transistors and pMOS transistors.

レベルシフト回路４２は、接地電位端子ＧＮＤに印加されるＧＮＤ電位（第１電位）を基準電位とし、ローサイド回路４１からのローサイドレベルのオン・オフ信号を、ハイサイド側で用いるハイサイドレベルのオン・オフ信号に変換する。レベルシフト回路４２は、例えばｎＭＯＳトランジスタ等からなるレベルシフタ（レベル変換素子）６９を備える。レベルシフタ６９のゲート端子はローサイド回路４１に接続され、レベルシフタ６９のソース端子は接地電位端子ＧＮＤに接続され、レベルシフタ６９のドレイン端子はハイサイド回路４３の入力端子に接続される。レベルシフタ６９のドレイン端子にはレベルシフト抵抗６８の一端が接続され、レベルシフト抵抗６８の他端が高電位側電源端子ＶＢに接続される。レベルシフタ６９のゲート・ソース間には保護ダイオード７０が接続されている。 The level shift circuit 42 uses the GND potential (first potential) applied to the ground potential terminal GND as a reference potential and converts the low-side level on/off signal from the low-side circuit 41 into a high-side level on/off signal used on the high-side side. The level shift circuit 42 includes a level shifter (level conversion element) 69, for example, made of an nMOS transistor. The gate terminal of the level shifter 69 is connected to the low-side circuit 41, the source terminal of the level shifter 69 is connected to the ground potential terminal GND, and the drain terminal of the level shifter 69 is connected to the input terminal of the high-side circuit 43. One end of a level shift resistor 68 is connected to the drain terminal of the level shifter 69, and the other end of the level shift resistor 68 is connected to the high potential side power supply terminal VB. A protection diode 70 is connected between the gate and source of the level shifter 69.

ハイサイド回路４３は、基準電位端子ＶＳに印加されるＶＳ電位を基準電位とし、高電位側電源端子ＶＢに印加されるＶＢ電位（第２電位）を電源電位として動作する。ハイサイド回路４３は、レベルシフト回路４２からのオン・オフ信号に応じて、出力端子ＯＵＴから駆動信号を出力して、高電位側スイッチング素子Ｓ１のゲートを駆動する。ハイサイド回路４３は、例えば高電位側能動素子としてのｎＭＯＳトランジスタ４６と、基準電位側能動素子としてのｐＭＯＳトランジスタ４５とのＣＭＯＳ回路を出力段に備える。ｐＭＯＳトランジスタ４５のソース端子は高電位側電源端子ＶＢに接続されている。ｎＭＯＳトランジスタ４６のソース端子は基準電位端子ＶＳに接続されている。ｐＭＯＳトランジスタ４５のドレイン端子とｎＭＯＳトランジスタ４６のドレイン端子との間には出力端子ＯＵＴが接続されている。 The high-side circuit 43 operates with the VS potential applied to the reference potential terminal VS as the reference potential and the VB potential (second potential) applied to the high-potential side power supply terminal VB as the power supply potential. The high-side circuit 43 outputs a drive signal from the output terminal OUT in response to the on/off signal from the level shift circuit 42 to drive the gate of the high-potential side switching element S1. The high-side circuit 43 has, for example, a CMOS circuit in the output stage, including an nMOS transistor 46 as a high-potential side active element and a pMOS transistor 45 as a reference potential side active element. The source terminal of the pMOS transistor 45 is connected to the high-potential side power supply terminal VB. The source terminal of the nMOS transistor 46 is connected to the reference potential terminal VS. The output terminal OUT is connected between the drain terminal of the pMOS transistor 45 and the drain terminal of the nMOS transistor 46.

実施形態に係る半導体集積回路５０としては、ブートストラップ回路方式を例示している。図１に例示した構成では低電位側電源端子ＶＣＣと高電位側電源端子ＶＢとの間には外付け素子としてのブートストラップダイオード６５が接続される。そして、高電位側電源端子ＶＢと基準電位端子ＶＳとの間には外付け素子としてのブートストラップコンデンサ６６が接続される。ブートストラップダイオード６５及びブートストラップコンデンサ６６は、高電位側スイッチング素子Ｓ１の駆動電源の回路の一部をなす。 As an example of the semiconductor integrated circuit 50 according to the embodiment, a bootstrap circuit method is illustrated. In the configuration illustrated in FIG. 1, a bootstrap diode 65 is connected as an external element between the low potential side power supply terminal VCC and the high potential side power supply terminal VB. A bootstrap capacitor 66 is connected as an external element between the high potential side power supply terminal VB and the reference potential terminal VS. The bootstrap diode 65 and the bootstrap capacitor 66 form part of the drive power supply circuit for the high potential side switching element S1.

ＶＢ電位は半導体集積回路５０に印加される最高電位であり、ノイズの影響を受けていない通常状態では、ブートストラップコンデンサ６６により、ＶＳ電位よりも１５Ｖ程度高く保たれている。ＶＳ電位は、高電位側スイッチング素子Ｓ１と低電位側スイッチング素子Ｓ２とが相補的にオン・オフされることによって、主電源ＶＤＣの高電位（例えば４００Ｖ～６００Ｖ程度）と低電位（ＧＮＤ電位）との間で上昇及び下降を繰り返し、０Ｖから数百Ｖまでの間で変動する。なお、ＶＳ電位はマイナスの電位になる場合もある。 The VB potential is the highest potential applied to the semiconductor integrated circuit 50, and in normal conditions when not affected by noise, it is maintained at about 15 V higher than the VS potential by the bootstrap capacitor 66. The VS potential repeatedly rises and falls between the high potential (e.g., about 400 V to 600 V) and low potential (GND potential) of the main power supply VDC as the high potential side switching element S1 and the low potential side switching element S2 are complementarily turned on and off, fluctuating between 0 V and several hundred V. Note that the VS potential may also become a negative potential.

図２は、図１に示した実施形態に係る半導体集積回路５０に対応する半導体集積回路の平面レイアウトを示す。図２では、実施形態に係る半導体集積回路の上層側の層間絶縁膜や電極等の図示を省略している。図２に示すように、実施形態に係る半導体集積回路は、高電位側回路領域（ハイサイド回路領域）１０１と、ハイサイド回路領域１０１の周囲に配置された低電位側回路領域（ローサイド回路領域）１０３とを１チップに備える。 Figure 2 shows a planar layout of a semiconductor integrated circuit corresponding to the semiconductor integrated circuit 50 according to the embodiment shown in Figure 1. In Figure 2, the interlayer insulating film and electrodes on the upper layer side of the semiconductor integrated circuit according to the embodiment are omitted. As shown in Figure 2, the semiconductor integrated circuit according to the embodiment includes a high-potential side circuit region (high side circuit region) 101 and a low-potential side circuit region (low side circuit region) 103 arranged around the high-side circuit region 101 in one chip.

ハイサイド回路領域１０１は、図１に示したハイサイド回路４３を内部回路として含み、ローサイド回路領域１０３は、図１に示したローサイド回路４１を内部回路として含む。図２において、ハイサイド回路領域１０１及びローサイド回路領域１０３にそれぞれ含まれる素子は図示を省略している。実施形態に係る半導体集積回路は、ハイサイド回路領域１０１の周囲に環状に配置された高耐圧接合終端構造（ＨＶＪＴ）１０２を更に備える。ＨＶＪＴ１０２は、ハイサイド回路領域１０１とローサイド回路領域１０３とを電気的に分離する。 The high-side circuit region 101 includes the high-side circuit 43 shown in FIG. 1 as an internal circuit, and the low-side circuit region 103 includes the low-side circuit 41 shown in FIG. 1 as an internal circuit. In FIG. 2, elements included in the high-side circuit region 101 and the low-side circuit region 103 are not shown. The semiconductor integrated circuit according to the embodiment further includes a high-voltage junction termination structure (HVJT) 102 arranged in a ring shape around the high-side circuit region 101. The HVJT 102 electrically isolates the high-side circuit region 101 and the low-side circuit region 103.

ハイサイド回路領域１０１は、第１導電型（ｎ型）の中央ウェル領域３に設けられている。図２に示すように、中央ウェル領域３は、略矩形の平面パターンを有する。中央ウェル領域３の周囲の一部には、ｎ＋型の第１コンタクト領域（第１ダイオード端子接触領域）１１が設けられている。第１コンタクト領域１１は、中央ウェル領域３の１辺に沿って直線状に設けられている。第１コンタクト領域１１は、図１に示したＶＢ電位が印加される高電位側電源端子ＶＢに電気的に接続されている。 The high-side circuit region 101 is provided in a central well region 3 of a first conductivity type (n-type). As shown in FIG. 2, the central well region 3 has a substantially rectangular planar pattern. An n + type first contact region (first diode terminal contact region) 11 is provided in a part of the periphery of the central well region 3. The first contact region 11 is provided linearly along one side of the central well region 3. The first contact region 11 is electrically connected to a high potential side power supply terminal VB to which the VB potential shown in FIG. 1 is applied.

中央ウェル領域３の周囲の他の一部には、ｐ型のスリット領域１２が設けられている。スリット領域１２は、第１コンタクト領域１１が設けられた１辺とは異なる中央ウェル領域３の３辺に沿って、上向きのＣ字状に設けられている。スリット領域１２の両端は、第１コンタクト領域１１よりも中央ウェル領域３の中央側（内側）に位置し、第１コンタクト領域１１と平行に設けられている。スリット領域１２よりも内側に、ｎ＋型のコンタクト領域１１１が環状（枠状）に設けられている。コンタクト領域１１１は高電位側電源端子ＶＢに電気的に接続されている。 A p-type slit region 12 is provided in another part of the periphery of the central well region 3. The slit region 12 is provided in an upward C-shape along three sides of the central well region 3 other than the side on which the first contact region 11 is provided. Both ends of the slit region 12 are located closer to the center (inner) of the central well region 3 than the first contact region 11 and are provided parallel to the first contact region 11. An n + -type contact region 111 is provided in a ring shape (frame shape) on the inner side of the slit region 12. The contact region 111 is electrically connected to the high potential side power supply terminal VB.

ＨＶＪＴ１０２には、中央ウェル領域３の周囲を囲むようにｎ－型のドリフト領域（耐圧領域）２が環状（枠状）に設けられている。ドリフト領域２の不純物濃度は、中央ウェル領域３の不純物濃度よりも低い。なお、図２では、第１コンタクト領域１１が中央ウェル領域３の上部に設けられた場合を例示するが、第１コンタクト領域１１がドリフト領域２の上部に設けられていてもよい。 In the HVJT 102, an n - type drift region (breakdown voltage region) 2 is provided in a ring shape (frame shape) so as to surround the periphery of the central well region 3. The impurity concentration of the drift region 2 is lower than the impurity concentration of the central well region 3. Note that, although FIG. 2 illustrates an example in which the first contact region 11 is provided on the upper part of the central well region 3, the first contact region 11 may be provided on the upper part of the drift region 2.

ドリフト領域２の外周側には、第２導電型（ｐ型）の環状ウェル領域（分離領域）５が環状（枠状）に設けられている。環状ウェル領域５の上部には、ｐ＋型の第２コンタクト領域（第２ダイオード端子接触領域）４が環状に設けられている。第２コンタクト領域４の不純物濃度は、環状ウェル領域５の不純物濃度よりも高い。第２コンタクト領域４は、図１に示したＧＮＤ電位が印加される接地電位端子ＧＮＤに電気的に接続されている。 A second conductive type (p type) annular well region (isolation region) 5 is provided in an annular (frame-shaped) shape on the outer periphery of the drift region 2. A p + type second contact region (second diode terminal contact region) 4 is provided in an annular shape on the upper portion of the annular well region 5. The impurity concentration of the second contact region 4 is higher than the impurity concentration of the annular well region 5. The second contact region 4 is electrically connected to a ground potential terminal GND to which the GND potential shown in FIG. 1 is applied.

ローサイド回路領域１０３は、環状ウェル領域５の外周側に設けられたｎ型のウェル領域で構成されている。ローサイド回路領域１０３を構成するｎ型のウェル領域は、中央ウェル領域３と同じ深さで設けられている。 The low-side circuit region 103 is composed of an n-type well region provided on the outer periphery of the annular well region 5. The n-type well region that constitutes the low-side circuit region 103 is provided at the same depth as the central well region 3.

ＨＶＪＴ１０２の一部には、第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂが設けられている。第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂは、図１に示したレベルシフタ６９に対応する。第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂは、入力信号がオン信号の場合にオンするｎＭＯＳトランジスタと、入力信号がオフ信号の場合にオンするｎＭＯＳトランジスタとを個別に構成してもよい。図２に示すように、第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂは、対称位置において互いに対向するように設けられている。なお、第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂの配置位置は対称位置に限定されず、ＨＶＪＴ１０２の一部にそれぞれ設けられていればよい。 A first level conversion element 10a and a second level conversion element 10b are provided in a part of the HVJT 102. The first level conversion element 10a and the second level conversion element 10b correspond to the level shifter 69 shown in FIG. 1. The first level conversion element 10a and the second level conversion element 10b may be individually configured with an nMOS transistor that turns on when the input signal is an on signal and an nMOS transistor that turns on when the input signal is an off signal. As shown in FIG. 2, the first level conversion element 10a and the second level conversion element 10b are provided so as to face each other in symmetrical positions. Note that the arrangement positions of the first level conversion element 10a and the second level conversion element 10b are not limited to symmetrical positions, and it is sufficient that they are provided in a part of the HVJT 102.

実施形態に係る半導体集積回路では、スリット領域１２がハイサイド回路領域１０１を囲むことにより、第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂの後述する第１担体受領領域７ａ及び第２担体受領領域７ｂとハイサイド回路領域１０１の第１コンタクト領域１１との間の寄生抵抗の抵抗値を大きくしている。これは、スリット領域１２の平面パターン上の長さにより、第１担体受領領域７ａ及び第２担体受領領域７ｂと第１コンタクト領域１１との間の抵抗値を調整する方式（寄生抵抗値調整方式）である。この寄生抵抗をレベルシフト抵抗６８として用いることができる。また、この寄生抵抗の抵抗値を十分大きくし、この寄生抵抗に比べて抵抗値の小さい抵抗素子をこの寄生抵抗に並列に設けてレベルシフト抵抗６８とすることもできる。抵抗素子は、例えば、多結晶シリコンにより形成でき、ハイサイド回路領域１０１に配置できる。 In the semiconductor integrated circuit according to the embodiment, the slit region 12 surrounds the high-side circuit region 101, thereby increasing the resistance value of the parasitic resistance between the first carrier receiving region 7a and the second carrier receiving region 7b of the first level conversion element 10a and the second level conversion element 10b, which will be described later, and the first contact region 11 of the high-side circuit region 101. This is a method (parasitic resistance adjustment method) for adjusting the resistance value between the first carrier receiving region 7a and the second carrier receiving region 7b and the first contact region 11 by the length of the planar pattern of the slit region 12. This parasitic resistance can be used as a level shift resistor 68. In addition, the resistance value of this parasitic resistance can be made sufficiently large, and a resistor element having a smaller resistance value than this parasitic resistance can be provided in parallel with this parasitic resistance to form the level shift resistor 68. The resistor element can be formed of, for example, polycrystalline silicon, and can be arranged in the high-side circuit region 101.

図２の右側に示した第１レベル変換素子１０ａは、環状のドリフト領域２と、ｐ型の環状ウェル領域５の一部で構成される共通ベース領域とを備える。更に、第１レベル変換素子１０ａは、ｎ＋型の第１ソース領域（第１担体供給領域）８ａと、第１担体供給領域８ａに対向して設けられたｎ＋型の第１ドレイン領域（第１担体受領領域）７ａとを備える。第１担体供給領域８ａ及び第１担体受領領域７ａの不純物濃度は、ドリフト領域２及び中央ウェル領域３の不純物濃度よりも高い。環状ウェル領域５はその内側に、ドリフト領域２の上部に環状に形成された浅い領域を備えていてもよい。この浅い領域が共通ベース領域となり、この浅い領域に第１担体供給領域８ａを形成してもよい。 The first level conversion element 10a shown on the right side of FIG. 2 includes an annular drift region 2 and a common base region formed of a part of a p-type annular well region 5. The first level conversion element 10a further includes an n + type first source region (first carrier supply region) 8a and an n + type first drain region (first carrier receiving region) 7a provided opposite the first carrier supply region 8a. The impurity concentrations of the first carrier supply region 8a and the first carrier receiving region 7a are higher than the impurity concentrations of the drift region 2 and the central well region 3. The annular well region 5 may include a shallow region formed annularly on the upper part of the drift region 2 inside the annular well region 5. This shallow region may be the common base region, and the first carrier supply region 8a may be formed in this shallow region.

第１担体供給領域８ａは、図１に示したＧＮＤ電位が印加される接地電位端子ＧＮＤに電気的に接続されている。第１担体受領領域７ａは、図１に示したＶＢ電位が印加される高電位側電源端子ＶＢにレベルシフト抵抗６８を介して電気的に接続されている。 The first carrier supply area 8a is electrically connected to the ground potential terminal GND to which the GND potential shown in FIG. 1 is applied. The first carrier receiving area 7a is electrically connected via a level shift resistor 68 to the high potential side power supply terminal VB to which the VB potential shown in FIG. 1 is applied.

更に、第１レベル変換素子１０ａは、第１担体供給領域８ａ及びドリフト領域２に挟まれた共通ベース領域上にゲート絶縁膜（図示省略）を介して配置された第１ゲート電極（制御電極）９ａを備える。ゲート絶縁膜は、例えばシリコン酸化膜（ＳｉＯ２膜）やＳｉＯ２膜以外のシリコン窒化膜（Ｓｉ３Ｎ４膜）等の種々の絶縁膜、或いはＳｉＯ２膜、Ｓｉ３Ｎ４膜等を含む絶縁膜の積層膜で形成することが可能である。第１ゲート電極９ａは、環状ウェル領域５の一部で構成される共通ベース領域の電位を制御する。第１ゲート電極９ａは、例えば不純物が導入された多結晶シリコン（ドープド・ポリシリコン）膜、高融点金属、高融点金属のシリサイド等で形成されている。 Furthermore, the first level conversion element 10a includes a first gate electrode (control electrode) 9a disposed on the common base region sandwiched between the first carrier supply region 8a and the drift region 2 via a gate insulating film (not shown). The gate insulating film can be formed of various insulating films such as a silicon oxide film ( SiO2 film) or a silicon nitride film ( Si3N4 film) other than a SiO2 film, or a laminated film of insulating films including a SiO2 film, a Si3N4 film, etc. The first gate electrode 9a controls the potential of the common base region formed of a part of the annular well region 5. The first gate electrode 9a is formed of, for example, a polycrystalline silicon (doped polysilicon) film into which an impurity has been introduced, a high melting point metal, a silicide of a high melting point metal, or the like.

図２の左側に示した第２レベル変換素子１０ｂは、第１レベル変換素子１０ａと鏡像関係で同様の構成を有する。第２レベル変換素子１０ｂは、環状のドリフト領域２と、ｐ型の環状ウェル領域５の一部で構成され、第１レベル変換素子１０ａと共通の共通ベース領域を備える。更に、第２レベル変換素子１０ｂは、ｎ＋型の第２ソース領域（第２担体供給領域）８ｂと、第２担体供給領域８ｂに対向して設けられたｎ＋型の第２ドレイン領域（第２担体受領領域）７ｂとを備える。更に、第２レベル変換素子１０ｂは、第２担体供給領域８ｂ及びドリフト領域２に挟まれた共通ベース領域上にゲート絶縁膜（図示省略）を介して配置された第２ゲート電極（制御電極）９ｂを備える。 The second level conversion element 10b shown on the left side of FIG. 2 has a mirror image of the first level conversion element 10a and has the same configuration. The second level conversion element 10b is composed of an annular drift region 2 and a part of a p-type annular well region 5, and has a common base region common to the first level conversion element 10a. Furthermore, the second level conversion element 10b has an n + type second source region (second carrier supply region) 8b and an n + type second drain region (second carrier receiving region) 7b provided opposite to the second carrier supply region 8b. Furthermore, the second level conversion element 10b has a second gate electrode (control electrode) 9b arranged on the common base region sandwiched between the second carrier supply region 8b and the drift region 2 via a gate insulating film (not shown).

図２の上側に示す、第２コンタクト領域４と第１コンタクト領域１１が対向する領域（ダイオード形成領域）３１を含むＡ－Ａ´方向から見た断面図を図３に示す。図３に示すように、実施形態に係る半導体集積回路は、基体１に設けられている。基体１は、ｐ型のシリコン（Ｓｉ）からなる半導体基板１４と、半導体基板１４上に設けられたｐ型のＳｉからなるエピタキシャル成長層１５の積層構造で構成されている。半導体集積回路５０を使用する際に半導体基板１４は、例えばＧＮＤ電位に固定されている。ダイオード形成領域３１には、第２コンタクト領域４と第１コンタクト領域１１との間にスリット領域１２は形成されていない。 Figure 3 shows a cross-sectional view seen from the A-A' direction including the region (diode formation region) 31 where the second contact region 4 and the first contact region 11 face each other, shown in the upper part of Figure 2. As shown in Figure 3, the semiconductor integrated circuit according to the embodiment is provided on a base 1. The base 1 is configured with a laminated structure of a semiconductor substrate 14 made of p-type silicon (Si) and an epitaxial growth layer 15 made of p-type Si provided on the semiconductor substrate 14. When the semiconductor integrated circuit 50 is used, the semiconductor substrate 14 is fixed to, for example, a GND potential. In the diode formation region 31, no slit region 12 is formed between the second contact region 4 and the first contact region 11.

図２及び図３に示すように、エピタキシャル成長層１５には、ｎ型の中央ウェル領域３が選択的に設けられている。中央ウェル領域３の下端、即ち半導体基板１４と中央ウェル領域３との間には、ｎ型の埋込層１３が一様に埋め込まれている。埋込層１３は、アンチモン（Ｓｂ）、燐（Ｐ）又は砒素（Ａｓ）等のｎ型不純物をドープした拡散層で構成されている。埋込層１３の不純物濃度は、中央ウェル領域３の不純物濃度よりも高い。図２では、中央ウェル領域３の下方に設けられたｎ型の埋込層１３の平面パターンの位置を破線で模式的に示している。埋込層１３は、略矩形の平面パターンを有する。図２の平面パターン上、ハイサイド回路領域１０１の内部回路は、埋込層１３の内側に形成される。また、コンタクト領域１１１が埋込層１３の内側に配置された場合を例示するが、コンタクト領域１１１は埋込層１３の外側に配置されていてもよい。 2 and 3, an n-type central well region 3 is selectively provided in the epitaxial growth layer 15. An n-type buried layer 13 is uniformly buried at the lower end of the central well region 3, i.e., between the semiconductor substrate 14 and the central well region 3. The buried layer 13 is composed of a diffusion layer doped with n-type impurities such as antimony (Sb), phosphorus (P) or arsenic (As). The impurity concentration of the buried layer 13 is higher than the impurity concentration of the central well region 3. In FIG. 2, the position of the planar pattern of the n-type buried layer 13 provided below the central well region 3 is shown by a dashed line. The buried layer 13 has a substantially rectangular planar pattern. On the planar pattern in FIG. 2, the internal circuit of the high side circuit region 101 is formed inside the buried layer 13. Although the contact region 111 is illustrated as being disposed inside the buried layer 13, the contact region 111 may be disposed outside the buried layer 13.

図２及び図３に示した埋込層１３は、ハイサイド回路領域１０１の内部回路で形成される深さ方向の寄生ｐｎｐバイポーラトランジスタの動作を抑制する機能を有する。即ち、ＨＶＩＣの動作時において、通常はＶＢ電位がＶＳ電位よりも高い状態であり、ハイサイド回路領域１０１の内部回路で形成される深さ方向の寄生ｐｎｐバイポーラトランジスタは動作しない。しかし、雷サージ等のノイズにより、ＶＢ電位がＶＳ電位よりも低い負電圧（マイナス電位の電圧）の状態となると、埋込層１３を設けない場合には寄生ｐｎｐバイポーラトランジスタがオンし、半導体基板１４に向けて大電流が流れる。これに対して、埋込層１３を設けることにより、寄生ｐｎｐバイポーラトランジスタの動作を防止することができ、ＨＶＩＣの破壊を防止することができる。 The buried layer 13 shown in Figures 2 and 3 has the function of suppressing the operation of the parasitic pnp bipolar transistor in the depth direction formed in the internal circuit of the high side circuit region 101. That is, during operation of the HVIC, the VB potential is usually higher than the VS potential, and the parasitic pnp bipolar transistor in the depth direction formed in the internal circuit of the high side circuit region 101 does not operate. However, when the VB potential becomes a negative voltage (negative potential voltage) lower than the VS potential due to noise such as a lightning surge, if the buried layer 13 is not provided, the parasitic pnp bipolar transistor will turn on and a large current will flow toward the semiconductor substrate 14. In contrast, by providing the buried layer 13, the operation of the parasitic pnp bipolar transistor can be prevented, and the destruction of the HVIC can be prevented.

中央ウェル領域３の上部には、ｎ＋型の第１コンタクト領域（第１ダイオード端子接触領域）１１が選択的に設けられている。第１コンタクト領域１１には、シリコン局部的酸化（ＬＯＣＯＳ）法等で形成したフィールド絶縁膜２１と、フィールド絶縁膜２１上の層間絶縁膜２２のコンタクトホールを介してカソード電極（第１ダイオード用電極）２４がオーミック接続されている。カソード電極２４は保護膜２５により覆われている。また、中央ウェル領域３の上部の第１コンタクト領域１１よりも内側には、ｎ＋型のコンタクト領域１１１が選択的に設けられている。コンタクト領域１１１には、高電位側電源端子ＶＢに対応する電極２８がオーミック接続されている。 An n + type first contact region (first diode terminal contact region) 11 is selectively provided on the upper part of the central well region 3. A cathode electrode (first diode electrode) 24 is ohmically connected to the first contact region 11 through a field insulating film 21 formed by a local oxidation of silicon (LOCOS) method or the like and a contact hole in an interlayer insulating film 22 on the field insulating film 21. The cathode electrode 24 is covered with a protective film 25. An n + type contact region 111 is selectively provided on the upper part of the central well region 3, inside the first contact region 11. An electrode 28 corresponding to a high potential side power supply terminal VB is ohmically connected to the contact region 111.

エピタキシャル成長層１５の上部には、中央ウェル領域３の外周側を囲むように、ｎ－型のドリフト領域２が設けられている。ドリフト領域２は、エピタキシャル成長層１５を深さ方向に貫通して半導体基板１４に接してもよい。エピタキシャル成長層１５の上部には、ドリフト領域２の周囲を囲むように、ｐ型の環状ウェル領域５が選択的に設けられている。環状ウェル領域５は、エピタキシャル成長層１５を深さ方向に貫通して半導体基板１４に接してもよい。環状ウェル領域５の上部には、ｐ＋型の第２コンタクト領域（第２ダイオード端子接触領域）４が選択的に設けられている。第２コンタクト領域４には、フィールド絶縁膜２１及び層間絶縁膜２２のコンタクトホールを介してアノード電極（第２ダイオード用電極）２３がオーミック接続されている。アノード電極２３は保護膜２５により覆われている。 An n - type drift region 2 is provided on the upper part of the epitaxial growth layer 15 so as to surround the outer periphery of the central well region 3. The drift region 2 may penetrate the epitaxial growth layer 15 in the depth direction and be in contact with the semiconductor substrate 14. A p-type annular well region 5 is selectively provided on the upper part of the epitaxial growth layer 15 so as to surround the periphery of the drift region 2. The annular well region 5 may penetrate the epitaxial growth layer 15 in the depth direction and be in contact with the semiconductor substrate 14. A p + type second contact region (second diode terminal contact region) 4 is selectively provided on the upper part of the annular well region 5. An anode electrode (second diode electrode) 23 is ohmically connected to the second contact region 4 via contact holes in the field insulating film 21 and the interlayer insulating film 22. The anode electrode 23 is covered with a protective film 25.

ダイオード形成領域３１において、図３に模式的に示すように、ｎ－型のドリフト領域２とｐ型の環状ウェル領域５とのｐｎ接合により寄生ダイオードＤ１が構成され、この寄生ダイオードＤ１によりＨＶＪＴ１０２が構成されている。環状ウェル領域５は寄生ダイオードＤ１のアノード領域として機能し、第２コンタクト領域４は寄生ダイオードＤ１のアノードコンタクト領域として機能する。第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂのドリフト領域２及び中央ウェル領域３は、寄生ダイオードＤ１のカソード領域として機能し、第１コンタクト領域１１は、寄生ダイオードＤ１のカソードコンタクト領域として機能する。 3, in the diode formation region 31, a parasitic diode D1 is formed by a pn junction between an n - type drift region 2 and a p-type annular well region 5, and this parasitic diode D1 constitutes an HVJT 102. The annular well region 5 functions as an anode region of the parasitic diode D1, and the second contact region 4 functions as an anode contact region of the parasitic diode D1. The drift region 2 and the central well region 3 of the first level conversion element 10a and the second level conversion element 10b function as cathode regions of the parasitic diode D1, and the first contact region 11 functions as a cathode contact region of the parasitic diode D1.

図４は、図２に示した第１レベル変換素子１０ａを含むＢ－Ｂ´方向から見た断面図を示す。図２及び図４に示すように、ｐ型の半導体基板１４上に設けられたｐ型のエピタキシャル成長層１５には、ｎ型の中央ウェル領域３が選択的に設けられている。半導体基板１４と中央ウェル領域３との間には、ｎ型の埋込層１３が埋め込まれている。中央ウェル領域３を深さ方向に貫通するように、ｐ型のスリット領域１２が選択的に設けられている。スリット領域１２の底部は、半導体基板１４に接している。スリット領域１２は、中央ウェル領域３の一部が欠落したエピタキシャル成長層１５により形成されてもよい。 Figure 4 shows a cross-sectional view seen from the B-B' direction including the first level conversion element 10a shown in Figure 2. As shown in Figures 2 and 4, an n-type central well region 3 is selectively provided in a p-type epitaxial growth layer 15 provided on a p-type semiconductor substrate 14. An n-type buried layer 13 is buried between the semiconductor substrate 14 and the central well region 3. A p-type slit region 12 is selectively provided so as to penetrate the central well region 3 in the depth direction. The bottom of the slit region 12 is in contact with the semiconductor substrate 14. The slit region 12 may be formed by the epitaxial growth layer 15 from which a portion of the central well region 3 is missing.

中央ウェル領域３の上部には、ｎ＋型の第１担体受領領域７ａが選択的に設けられている。第１担体受領領域７ａには、フィールド絶縁膜２１及び層間絶縁膜２２のコンタクトホールを介して担体受領電極（ドレイン電極）２７が接続されている。担体受領電極２７は保護膜２５により覆われている。 An n + type first carrier receiving region 7a is selectively provided on the upper part of the central well region 3. A carrier receiving electrode (drain electrode) 27 is connected to the first carrier receiving region 7a via a contact hole in the field insulating film 21 and the interlayer insulating film 22. The carrier receiving electrode 27 is covered with a protective film 25.

エピタキシャル成長層１５の上部には、中央ウェル領域３の周囲を囲むように、ｎ－型のドリフト領域２が選択的に設けられている。エピタキシャル成長層１５の上部にはドリフト領域２の周囲を囲むように、共通ベース領域として機能するｐ型の環状ウェル領域５が選択的に設けられている。環状ウェル領域５の上部には、ｎ＋型の第１担体供給領域８ａが選択的に設けられている。 An n- type drift region 2 is selectively provided on the upper part of the epitaxial growth layer 15 so as to surround the periphery of the central well region 3. A p- type annular well region 5 functioning as a common base region is selectively provided on the upper part of the epitaxial growth layer 15 so as to surround the periphery of the drift region 2. An n + type first carrier supply region 8a is selectively provided on the upper part of the annular well region 5.

環状ウェル領域５の上部には、ｐ＋型の第２コンタクト領域４が選択的に設けられている。第２コンタクト領域４は、第１担体供給領域８ａに接し、バックゲート領域として機能する。第１担体供給領域８ａ及び第２コンタクト領域４には、フィールド絶縁膜２１及び層間絶縁膜２２のコンタクトホールを介して担体供給電極（ソース電極）２６が接続されている。担体供給電極２６は保護膜２５により覆われている。担体供給電極２６は、アノード電極（第２ダイオード用電極）２３と共通の電極であり、接地電位端子ＧＮＤに電気的に接続されている。第１担体供給領域８ａとドリフト領域２とに挟まれた環状ウェル領域５上には、ゲート絶縁膜２０を介して第１ゲート電極（制御電極）９ａが設けられている。 A p + type second contact region 4 is selectively provided on the upper portion of the annular well region 5. The second contact region 4 is in contact with the first carrier supply region 8a and functions as a back gate region. A carrier supply electrode (source electrode) 26 is connected to the first carrier supply region 8a and the second contact region 4 through contact holes in the field insulating film 21 and the interlayer insulating film 22. The carrier supply electrode 26 is covered with a protective film 25. The carrier supply electrode 26 is a common electrode with the anode electrode (second diode electrode) 23, and is electrically connected to the ground potential terminal GND. A first gate electrode (control electrode) 9a is provided on the annular well region 5 sandwiched between the first carrier supply region 8a and the drift region 2 through a gate insulating film 20.

実施形態に係る半導体集積回路では、図２の上側に示した第２コンタクト領域４と第１コンタクト領域１１が対向するダイオード形成領域３１に位置する埋込層１３よりも、第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂの形成部分に位置する埋込層１３が、環状ウェル領域５から離れるように配置されている。即ち、図２及び図３に示したダイオード形成領域３１における、ｐｎ接合ダイオードＤ１のアノード領域として機能する環状ウェル領域５と、埋込層１３との距離（第１距離）Ｌ１１が、図２及び図４に示した第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂの共通ベース領域として機能する環状ウェル領域５と、埋込層１３との距離（第２距離）Ｌ１２よりも短い。例えば、第１距離Ｌ１１は、９０μｍ～１００μｍ程度であり、第２距離Ｌ１２は、１００μｍ～１１０μｍ程度である。 In the semiconductor integrated circuit according to the embodiment, the buried layer 13 located in the formation portion of the first level conversion element 10a and the second level conversion element 10b is arranged so as to be farther away from the annular well region 5 than the buried layer 13 located in the diode formation region 31 where the second contact region 4 and the first contact region 11 shown in the upper part of FIG. 2 face each other. That is, the distance (first distance) L11 between the annular well region 5 functioning as the anode region of the pn junction diode D1 in the diode formation region 31 shown in FIG. 2 and FIG. 3 and the buried layer 13 is shorter than the distance (second distance) L12 between the annular well region 5 functioning as the common base region of the first level conversion element 10a and the second level conversion element 10b shown in FIG. 2 and FIG. 4 and the buried layer 13. For example, the first distance L11 is about 90 μm to 100 μm, and the second distance L12 is about 100 μm to 110 μm.

ダイオード形成領域３１の全てに亘って第１距離Ｌ１１が同じ長さでなくてもよく、例えば、ダイオード形成領域３１の一部の領域においてＬ１２と同じであってもよい。また、第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂの形成領域の全てに亘って第２距離Ｌ１２が同じ長さでなくてもよい。しかし、第１距離Ｌ１１のうちの最小値は、第２距離Ｌ１２のうちの最小値より短くする。即ち、第１コンタクト領域１１が形成されるダイオード形成領域３１における環状ウェル領域５と埋込層１３との第１距離Ｌ１１の内の最小値は、第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂの形成領域における環状ウェル領域５と埋込層１３との第２距離Ｌ１２の内の最小値よりも短い。 The first distance L11 does not have to be the same length over the entire diode formation region 31, and may be the same as L12 in a portion of the diode formation region 31, for example. The second distance L12 does not have to be the same length over the entire formation region of the first level conversion element 10a and the second level conversion element 10b. However, the minimum value of the first distance L11 is shorter than the minimum value of the second distance L12. That is, the minimum value of the first distance L11 between the annular well region 5 and the buried layer 13 in the diode formation region 31 where the first contact region 11 is formed is shorter than the minimum value of the second distance L12 between the annular well region 5 and the buried layer 13 in the formation region of the first level conversion element 10a and the second level conversion element 10b.

第１距離Ｌ１１が第２距離Ｌ１２より短い第１コンタクト領域１１の長さ（ダイオード形成領域３１の幅）Ｗ０は、どの程度ＥＳＤ耐量を向上させるかに応じて適宜決定される。第１距離Ｌ１１が第２距離Ｌ１２より短いダイオード形成領域３１の幅Ｗ０は、第１レベル変換素子１０ａのチャネル幅Ｗ１と第２レベル変換素子１０ｂのチェネル幅Ｗ２の和以上であると好ましい。さらには、チャネル幅Ｗ１とチャネル幅Ｗ２の和の２倍以上であるとさらに好ましい。 The length W0 of the first contact region 11 (width of the diode formation region 31) where the first distance L11 is shorter than the second distance L12 is appropriately determined depending on the extent to which the ESD tolerance is to be improved. The width W0 of the diode formation region 31 where the first distance L11 is shorter than the second distance L12 is preferably equal to or greater than the sum of the channel width W1 of the first level conversion element 10a and the channel width W2 of the second level conversion element 10b. Furthermore, it is even more preferable that it is equal to or greater than twice the sum of the channel width W1 and the channel width W2.

なお、図２では、中央ウェル領域３の矩形の平面パターンの１辺に位置するダイオード形成領域３１のみにおいて、第１距離Ｌ１１を第２距離Ｌ１２よりも短くしているが、中央ウェル領域３の周縁の第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂが形成されていない領域であれば、中央ウェル領域３の２辺、３辺又は４辺の位置に亘って、環状ウェル領域５と埋込層１３との距離を第１距離Ｌ１１としてもよい。例えば、図２の下側に示す中央ウェル領域３の１辺の位置において、環状ウェル領域５と埋込層１３との距離Ｌ１３が、第２距離Ｌ１２と同等である場合を例示しているが、環状ウェル領域５と埋込層１３との距離Ｌ１３を第１距離Ｌ１１としてもよい。 2, the first distance L11 is shorter than the second distance L12 only in the diode formation region 31 located on one side of the rectangular planar pattern of the central well region 3. However, the distance between the annular well region 5 and the buried layer 13 may be the first distance L11 over two, three or four sides of the central well region 3 in a region where the first level conversion element 10a and the second level conversion element 10b are not formed on the periphery of the central well region 3. For example, the case where the distance L13 between the annular well region 5 and the buried layer 13 is equal to the second distance L12 at the position of one side of the central well region 3 shown in the lower part of FIG. 2 is illustrated, but the distance L13 between the annular well region 5 and the buried layer 13 may be the first distance L11.

また、図２に示すように、ダイオード形成領域３１のドリフト長Ｌ１４と、第１レベル変換素子１０ａのドリフト長Ｌ１５及び第２レベル変換素子１０ｂのドリフト長Ｌ１６とは、略同一であってもよく、互いに異なっていてもよい。例えば、ダイオード形成領域３１のドリフト長Ｌ１４は、第１レベル変換素子１０ａのドリフト長Ｌ１５及び第２レベル変換素子１０ｂのドリフト長Ｌ１６よりも短くてもよい。例えば、ダイオード形成領域３１のドリフト長Ｌ１４は、第１コンタクト領域１１と第２コンタクト領域４との間の距離として定義される。第１レベル変換素子１０ａのドリフト長Ｌ１５は、第１レベル変換素子１０ａの第１担体供給領域８ａと第１担体受領領域７ａとの間の距離として定義される。第２レベル変換素子１０ｂのドリフト長Ｌ１６は、第２レベル変換素子１０ｂの第２担体供給領域８ｂと第２担体受領領域７ｂとの間の距離として定義される。 2, the drift length L14 of the diode-forming region 31, the drift length L15 of the first level conversion element 10a, and the drift length L16 of the second level conversion element 10b may be substantially the same or different from each other. For example, the drift length L14 of the diode-forming region 31 may be shorter than the drift length L15 of the first level conversion element 10a and the drift length L16 of the second level conversion element 10b. For example, the drift length L14 of the diode-forming region 31 is defined as the distance between the first contact region 11 and the second contact region 4. The drift length L15 of the first level conversion element 10a is defined as the distance between the first carrier supply region 8a and the first carrier receiving region 7a of the first level conversion element 10a. The drift length L16 of the second level conversion element 10b is defined as the distance between the second carrier supply region 8b and the second carrier receiving region 7b of the second level conversion element 10b.

実施形態に係る半導体集積回路によれば、ダイオード形成領域３１における環状ウェル領域５と埋込層１３との第１距離Ｌ１１を、第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂの形成領域における環状ウェル領域５と埋込層１３との第２距離Ｌ１２よりも短くすることにより、第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂの形成領域の電界を緩和することができ、第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂの形成領域のオフ耐圧を、ダイオード形成領域３１のオフ耐圧よりも大きくすることができる。そのため、ＥＳＤサージが入力されて、同時にアバランシェ状態になった場合でも、アバランシェ電流は主として寄生構造を持たない寄生ダイオードＤ１を経由して流れる。寄生動作の原因となる寄生ダイオードＤ１のアバランシェ電流が、第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂに流れ込むのを抑制できるため、半導体集積回路全体としてのＥＳＤ耐量を向上させることができる。 According to the semiconductor integrated circuit of the embodiment, the first distance L11 between the annular well region 5 and the buried layer 13 in the diode formation region 31 is made shorter than the second distance L12 between the annular well region 5 and the buried layer 13 in the formation region of the first level conversion element 10a and the second level conversion element 10b, so that the electric field in the formation region of the first level conversion element 10a and the second level conversion element 10b can be relaxed, and the off-breakdown voltage of the formation region of the first level conversion element 10a and the second level conversion element 10b can be made larger than the off-breakdown voltage of the diode formation region 31. Therefore, even if an ESD surge is input and an avalanche state occurs at the same time, the avalanche current mainly flows through the parasitic diode D1 that does not have a parasitic structure. Since the avalanche current of the parasitic diode D1, which causes parasitic operation, can be prevented from flowing into the first level conversion element 10a and the second level conversion element 10b, the ESD tolerance of the entire semiconductor integrated circuit can be improved.

＜シミュレーション結果＞
図５及び図６に、図２のＡ－Ａ´方向から見た図３に対応するダイオード形成領域３１の断面、及び図２のＢ－Ｂ´方向から見た図４に対応する第１レベル変換素子１０ａの形成領域の断面における電界強度シミュレーション結果をそれぞれ示す。図５の丸で囲んだ領域Ａ１は、８５０Ｖ印加時のダイオード形成領域３１の電界集中ポイントを示す。図６の丸で囲んだ領域Ａ２は、１０００Ｖ印加時の第１レベル変換素子１０ａの形成領域の電界集中ポイントを示す。図５及び図６に示すように、埋込層１３の端部に電界が集中していることが分かる。 <Simulation results>
5 and 6 show the results of electric field intensity simulations in a cross section of the diode formation region 31 corresponding to FIG. 3 as viewed from the A-A' direction in FIG. 2, and in a cross section of the formation region of the first level conversion element 10a corresponding to FIG. 4 as viewed from the B-B' direction in FIG. 2, respectively. The circled region A1 in FIG. 5 shows the electric field concentration point in the diode formation region 31 when 850 V is applied. The circled region A2 in FIG. 6 shows the electric field concentration point in the formation region of the first level conversion element 10a when 1000 V is applied. As shown in FIG. 5 and FIG. 6, it can be seen that the electric field is concentrated at the end of the buried layer 13.

図７に、実施形態に係る半導体集積回路の耐圧シミュレーション結果を示す。図７の「Ａ－Ａ´」のプロファイルはダイオード形成領域３１の耐圧を示し、図７の「Ｂ－Ｂ´」のプロファイルは第１レベル変換素子１０ａの形成領域の耐圧を示す。図７に示すように、ダイオード形成領域３１の耐圧と比較して、第１レベル変換素子１０ａの形成領域の耐圧が高いことが分かる。 Figure 7 shows the results of a breakdown voltage simulation of the semiconductor integrated circuit according to the embodiment. The profile "A-A'" in Figure 7 shows the breakdown voltage of the diode formation region 31, and the profile "B-B'" in Figure 7 shows the breakdown voltage of the formation region of the first level conversion element 10a. As shown in Figure 7, it can be seen that the breakdown voltage of the formation region of the first level conversion element 10a is higher than the breakdown voltage of the diode formation region 31.

＜比較例＞
次に、図８～図１０を参照して、第１～第３比較例に係る半導体集積回路を説明する。まず、第１比較例に係る半導体集積回路は、図８に示すように、中央ウェル領域３の下方に図３に示した埋込層１３が無い点が、実施形態に係る半導体集積回路の構成と異なる。第１比較例に係る半導体集積回路では、図３に示したような、中央ウェル領域３の下方の埋込層１３が無いため、ハイサイド回路領域１０１の内部回路の寄生素子が動作し易い。これに対して、実施形態に係る半導体集積回路では、図３に示したように、中央ウェル領域３の下方の埋込層１３が有るため、ハイサイド回路領域１０１の内部回路の寄生素子の動作を抑制することができる。 Comparative Example
Next, semiconductor integrated circuits according to first to third comparative examples will be described with reference to Figures 8 to 10. First, the semiconductor integrated circuit according to the first comparative example differs from the semiconductor integrated circuit according to the embodiment in that, as shown in Figure 8, there is no buried layer 13 shown in Figure 3 below the central well region 3. In the semiconductor integrated circuit according to the first comparative example, there is no buried layer 13 below the central well region 3 as shown in Figure 3, so that parasitic elements of the internal circuit in the high side circuit region 101 tend to operate. In contrast, in the semiconductor integrated circuit according to the embodiment, there is the buried layer 13 below the central well region 3 as shown in Figure 3, so that the operation of parasitic elements of the internal circuit in the high side circuit region 101 can be suppressed.

また、第１比較例に係る半導体集積回路では、ダイオード形成領域３１のドリフト長Ｌ２１と第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂのドリフト長Ｌ２２を揃えており、オフ耐圧も等しい。オフ耐圧が等しいと、ＥＳＤサージ等が入力された場合、ダイオード形成領域３１と第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂが同時にアバランシェ状態に陥るため、ダイオード形成領域３１と第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂに略均一にアバランシェ電流が流れる。そのため、局所的な電流集中を起こしにくい。しかし、高耐圧ｎ型ＭＯＳＦＥＴ等の第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂではアバランシェ電流により寄生ｎｐｎバイポーラトランジスタがオンし、寄生動作が誘発されるため、ｐｎ接合ダイオードＤ１に比べて破壊しやすい。レベルシフト抵抗を調整することで第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂに流れるアバランシェ電流を制限し、この破壊耐量のアンバランスを解消する方法もあるが、その場合、レベルシフト抵抗を必要以上に大きくする必要があるため、設計上の制限を受けることになる。 In addition, in the semiconductor integrated circuit according to the first comparative example, the drift length L21 of the diode formation region 31 and the drift length L22 of the first level conversion element 10a and the second level conversion element 10b are aligned, and the off-state breakdown voltages are also equal. If the off-state breakdown voltages are equal, when an ESD surge or the like is input, the diode formation region 31, the first level conversion element 10a, and the second level conversion element 10b simultaneously fall into an avalanche state, so that an avalanche current flows approximately uniformly through the diode formation region 31, the first level conversion element 10a, and the second level conversion element 10b. Therefore, localized current concentration is unlikely to occur. However, in the first level conversion element 10a and the second level conversion element 10b, such as a high-voltage n-type MOSFET, the avalanche current turns on the parasitic npn bipolar transistor, inducing parasitic operation, and therefore, they are more likely to be destroyed than the pn junction diode D1. One method of eliminating this imbalance in breakdown resistance is to limit the avalanche current flowing through the first level conversion element 10a and the second level conversion element 10b by adjusting the level shift resistance, but in that case, the level shift resistance must be made larger than necessary, which imposes design limitations.

これに対して、実施形態に係る半導体集積回路では、図２～図４に示すように、ダイオード形成領域３１における環状ウェル領域５と埋込層１３との第１距離Ｌ１１を、第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂの形成領域における環状ウェル領域５と埋込層１３との第２距離Ｌ１２よりも短くすることにより、第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂの電界を緩和して、半導体集積回路全体のＥＳＤ耐量を向上させることができる。更に、レベルシフト抵抗だけでアバランシェ電流を制限する方法に比べて、設計上の自由度が高い。また、埋込層１３の配置によって、ダイオード形成領域３１と第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂの形成領域との耐圧バランスを変えられるため、ＨＶＪＴ１０２を構成するドリフト領域（耐圧領域）２の幅（ドリフト長）自体の拡張等が不要で、チップ面積の増大を抑制することができる。 In contrast, in the semiconductor integrated circuit according to the embodiment, as shown in FIG. 2 to FIG. 4, the first distance L11 between the annular well region 5 and the buried layer 13 in the diode formation region 31 is made shorter than the second distance L12 between the annular well region 5 and the buried layer 13 in the formation region of the first level conversion element 10a and the second level conversion element 10b, thereby mitigating the electric field of the first level conversion element 10a and the second level conversion element 10b, thereby improving the ESD resistance of the entire semiconductor integrated circuit. Furthermore, compared to the method of limiting the avalanche current using only a level shift resistor, the design has a higher degree of freedom. In addition, since the breakdown voltage balance between the diode formation region 31 and the formation region of the first level conversion element 10a and the second level conversion element 10b can be changed by the arrangement of the buried layer 13, there is no need to expand the width (drift length) of the drift region (breakdown voltage region) 2 constituting the HVJT 102, and an increase in the chip area can be suppressed.

次に、第２比較例に係る半導体集積回路は、図９に示すように、ＨＶＪＴ１０２を構成するドリフト領域（耐圧領域）の内周面の一部を内側へ凸状に突出させることにより、第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂのドリフト長Ｌ２２を拡大する点が、実施形態に係る半導体集積回路の構成と異なる。第２比較例に係る半導体集積回路では、第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂが内側に突出することで、ハイサイド回路領域１０１の内部回路の有効面積が減少する。これに対して、実施形態に係る半導体集積回路では、ハイサイド回路領域１０１の内部回路の有効面積を減少させずに、半導体集積回路全体のＥＳＤ耐量を向上させることができる。 Next, the semiconductor integrated circuit according to the second comparative example differs from the semiconductor integrated circuit according to the embodiment in that, as shown in FIG. 9, a part of the inner circumferential surface of the drift region (voltage-resistant region) constituting the HVJT 102 is protruded inward in a convex shape to increase the drift length L22 of the first level conversion element 10a and the second level conversion element 10b. In the semiconductor integrated circuit according to the second comparative example, the effective area of the internal circuit of the high side circuit region 101 is reduced by the first level conversion element 10a and the second level conversion element 10b protruding inward. In contrast, in the semiconductor integrated circuit according to the embodiment, the ESD tolerance of the entire semiconductor integrated circuit can be improved without reducing the effective area of the internal circuit of the high side circuit region 101.

次に、第３比較例に係る半導体集積回路は、図１０に示すように、ドリフト領域２の外周面の一部を外側へ凸状に突出させることにより、第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂのドリフト長Ｌ２２を拡大する点が、実施形態に係る半導体集積回路の構成と異なる。第３比較例に係る半導体集積回路では、第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂが外側に突出することで、チップ面積が増大する。これに対して、実施形態に係る半導体集積回路では、チップ面積の増大を最小限に抑えつつ、半導体集積回路全体のＥＳＤ耐量を向上させることができる。 Next, the semiconductor integrated circuit according to the third comparative example differs from the configuration of the semiconductor integrated circuit according to the embodiment in that, as shown in FIG. 10, a portion of the outer peripheral surface of the drift region 2 is protruded outward in a convex shape to increase the drift length L22 of the first level conversion element 10a and the second level conversion element 10b. In the semiconductor integrated circuit according to the third comparative example, the chip area increases as the first level conversion element 10a and the second level conversion element 10b protrude outward. In contrast, in the semiconductor integrated circuit according to the embodiment, the increase in chip area can be minimized while improving the ESD tolerance of the entire semiconductor integrated circuit.

（第１変形例）
図１１は、図２に示した実施形態に係る半導体集積回路の平面レイアウトに対応する、実施形態の第１変形例に係る半導体集積回路の平面レイアウトを示す。図１２は、図１１に示したダイオード形成領域３１を含むＡ－Ａ´方向から見た断面図を示す。図１３は、図１１に示した第１レベル変換素子１０ａを含むＢ－Ｂ´方向から見た断面図を示す。第１変形例に係る半導体集積回路は、図１１及び図１２に示すように、第１コンタクト領域１１がドリフト領域２の上部に設けられている点が、図２及び図３に示した実施形態に係る半導体集積回路と異なる。即ち、第１コンタクト領域１１は、ドリフト領域２よりも内側に設けられていればよい。 (First Modification)
11 shows a planar layout of a semiconductor integrated circuit according to a first modification of the embodiment, which corresponds to the planar layout of the semiconductor integrated circuit according to the embodiment shown in FIG. 2. FIG. 12 shows a cross-sectional view seen from the A-A' direction including the diode formation region 31 shown in FIG. 11. FIG. 13 shows a cross-sectional view seen from the B-B' direction including the first level conversion element 10a shown in FIG. 11. As shown in FIGS. 11 and 12, the semiconductor integrated circuit according to the first modification is different from the semiconductor integrated circuit according to the embodiment shown in FIGS. 2 and 3 in that the first contact region 11 is provided above the drift region 2. That is, it is sufficient that the first contact region 11 is provided inside the drift region 2.

更に、実施形態の第１変形例に係る半導体集積回路は、図１１及び図１３に示すように、第１レベル変換素子１０ａのｎ＋型の第１ドレイン領域（第１担体受領領域）７ａ及び第２レベル変換素子１０ｂのｎ＋型の第２ドレイン領域（第２担体受領領域）７ｂがドリフト領域２の上部にそれぞれ設けられている点が、図２及び図４に示した実施形態に係る半導体集積回路と異なる。即ち、第１担体受領領域７ａ及び第２担体受領領域７ｂは、ドリフト領域２よりも内側に設けられていればよい。そして、スリット領域１２は、ドリフト領域２を深さ方向に貫通するように設けられている。スリット領域１２の底部は、エピタキシャル成長層１５に接している。スリット領域１２は、ドリフト領域２の一部が欠落したエピタキシャル成長層１５により形成されてもよい。第１変形例に係る半導体集積回路の他の構成は、実施形態に係る半導体集積回路と同様であるので、重複した説明を省略する。 Furthermore, as shown in FIG. 11 and FIG. 13, the semiconductor integrated circuit according to the first modification of the embodiment differs from the semiconductor integrated circuit according to the embodiment shown in FIG. 2 and FIG. 4 in that the n + type first drain region (first carrier receiving region) 7a of the first level conversion element 10a and the n + type second drain region (second carrier receiving region) 7b of the second level conversion element 10b are provided in the upper part of the drift region 2. That is, the first carrier receiving region 7a and the second carrier receiving region 7b may be provided inside the drift region 2. The slit region 12 is provided so as to penetrate the drift region 2 in the depth direction. The bottom of the slit region 12 is in contact with the epitaxial growth layer 15. The slit region 12 may be formed by the epitaxial growth layer 15 from which a part of the drift region 2 is missing. The other configurations of the semiconductor integrated circuit according to the first modification are the same as those of the semiconductor integrated circuit according to the embodiment, so that a duplicated description will be omitted.

第１変形例に係る半導体集積回路によれば、実施形態に係る半導体集積回路と同様に、ダイオード形成領域３１における環状ウェル領域５と埋込層１３との第１距離Ｌ１１を、第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂの形成領域における環状ウェル領域５と埋込層１３との第２距離Ｌ１２よりも短くすることにより、第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂの電界を緩和して、半導体集積回路全体のＥＳＤ耐量を向上させることができる。 In the semiconductor integrated circuit of the first modification, as in the semiconductor integrated circuit of the embodiment, the first distance L11 between the annular well region 5 and the buried layer 13 in the diode formation region 31 is made shorter than the second distance L12 between the annular well region 5 and the buried layer 13 in the formation regions of the first level conversion element 10a and the second level conversion element 10b, thereby mitigating the electric field of the first level conversion element 10a and the second level conversion element 10b, thereby improving the ESD tolerance of the entire semiconductor integrated circuit.

（第２変形例）
図１４及び図１５は、実施形態の第２変形例に係る半導体集積回路の断面図を示す。図１４は、図１２に示した第１変形例に係る半導体集積回路のダイオード形成領域３１を含む断面図に対応し、図１５は、図１３に示した第１変形例に係る半導体集積回路の第１レベル変換素子１０ａを含む断面図に対応する。 (Second Modification)
14 and 15 are cross-sectional views of a semiconductor integrated circuit according to a second modification of the embodiment. Fig. 14 corresponds to the cross-sectional view including the diode formation region 31 of the semiconductor integrated circuit according to the first modification shown in Fig. 12, and Fig. 15 corresponds to the cross-sectional view including the first level conversion element 10a of the semiconductor integrated circuit according to the first modification shown in Fig. 13.

第２変形例に係る半導体集積回路は、図１４及び図１５に示すように、基体１ａが、ｐ型のＳｉからなる半導体基板１４と、半導体基板１４上のｎ型のＳｉからなるエピタキシャル成長層１６とから構成される点が、図１２及び図１３に示した第１変形例に係る半導体集積回路と異なる。図１４に示すように、ｎ＋型の第１コンタクト領域１１が、エピタキシャル成長層１６の上部に設けられている。図１５に示すように、エピタキシャル成長層１６は、第１レベル変換素子１０ａのドリフト領域を構成する。エピタキシャル成長層１６は、図１１に示したドリフト領域２と同様の環状の平面パターンを有する。そして、スリット領域１２は、エピタキシャル成長層１６を深さ方向に貫通するように設けられている。スリット領域１２の底部は、半導体基板１４に接している。スリット領域１２は、中央ウェル領域３を深さ方向に貫通するように設けられてもよい。この場合、図３及び図４のように、第１コンタクト領域１１、第１ドレイン領域７ａ及び第２ドレイン領域７ｂを中央ウェル領域３の上部に設けてもよい。第２変形例に係る半導体集積回路の他の構成は、実施形態に係る半導体集積回路と同様であるので、重複した説明を省略する。 As shown in Figs. 14 and 15, the semiconductor integrated circuit according to the second modification is different from the semiconductor integrated circuit according to the first modification shown in Figs. 12 and 13 in that the base 1a is composed of a semiconductor substrate 14 made of p-type Si and an epitaxial growth layer 16 made of n-type Si on the semiconductor substrate 14. As shown in Fig. 14, an n + type first contact region 11 is provided on the upper part of the epitaxial growth layer 16. As shown in Fig. 15, the epitaxial growth layer 16 constitutes the drift region of the first level conversion element 10a. The epitaxial growth layer 16 has a circular planar pattern similar to the drift region 2 shown in Fig. 11. The slit region 12 is provided so as to penetrate the epitaxial growth layer 16 in the depth direction. The bottom of the slit region 12 is in contact with the semiconductor substrate 14. The slit region 12 may be provided so as to penetrate the central well region 3 in the depth direction. 3 and 4, the first contact region 11, the first drain region 7a, and the second drain region 7b may be provided above the central well region 3. Other configurations of the semiconductor integrated circuit according to the second modification are similar to those of the semiconductor integrated circuit according to the embodiment, and therefore repeated explanations will be omitted.

第２変形例に係る半導体集積回路によれば、実施形態に係る半導体集積回路と同様に、ダイオード形成領域３１における環状ウェル領域５と埋込層１３との第１距離Ｌ１１を、第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂの形成領域における環状ウェル領域５と埋込層１３との第２距離Ｌ１２よりも短くすることにより、第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂの電界を緩和して、半導体集積回路全体のＥＳＤ耐量を向上させることができる。 In the semiconductor integrated circuit of the second modification, as in the semiconductor integrated circuit of the embodiment, the first distance L11 between the annular well region 5 and the buried layer 13 in the diode formation region 31 is made shorter than the second distance L12 between the annular well region 5 and the buried layer 13 in the formation regions of the first level conversion element 10a and the second level conversion element 10b, thereby mitigating the electric field of the first level conversion element 10a and the second level conversion element 10b, thereby improving the ESD tolerance of the entire semiconductor integrated circuit.

（第３変形例）
図１６及び図１７は、実施形態の第３変形例に係る半導体集積回路の断面図を示す。図１６は、図１４に示した第２変形例に係る半導体集積回路のダイオード形成領域３１を含む断面図に対応し、図１７は、図１５に示した第２変形例に係る半導体集積回路の第１レベル変換素子１０ａを含む断面図に対応する。 (Third Modification)
16 and 17 are cross-sectional views of a semiconductor integrated circuit according to a third modification of the embodiment. Fig. 16 corresponds to the cross-sectional view including the diode formation region 31 of the semiconductor integrated circuit according to the second modification shown in Fig. 14, and Fig. 17 corresponds to the cross-sectional view including the first level conversion element 10a of the semiconductor integrated circuit according to the second modification shown in Fig. 15.

第３変形例に係る半導体集積回路は、図１６及び図１７に示すように、基体１ａが、ｐ型のＳｉからなる半導体基板１４と、半導体基板１４上のｎ型のＳｉからなるエピタキシャル成長層１６とから構成される点では、図１４及び図１５に示した第２変形例に係る半導体集積回路と同様である。しかしながら、ｎ型のエピタキシャル成長層１６の上部に、エピタキシャル成長層１６よりも高不純物濃度のｎ－型の不純物添加領域（拡散領域）１７が更に設けられている点が、第２変形例に係る半導体集積回路と異なる。図１６に示すように、ｎ＋型の第１コンタクト領域１１が、拡散領域１７の上部に設けられている。図１７に示すように、拡散領域１７は、第１レベル変換素子１０ａのドリフト領域を構成する。拡散領域１７は、図１１に示したドリフト領域２と同様の環状の平面パターンを有する。 As shown in Figs. 16 and 17, the semiconductor integrated circuit according to the third modification is similar to the semiconductor integrated circuit according to the second modification shown in Figs. 14 and 15 in that the base 1a is composed of a semiconductor substrate 14 made of p-type Si and an epitaxial growth layer 16 made of n-type Si on the semiconductor substrate 14. However, the semiconductor integrated circuit according to the third modification is different from the semiconductor integrated circuit according to the second modification in that an n - type impurity doped region (diffusion region) 17 having a higher impurity concentration than the epitaxial growth layer 16 is further provided on the upper portion of the n-type epitaxial growth layer 16. As shown in Fig. 16, an n + type first contact region 11 is provided on the upper portion of the diffusion region 17. As shown in Fig. 17, the diffusion region 17 constitutes the drift region of the first level conversion element 10a. The diffusion region 17 has a circular planar pattern similar to that of the drift region 2 shown in Fig. 11.

拡散領域１７は、中央ウェル領域３と接してもよい。この場合、スリット領域１２は、拡散領域１７とエピタキシャル成長層１６とを深さ方向に貫通するように設けられる。また、スリット領域１２は、中央ウェル領域３を深さ方向に貫通するように設けられてもよい。この場合、図３及び図４のように、第１コンタクト領域１１及び第１ドレイン領域７ａ及び第２ドレイン領域７ｂを中央ウェル領域３の上部に設けてもよい。第３変形例に係る半導体集積回路の他の構成は、第２変形例に係る半導体集積回路と同様であるので、重複した説明を省略する。 The diffusion region 17 may be in contact with the central well region 3. In this case, the slit region 12 is provided so as to penetrate the diffusion region 17 and the epitaxial growth layer 16 in the depth direction. The slit region 12 may also be provided so as to penetrate the central well region 3 in the depth direction. In this case, as shown in Figures 3 and 4, the first contact region 11 and the first drain region 7a and second drain region 7b may be provided above the central well region 3. The other configurations of the semiconductor integrated circuit according to the third modification are the same as those of the semiconductor integrated circuit according to the second modification, so duplicated explanations will be omitted.

第３変形例に係る半導体集積回路によれば、実施形態に係る半導体集積回路と同様に、ダイオード形成領域３１における環状ウェル領域５と埋込層１３との第１距離Ｌ１１を、第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂの形成領域における環状ウェル領域５と埋込層１３との第２距離Ｌ１２よりも短くすることにより、第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂの電界を緩和して、半導体集積回路全体のＥＳＤ耐量を向上させることができる。 In the semiconductor integrated circuit of the third modification, as in the semiconductor integrated circuit of the embodiment, the first distance L11 between the annular well region 5 and the buried layer 13 in the diode formation region 31 is made shorter than the second distance L12 between the annular well region 5 and the buried layer 13 in the formation region of the first level conversion element 10a and the second level conversion element 10b, thereby mitigating the electric field of the first level conversion element 10a and the second level conversion element 10b, thereby improving the ESD tolerance of the entire semiconductor integrated circuit.

（第４変形例）
図１８は、図２に示した実施形態に係る半導体集積回路の平面レイアウトに対応する、実施形態の第４変形例に係る半導体集積回路の平面レイアウトを示す。第４変形例に係る半導体集積回路は、図１８に示すように、ｐ型のスリット領域１２ａ，１２ｂが第１レベル変換素子１０ａの第１担体受領領域７ａ及び第２レベル変換素子１０ｂの第２担体受領領域７ｂの周囲をそれぞれ囲むことにより、第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂとハイサイド回路領域１０１とを電気的に分離する方式（分割リサーフ方式）を採用する点が、図２に示した寄生抵抗値調整方式を採用した実施形態に係る半導体集積回路と異なる。 (Fourth Modification)
Fig. 18 shows a planar layout of a semiconductor integrated circuit according to a fourth modified example of the embodiment, which corresponds to the planar layout of the semiconductor integrated circuit according to the embodiment shown in Fig. 2. As shown in Fig. 18, the semiconductor integrated circuit according to the fourth modified example adopts a method (divided RESURF method) in which the first level conversion element 10a and the second level conversion element 10b are electrically isolated from the high-side circuit region 101 by p-type slit regions 12a and 12b surrounding the periphery of the first carrier receiving region 7a of the first level conversion element 10a and the second carrier receiving region 7b of the second level conversion element 10b, respectively, thereby differing from the semiconductor integrated circuit according to the embodiment adopting the parasitic resistance adjustment method shown in Fig. 2.

図１８に示すように、ハイサイド回路領域１０１は、ｎ型の中央ウェル領域３に設けられている。中央ウェル領域３は、直線部と円弧部とからなる略矩形の平面パターンを有する。中央ウェル領域３の周囲の一部には、ｎ＋型の第１コンタクト領域１１ａ，１１ｂが設けられている。第１コンタクト領域１１ａは、中央ウェル領域３の１辺（上辺）に沿って直線状に設けられている。第１コンタクト領域１１ｂは、中央ウェル領域３の上辺に対向する１辺（下辺）に沿って直線状に設けられている。 18, the high-side circuit region 101 is provided in an n-type central well region 3. The central well region 3 has a substantially rectangular planar pattern consisting of straight line portions and arc portions. N + type first contact regions 11a and 11b are provided in a part of the periphery of the central well region 3. The first contact region 11a is provided linearly along one side (upper side) of the central well region 3. The first contact region 11b is provided linearly along one side (lower side) of the central well region 3 that faces the upper side.

中央ウェル領域３の周囲の他の一部には、ｐ型のスリット領域１２ａ，１２ｂが設けられている。スリット領域１２ａ，１２ｂは、中央ウェル領域３の対向する２辺（左辺及び右辺）に、互いに逆向きのＣ字状に設けられている。スリット領域１２ａ，１２ｂは、第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂを囲むように設けられている。スリット領域１２ａ，１２ｂの端部は、環状ウェル領域５に接している。第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂの構成は、図２に示した実施形態に係る半導体集積回路と同様であるので、重複した説明を省略する。 P-type slit regions 12a and 12b are provided in another part of the periphery of the central well region 3. The slit regions 12a and 12b are provided in a C-shape facing in opposite directions on two opposing sides (left and right sides) of the central well region 3. The slit regions 12a and 12b are provided so as to surround the first level conversion element 10a and the second level conversion element 10b. The ends of the slit regions 12a and 12b are in contact with the annular well region 5. The configurations of the first level conversion element 10a and the second level conversion element 10b are the same as those of the semiconductor integrated circuit according to the embodiment shown in FIG. 2, so a duplicated description will be omitted.

ＨＶＪＴ１０２には、中央ウェル領域３の周囲を囲むようにｎ－型のドリフト領域（耐圧領域）２が環状に設けられている。ドリフト領域２の外周側には、ｐ型の環状ウェル領域５が環状に設けられている。環状ウェル領域５の外周側には、ｐ＋型の第２コンタクト領域４が環状に設けられている。図１８の上側では、第１コンタクト領域１１ａと第２コンタクト領域４の一部が対向するダイオード形成領域３１が設けられている。図１８の下側では、第１コンタクト領域１１ｂが第２コンタクト領域４の一部と対向するダイオード形成領域３２が設けられている。 In the HVJT 102, an n - type drift region (breakdown voltage region) 2 is provided in an annular shape so as to surround a central well region 3. A p-type annular well region 5 is provided in an annular shape on the outer periphery of the drift region 2. A p + -type second contact region 4 is provided in an annular shape on the outer periphery of the annular well region 5. In the upper part of FIG. 18, a diode formation region 31 is provided in which the first contact region 11a and a part of the second contact region 4 face each other. In the lower part of FIG. 18, a diode formation region 32 is provided in which the first contact region 11b and a part of the second contact region 4 face each other.

図１８に示したダイオード形成領域３１を含むＡ－Ａ´方向から見た断面は、図３に示した実施形態に係る半導体集積回路の断面図と同様である。図１８に示した第１レベル変換素子１０ａを含むＢ－Ｂ´方向から見た断面は、図４に示した実施形態に係る半導体集積回路の断面図と同様である。 The cross section seen from the A-A' direction including the diode formation region 31 shown in FIG. 18 is similar to the cross section of the semiconductor integrated circuit according to the embodiment shown in FIG. 3. The cross section seen from the B-B' direction including the first level conversion element 10a shown in FIG. 18 is similar to the cross section of the semiconductor integrated circuit according to the embodiment shown in FIG. 4.

図１８では、中央ウェル領域３の下方に設けられたｎ型の埋込層１３ａの平面パターンの位置を破線で模式的に示している。埋込層１３ａは、略矩形の平面パターンを有する。第４変形例に係る半導体集積回路では、ダイオード形成領域３１，３２における環状ウェル領域５と埋込層１３ａとの第１距離Ｌ３１が、第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂの形成領域における環状ウェル領域５と埋込層１３ａとの第２距離Ｌ３２よりもそれぞれ短い。第４変形例に係る半導体集積回路の他の構成は、実施形態に係る半導体集積回路と同様であるので、重複した説明を省略する。 In FIG. 18, the position of the planar pattern of the n-type buried layer 13a provided below the central well region 3 is shown by a dashed line. The buried layer 13a has a substantially rectangular planar pattern. In the semiconductor integrated circuit according to the fourth modification, the first distance L31 between the annular well region 5 and the buried layer 13a in the diode formation regions 31 and 32 is shorter than the second distance L32 between the annular well region 5 and the buried layer 13a in the formation regions of the first level conversion element 10a and the second level conversion element 10b. The other configurations of the semiconductor integrated circuit according to the fourth modification are the same as those of the semiconductor integrated circuit according to the embodiment, so duplicated explanations will be omitted.

第４変形例に係る半導体集積回路によれば、実施形態に係る半導体集積回路と同様に、ダイオード形成領域３１，３２における環状ウェル領域５と埋込層１３ａとの第１距離Ｌ３１を、第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂの形成領域における環状ウェル領域５と埋込層１３ａとの第２距離Ｌ３２よりも短くすることにより、第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂの電界を緩和して、半導体集積回路全体のＥＳＤ耐量を向上させることができる。 In the semiconductor integrated circuit of the fourth modification, as in the semiconductor integrated circuit of the embodiment, the first distance L31 between the annular well region 5 and the buried layer 13a in the diode formation regions 31, 32 is made shorter than the second distance L32 between the annular well region 5 and the buried layer 13a in the formation regions of the first level conversion element 10a and the second level conversion element 10b, thereby mitigating the electric field of the first level conversion element 10a and the second level conversion element 10b, thereby improving the ESD tolerance of the entire semiconductor integrated circuit.

（第５変形例）
図１９は、図１８に示した第４変形例に係る半導体集積回路の平面レイアウトに対応する、実施形態の第５変形例に係る半導体集積回路の平面レイアウトを示す。第５変形例に係る半導体集積回路は、図１９に示すように、ｐ型のスリット領域１２ａ，１２ｂが第１レベル変換素子１０ａの第１担体受領領域７ａ及び第２レベル変換素子１０ｂの第２担体受領領域７ｂの周囲をそれぞれ囲むことにより、第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂとハイサイド回路領域１０１とを電気的に分離する方式（分割リサーフ方式）を採用する点は、図１８に示した第４変形例に係る半導体集積回路と同様である。 (Fifth Modification)
Fig. 19 shows a planar layout of a semiconductor integrated circuit according to a fifth modified example of the embodiment, which corresponds to the planar layout of the semiconductor integrated circuit according to the fourth modified example shown in Fig. 18. As shown in Fig. 19, the semiconductor integrated circuit according to the fifth modified example is similar to the semiconductor integrated circuit according to the fourth modified example shown in Fig. 18 in that it employs a method (divided RESURF method) in which p-type slit regions 12a, 12b surround the periphery of the first carrier receiving region 7a of the first level conversion element 10a and the second carrier receiving region 7b of the second level conversion element 10b, respectively, to electrically isolate the first level conversion element 10a and the second level conversion element 10b from the high-side circuit region 101.

しかしながら、第５変形例に係る半導体集積回路は、図１９に示すように、ｎ型の中央ウェル領域３の４隅に、ｎ＋型の第１コンタクト領域１１ｃ，１１ｄ，１１ｅ，１１ｆが更に設けられている点が、図１８に示した第４変形例に係る半導体集積回路と異なる。第１コンタクト領域１１ｄ，１１ｆは、第１レベル変換素子１０ａと同じ中央ウェル領域３の右辺側に設けられている。第１コンタクト領域１１ｃ，１１ｅは、第２レベル変換素子１０ｂと同じ中央ウェル領域３の左辺側に設けられている。第１コンタクト領域１１ｃ～１１ｆは、環状のｐ＋型の第２コンタクト領域４の一部とそれぞれ対向し、ダイオード形成領域３３，３４，３５，３６をそれぞれ構成している。 However, the semiconductor integrated circuit according to the fifth modification is different from the semiconductor integrated circuit according to the fourth modification shown in FIG. 18 in that, as shown in FIG. 19, n + type first contact regions 11c, 11d, 11e, and 11f are further provided at the four corners of the n-type central well region 3. The first contact regions 11d and 11f are provided on the right side of the central well region 3, which is the same as the first level conversion element 10a. The first contact regions 11c and 11e are provided on the left side of the central well region 3, which is the same as the second level conversion element 10b. The first contact regions 11c to 11f each face a part of the annular p + type second contact region 4, and constitute diode formation regions 33, 34, 35, and 36, respectively.

なお、第１コンタクト領域１１ｃ～１１ｆは、例えば略矩形状又は直線状の平面パターンを有するが、第１コンタクト領域１１ｃ～１１ｆの平面パターンはこれに限定されない。また、第１コンタクト領域１１ｃ，１１ｄと第１コンタクト領域１１ａとを接続し、一体の第１コンタクト領域としてもよい。また、第１コンタクト領域１１ｅ，１１ｆと第１コンタクト領域１１ｂとを接続し、一体の第１コンタクト領域としてもよい。 The first contact regions 11c to 11f have, for example, a substantially rectangular or linear planar pattern, but the planar pattern of the first contact regions 11c to 11f is not limited to this. The first contact regions 11c and 11d may be connected to the first contact region 11a to form an integrated first contact region. The first contact regions 11e and 11f may be connected to the first contact region 11b to form an integrated first contact region.

更に、第５変形例に係る半導体集積回路は、図１９に破線で模式的に示すように、埋込層１３ａの平面パターンが、矩形パターンの左辺及び右辺の中央部を内側に窪ませた形状である点が、図１８に示した第４変形例に係る半導体集積回路と異なる。埋込層１３ａは、第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂの形成領域に近づくにつれてｐ型の環状ウェル領域５から離れるように内側に窪んでいき、第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂの形成領域において最も環状ウェル領域５から離れるように設けられている。 Furthermore, the semiconductor integrated circuit according to the fifth modification differs from the semiconductor integrated circuit according to the fourth modification shown in FIG. 18 in that the planar pattern of the buried layer 13a has a shape in which the central portions of the left and right sides of the rectangular pattern are recessed inward, as shown typically by the dashed lines in FIG. 19. The buried layer 13a recesses inward away from the p-type annular well region 5 as it approaches the formation region of the first level conversion element 10a and the second level conversion element 10b, and is provided so as to be furthest from the annular well region 5 in the formation region of the first level conversion element 10a and the second level conversion element 10b.

第５変形例に係る半導体集積回路では、ダイオード形成領域３１～３６における環状ウェル領域５と埋込層１３ａとの第１距離Ｌ３１が、第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂの形成領域における環状ウェル領域５と埋込層１３ａとの第２距離Ｌ３２よりもそれぞれ短い。即ち、埋込層１３ａの矩形パターンの一部を内側に窪ませる（後退させる）ことにより、第２距離Ｌ３２とした第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂの形成領域の近傍に、第１距離Ｌ３１としたダイオード形成領域３３～３６を設けることができる。第５変形例に係る半導体集積回路の他の構成は、第４変形例に係る半導体集積回路と同様であるので、重複した説明を省略する。 In the semiconductor integrated circuit according to the fifth modification, the first distance L31 between the annular well region 5 and the buried layer 13a in the diode formation regions 31-36 is shorter than the second distance L32 between the annular well region 5 and the buried layer 13a in the formation regions of the first level conversion element 10a and the second level conversion element 10b. That is, by recessing (retreating) a part of the rectangular pattern of the buried layer 13a inward, the diode formation regions 33-36 with the first distance L31 can be provided near the formation regions of the first level conversion element 10a and the second level conversion element 10b with the second distance L32. The other configurations of the semiconductor integrated circuit according to the fifth modification are the same as those of the semiconductor integrated circuit according to the fourth modification, so a duplicated description will be omitted.

第５変形例に係る半導体集積回路によれば、実施形態に係る半導体集積回路と同様に、ダイオード形成領域３１における環状ウェル領域５と埋込層１３との第１距離Ｌ３１を、第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂの形成領域における環状ウェル領域５と埋込層１３との第２距離Ｌ３２よりも短くすることにより、第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂの電界を緩和して、半導体集積回路全体のＥＳＤ耐量を向上させることができる。 In the semiconductor integrated circuit of the fifth modification, as in the semiconductor integrated circuit of the embodiment, the first distance L31 between the annular well region 5 and the buried layer 13 in the diode formation region 31 is made shorter than the second distance L32 between the annular well region 5 and the buried layer 13 in the formation region of the first level conversion element 10a and the second level conversion element 10b, thereby mitigating the electric field of the first level conversion element 10a and the second level conversion element 10b, thereby improving the ESD tolerance of the entire semiconductor integrated circuit.

更に、埋込層１３ａを、第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂの形成領域に近づくにつれてｐ型の環状ウェル領域５から徐々に離れるように設けることにより、局所的な電界の集中を防止することができる。更に、第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂの形成領域の近傍に、環状ウェル領域５と埋込層１３との距離を第１距離Ｌ３１としたダイオード形成領域３３～３６を形成し易くなる。 Furthermore, by providing the buried layer 13a so that it gradually moves away from the p-type annular well region 5 as it approaches the formation region of the first level conversion element 10a and the second level conversion element 10b, localized concentration of an electric field can be prevented. Furthermore, it becomes easier to form the diode formation regions 33 to 36, in which the distance between the annular well region 5 and the buried layer 13 is the first distance L31, near the formation region of the first level conversion element 10a and the second level conversion element 10b.

（第６変形例）
図２０は、図１８に示した第４変形例に係る半導体集積回路の平面レイアウトに対応する、実施形態の第６変形例に係る半導体集積回路の平面レイアウトを示す。図２１は、図２０の上側に示す、第２コンタクト領域４と第１コンタクト領域１１が対向する領域（ダイオード形成領域）３１を含むＡ－Ａ´方向から見た断面図を示す。図２２は、図２０に示した第１レベル変換素子１０ａを含むＢ－Ｂ´方向から見た断面図を示す。第６変形例に係る半導体集積回路は、図２０に示すように、ｐ型のスリット領域１２ａ，１２ｂにより、第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂとハイサイド回路領域１０１とを電気的に分離する方式（分割リサーフ方式）を採用する点は、図１８に示した第４変形例に係る半導体集積回路と同様である。 (Sixth Modification)
20 shows a planar layout of a semiconductor integrated circuit according to a sixth modification of the embodiment, which corresponds to the planar layout of the semiconductor integrated circuit according to the fourth modification shown in FIG. 18. FIG. 21 shows a cross-sectional view seen from the A-A' direction including a region (diode forming region) 31 where the second contact region 4 and the first contact region 11 face each other, shown in the upper part of FIG. 20. FIG. 22 shows a cross-sectional view seen from the B-B' direction including the first level conversion element 10a shown in FIG. 20. As shown in FIG. 20, the semiconductor integrated circuit according to the sixth modification is similar to the semiconductor integrated circuit according to the fourth modification shown in FIG. 18 in that it employs a method (division resurf method) in which the first level conversion element 10a and the second level conversion element 10b are electrically isolated from the high-side circuit region 101 by p-type slit regions 12a and 12b.

しかしながら、第６変形例に係る半導体集積回路は、図２１に示すように、環状ウェル領域５はその内側に浅い領域５ｃを備える点が、図１８に示した第４変形例に係る半導体集積回路と異なる。浅い領域５ｃの上部にｐ＋型の第２コンタクト領域４が設けられている。 However, the semiconductor integrated circuit according to the sixth modification is different from the semiconductor integrated circuit according to the fourth modification shown in Fig. 18 in that the annular well region 5 has a shallow region 5c therein as shown in Fig. 21. A p + type second contact region 4 is provided on the shallow region 5c.

また、図２０及び図２２に示すように、第１レベル変換素子１０ａの形成領域において、環状ウェル領域５よりも内側に環状ウェル領域５と離れて形成されたｐ型のベース領域５ａを備える点が、図１８に示した第４変形例に係る半導体集積回路と異なる。ベース領域５ａの不純物濃度は、環状ウェル領域５の不純物濃度と同一であってよく、或いは環状ウェル領域５の不純物濃度より高くてもよい。ベース領域５ａの上部に、ｎ＋型の第１担体供給領域８ａ及びｎ＋型のコンタクト領域４ａが互いに接するように設けられている。コンタクト領域４ａの不純物濃度は、第２コンタクト領域４の不純物濃度と同一であってよい。アノード電極２３と担体供給電極２６は分離されており、担体供給電極２６は、抵抗素子を介して接地電位端子ＧＮＤに電気的に接続される。 20 and 22, the semiconductor integrated circuit according to the fourth modification shown in FIG. 18 is different in that the semiconductor integrated circuit according to the fourth modification includes a p-type base region 5a formed on the inside of the annular well region 5 and separated from the annular well region 5 in the formation region of the first level conversion element 10a. The impurity concentration of the base region 5a may be the same as the impurity concentration of the annular well region 5, or may be higher than the impurity concentration of the annular well region 5. An n + type first carrier supply region 8a and an n + type contact region 4a are provided on the upper part of the base region 5a so as to be in contact with each other. The impurity concentration of the contact region 4a may be the same as the impurity concentration of the second contact region 4. The anode electrode 23 and the carrier supply electrode 26 are separated, and the carrier supply electrode 26 is electrically connected to the ground potential terminal GND via a resistance element.

図２０に示した第２レベル変換素子１０ｂも、第１レベル変換素子１０ａと鏡像関係で同様の構成を有する。第２レベル変換素子１０ｂは、環状ウェル領域５よりも内側に環状ウェル領域５と離れて形成されたｐ型のベース領域５ｂを備える。ベース領域５ｂの上部に、ｎ＋型の第２担体供給領域８ｂ及びｎ＋型のコンタクト領域４ｂが互いに接するように設けられている。 20 has a similar configuration to the first level conversion element 10a in a mirror image relationship. The second level conversion element 10b includes a p-type base region 5b formed on the inside of the annular well region 5 and separated from the annular well region 5. An n + type second carrier supply region 8b and an n + type contact region 4b are provided on the upper portion of the base region 5b so as to be in contact with each other.

このような構成の場合、ダイオード形成領域３１における第１距離Ｌ４１は、浅い領域５ｃと埋込層１３との距離であり、第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂの形成領域における第２距離Ｌ４２は、ベース領域５ａ，５ｂと埋込層１３との距離である。第１距離Ｌ４１は、第２距離Ｌ４２より短い。第６変形例に係る半導体集積回路の他の構成は、第４変形例に係る半導体集積回路と同様であるので、重複した説明を省略する。 In this configuration, the first distance L41 in the diode formation region 31 is the distance between the shallow region 5c and the buried layer 13, and the second distance L42 in the formation region of the first level conversion element 10a and the second level conversion element 10b is the distance between the base regions 5a, 5b and the buried layer 13. The first distance L41 is shorter than the second distance L42. The other configurations of the semiconductor integrated circuit according to the sixth modification are the same as those of the semiconductor integrated circuit according to the fourth modification, so duplicated explanations will be omitted.

第６変形例に係る半導体集積回路によれば、実施形態に係る半導体集積回路と同様に、ダイオード形成領域３１における第１距離Ｌ４１を、第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂの形成領域における第２距離Ｌ４２よりも短くすることにより、第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂの電界を緩和して、半導体集積回路全体のＥＳＤ耐量を向上させることができる。 In the semiconductor integrated circuit of the sixth modification, as in the semiconductor integrated circuit of the embodiment, the first distance L41 in the diode formation region 31 is made shorter than the second distance L42 in the formation regions of the first level conversion element 10a and the second level conversion element 10b, thereby mitigating the electric field of the first level conversion element 10a and the second level conversion element 10b, thereby improving the ESD tolerance of the entire semiconductor integrated circuit.

第６変形例に係る半導体集積回路では、環状ウェル領域５とベース領域５ａ，５ｂとは離れて形成されているが、ベース領域５ａ，５ｂを環状ウェル領域５と接続して浅いベース領域を備えた環状ウェル領域５としてもよい。この場合、アノード電極２３と担体供給電極２６は共通の電極となり、接地電位端子ＧＮＤに電気的に接続される。 In the semiconductor integrated circuit according to the sixth modification, the annular well region 5 and the base regions 5a and 5b are formed separately, but the base regions 5a and 5b may be connected to the annular well region 5 to form an annular well region 5 with a shallow base region. In this case, the anode electrode 23 and the carrier supply electrode 26 become a common electrode and are electrically connected to the ground potential terminal GND.

また、第６変形例に係る半導体集積回路では、分割リサーフ方式について説明したが、上記した寄生抵抗値調整方式にも適用できる。 In addition, in the semiconductor integrated circuit according to the sixth modification, the divided RESURF method has been described, but it can also be applied to the parasitic resistance adjustment method described above.

（第７変形例）
図２３は、図２に示した実施形態に係る半導体集積回路の平面レイアウトに対応する、実施形態の第７変形例に係る半導体集積回路の平面レイアウトを示す。ハイサイド回路領域１０１は、ｎ型の中央ウェル領域３に設けられている。中央ウェル領域３は、略矩形の平面パターンを有する。ＨＶＪＴ１０２には、中央ウェル領域３の周囲を囲むようにｎ－型のドリフト領域（耐圧領域）２が環状（枠状）に設けられている。ドリフト領域２の外周側には、ｐ型の環状ウェル領域５が環状に設けられている。 (Seventh Modification)
23 shows a planar layout of a semiconductor integrated circuit according to a seventh modification of the embodiment, which corresponds to the planar layout of the semiconductor integrated circuit according to the embodiment shown in FIG. 2. The high side circuit region 101 is provided in an n-type central well region 3. The central well region 3 has a substantially rectangular planar pattern. In the HVJT 102, an n - type drift region (voltage-resistant region) 2 is provided in an annular (frame-shaped) shape so as to surround the periphery of the central well region 3. A p-type annular well region 5 is provided in an annular shape on the outer periphery of the drift region 2.

図２３では、中央ウェル領域３の下方に設けられたｎ型の埋込層１３の平面パターンの位置を破線で模式的に示している。この破線は、ハイサイド回路領域１０１の平面パターンの外周と一致する。埋込層１３は、略矩形の平面パターンを有する。ダイオード形成領域３１における環状ウェル領域５と埋込層１３との第１距離Ｌ１１は、第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂの形成領域における環状ウェル領域５と埋込層１３との第２距離Ｌ１２よりもそれぞれ短い。 23, the position of the planar pattern of the n-type buried layer 13 provided below the central well region 3 is shown by a dashed line. This dashed line coincides with the outer periphery of the planar pattern of the high side circuit region 101. The buried layer 13 has a substantially rectangular planar pattern. The first distance L11 between the annular well region 5 and the buried layer 13 in the diode formation region 31 is shorter than the second distance L12 between the annular well region 5 and the buried layer 13 in the formation regions of the first level conversion element 10a and the second level conversion element 10b.

平面パターン上、埋込層１３の略矩形の４つの角部の曲率半径Ｒは、中央ウェル領域３の略矩形の角部の曲率半径ｒ１よりも大きいことが望ましい。また、例えば、ダイオード形成領域の耐圧が８２５Ｖの場合、埋込層１３の略矩形の４つの角部の曲率半径Ｒは、８０μｍ以上程度であることが好ましく、中央ウェル領域３の曲率半径ｒ１は、例えば５０μｍ～６０μｍ程度が望ましい。埋込層１３の曲率半径Ｒが中央ウェル領域３の曲率半径ｒ１よりも小さい場合には、埋込層１３の角部で電界が集中するため、ダイオード形成領域３１でアバランシェ電流が流れる前に、埋込層１３の角部でアバランシェ電流が流れる。そこで、埋込層１３の曲率半径Ｒを中央ウェル領域３の曲率半径ｒ１よりも大きくすることで、埋込層１３の角部における電界を緩和することができ、埋込層１３の角部における耐圧を、ダイオード形成領域３１における耐圧よりも高くすることができる。 In terms of the planar pattern, it is desirable that the radius of curvature R of the four corners of the approximately rectangular shape of the buried layer 13 is larger than the radius of curvature r1 of the approximately rectangular corners of the central well region 3. Also, for example, when the breakdown voltage of the diode formation region is 825 V, it is desirable that the radius of curvature R of the four corners of the approximately rectangular shape of the buried layer 13 is approximately 80 μm or more, and the radius of curvature r1 of the central well region 3 is, for example, approximately 50 μm to 60 μm. When the radius of curvature R of the buried layer 13 is smaller than the radius of curvature r1 of the central well region 3, an electric field is concentrated at the corners of the buried layer 13, so that an avalanche current flows at the corners of the buried layer 13 before an avalanche current flows in the diode formation region 31. Therefore, by making the radius of curvature R of the buried layer 13 larger than the radius of curvature r1 of the central well region 3, the electric field at the corners of the buried layer 13 can be alleviated, and the breakdown voltage at the corners of the buried layer 13 can be made higher than the breakdown voltage in the diode formation region 31.

図２３に示したダイオード形成領域３１を含むＡ－Ａ´方向から見た断面は、図３に示した実施形態に係る半導体集積回路の断面図と同様である。図２３に示した第１レベル変換素子１０ａを含むＢ－Ｂ´方向から見た断面は、図４に示した実施形態に係る半導体集積回路の断面図と同様である。第７変形例に係る半導体集積回路の他の構成は、実施形態に係る半導体集積回路と同様であるので、重複した説明を省略する。 The cross section seen from the A-A' direction including the diode formation region 31 shown in FIG. 23 is similar to the cross section of the semiconductor integrated circuit according to the embodiment shown in FIG. 3. The cross section seen from the B-B' direction including the first level conversion element 10a shown in FIG. 23 is similar to the cross section of the semiconductor integrated circuit according to the embodiment shown in FIG. 4. Other configurations of the semiconductor integrated circuit according to the seventh modification example are similar to those of the semiconductor integrated circuit according to the embodiment, so duplicated explanations will be omitted.

図２４は、埋込層１３の曲率半径Ｒと耐圧の関係を示すグラフである。図２４では、半導体集積回路の定格電圧が６００Ｖの場合について示している。図１に示した回路図の端子ＶＳに印加されるサージ電圧によって、半導体集積回路の耐圧が設定され、８２０Ｖに設定されている。埋込層１３の曲率半径Ｒが大きいほど、埋込層１３の角部での電界が緩和するため、耐圧が大きくなっている。このため、要求される耐圧が高いほど、埋込層１３の曲率半径Ｒを大きくすることが好ましい。図２４中に破線で示すように、ダイオード形成領域３１の耐圧が８２５Ｖである場合、埋込層１３の曲率半径Ｒを８０μｍ以上とすることにより、埋込層１３の耐圧がダイオード形成領域３１の耐圧よりも大きくなる。 24 is a graph showing the relationship between the radius of curvature R of the buried layer 13 and the breakdown voltage. FIG. 24 shows the case where the rated voltage of the semiconductor integrated circuit is 600 V. The breakdown voltage of the semiconductor integrated circuit is set by the surge voltage applied to the terminal VS of the circuit diagram shown in FIG. 1, and is set to 820 V. The larger the radius of curvature R of the buried layer 13, the greater the breakdown voltage because the electric field at the corners of the buried layer 13 is relaxed. For this reason, it is preferable to increase the radius of curvature R of the buried layer 13 as the required breakdown voltage increases. As shown by the dashed line in FIG. 24, when the breakdown voltage of the diode formation region 31 is 825 V, the breakdown voltage of the buried layer 13 is greater than the breakdown voltage of the diode formation region 31 by setting the radius of curvature R of the buried layer 13 to 80 μm or more.

図２５は、図２３に示した第７変形例に係る半導体集積回路の平面レイアウトと同様の平面レイアウトであるが、埋込層１３の略矩形の角部の曲率半径Ｒと、ドリフト領域２の外側の角部の曲率半径ｒ２を模式的に示している。平面パターン上、埋込層１３の曲率半径Ｒは、ドリフト領域２の曲率半径ｒ２よりも大きくてもよい。ドリフト領域２の曲率半径ｒ２は、図２３に示した中央ウェル領域３の曲率半径ｒ１よりも大きく、例えば１００μｍ程度である。 Figure 25 is a planar layout similar to that of the semiconductor integrated circuit according to the seventh modification shown in Figure 23, but it also shows the radius of curvature R of the substantially rectangular corners of the buried layer 13 and the radius of curvature r2 of the outer corners of the drift region 2. In terms of the planar pattern, the radius of curvature R of the buried layer 13 may be larger than the radius of curvature r2 of the drift region 2. The radius of curvature r2 of the drift region 2 is larger than the radius of curvature r1 of the central well region 3 shown in Figure 23, and is, for example, about 100 μm.

第７変形例に係る半導体集積回路によれば、実施形態に係る半導体集積回路と同様に、ダイオード形成領域３１における環状ウェル領域５と埋込層１３との第１距離Ｌ１１を、第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂの形成領域における環状ウェル領域５と埋込層１３との第２距離Ｌ１２よりも短くすることにより、第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂの電界を緩和して、半導体集積回路全体のＥＳＤ耐量を向上させることができる。 In the semiconductor integrated circuit of the seventh modification, as in the semiconductor integrated circuit of the embodiment, the first distance L11 between the annular well region 5 and the buried layer 13 in the diode formation region 31 is made shorter than the second distance L12 between the annular well region 5 and the buried layer 13 in the formation region of the first level conversion element 10a and the second level conversion element 10b, thereby mitigating the electric field of the first level conversion element 10a and the second level conversion element 10b, thereby improving the ESD tolerance of the entire semiconductor integrated circuit.

更に、ダイオード形成領域３１における耐圧が高くても、埋込層１３の曲率半径Ｒを中央ウェル領域３の曲率半径ｒ１よりも大きくし、埋込層１３の曲率半径Ｒを８０μｍ以上とすることで、埋込層１３の角部における電界を緩和することができる。これにより、埋込層１３の角部における耐圧を、ダイオード形成領域３１における耐圧よりも高くすることができる。なお、第７変形例に係る半導体集積回路として、寄生抵抗値調整方式を採用した構造を例示したが、分割リサーフ方式を採用した構造にも適用可能である。 Furthermore, even if the breakdown voltage in the diode formation region 31 is high, the electric field at the corners of the buried layer 13 can be alleviated by making the radius of curvature R of the buried layer 13 larger than the radius of curvature r1 of the central well region 3 and making the radius of curvature R of the buried layer 13 80 μm or more. This makes it possible to make the breakdown voltage at the corners of the buried layer 13 higher than the breakdown voltage in the diode formation region 31. Note that although a structure employing a parasitic resistance adjustment method has been exemplified as the semiconductor integrated circuit according to the seventh modification, it is also applicable to a structure employing a divided RESURF method.

（第８変形例）
図２６は、図１１に示した第１変形例に係る半導体集積回路の平面レイアウトに対応する、実施形態の第８変形例に係る半導体集積回路の平面レイアウトを示す。図２６に示したダイオード形成領域３１を含むＡ－Ａ´方向から見た断面を図２７に示し、図２６に示した第１レベル変換素子１０ａを含むＢ－Ｂ´方向から見た断面を図２８に示す。 (Eighth Modification)
Fig. 26 shows a planar layout of a semiconductor integrated circuit according to an eighth modified example of the embodiment, which corresponds to the planar layout of the semiconductor integrated circuit according to the first modified example shown in Fig. 11. Fig. 27 shows a cross section seen from the A-A' direction including the diode formation region 31 shown in Fig. 26, and Fig. 28 shows a cross section seen from the B-B' direction including the first level conversion element 10a shown in Fig. 26.

図２６～図２８に示すように、第８変形例に係る半導体集積回路は、ハイサイド回路領域１０１にｎ型の中央ウェル領域３に設けられていない点が、図１１に示した第１変形例に係る半導体集積回路と異なる。更に、第８変形例に係る半導体集積回路は、ドリフト領域１６がｎ型のエピタキシャル成長層である点が、図１１に示した第１変形例に係る半導体集積回路と異なる。ドリフト領域１６と環状ウェル領域５とのｐｎ接合部の表面露出部（ＨＶＪＴ１０２の外周）の平面レイアウトは、略矩形の平面パターンを有する。これをドリフト領域１６の平面パターンとする。なお、ドリフト領域１６はｎ型のエピタキシャル成長層に限定されず、例えば実施形態に係る半導体集積回路と同様に、ｐ型のエピタキシャル成長層に形成したｎ－型の拡散領域であってもよい。 As shown in FIGS. 26 to 28, the semiconductor integrated circuit according to the eighth modification is different from the semiconductor integrated circuit according to the first modification shown in FIG. 11 in that the n-type central well region 3 is not provided in the high side circuit region 101. Furthermore, the semiconductor integrated circuit according to the eighth modification is different from the semiconductor integrated circuit according to the first modification shown in FIG. 11 in that the drift region 16 is an n-type epitaxial growth layer. The planar layout of the surface exposed portion (outer periphery of the HVJT 102) of the pn junction between the drift region 16 and the annular well region 5 has a substantially rectangular planar pattern. This is the planar pattern of the drift region 16. Note that the drift region 16 is not limited to an n-type epitaxial growth layer, and may be, for example, an n - type diffusion region formed in a p-type epitaxial growth layer, as in the semiconductor integrated circuit according to the embodiment.

更に、第８変形例に係る半導体集積回路は、ドリフト領域１６の上部にｎ型のバッファ層１８が環状（枠状）に設けられている点が、図１１に示した第１変形例に係る半導体集積回路と異なる。バッファ層１８の上部に、ｎ＋型のコンタクト領域１１１が環状（枠状）に設けられている。バッファ層１８は必要に応じて設ければよく、設けなくてもよい。 11 in that an n-type buffer layer 18 is provided in a ring shape (frame shape) on the upper part of the drift region 16. An n + -type contact region 111 is provided in a ring shape (frame shape) on the upper part of the buffer layer 18. The buffer layer 18 may be provided as necessary, or may not be provided.

図２６に示すように、平面パターン上、埋込層１３の曲率半径Ｒは、ドリフト領域１６の略矩形の角部の曲率半径ｒ２よりも大きいことが望ましい。ドリフト領域１６の曲率半径ｒ２は、例えば１００μｍ程度である。第８変形例に係る半導体集積回路の他の構成は、第１変形例に係る半導体集積回路と同様であるので、重複した説明を省略する。 26, in the planar pattern, it is desirable that the radius of curvature R of the buried layer 13 is larger than the radius of curvature r2 of the corner of the approximately rectangular drift region 16. The radius of curvature r2 of the drift region 16 is, for example, about 100 μm. The other configurations of the semiconductor integrated circuit according to the eighth modification are the same as those of the semiconductor integrated circuit according to the first modification, so duplicated explanations will be omitted.

第８変形例に係る半導体集積回路によれば、実施形態に係る半導体集積回路と同様に、ダイオード形成領域３１における環状ウェル領域５と埋込層１３との第１距離Ｌ１１を、第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂの形成領域における環状ウェル領域５と埋込層１３との第２距離Ｌ１２よりも短くすることにより、第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂの電界を緩和して、半導体集積回路全体のＥＳＤ耐量を向上させることができる。 In the semiconductor integrated circuit of the eighth modification, as in the semiconductor integrated circuit of the embodiment, the first distance L11 between the annular well region 5 and the buried layer 13 in the diode formation region 31 is made shorter than the second distance L12 between the annular well region 5 and the buried layer 13 in the formation region of the first level conversion element 10a and the second level conversion element 10b, thereby mitigating the electric field of the first level conversion element 10a and the second level conversion element 10b, thereby improving the ESD tolerance of the entire semiconductor integrated circuit.

更に、ダイオード形成領域３１における耐圧が高くても、埋込層１３の曲率半径Ｒをドリフト領域１６の略矩形の角部の曲率半径ｒ２よりも大きくすることで、埋込層１３の角部における電界を緩和することができる。これにより、埋込層１３の角部における耐圧を、ダイオード形成領域３１における耐圧よりも高くすることができる。なお、第８変形例に係る半導体集積回路として、寄生抵抗値調整方式を採用した構造を例示したが、分割リサーフ方式を採用した構造にも適用可能である。 Furthermore, even if the breakdown voltage in the diode formation region 31 is high, the electric field at the corners of the buried layer 13 can be alleviated by making the radius of curvature R of the buried layer 13 larger than the radius of curvature r2 of the approximately rectangular corners of the drift region 16. This makes it possible to make the breakdown voltage at the corners of the buried layer 13 higher than the breakdown voltage in the diode formation region 31. Note that although a structure employing a parasitic resistance adjustment method has been exemplified as the semiconductor integrated circuit according to the eighth modification, it is also applicable to a structure employing a divided RESURF method.

（その他の実施形態）
上記のように、本発明は実施形態によって記載したが、この開示の一部をなす論述及び図面は本発明を限定するものであると理解すべきではない。この開示から当業者には様々な代替実施形態、実施例及び運用技術が明らかとなろう。 Other Embodiments
As described above, the present invention has been described by the embodiment, but the description and drawings forming a part of this disclosure should not be understood as limiting the present invention. Various alternative embodiments, examples and operating techniques will become apparent to those skilled in the art from this disclosure.

例えば、実施形態においては、第１レベル変換素子１０ａと第２レベル変換素子１０ｂの２つの能動素子を有する場合を主に例示的に示したが、レベルシフタを構成する能動素子の数は少なくとも１個あればよく、３つでも、５つ以上でも構わない。 For example, in the embodiment, the case having two active elements, the first level conversion element 10a and the second level conversion element 10b, is mainly shown as an example, but the number of active elements constituting the level shifter needs to be at least one, and may be three, five or more.

また、実施形態においては、基体１としてＳｉ基板を用いた半導体集積回路を例示したが、実施形態で説明した技術的思想は、ガリウムヒ素（ＧａＡｓ）等の化合物半導体を用いた半導体集積回路にも適用可能である。更に、実施形態で説明した技術的思想は、ＳｉＣ、窒化ガリウム（ＧａＮ）又はダイヤモンド等のワイドバンドギャップ半導体を用いた半導体集積回路にも適用可能である。更に、インジウムアンチモン（ＩｎＳｂ）等のナローギャップ半導体や半金属等を用いた半導体集積回路にも適用可能である。 In the embodiment, a semiconductor integrated circuit using a Si substrate as the base 1 is exemplified, but the technical ideas described in the embodiment are also applicable to semiconductor integrated circuits using compound semiconductors such as gallium arsenide (GaAs). Furthermore, the technical ideas described in the embodiment are also applicable to semiconductor integrated circuits using wide band gap semiconductors such as SiC, gallium nitride (GaN) or diamond. Furthermore, they are also applicable to semiconductor integrated circuits using narrow gap semiconductors such as indium antimony (InSb) and semimetals.

また、第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂとハイサイド回路領域１０１の内部回路のスリット領域１２の形成方法は、寄生抵抗値調整方式及び分割リサーフ方式のいずれの方式を採用してもよい。例えば、図１８に示したｐ型のスリット領域１２ａ，１２ｂの代わりに、絶縁膜等を充填したトレンチにより、第１レベル変換素子１０ａ及び第２レベル変換素子１０ｂとハイサイド回路領域１０１の内部回路とを分離した構造であってもよい。 The method of forming the slit region 12 of the first level conversion element 10a, the second level conversion element 10b, and the internal circuit of the high side circuit region 101 may be either the parasitic resistance adjustment method or the divided resurf method. For example, instead of the p-type slit regions 12a and 12b shown in FIG. 18, a structure in which the first level conversion element 10a, the second level conversion element 10b, and the internal circuit of the high side circuit region 101 are separated by a trench filled with an insulating film or the like may be used.

このように、上記実施形態が開示する技術内容の趣旨を理解すれば、当業者には様々な代替実施形態、実施例及び運用技術が本発明に含まれ得ることが明らかとなろう。また、上記の実施形態及び各変形例において説明される各構成を任意に応用した構成等、本発明はここでは記載していない様々な実施形態等を含むことは勿論である。したがって、本発明の技術的範囲は上記の例示的説明から妥当な、特許請求の範囲に係る発明特定事項によってのみ定められるものである。 In this way, if one of ordinary skill in the art understands the gist of the technical content disclosed in the above embodiment, it will be clear that various alternative embodiments, examples, and operational techniques can be included in the present invention. Furthermore, the present invention naturally includes various embodiments not described here, such as configurations that arbitrarily apply each configuration described in the above embodiment and each modified example. Therefore, the technical scope of the present invention is determined only by the invention-specific matters related to the claims that are appropriate from the above exemplary explanation.

１，１ａ…基体
２…ドリフト領域
３…中央ウェル領域
４，４ａ，４ｂ，１１，１１ａ，１１ｂ，１１ｃ，１１ｄ，１１ｅ，１１ｆ，１１１…コンタクト領域
５…環状ウェル領域
５ａ，５ｂ…ベース領域
７ａ，７ｂ…担体受領領域
８ａ，８ｂ…担体供給領域
９ａ，９ｂ…ゲート電極
１０ａ，１０ｂ…第１レベル変換素子
１２，１２ａ，１２ｂ…スリット領域
１３，１３ａ…埋込層
１４…半導体基板
１５，１６…エピタキシャル成長層
１７…拡散領域
２０…ゲート絶縁膜
２１…フィールド絶縁膜
２２…層間絶縁膜
２３…アノード電極
２４…カソード電極
２５…保護膜
２６…ソース電極
２７…ドレイン電極
３１，３２，３３，３４，３５，３６…ダイオード形成領域
４１…ローサイド回路
４２…レベルシフト回路
４３…ハイサイド回路
４５…ｐＭＯＳトランジスタ
４６…ｎＭＯＳトランジスタ
５０…半導体集積回路
６０…電力変換部
６１…接続点
６５…ブートストラップダイオード
６６…ブートストラップコンデンサ
６７…負荷
６８…レベルシフト抵抗
６９…レベルシフタ
７０…保護ダイオード
１０１…ハイサイド回路領域
１０２…ＨＶＪＴ
１０３…ローサイド回路領域 1, 1a... Substrate 2... Drift region 3... Central well region 4, 4a, 4b, 11, 11a, 11b, 11c, 11d, 11e, 11f, 111... Contact region 5... Annular well region 5a, 5b... Base region 7a, 7b... Carrier receiving region 8a, 8b... Carrier supply region 9a, 9b... Gate electrode 10a, 10b... First level conversion element 12, 12a, 12b... Slit region 13, 13a... Buried layer 14... Semiconductor substrate 15, 16... Epitaxial growth layer 17... Diffusion region 20... Gate insulating film 21... Field insulating film 22... Interlayer insulating film 23... A Node electrode 24...cathode electrode 25...protective film 26...source electrode 27...drain electrodes 31, 32, 33, 34, 35, 36...diode forming region 41...low side circuit 42...level shift circuit 43...high side circuit 45...pMOS transistor 46...nMOS transistor 50...semiconductor integrated circuit 60...power conversion section 61...connection point 65...bootstrap diode 66...bootstrap capacitor 67...load 68...level shift resistor 69...level shifter 70...protective diode 101...high side circuit region 102...HVJT
103...Low side circuit area

Claims (16)

高電位側回路領域と、該高電位側回路領域を囲む高耐圧接合終端構造と、該高耐圧接合終端構造を介して前記高電位側回路領域を囲む低電位側回路領域が同一半導体チップに集積化された半導体集積回路であって、
前記高電位側回路領域に配置された第１導電型の中央ウェル領域と、
前記中央ウェル領域の下端に埋め込まれた第１導電型の埋込層と、
前記中央ウェル領域の周囲を囲む前記高耐圧接合終端構造の位置に配置された、第１導電型の環状のドリフト領域と、
前記ドリフト領域の周囲を囲む第２導電型の環状ウェル領域と、
前記低電位側回路領域と前記高電位側回路領域との間で信号を伝達するレベルシフト回路に含まれるレベル変換素子の担体供給領域であって、前記環状ウェル領域に配置された第１導電型の担体供給領域と、
前記レベル変換素子の担体受領領域であって、前記ドリフト領域もしくは前記中央ウェル領域に配置された、前記ドリフト領域もしくは前記中央ウェル領域よりも高不純物濃度で第１導電型の担体受領領域と、
前記ドリフト領域もしくは前記中央ウェル領域に、前記担体受領領域と離して配置された、前記ドリフト領域もしくは前記中央ウェル領域よりも高不純物濃度で第１導電型の第１コンタクト領域と、
を備え、前記第１コンタクト領域が形成される領域における前記環状ウェル領域と前記埋込層との第１距離の内の最小値は、前記担体受領領域が形成される領域における前記環状ウェル領域と前記埋込層との第２距離の内の最小値よりも短いことを特徴とする半導体集積回路。 A semiconductor integrated circuit in which a high-potential side circuit region, a high-voltage junction termination structure surrounding the high-potential side circuit region, and a low-potential side circuit region surrounding the high-potential side circuit region via the high-voltage junction termination structure are integrated on a single semiconductor chip,
a first conductivity type central well region disposed in the high potential side circuit region;
a buried layer of a first conductivity type buried in a lower end of the central well region;
a first conductivity type annular drift region disposed at the position of the high voltage junction termination structure surrounding the central well region;
a second conductive type annular well region surrounding the drift region;
a carrier supply region of a first conductivity type included in a level shift circuit that transmits a signal between the low potential side circuit region and the high potential side circuit region, the carrier supply region being disposed in the annular well region;
a carrier receiving region of the level conversion element, the carrier receiving region being disposed in the drift region or the central well region, the carrier receiving region being of a first conductivity type and having a higher impurity concentration than the drift region or the central well region;
a first contact region of a first conductivity type, the first contact region being disposed in the drift region or the central well region and spaced apart from the carrier receiving region, the first contact region having a higher impurity concentration than the drift region or the central well region;
a minimum value of a first distance between the annular well region and the buried layer in a region where the first contact region is formed is shorter than a minimum value of a second distance between the annular well region and the buried layer in a region where the carrier receiving region is formed. 高電位側回路領域と、該高電位側回路領域を囲む高耐圧接合終端構造と、該高耐圧接合終端構造を介して前記高電位側回路領域を囲む低電位側回路領域が同一半導体チップに集積化された半導体集積回路であって、
前記高電位側回路領域に配置された第１導電型の中央ウェル領域と、
前記中央ウェル領域の下端に埋め込まれた第１導電型の埋込層と、
前記中央ウェル領域の周囲を囲む前記高耐圧接合終端構造の位置に配置された、第１導電型の環状のドリフト領域と、
前記ドリフト領域の周囲を囲む第２導電型の環状ウェル領域と、
前記ドリフト領域に配置された第２導電型のベース領域と、
前記低電位側回路領域と前記高電位側回路領域との間で信号を伝達するレベルシフト回路に含まれるレベル変換素子の担体供給領域であって、前記ベース領域に配置された第１導電型の担体供給領域と、
前記レベル変換素子の担体受領領域であって、前記ドリフト領域もしくは前記中央ウェル領域に配置された、前記ドリフト領域もしくは前記中央ウェル領域よりも高不純物濃度で第１導電型の担体受領領域と、
前記ドリフト領域もしくは前記中央ウェル領域に、前記担体受領領域と離して配置された、前記ドリフト領域もしくは前記中央ウェル領域よりも高不純物濃度で第１導電型の第１コンタクト領域と、
を備え、前記第１コンタクト領域が形成される領域における前記環状ウェル領域と前記埋込層との第１距離の内の最小値は、前記担体受領領域が形成される領域における前記環状ウェル領域と前記埋込層との第２距離の内の最小値よりも短いことを特徴とする半導体集積回路。 A semiconductor integrated circuit in which a high-potential side circuit region, a high-voltage junction termination structure surrounding the high-potential side circuit region, and a low-potential side circuit region surrounding the high-potential side circuit region via the high-voltage junction termination structure are integrated on a single semiconductor chip,
a first conductivity type central well region disposed in the high potential side circuit region;
a buried layer of a first conductivity type buried in a lower end of the central well region;
a first conductivity type annular drift region disposed at the position of the high voltage junction termination structure surrounding the central well region;
a second conductive type annular well region surrounding the drift region;
a base region of a second conductivity type disposed in the drift region;
a carrier supply region of a level conversion element included in a level shift circuit that transmits a signal between the low potential side circuit region and the high potential side circuit region, the carrier supply region being a first conductivity type that is disposed in the base region;
a carrier receiving region of the level conversion element, the carrier receiving region being disposed in the drift region or the central well region, the carrier receiving region being of a first conductivity type and having a higher impurity concentration than the drift region or the central well region;
a first contact region of a first conductivity type, the first contact region being disposed in the drift region or the central well region and spaced apart from the carrier receiving region, the first contact region having a higher impurity concentration than the drift region or the central well region;
a minimum value of a first distance between the annular well region and the buried layer in a region where the first contact region is formed is shorter than a minimum value of a second distance between the annular well region and the buried layer in a region where the carrier receiving region is formed. 前記環状ウェル領域の、前記担体供給領域と前記ドリフト領域とに挟まれた部分の表面上にゲート絶縁膜を介して設けられた前記レベル変換素子の制御電極と、
前記担体供給領域及び第２コンタクト領域に接する担体供給電極と、
前記担体受領領域に接する担体受領電極と、
前記第１コンタクト領域に接するダイオード用電極と、
を更に備えることを特徴とする請求項１に記載の半導体集積回路。 a control electrode of the level conversion element provided on a surface of a portion of the annular well region between the carrier supply region and the drift region via a gate insulating film;
a carrier supply electrode in contact with the carrier supply region and the second contact region;
a carrier receiving electrode in contact with the carrier receiving area;
a diode electrode in contact with the first contact region;
2. The semiconductor integrated circuit according to claim 1, further comprising: 前記担体供給領域は、前記環状ウェル領域の内側に配置された第２導電型のベース領域に配置され、
前記ベース領域の、前記担体供給領域と前記ドリフト領域とに挟まれた部分の表面上にゲート絶縁膜を介して設けられた前記レベル変換素子の制御電極と、
前記担体供給領域に接する担体供給電極と、
前記担体受領領域に接する担体受領電極と、
前記第１コンタクト領域に接するダイオード用電極と、
を更に備えることを特徴とする請求項２に記載の半導体集積回路。 the carrier supply region is disposed in a base region of a second conductivity type disposed inside the annular well region;
a control electrode of the level conversion element provided on a surface of a portion of the base region between the carrier supply region and the drift region via a gate insulating film;
a carrier supply electrode in contact with the carrier supply region;
a carrier receiving electrode in contact with the carrier receiving area;
a diode electrode in contact with the first contact region;
3. The semiconductor integrated circuit according to claim 2, further comprising: 前記中央ウェル領域が、第２導電型の半導体基板上に設けられた第２導電型のエピタキシャル成長層に選択的に設けられていることを特徴とする請求項１～４のいずれか１項に記載の半導体集積回路。 The semiconductor integrated circuit according to any one of claims 1 to 4, characterized in that the central well region is selectively provided in a second conductivity type epitaxial growth layer provided on a second conductivity type semiconductor substrate. 前記ドリフト領域が、第２導電型の半導体基板上に設けられた第１導電型のエピタキシャル成長層で構成され、
前記中央ウェル領域が、前記エピタキシャル成長層に選択的に設けられている
ことを特徴とする請求項１～４のいずれか１項に記載の半導体集積回路。 the drift region is formed of an epitaxially grown layer of a first conductivity type provided on a semiconductor substrate of a second conductivity type,
5. The semiconductor integrated circuit according to claim 1, wherein the central well region is selectively provided in the epitaxial growth layer. 前記中央ウェル領域が、第２導電型の半導体基板上に設けられた第１導電型のエピタキシャル成長層に選択的に設けられ、
前記ドリフト領域が、前記エピタキシャル成長層に選択的に設けられている
ことを特徴とする請求項１～４のいずれか１項に記載の半導体集積回路。 the central well region is selectively provided in an epitaxial growth layer of a first conductivity type provided on a semiconductor substrate of a second conductivity type;
5. The semiconductor integrated circuit according to claim 1, wherein the drift region is selectively provided in the epitaxial growth layer. 前記埋込層が、前記半導体基板と前記中央ウェル領域との間に位置することを特徴とする請求項５～７のいずれか１項に記載の半導体集積回路。 The semiconductor integrated circuit according to any one of claims 5 to 7, characterized in that the buried layer is located between the semiconductor substrate and the central well region. 前記担体供給領域と前記担体受領領域とを結ぶ方向において、前記担体受領領域と前記高電位側回路領域との間に設けられ、前記ドリフト領域もしくは前記中央ウェル領域を深さ方向に貫通し、前記エピタキシャル成長層もしくは前記半導体基板に達する第２導電型のスリット領域を更に備えることを特徴とする請求項５～８のいずれか１項に記載の半導体集積回路。 The semiconductor integrated circuit according to any one of claims 5 to 8, further comprising a second conductive type slit region provided between the carrier receiving region and the high potential side circuit region in a direction connecting the carrier supply region and the carrier receiving region, penetrating the drift region or the central well region in a depth direction and reaching the epitaxial growth layer or the semiconductor substrate. 前記スリット領域が、平面パターン上、前記中央ウェル領域を囲むように設けられていることを特徴とする請求項９に記載の半導体集積回路。 The semiconductor integrated circuit according to claim 9, characterized in that the slit region is provided so as to surround the central well region in a planar pattern. 前記スリット領域が、前記ドリフト領域に延在し、平面パターン上、前記担体受領領域を囲むように設けられていることを特徴とする請求項９に記載の半導体集積回路。 The semiconductor integrated circuit according to claim 9, characterized in that the slit region extends into the drift region and is arranged in a planar pattern so as to surround the carrier receiving region. 前記埋込層が、平面パターン上、前記レベル変換素子に近づくほど前記環状ウェル領域から離れるように設けられていることを特徴とする請求項１１に記載の半導体集積回路。 The semiconductor integrated circuit according to claim 11, characterized in that the buried layer is arranged in a planar pattern so that the closer it is to the level conversion element, the farther it is from the annular well region. 前記中央ウェル領域が矩形の平面パターンを有し、
前記中央ウェル領域の矩形の１辺側に、前記レベル変換素子が形成される領域と、ｐｎ接合ダイオードが形成される領域とが設けられている
ことを特徴とする請求項１２に記載の半導体集積回路。 the central well region has a rectangular planar pattern;
13. The semiconductor integrated circuit according to claim 12, wherein a region in which the level conversion element is formed and a region in which a pn junction diode is formed are provided on one side of the rectangular central well region . 前記埋込層及び前記中央ウェル領域が矩形の平面パターンをそれぞれ有し、
平面パターン上、前記埋込層の角部の曲率半径が、前記中央ウェル領域の角部の曲率半径よりも大きい
ことを特徴とする請求項１～１３のいずれか１項に記載の半導体集積回路。 the buried layer and the central well region each have a rectangular planar pattern;
14. The semiconductor integrated circuit according to claim 1, wherein a radius of curvature of a corner of the buried layer is larger than a radius of curvature of a corner of the central well region in a planar pattern. 前記埋込層が矩形の平面パターンを有し、
前記ドリフト領域が枠状の平面パターンを有し、
平面パターン上、前記埋込層の角部の曲率半径が、前記ドリフト領域の角部の曲率半径よりも大きい
ことを特徴とする請求項１～１３のいずれか１項に記載の半導体集積回路。 the buried layer has a rectangular planar pattern;
The drift region has a frame-shaped planar pattern,
14. The semiconductor integrated circuit according to claim 1, wherein a radius of curvature of the corners of the buried layer is larger than a radius of curvature of the corners of the drift region in a planar pattern. 前記埋込層が矩形の平面パターンを有し、
平面パターン上、前記埋込層の角部の曲率半径が８０μｍ以上である
ことを特徴とする請求項１～１３のいずれか１項に記載の半導体集積回路。 the buried layer has a rectangular planar pattern;
14. The semiconductor integrated circuit according to claim 1, wherein the corners of the buried layer have a radius of curvature of 80 μm or more in a plane pattern.
JP2020022332A 2019-04-11 2020-02-13 Semiconductor Integrated Circuit Active JP7472522B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US16/813,104 US11562995B2 (en) 2019-04-11 2020-03-09 Semiconductor integrated circuit
CN202010167105.1A CN111834358A (en) 2019-04-11 2020-03-11 Semiconductor integrated circuit having a plurality of transistors

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2019075656 2019-04-11
JP2019075656 2019-04-11

Publications (2)

Publication Number Publication Date
JP2020174173A JP2020174173A (en) 2020-10-22
JP7472522B2 true JP7472522B2 (en) 2024-04-23

Family

ID=72831835

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2020022332A Active JP7472522B2 (en) 2019-04-11 2020-02-13 Semiconductor Integrated Circuit

Country Status (2)

Country Link
JP (1) JP7472522B2 (en)
CN (1) CN111834358A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117316947B (en) * 2023-11-27 2024-05-24 厦门科塔电子有限公司 ESD protection device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012176347A1 (en) 2011-06-24 2012-12-27 富士電機株式会社 High-voltage integrated circuit device
JP2015173255A (en) 2014-02-19 2015-10-01 富士電機株式会社 High voltage integrated circuit device
WO2017086069A1 (en) 2015-11-19 2017-05-26 富士電機株式会社 Semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012176347A1 (en) 2011-06-24 2012-12-27 富士電機株式会社 High-voltage integrated circuit device
JP2015173255A (en) 2014-02-19 2015-10-01 富士電機株式会社 High voltage integrated circuit device
WO2017086069A1 (en) 2015-11-19 2017-05-26 富士電機株式会社 Semiconductor device
US20180069076A1 (en) 2015-11-19 2018-03-08 Fuji Electric Co., Ltd. Semiconductor device

Also Published As

Publication number Publication date
JP2020174173A (en) 2020-10-22
CN111834358A (en) 2020-10-27

Similar Documents

Publication Publication Date Title
US20210143148A1 (en) Semiconductor device
US11257806B2 (en) Semiconductor integrated circuit
US10547304B2 (en) Semiconductor integrated circuit for driving switching device with integrated negative voltage clamp diode
WO2017086069A1 (en) Semiconductor device
JPH04768A (en) Mos semiconductor device
JP6743955B2 (en) Method for manufacturing semiconductor integrated circuit
US9893065B2 (en) Semiconductor integrated circuit
JP7472522B2 (en) Semiconductor Integrated Circuit
JP7115637B2 (en) semiconductor integrated circuit
US10217765B2 (en) Semiconductor integrated circuit
US11562995B2 (en) Semiconductor integrated circuit
US10763854B2 (en) Semiconductor integrated circuit
US20230187437A1 (en) Semiconductor device
US20240128266A1 (en) Semiconductor device
JP7143734B2 (en) semiconductor integrated circuit
US20230178540A1 (en) Semiconductor device
CN114843259A (en) Semiconductor device with a plurality of semiconductor chips
JP2022094896A (en) Semiconductor device

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20211217

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20230116

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20231012

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20231031

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20231208

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20240312

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20240325

R150 Certificate of patent or registration of utility model

Ref document number: 7472522

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150