JP2022094896A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device with high noise tolerance and capable of suppressing an operation of a parasitic bipolar transistor of a high-withstand-voltage MOSFET, which is a level shifter, in a self-shielding method HVIC.SOLUTION: A semiconductor device comprises: a well region 3 of a second conductivity type provided in a surface layer of a semiconductor layer 1 of a first conductivity type; a breakdown voltage region 4 of the second conductivity type surrounding a periphery of the well region 3 and having lower impurity concentration than the well region 3; a base region 61 of the first conductivity type surrounding a periphery of the breakdown voltage region 4; a carrier supply region 56 of the second conductivity type of a level shifter 41a provided in a surface layer of the base region 61; and a carrier reception region (51, 52) of the level shifter 41a provided in a surface layer of the well region 3 or the breakdown voltage region 4. The carrier reception region (51, 52) is composed of a first universal contact region in which a region 51 of the first conductivity type and a region 52 of the second conductivity type are provided in contact with each other.SELECTED DRAWING: Figure 3

Description

The present invention relates to a semiconductor device, and is a high withstand voltage integrated circuit device (HVIC) used particularly when transmitting an on / off drive signal to the gate of a switching power device in a pulse width modulation (PWM) inverter, a switching power supply, or the like. Regarding.

As a means for driving a switching power device constituting an upper arm of a bridge circuit for reverse power conversion (DC / AC conversion) such as a PWM inverter, an element separation type HVIC using a high withstand voltage junction is used. The HVIC can be enhanced in functionality by providing overcurrent detection and temperature detection means at the time of abnormality of the switching power device. Further, since the HVIC does not perform potential insulation by a transformer, a photocoupler, or the like, it is possible to reduce the size and cost of the power supply system.

Power conversion systems that are configured by combining half-bridge circuits composed of switching power devices include inverters for motor control, amusement equipment, power supply applications such as liquid crystal panels, and inverters for home appliances such as air conditioners and lighting. Widely used in the field. Since these motors, lighting, and the like have an inductance load (L load), the influence of parasitic inductance components and the like due to wiring on the printed circuit board, cables to the L load, and the like occurs.

That is, when the switching power device of the upper arm is turned off or when the switching power device of the lower arm is turned on, the potential of the Vs terminal which is the reference potential on the high potential side of the high side circuit portion constituting the HVIC or H -The potential of the VDD terminal fluctuates to the negative potential side with respect to the ground potential (GND potential). This fluctuation to the negative potential side (negative surge voltage) causes a malfunction or latch-up of the high-side circuit portion, which may lead to destruction of the HVIC.

A chip layout configuration for preventing malfunction or destruction of the HVIC itself that drives a power device having a half-bridge configuration against such a negative surge voltage is disclosed (see Patent Document 1). In Patent Document 1, the pickup region of the region fixed to the potential on the high potential side of the power supply of the high side circuit portion arranged on the outer peripheral portion of the high side circuit portion is set as the universal contact region, and thus flows into the low side circuit portion. It is disclosed that the amount of carriers is reduced and the malfunction of the logic part of the low-side circuit part and the destruction due to latch-up are prevented. Further, Patent Document 2 discloses that an n ⁺ / p ⁺ type short region is provided in each of the anode and the cathode of the high withstand voltage horizontal diode to promote the extraction of a small number of carriers.

In recent years, from the viewpoint of chip miniaturization, in self-separated type and junction-separated HVICs, a self-shielding method that integrates a level shifter composed of high-voltage n-channel MOSFETs and a high-voltage junction termination region (HVJT) has been adopted. It is the mainstream to use. In order to realize stable level shift circuit operation by the self-shielding method, a p ^- type opening is provided in the withstand voltage region surrounding the high side circuit section for the purpose of increasing the parasitic resistance component in the drain of the level shifter and the H- VDD potential region. (See Patent Documents 3 to 5). Further, the configuration in which the high withstand voltage n-channel MOSFET is integrated into the HVJT without using the p ^- opening as shown in FIG. 15 of Patent Document 3 also belongs to the above-mentioned self-shielding method. Further, there is disclosed a split RESURF technique in which the circumference of the level shifter is joined and separated by a p ^- layer to completely eliminate the drain of the level shifter and the parasitic resistance component in the H- VDD potential region (see Patent Document 6). The configuration disclosed in Patent Document 6 also belongs to the above-mentioned self-shielding method.

Further, Patent Document 7 describes at least a part of the outer peripheral region with respect to the thickness of the low concentration layer in the cell region in order to improve the soft recovery characteristics so that the diode having a built-in power MOSFET can be used as the protection diode of the MOSFET. Discloses a configuration in which the thickness of the low-concentration layer is large. Further, in Patent Document 8, in order to improve the trade-off between heat generation of the level shifter and the transmission delay time in HVIC, the effective channel width defined by the width of the base region of the portion overlapping the control electrode of the level shifter is the effective channel. Disclosed is a configuration wider than the width of the drain region measured along the same direction as the width.

Further, Patent Document 9 discloses a technique for improving the short-circuit tolerance by providing a channel layer on the trench side wall of the trench MOSFET. Patent Document 10 discloses a MOSFET technique having a trench contact structure in which an SBD for Schottky contact is built in a trench side wall. In Patent Document 11, a groove portion leading to the silicon substrate is formed in the source region, and the source electrode, the source region, and the silicon substrate are electrically connected by the groove portion so that the source region is shortened, and the lower portion of the source region is formed. A technique for directly connecting to a source electrode to reduce the resistance component at the bottom of the source region is disclosed.

Japanese Patent No. 5099282 Japanese Patent No. 4935037 Japanese Patent No. 3941206 Japanese Patent No. 5720792 Japanese Unexamined Patent Publication No. 2015-173255 Japanese Patent No. 3917211 Japanese Unexamined Patent Publication No. 8-102536 Japanese Unexamined Patent Publication No. 2020-08287 Patent No. 4225711 Japanese Unexamined Patent Publication No. 2018-182235 Japanese Unexamined Patent Publication No. 5-326944

In the technique described in Patent Document 1, when a negative surge voltage is applied via the H- VDD terminal, electrons are transferred from the n ^- region (H- VDD side) of the parasitic pn diode of the HVJT to the p-region as a minority carrier. It is injected and electrons flow into the n ^- region of the low-side circuit section via this p-region. At that time, some of the electrons that have entered the p-region in the middle of the movement path of the electrons that flow from the n ^- region (H- VDD side) to the n ^- region (low-side circuit side) have a higher bonding barrier than this p-region. (High by about 0.6V), that is, the electron energy barrier is trapped in the low n ⁺ region and pulled out in the anode electrode. Therefore, the amount of electrons flowing into the n ^- region (low-side circuit side) is reduced, and it is possible to prevent malfunction of the logic of the low-side circuit portion and destruction due to latch-up. Further, the amount of holes released from the p ⁺ region (GND side) to the p region is suppressed because there is an n ⁺ region adjacent to the p ⁺ region (GND side). Therefore, the amount of holes injected from the p region to the n ⁻ region of the parasitic pn diode is also reduced, and it is possible to prevent malfunction of the logic of the high-side circuit portion and destruction due to latch-up.

However, in the self-shielding type HVIC in which the high withstand voltage n-channel MOSFET is formed in the HVJT, when a negative surge voltage is applied to the H- VDD terminal, the forward current of the parasitic diode of the HVJT starts to flow and the high withstand voltage n Forward current also begins to flow in the body diode of the channel MOSFET. At this time, the p ^- opening existing between the drain of the high withstand voltage n-channel MOSFET and the H- VDD potential region has a higher potential than the n region, the junction barrier is crushed, and the junction separation region does not function. As a result, excess electron carriers injected from the H- VDD potential region through the drain of the high withstand voltage n-channel MOSFET and the p ^- opening flow into the p ⁺ region of the GND potential. On the other hand, excess hole carriers flow into the drain region from the p ⁺ region of the GND potential.

Then, when the VS potential is recovered from the negative surge state, the body diode of the high withstand voltage n-channel MOSFET is in the reverse recovery state, and an excessive reverse recovery current Irr flows. Excessive reverse recovery current Irr (hole current) induces a voltage drop of 0.6 V or more in the base region below the source region of the high withstand voltage n-channel MOSFET, and the parasitic npn bipolar operates. When the parasitic npn bipolar operates, not only the potential of the drain is lowered for a certain period of time and the input signal is not accepted (signal is ignored), but also a malfunction of the level shift circuit or a thermal runaway destruction is caused in a high temperature state.

That is, the universal electrode described in Patent Documents 1 and 2 in which the p region and the n region are provided in contact with each other is applied only to the high withstand voltage diode region, and the above-mentioned reverse recovery current Irr is applied. It is not possible to avoid the parasitic npn bipolar transistor operation of the high withstand voltage MOSFET used as a trigger.

In view of the above problems, it is an object of the present invention to provide a semiconductor device having high noise immunity capable of suppressing the operation of a parasitic bipolar transistor of a high withstand voltage MOSFET as a level shifter in a self-shielding HVIC.

One aspect of the present invention is provided around the high potential side circuit region via the high potential side circuit region, the high withstand voltage junction termination structure provided around the high potential side circuit region, and the high withstand voltage junction termination structure. This is a semiconductor device in which the low-potential side circuit region is integrated on the same semiconductor chip, and is located in (a) the first conductive type semiconductor layer and (b) the high-potential side circuit region, and is the surface layer of the semiconductor layer. The second conductive type well region provided in the above, and (c) the second conductive type pressure resistant region having a lower impurity concentration than the well region, which surrounds the well region and is provided in contact with the well region. d) A level shift that transmits a signal between the first conductive type base region that surrounds the withstand voltage region and is provided in contact with the withstand voltage region, and (e) the low potential side circuit region and the high potential side circuit region. A second conductive type carrier supply region provided on the surface layer of the base region, which is a carrier supply region of the level shifter included in the circuit, and (f) a carrier receiving region of the level shifter, which is a well region or a pressure resistant region. A semiconductor device comprising a carrier receiving region provided on a surface layer, and the carrier receiving region is composed of a universal contact region provided in which a first conductive type region and a second conductive type region are in contact with each other. The gist is that there is.

Another aspect of the present invention is provided around the high potential side circuit region via the high potential side circuit region, the high withstand voltage junction termination structure provided around the high potential side circuit region, and the high withstand voltage junction termination structure. The low-potential side circuit region is integrated into the same semiconductor chip, and is located in (a) the first conductive type semiconductor layer and (b) the high-potential side circuit region, and is the surface of the semiconductor layer. A second conductive type well region provided in the layer, and (c) a second conductive type pressure resistant region having a lower impurity concentration than the well region, which surrounds the well region and is provided in contact with the well region. (D) A level at which a signal is transmitted between a first conductive type base region that surrounds the withstand voltage region and is provided in contact with the withstand voltage region, and (e) between a low potential side circuit region and a high potential side circuit region. A second conductive type carrier supply region provided on the surface layer of the base region, which is a carrier supply region of the level shifter included in the shift circuit, and (f) a carrier receiving region of the level shifter, which is a well region or a pressure resistant region. A carrier receiving region provided on the surface layer of the above, and a plurality of pickup regions provided on the surface layer of the (g) well region, and the pickup region includes a first conductive type region and a second conductive type region. The gist is that is a semiconductor device composed of universal contact regions provided in contact with each other.

Yet another aspect of the present invention is around the high potential side circuit region via the high potential side circuit region, the high withstand voltage junction termination structure provided around the high potential side circuit region, and the high withstand voltage junction termination structure. The provided low-potential side circuit region is a semiconductor device integrated on the same semiconductor chip, and is located in (a) a first conductive type semiconductor layer and (b) a high-potential side circuit region, and is a semiconductor layer. A second conductive type well region provided on the surface layer, and (c) a second conductive type pressure resistant region having a lower impurity concentration than the well region, which surrounds the well region and is provided in contact with the well region. , (D) A first conductive type base region that surrounds the withstand voltage region and is provided in contact with the withstand voltage region, and (e) transmits a signal between the low potential side circuit region and the high potential side circuit region. The carrier supply region of the level shifter included in the level shift circuit, which is the second conductive type carrier supply region provided on the surface layer of the base region, and (f) the carrier receiving region of the level shifter, which is the well region or the withstand voltage. The carrier receiving region is provided on the surface layer of the region, the carrier supply region and the carrier receiving region are provided parallel to each other on the plane pattern, the width of the carrier supply region is wider than the width of the carrier receiving region, and the plane pattern. The gist of the present invention is that the density of the carrier supply region at a position facing the carrier receiving region is lower than the density of the carrier supply region at a position not facing the carrier receiving region.

According to the present invention, it is possible to provide a semiconductor device having high noise immunity capable of suppressing the operation of a parasitic bipolar transistor of a high withstand voltage MOSFET as a level shifter in a self-shielding HVIC.

It is a circuit diagram which shows the connection example of the semiconductor device which concerns on 1st Embodiment of this invention. It is a circuit diagram of the semiconductor device which concerns on 1st Embodiment of this invention. It is a top view which shows the main part of the semiconductor device which concerns on 1st Embodiment of this invention. It is sectional drawing seen from the AA'direction of FIG. It is sectional drawing seen from the BB'direction of FIG. It is a top view around the level shifter which concerns on 1st Embodiment of this invention. It is a top view of the universal contact area which concerns on 1st Embodiment of this invention. It is sectional drawing which shows the behavior of an electron and a hole when a negative surge voltage of the semiconductor device which concerns on 1st Embodiment of this invention is applied. It is a top view of the semiconductor device which concerns on a comparative example. 9 is a cross-sectional view taken from the direction of AA'in FIG. It is a top view which shows the main part of the semiconductor device which concerns on 2nd Embodiment of this invention. It is sectional drawing seen from the AA'direction of FIG. It is a top view which shows the main part of the semiconductor device which concerns on 3rd Embodiment of this invention. It is sectional drawing seen from the AA'direction of FIG. It is a top view around the level shifter which concerns on 4th Embodiment of this invention. It is a top view of the semiconductor device which concerns on 5th Embodiment of this invention. It is sectional drawing of the semiconductor device which concerns on 5th Embodiment of this invention. It is another plan view of the semiconductor device which concerns on 6th Embodiment of this invention. It is another sectional view of the semiconductor device which concerns on 6th Embodiment of this invention. It is a top view of the semiconductor device which concerns on 7th Embodiment of this invention. It is sectional drawing seen from the AA'direction of FIG. It is sectional drawing seen from the BB'direction of FIG. It is sectional drawing which shows the behavior of electron and hole at the time of reverse recovery after the negative surge voltage of the semiconductor device which concerns on 7th Embodiment of this invention is applied. It is a top view around the level shifter which concerns on 8th Embodiment of this invention. It is sectional drawing of the semiconductor device which concerns on 9th Embodiment of this invention.

Hereinafter, the first to ninth embodiments of the present invention will be described with reference to the drawings. In the description of the drawings, the same or similar parts are designated by the same or similar reference numerals, and duplicate description will be omitted. However, the drawings are schematic, and the relationship between the thickness and the plane dimensions, the ratio of the thickness of each layer, etc. may differ from the actual ones. In addition, parts having different dimensional relationships and ratios may be included between the drawings. Further, the embodiments shown below exemplify devices and methods for embodying the technical idea of the present invention, and the technical idea of the present invention describes the material, shape, structure, and arrangement of constituent parts. Etc. are not specified as the following.

In the present specification, the “carrier supply region” refers to a large number of main currents such as a field effect transistor (FET), a static induction transistor (SIT) source region, and an insulated gate bipolar transistor (IGBT) emitter region. It means the semiconductor area that supplies carriers. Further, in the electrostatic induction (SI) thyristor and the gate turn-off (GTO) thyristor, the anode region is the carrier supply region. Further, the “carrier receiving region” means a semiconductor region that receives a large number of carriers constituting a main current, such as a drain region of FETs and SITs, and a collector region of IGBTs. In SI thyristors and GTO thyristors, the cathode region functions as a carrier receiving region. Further, the “control electrode” means a gate electrode of a FET, SIT, IGBT, SI thyristor or GTO thyristor, and has a function of controlling the flow of the main current flowing between the carrier supply region and the carrier receiving region.

Further, the definition of the direction such as up and down in the following description is merely a definition for convenience of explanation, and does not limit the technical idea of the present invention. For example, if the object is rotated by 90 ° and observed, the top and bottom are converted to left and right and read, and if the object is rotated by 180 ° and observed, the top and bottom are reversed and read.

Further, in the following description, the case where the first conductive type is the p type and the second conductive type is the n type will be exemplified. However, the conductive type may be selected in the reverse relationship, the first conductive type may be the n type, and the second conductive type may be the p type. Further, "+" and "-" attached to "n" and "p" are semiconductor regions having a relatively high or low impurity concentration, respectively, as compared with the semiconductor regions to which "+" and "-" are not added. Means that However, even in the semiconductor regions with the same "n" and "n", it does not mean that the impurity concentrations of the respective semiconductor regions are exactly the same. Further, in the following description, the member or region to which the "first conductive type" and the "second conductive type" are limited means a member or region made of a semiconductor material without any particular limitation.

(First Embodiment)
As a semiconductor device (semiconductor integrated circuit) according to the first embodiment of the present invention, a self-shielding high withstand voltage integrated circuit device (HVIC) will be described. FIG. 1 shows an example of connection between HVIC111, which is a semiconductor device according to the first embodiment of the present invention, and IGBTs 114, 115, which are switching power devices (switching elements) of a power conversion device such as an inverter driven by HVIC111. .. The switching element of the power conversion device is not limited to the IGBTs 114 and 115, and may be a switching element such as a MOSFET.

The IGBTs 114 and 115 are connected in series to form a half bridge. Reflux diodes (FWD) 116 and 117 are connected in antiparallel to the IGBTs 114 and 115. A ground potential (GND potential) is connected to the emitter of the IGBT 114. The Vss potential on the high potential side of the high voltage power supply, which is the main circuit power supply, is connected to the collector of the IGBT 115.

By alternately turning on the IGBT 115 of the upper arm and the IGBT 114 of the lower arm of the power conversion device shown in FIG. 1, high potential or low potential is alternately output from the Vs terminal 110 which is an output terminal to the L load 118. Supply AC power (flow AC current). That is, when outputting a high potential, the IGBTs 114 and 115 are operated so that the IGBT 115 of the upper arm is turned on and the IGBT 114 of the lower arm is turned off. On the contrary, when the low potential is output, the IGBTs 114 and 115 are operated so that the IGBT 115 of the upper arm is turned off and the IGBT 114 of the lower arm is turned on.

At this time, the HVIC 111 for driving the IGBTs 114 and 115 outputs a GND-referenced gate signal to the gate of the IGBT 114 of the lower arm, and outputs a gate signal based on the Vs potential of the Vs terminal 110 to the gate of the IGBT 115 of the upper arm. Output. Therefore, the HVIC 111 needs to have a level shift function.

The reference numeral “Vs” of the HVIC 111 shown in FIG. 1 is an intermediate potential that fluctuates from the Vss potential to the GND potential. “H— VDD” is the high potential side of the low voltage power supply 113 with respect to the Vs potential. “L- VDD” is the high potential side of the low voltage power supply 112 with respect to the GND potential. In the case of the bootstrap circuit system, the low voltage power supply 113 is composed of an external capacitor (not shown) by an external bootstrap diode (not shown) connected between "L- VDD" and "H- VDD". Will be done.

“H-IN” is an input signal and an input terminal input to the gate of the CMOS circuit on the low side connected to the level-up circuit. “L-IN” is an input signal and an input terminal input to the gate of the CMOS circuit on the low side connected to the gate of the IGBT 114 of the lower arm. “H-OUT” is an output signal and an output terminal of the CMOS circuit on the high side that outputs to the gate of the IGBT 115 of the upper arm. “L-OUT” is an output signal and an output terminal to be output to the gate of the IGBT 114 of the lower arm. "ALM-IN" is an input signal and an input terminal of the detection signal 119 when the temperature or overcurrent of the IGBT 115 of the upper arm is detected. “ALM-OUT” is an output signal and an output terminal of the level-down detection signal.

FIG. 2 is a circuit diagram showing a level shift circuit (level up circuit) 132 inside the HVIC 111 shown in FIG. 1 and peripheral circuits (131, 133) of the level up circuit 132. As peripheral circuits (131, 133), a low-side circuit 131 on the low-side side that transmits an input signal to the level-up circuit 132 and a high-side circuit on the high-side side that transmits an output signal from the level-up circuit 132 to the IGBT 115 on the upper arm. The circuit 133 is illustrated. The low-side circuit 131 has a p-channel MOSFET 71 and an n-channel MOSFET 72 that constitute a CMOS circuit. The high-side circuit 133 has a p-channel MOSFET 75 and an n-channel MOSFET 76 that constitute a CMOS circuit.

The level-up circuit 132 includes a level shift resistor 73 and an n-channel MOSFET 41 having a drain connected to the level shift resistor 73. The connection portion between the level shift resistor 73 and the n-channel MOSFET 41 is used as the output portion 101 of the level-up circuit 132. The anode and cathode of the diode 74 are connected to both ends of the level shift resistance 73, respectively. The diode 74 clamps the overvoltage drop across the level shift resistance 73. One end of the level shift resistance 73 and the source of the p-channel MOSFET 75 of the high-side circuit 133 are connected to the H- VDD terminal 120 on the high-potential side of the low-voltage power supply 113 with reference to the Vs potential.

When the input signal H-IN is input to the low-side circuit 131 shown in FIG. 2, the low-side level on / off signal is sent to the level-up circuit 132 n via the CMOS circuit (71, 72) of the low-side circuit 131. It is input to the gate of the channel MOSFET 41. This signal turns the n-channel MOSFET 41 on and off, and outputs a high-side level on / off signal from the output unit 101 of the level-up circuit 132. By this signal, the CMOS circuit (75,76) of the high-side circuit 133 is turned on and off, and the output signal H-OUT is output. The output signal H-OUT is converted into a signal based on the Vs potential. The output signal H-OUT is applied to the gate of the IGBT 115 of the upper arm shown in FIG. 1 to turn on / off the IGBT 115 of the upper arm.

Next, the structure of the semiconductor device according to the first embodiment of the present invention will be described. FIG. 3 is a plan view showing a main part of the semiconductor device according to the first embodiment of the present invention. FIG. 4 is a cross-sectional view including a high withstand voltage n-channel MOSFET 41a seen from the direction AA'of FIG. 3, and FIG. 5 is a cross-sectional view seen from the direction BB'of FIG.

As shown in FIG. 3, the HVIC 111, which is the semiconductor device according to the first embodiment of the present invention, is provided in a ring around the high potential side circuit region (high side circuit region) 301 and the high side circuit region 301. One chip includes a high withstand voltage junction termination structure (HVJT) 303 and a low potential side circuit region (low side circuit region) 302 provided around the high side circuit region 301 via the HVJT 303. The high-side circuit region 301 includes the high-side circuit 133 shown in FIG. 2 as an internal circuit. The low-side circuit region 302 includes the low-side circuit 131 shown in FIG. 2 as an internal circuit. The HVJT 303 electrically separates the high-side circuit region 301 and the low-side circuit region 302.

As shown in FIGS. 3 to 5, the HVIC 111 is an n-type high-side floating potential region provided on one main surface side (hereinafter referred to as “surface layer”) inside the p-type semiconductor layer 1. A well region 3 is provided. As the p-type semiconductor layer 1, for example, a silicon (Si) substrate can be used, but a compound semiconductor substrate such as silicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs), a metalloid substrate, or the like can be used. You may use it. Further, the semiconductor layer 1 may be a p-type or n-type epitaxial growth layer provided on a p-type semiconductor substrate. In this case, an n-type embedded layer may be provided in a part between the p-type semiconductor substrate and the epitaxial growth layer. Further, the n-type well region 3 may be provided at a depth in contact with the n-type embedded layer.

The n-type well region 3 is located in the high side circuit region 301. The n-type well region 3 is provided with a Vs potential region 200 and an H— VDD potential region 201. The Vs potential region 200 includes an n ⁺ type source region, a p-type base region and an n-type drain region of the n-channel MOSFET, which is a high-side logic unit, and a p-type drain region of the p-channel MOSFET. The H- VDD potential region 201 includes a p ⁺ type source and an n-type base region of the p-channel MOSFET, which is a high-side logic unit. Further, an H- VDD pad 102, an H-OUT pad 103, and a Vs pad 104 are provided on the n-type well region 3.

As shown in FIG. 3, in the n-type well region 3, the p-type junction separation region (slit region) 63 is annular (C-shaped) so as to surround the Vs potential region 200 and the H- VDD potential region 201. It is provided in. As shown in FIGS. 4 and 5, the p-type junction separation region 63 has a depth that penetrates the n-type well region 3 and reaches the p-type semiconductor layer 1, and the n-type well region 3 is junction-separated. .. In the cross section shown in FIG. 5, the pickup electrode 203 is provided on the p-type junction separation region 63 via the insulating films 81 and 82.

As shown in FIG. 3, n ⁺ type pickup regions 62a, 62b, 62c are provided in a band shape or an annular shape on the surface layer of the n-type well region 3 inside the p-type junction separation region 63. Pickup electrodes (pickup contacts) 203a, 203b, 203c connected to the H— VDD terminal are provided on the n ⁺ type pickup regions 62a, 62b, 62c, respectively.

Further, at the position of the opening (missing portion) of the plane pattern of the p-type junction separation region 63, the n ⁺ type pickup region 62d is formed on the surface layer of the n-type well region 3 outside the p-type junction separation region 63. It is provided. The n ⁺ type pickup area 62d is provided at a position facing the n ⁺ type pickup area 62c. On the n ⁺ type pickup region 62d, a pickup electrode (pickup contact) 203d connected to the H— VDD terminal is provided.

As shown in FIGS. 3 to 5, the n ^- type pressure resistant region 4 having a lower impurity concentration than the n-type well region 3 is annular so as to surround the n-type well region 3 and be in contact with the n-type well region 3. It is provided in. Further, a p-type base region 61 is provided in an annular shape so as to surround the n ^- type pressure-resistant region 4 and to be in contact with the n ^- type pressure-resistant region 4. Insulating films 81, 82, and 83 are provided on the n-type well region 3, the n ^- type pressure-resistant region 4, and the p-type base region 61. As schematically shown in FIG. 4, a parasitic diode 42 is formed by a pn junction between an n ^- type withstand voltage region 4 and a p-type base region 61, and the parasitic diode 42 constitutes an HVJT 303.

The impurity concentration of the p-type base region 61 is higher than the impurity concentration of the p-type semiconductor layer 1. The p-type base region 61 fixes the p-type semiconductor layer 1 to the GND potential. The surface layer of the p-type base region 61 is provided with a p ⁺ type contact region 56 having a higher impurity concentration than the p-type base region 61 in a ring shape along the surface of the p-type semiconductor layer 1. As shown in FIGS. 3 and 5, a pickup electrode (pickup contact) 202 connected to the GND potential is provided in an annular shape on the p ⁺ type contact region 56.

As shown on the lower side of FIG. 3, a low-side circuit region 302 is provided in the p-type well region 2 provided so as to surround the p-type base region 61. Further, the p-type well region 2 is provided with an H-IN pad 105, an L- VDD pad 106, and a GND pad 107.

As shown in FIG. 3, a part of the HVJT 303 is provided with high withstand voltage n-channel MOSFETs 41a and 41b, which are level shifters for transmitting signals between the high-side circuit region 301 and the low-side circuit region 302. The high withstand voltage n-channel MOSFETs 41a and 41b correspond to the n-channel MOSFET 41 shown in FIG. Since signal transmission to the high-side logic and the output circuit is performed by a two-input method of a SET signal and a RESET signal, two high-voltage n-channel MOSFETs 41a and 41b for the SET signal and the RESET signal are provided. The structures of the high withstand voltage n-channel MOSFETs 41a and 41b are the same, and the description thereof will be described below mainly focusing on the high withstand voltage n-channel MOSFETs 41a.

As shown in FIGS. 3 and 4, the high withstand voltage n-channel MOSFET 41a uses the n ^- type withstand voltage region 4 as the drift region. The high withstand voltage n-channel MOSFET 41a has an n ⁺ -type source region 53 provided adjacent to the p ⁺ -type contact region 56 on the surface layer of the p-type base region 61. A source electrode 400 is provided on the p ⁺ type contact region 56 and the n ⁺ type source region 53 in contact with the p ⁺ type contact region 56 and the n ⁺ type source region 53.

The high withstand voltage n-channel MOSFET 41a has a universal contact region (51, 52) which is a drain region provided on the surface layer of the n-type well region 3. Here, the "universal contact area" refers to an area in which at least one p ⁺ type contact area (p ⁺ type area) and at least one n ⁺ type contact area (n ⁺ type area) are arranged in contact with each other. means. In FIGS. 3 and 4, the universal contact region (51, 52) is configured such that the p ⁺ type contact region 51 and the n ⁺ type contact region 52 are alternately arranged in contact with each other along the surface of the p-type semiconductor layer 1. Has been done. The depths of the p ⁺ type contact region 51 and the n ⁺ type contact region 52 may be the same as each other, and either one of the p ⁺ type contact region 51 and the n ⁺ type contact region 52 may be relatively deep. ..

3 and 4 illustrate a structure in which the universal contact region (51, 52) is provided on the surface layer of the n-type well region 3, but the universal contact region (51, 52) is the n ^- type pressure resistant region 4. It may be provided on the surface layer.

On the universal contact region (51, 52), a universal electrode (universal contact) 401 that makes ohmic contact with the universal contact region (51, 52) is provided. The universal contact region (51, 52) and the universal electrode 401 constitute a universal contact structure (51, 52, 401).

As shown in FIG. 4, a gate electrode 402 is provided on the p-type base region 61 between the source electrode 400 and the drain electrode 401 via a gate insulating film. The gate electrode 402 is made of, for example, polysilicon. The pickup electrode 202 and the source electrode 400 are connected to the GND potential and have the same potential.

FIG. 6 is a partially enlarged view of the peripheral portion of the high withstand voltage n-channel MOSFET 41a of FIG. In FIG. 6, the contact portion of the source electrode 400 is shown by a broken line. As shown in FIG. 6, the n ⁺ type source region 53 and the universal contact region (51, 52) are provided in parallel with each other. The n ⁺ type source region 53 and the universal contact region (51, 52) have a linear planar pattern. In the vertical direction of FIG. 6, the width Ws of the n ⁺ type source region 53 of the high withstand voltage n-channel MOSFET 41a is wider than the width Wd of the universal contact region (51, 52) which is the drain region of the high withstand voltage n-channel MOSFET 41a. Further, the effective channel width defined by the width of the p-type base region 61 of the portion overlapping the gate electrode 402 is also substantially the same as the width Ws of the n ⁺ type source region 53, and is the width of the universal contact region (51, 52). Wider than Wd.

The width Ws of the n ⁺ type source region 53 is the width between both ends of the n ⁺ type source region 53, and as shown in FIG. 6, a p ⁺ type contact region 56 is provided between the n ⁺ type source regions 53. May be. Although the p ⁺ type contact region 56 is provided between the n ⁺ type source regions 53 in FIG. 6, it is not necessary to provide the p ⁺ type contact region 56 between the n ⁺ type source regions 53. In that case, the n ⁺ type source region 53 may have a planar pattern extending linearly.

FIG. 7 shows a planar pattern of the universal contact region (51, 52). Each of the p ⁺ type contact regions 51 has a rectangular planar shape and is provided in an island shape. The n ⁺ type contact region 52 is provided so as to surround the p ⁺ type contact region 51. In FIG. 7, the plane pattern of the contact portion of the universal electrode 401 is shown by a broken line. Here, the case where the plane pattern of the contact portion of the universal electrode 401 is rectangular is illustrated, but it may be a line shape extending in the longitudinal direction of the universal contact region (51, 52).

The p ⁺ type contact region 51 and the n ⁺ type contact region 52 are each formed by using a separate ion implantation mask. For example, after forming the p ⁺ type contact region 51, the n ⁺ type contact region 52 deeper than the p ⁺ type contact region 51 may be selectively formed from the surface of the p ⁺ type contact region 51.

By setting the drain region of the high withstand voltage n-channel MOSFET 41a as the universal contact region (51, 52), when a negative surge voltage is applied to the H- VDD terminal via the Vs terminal 110, as shown in FIG. Holes, which are minority carriers flowing through the parasitic body diode 42, can be quickly extracted from the universal electrode 401. As a result, the reverse recovery current Irr (hole current) when the Vs potential is restored and the body diode 42 is in the reverse recovery state can be reduced, and the n ⁺ type source region 53, the p-type base region 61, and the p-type base region 61 can be reduced. By suppressing the operation of the parasitic npn bipolar transistor composed of the n ^- type withstand voltage region 4, it is possible to prevent the level shift circuit from malfunctioning or thermal runaway destruction due to the parasitic operation.

In order to enhance the extraction effect of hole carriers in the n ^- type withstand voltage region 4 and the n-type well region 3 of the body diode 42 of the high withstand voltage n-channel MOSFET 41a during the period when the negative surge voltage is applied to the Vs terminal 110. In the universal contact region (51, 52), it is desirable to increase the proportion of the p ⁺ type contact region 51 as compared with the n ⁺ type contact region 52.

However, increasing the proportion of the p ⁺ type contact region 51 not only increases the drain contact resistance of the high withstand voltage n-channel MOSFET 41a and causes a decrease in the on-current, but also increases the ratio from the H— VDD terminal to the n ⁺ type contact region 52. When a positive surge such as electrostatic discharge (ESD) is input, the body diode 42 is in a reverse bias state and avalanche breakdown occurs. At this time, a large number of electrons generated by the avalanche breakdown flow in the n-type well region 3 as carriers. This electron is taken into the n ⁺ type contact region 52 of the universal contact region (51, 52). When the p ⁺ type contact region 51 is arranged in a wide double or triple line shape so as to surround the n ⁺ type contact region 52, the resistance in the n-type well region 3 directly below the p ⁺ type contact region 51 ( Base resistance) becomes high. Therefore, when a voltage drop of 0.6 V occurs in the n-type well region 3 directly under the p ⁺ type contact region 51, the parasitic pnp composed of the p-type semiconductor layer 1, the n-type well region 3 and the p ⁺ type contact region 51 Bipolar transistors operate and may lead to current destruction.

In order to suppress such parasitic pnp bipolar transistor operation, as shown in FIG. 7, the n ⁺ type contact region 52 is arranged on the outer periphery, and the p ⁺ type contact region 51 is lined in the n ⁺ type contact region 52. It is desirable to arrange two or more layers (an example of a double structure in FIG. 7) so that they are alternately overlapped in a short island shape instead of a shape. Then, the contact of the universal electrode 401 is formed so as to straddle the n ⁺ type contact region 52 and the p ⁺ type contact region 51. When arranged in this way, electrons can be absorbed even in the n ⁺ type contact region 52 sandwiched between the p ⁺ type contact regions 51, so that the local increase in the base resistance is suppressed and the parasitic pnp bipolar transistor operation is performed. It can be suppressed.

As the plane pattern of the universal contact region (51, 52), the plane pattern of the p ⁺ type contact region 51 provided in an island shape may be a circle or a polygon such as a quadrangle. Further, the n ⁺ type contact region 52 and the p ⁺ type contact region 51 may be formed in a striped shape (for example, in a striped shape) in contact with each other. By arranging the n ⁺ type contact region 52 on the outer peripheral side, it is possible to suppress a significant decrease in the on-current of the high withstand voltage n-channel MOSFET 41a, so that it is possible to prevent the parasitic pnp bipolar transistor operation without impairing the stability of the level shift operation. Become.

Although not shown in FIG. 3, as shown in FIG. 4, a resistance (level shift resistance) 173 is provided on the n-type well region 3 via the insulating film 81. The level shift resistor 173 corresponds to the level shift resistor 73 in the equivalent circuit diagram shown in FIG. The level shift resistor 173 can be made of, for example, polysilicon. The level shift resistor 173 can be formed in the same layer as or in a different layer from the gate electrode 402 of the high withstand voltage n-channel MOSFET 41a.

A first electrode 501 and a second electrode 502 are provided on the upper surface side of the level shift resistor 173. The first electrode 501 and the second electrode 502 are electrically connected to both ends of the level shift resistance 173. In FIG. 4, for convenience, the electrical connection between the pickup electrode 203a and the first electrode 501 is shown by a solid line, but it is formed by a wiring layer of the same layer as the pickup electrode 203a and the first electrode 501, or a wiring layer of a different layer. , The pickup electrode 203a and the first electrode 501 may be connected to each other via vias. Further, in FIG. 4, for convenience, the electrical connection between the universal electrode 401 and the second electrode 502 is shown by a solid line, but it may be a wiring layer in the same layer as the universal electrode 401 and the second electrode 502, or a wiring layer in a different layer. It may be formed and connected to the universal electrode 401 and the second electrode 502 via a via. The pickup electrode 203a is electrically connected to the universal contact region (51, 52), which is the drain region of the high withstand voltage n-channel MOSFET 41a, via the level shift resistor 173.

Regarding the manufacturing process of the semiconductor device according to the first embodiment of the present invention, the n ^- type pressure resistant region 4, the n-type well region 3, the p-type base region 61 and the p-type junction separation region 63 are subjected to a patterning step to obtain phosphorus or the like. It is formed by ion-implanting n-type impurities or p-type impurities such as boron, and then diffusing to a predetermined diffusion depth in a diffusion step of, for example, a high temperature (about 1100 to 1200 ° C.). Further, the Vs potential region 200 provided in the high-side circuit section, the well region of the low-side circuit section, and the like are, for example, an n ^- type withstand voltage region 4, an n-type well region 3, and a p-type base at a high temperature (about 1100-1200 ° C.). It is formed by diffusing to a predetermined diffusion depth in a diffusion step different from the diffusion step for forming the region 61 and the p-type junction separation region 63.

In the n ⁺ type pickup region 62, for example, an n-type impurity such as arsenic is ion-implanted so as to have a surface concentration of about 1 × 10 ²⁰ / cm ³ , and then a predetermined annealing step is performed, for example, at about 750 to 900 ° C. Formed at depth. The n ⁺ source region 53 and the n ⁺ type contact region 52 of the high withstand voltage n-channel MOSFET 41a are also formed by ion implantation and annealing treatment, similarly to the n ⁺ type pickup region 62. The p ⁺ type contact region 56 and the p ⁺ type contact region 51 are subjected to a patterning step for forming the p ⁺ region, and for example, BF ₂ is ion-implanted so as to have a surface concentration of about 1 × 10 ²⁰ / cm ³ . For example, it is formed at a predetermined diffusion depth by the same annealing step of about 750 to 900 ° C. as described above.

<Comparison example>
Next, a conventional self-shielding HVIC will be described as a comparative example. FIG. 9 is a plan layout of the HVIC according to the comparative example, and FIG. 10 is a cross-sectional view including a high withstand voltage n-channel MOSFET 41a as seen from the direction of AA'in FIG. In FIG. 9, the parasitic resistances Rs1, Rr1, and Rsr inherent in the self-shielding HVIC are schematically shown. Such parasitic resistances Rs1, Rr1, and Rsr are also inherent in the semiconductor device according to the first embodiment shown in FIG.

As shown in FIGS. 9 and 10, the HVIC according to the comparative example is a semiconductor according to the first embodiment shown in FIG. 3 in that the n ⁺ type drain region 52 of the high withstand voltage n-channel MOSFET 41a is not a universal contact region. Different from the device. Further, the width Ws of the n ⁺ type source region 53 of the high withstand voltage n channel MOSFET 41a is the same as the width Wd of the n ⁺ type drain region 52, which is different from the semiconductor device according to the first embodiment shown in FIG. .. The high withstand voltage n-channel MOSFET 41b has the same structure as the high withstand voltage n-channel MOSFET 41a.

When driving the IGBT 115 of the upper arm shown in FIG. 1 using the HVIC according to the comparative example, the high-side circuit constituting the HVIC when the IGBT 115 of the upper arm is turned off or when the IGBT 114 of the lower arm is turned on. The potential of the Vs terminal and the potential of the H— VDD terminal, which are the reference potentials on the high potential side of the unit, fluctuate to the negative potential side with respect to the GND potential. This fluctuation to the negative potential side (negative surge voltage) causes a malfunction or latch-up of the high-side circuit portion, which may lead to destruction of the HVIC.

When the negative surge voltage VS0 becomes lower than the GND potential (0V)-(Vspy + Vfd), the parasitic pn diode of the HVIC begins to conduct. However, Vspy is the battery voltage between both ends of the high-side low-voltage power supply 113 or a bootstrap capacitor (not shown), and Vfd is the forward voltage drop of the parasitic pn diode. When the negative surge voltage VS0 is greatly pulled in the negative direction, an overcurrent flows in the HVIC, and as a result, a malfunction occurs in the high-side circuit section and the high withstand voltage n-channel MOSFETs 41a and 41b, which are level shifters, parasitize. Therefore, there is a risk that the HVIC will be destroyed.

The applied negative surge voltage VS0 is the product of the parasitic inductance component L1 due to the wiring on the printed circuit board and the cable up to the L load 118 and the dI1 / dt due to the off period of the on-current I1 flowing through the IGBT 115 {L1 ×. (DI1 / dt)}, this spike-shaped negative surge voltage VS0 is applied to the Vs terminal. The applied voltage varies depending on the above-mentioned inductance, the on-current of the IGBT, the transient VF characteristic of the FWD, etc., but is about −50 V, and the applied period is about 100 to 500 ns.

On the other hand, according to the semiconductor device according to the first embodiment of the present invention, the drain region of the high withstand voltage n-channel MOSFETs 41a and 41b is set to the universal contact region (51, 52), so that the Vs terminal 110 has a negative surge. The hole carriers can be efficiently extracted in the p ⁺ type contact region 51 of the universal contact region (51, 52) by the body diode current flowing when the voltage is input, and the residual carriers can be reduced. Therefore, the reverse recovery current Irr (hole current) when the Vs potential is recovered can be reduced, and the operation of the parasitic npn bipolar transistor triggered by the reverse recovery current Irr can be suppressed. Therefore, in the self-shielding type HVIC111, the noise immunity against the negative surge voltage of the Vs terminal is improved, and it is possible to realize a tough and highly reliable HVIC111 that does not cause malfunction or destruction.

Further, in the self-shielding type HVIC 111, the width Ws of the n ⁺ type source region 53 of the high withstand voltage n-channel MOSFETs 41a and 41b which are level shifters is set to the universal contact region (51, 52) which is the drain region of the high withstand voltage n-channel MOSFETs 41a and 41b. By making the width Wd wider than the width Wd of), the carrier density under the n ⁺ type source region 53 of the minority carriers (holes) that try to return from the drain side during the reverse recovery of the body diode 42 can be reduced, and the n ⁺ type can be reduced. It is possible to suppress the voltage drop in the p-type base region 61 under the source region 53 and prevent the operation of the parasitic npn bipolar transistor.

Further, the area required to form the universal contact region (51, 52) as the drain region of the high withstand voltage n-channel MOSFETs 41a and 41b is the n ⁺ type drain region in the HVIC of the comparative example shown in FIGS. 9 and 10. It is the same as the area of 52. Therefore, the chip size does not increase and the process man-hours do not change, so that the manufacturing cost does not increase.

In the semiconductor device according to the first embodiment of the present invention, the width Ws of the n ⁺ type source region 53 of the high withstand voltage n-channel MOSFETs 41a and 41b, which are level shifters, is set to the n ⁺ type drain region of the high withstand voltage n-channel MOSFETs 41a and 41b. Although it is wider than the width of 52, the width Ws of the n ⁺ type source region 53 and the width Wd of the universal contact region (51, 52) are substantially the same as in the HVIC according to the comparative examples shown in FIGS. 9 and 10. May be. In that case, the drain region of the high withstand voltage n-channel MOSFETs 41a and 41b may be the universal contact region (51, 52).

(Second Embodiment)
FIG. 11 is a plan view showing a main part of the semiconductor device (HVIC) according to the second embodiment of the present invention, and FIG. 12 shows a high withstand voltage n-channel MOSFET 41a seen from the direction of AA'in FIG. It is a sectional view including. As shown in FIGS. 11 and 12, the HVIC according to the second embodiment of the present invention has a high withstand voltage n-channel MOSFET 41a, 41b among the pickup regions (62a, 64), 62b, 62c, 62d of the H— VDD potential. It is different from the semiconductor device according to the first embodiment of the present invention shown in FIG. 3 in that the contact of the pickup region (62a, 64) in the vicinity of the drain region of the above is used as the universal contact region.

As shown in FIGS. 11 and 12, in the pickup regions (62a, 64), the n ⁺ type pickup regions 62a and the p ⁺ type contact regions 64 are alternately arranged in contact with each other along the surface of the p-type semiconductor layer 1. It constitutes a universal contact area. The pickup region (62a, 64) and the pickup electrode 203a form a universal contact structure (62a, 64, 203a).

The planar pattern of the pickup region (62a, 64) is the same as the planar pattern of the universal contact region (51, 52) shown in FIG. 7. For example, each of the p ⁺ type contact regions 64 has a rectangular planar shape and is provided in an island shape. The n ⁺ type pickup region 62a is provided so as to surround the p ⁺ type contact region 51. Other configurations of the semiconductor device according to the second embodiment of the present invention are the same as those of the semiconductor device according to the first embodiment of the present invention, and duplicate description will be omitted.

According to the semiconductor device according to the second embodiment of the present invention, the pickup region (62a, 64) of the H- VDD potential near the drain region of the high withstand voltage n-channel MOSFETs 41a, 41b is set as the universal contact region. The amount of hole carriers that penetrate the p-type junction separation region 63 and flow into the body diode 42 can be reduced. Therefore, it is possible to prevent the operation of the parasitic npn bipolar transistor due to the reverse recovery phenomenon of the body diode 42 at the time of recovery from the negative surge of the Vs potential.

(Third Embodiment)
FIG. 13 is a plan view showing a main part of the semiconductor device (HVIC) according to the third embodiment of the present invention, and FIG. 14 shows a high withstand voltage n-channel MOSFET 41a seen from the direction of AA'in FIG. It is a sectional view including. In the HVIC according to the second embodiment of the present invention, as shown in FIGS. 13 and 14, the drain region 52 of the high withstand voltage n-channel MOSFETs 41a and 41b is not a universal contact region. It is different from the semiconductor device according to the second embodiment.

According to the semiconductor device according to the third embodiment of the present invention, the pickup region (62a, 64) of the H— VDD potential near the drain region 52 of the high withstand voltage n-channel MOSFETs 41a, 41b is set as the universal contact region. , The amount of hole carriers that penetrate the p-type junction separation region 63 and flow into the body diode 42 can be reduced. Therefore, it is possible to prevent the operation of the parasitic npn bipolar transistor due to the reverse recovery phenomenon of the body diode 42 at the time of recovery from the negative surge of the Vs potential. Therefore, the on-current of the high withstand voltage n-channel MOSFETs 41a and 41b can be increased as compared with the second embodiment.

In the second embodiment and the third embodiment, the pickup region (62a, 64) as the universal contact region is inside the drain region of the high withstand voltage n-channel MOSFETs 41a, 41b on the plane pattern, and is in the high-side circuit region 301. It is desirable that the circuit unit is arranged outside the high-side circuit unit (the region connected to the Vs potential region 200, the H- VDD potential region 201, the Vs potential region 200, and the H- VDD potential region 201). Further, it is desirable that the pickup regions (62a, 64) are arranged between the drain region of the high withstand voltage n-channel MOSFETs 41a, 41b and the high-side circuit portion on a planar pattern. Further, it is desirable that the pickup region (62a, 64) has a distance of 100 μm or less from the drain region of the high withstand voltage n-channel MOSFETs 41a, 41b on the plane pattern. With such a configuration, the amount of hole carriers that penetrate the p-type junction separation region 63 and flow into the body diode 42 can be reduced. Therefore, it is possible to prevent the operation of the parasitic npn bipolar transistor due to the reverse recovery phenomenon of the body diode 42 at the time of recovery from the negative surge of the Vs potential.

(Fourth Embodiment)
FIG. 15 is a plan view of the periphery of the high withstand voltage n-channel MOSFET 41a of the semiconductor device (HVIC) according to the fourth embodiment of the present invention. As shown in FIG. 15, in the semiconductor device according to the fourth embodiment of the present invention, the density of the n ⁺ type source region 53 of the high withstand voltage n-channel MOSFET 41a is higher than the position facing the universal contact region (51, 52). , The high point at a position not facing the universal contact region (51, 52) is different from the semiconductor device according to the first embodiment of the present invention shown in FIG.

As shown in FIG. 15, the n ⁺ type source region 53 sandwiches a plurality of facing regions 53a provided at positions facing the universal contact region (51, 52) and a plurality of facing regions 53a, and is a universal contact region (universal contact region). It has end regions (overhanging regions) 53b and 53c provided at positions not facing 51, 52). The plurality of facing regions 53a are rectangular planar patterns, and are provided parallel to the universal contact regions (51, 52) and separated from each other. The end regions 53b, 53c have a linear planar pattern.

Although not shown, the high withstand voltage n-channel MOSFET 41b shown in FIG. 3 has the same structure as the high withstand voltage n-channel MOSFET 41a shown in FIG. Other configurations of the semiconductor device according to the fourth embodiment of the present invention are the same as those of the semiconductor device according to the first embodiment of the present invention, and duplicate description will be omitted.

According to the semiconductor device according to the fourth embodiment of the present invention, as shown in FIG. 15, the drain current Id of the high withstand voltage n-channel MOSFET 41a is the end region 53b at a position not facing the universal contact region (51, 52). , 53c is also supplied, and it is possible to secure the drain current Id required for the operation of the level shift circuit. On the other hand, by arranging the plurality of facing regions 53a at positions facing the universal contact regions (51, 52) alternately with the p ⁺ type contact region 56, the reverse recovery current Irr at the time of reverse recovery is a plurality of low impedances. Since it concentrates on the facing region 53a of the above, it is possible to suppress the operation of the parasitic npn bipolar transistor from the voltage drop under the plurality of facing regions 53a. That is, it is possible to suppress the operation of the parasitic npn bipolar transistor at the time of reverse recovery while maintaining the operation margin of the level shift circuit.

In the semiconductor device according to the fourth embodiment, the drain region of the high withstand voltage n-channel MOSFET 41a is a universal contact region (51, 52), but n is the same as the HVIC according to the comparative example shown in FIGS. 9 and 10. ^{The +} type drain region 52 may be used.

(Fifth Embodiment)
FIG. 16 is a plan view of the periphery of the high withstand voltage n-channel MOSFET 41a and the pickup region (62a, 64) of the semiconductor device (HVIC) according to the fifth embodiment of the present invention. FIG. 17 is a cross-sectional view of the semiconductor device according to the fifth embodiment of the present invention, and corresponds to the position seen from the direction of AA'in FIG.

As shown in FIGS. 16 and 17, the semiconductor device according to the fifth embodiment of the present invention has a pickup region (62a, 64) configuration according to the first embodiment of the present invention shown in FIG. Is different. Further, the point that the drain region of the high withstand voltage n-channel MOSFET 41a is the n ⁺ type drain region 52 is different from the semiconductor device according to the first embodiment of the present invention shown in FIG.

As shown in FIG. 16, the pickup region (62a, 64) has an n ⁺ type pickup region 62a and a p ⁺ type contact region 64 that extend linearly (line-like) on a plane pattern and are in contact with each other. The n ⁺ type pickup area 62a and the p ⁺ type contact area 64 constitute a universal contact area.

As shown in FIG. 17, a pickup electrode 203a that makes ohmic contact with the pickup region (62a, 64) is provided on the pickup region (62a, 64). The pickup region (62a, 64) and the pickup electrode 203a form a universal contact structure (62a, 64, 203a).

Although not shown, the high withstand voltage n-channel MOSFET 41b shown in FIG. 3 has the same structure as the high withstand voltage n-channel MOSFET 41a shown in FIGS. 16 and 17. Other configurations of the semiconductor device according to the fifth embodiment of the present invention are the same as those of the semiconductor device according to the first embodiment of the present invention, and duplicate description will be omitted.

According to the semiconductor device according to the fifth embodiment of the present invention, a line-shaped n ⁺ type pickup region (62a, 64) in the vicinity of the drain region of the high withstand voltage n-channel MOSFETs 41a, 41b is defined as a line-shaped pick-up region (62a, 64). By making the universal contact region composed of 62a and the p ⁺ type contact region 64, the hole carrier extraction effect can be enhanced, and the amount of hole carriers that penetrate the p-type junction separation region 63 and flow into the body diode 42. Can be reduced.

(Sixth Embodiment)
FIG. 18 is a plan view of the periphery of the high withstand voltage n-channel MOSFET 41a and the pickup region (62a, 64) of the semiconductor device (HVIC) according to the sixth embodiment of the present invention. FIG. 19 is a cross-sectional view of the semiconductor device according to the sixth embodiment of the present invention, and corresponds to the position seen from the direction of AA'in FIG.

In the semiconductor device according to the sixth embodiment of the present invention, as shown in FIGS. 18 and 19, the drain region of the high withstand voltage n-channel MOSFET 41a is composed of a universal contact region (51, 52). It is different from the semiconductor device according to the fifth embodiment of the present invention shown in 16 and 17. As shown in FIG. 18, the universal contact region (51, 52) has a p ⁺ type contact region 51 and an n ⁺ type contact region 52 that extend linearly (line-shaped) on a planar pattern and are in contact with each other.

As shown in FIG. 19, a universal electrode (universal contact) 401 that makes ohmic contact with the universal contact region (51, 52) is provided on the universal contact region (51, 52). The universal contact region (51, 52) and the universal electrode 401 constitute a universal contact structure (51, 52, 401).

Although not shown, the high withstand voltage n-channel MOSFET 41b shown in FIG. 3 has the same structure as the high withstand voltage n-channel MOSFET 41a shown in FIGS. 18 and 19. Other configurations of the semiconductor device according to the sixth embodiment of the present invention are the same as those of the semiconductor device according to the fifth embodiment of the present invention, and duplicate description will be omitted.

According to the semiconductor device according to the sixth embodiment of the present invention, the drain region of the high withstand voltage n-channel MOSFET 41a is a universal contact region (51) composed of a line-shaped p ⁺ type contact region 51 and an n ⁺ type contact region 52. , 52), it is possible to enhance the effect of extracting holes, which are minority carriers flowing through the parasitic body diode, when a negative surge voltage is applied, and to quickly extract holes from the universal electrode 401.

(7th Embodiment)
FIG. 20 is a plan view showing a main part of the semiconductor device according to the seventh embodiment of the present invention. 21 is a cross-sectional view including a high withstand voltage n-channel MOSFET 41a seen from the direction AA'of FIG. 20, and FIG. 22 is a cross-sectional view seen from the direction BB'of FIG. 20.

As shown in FIGS. 20 to 22, trenches 65 formed on the surface of the p-type semiconductor layer 1 are provided in an annular shape on the surface side of the p-type base region 61. Further, a p ⁺ type trench contact region (p ⁺ type high concentration base region) 57 having a higher impurity concentration than the p-type base region 61 formed on the side wall of the trench 65 is provided in an annular shape. As shown in FIGS. 20 and 22, the p ⁺ type trench contact region 57 is connected to a pickup electrode (pickup contact) 202 connected to the GND potential.

As shown in FIG. 21, in the high withstand voltage n-channel MOSFET 41a seen from the AA'direction of FIG. 20, the p ⁺ type trench contact region 57 is formed on the side wall and the lower surface of the trench 65 so as to surround the circumference of the trench 65. I'm in contact. The p ⁺ type trench contact region 57 is provided in contact with the side surface and the lower surface of the n ⁺ type source region 53.

A source electrode (trench contact electrode) 400 is provided on the p ⁺ type trench contact region 57 and the n ⁺ type source region 53. The source electrode 400 is embedded in the trench 65 and is in ohmic contact with the p ⁺ type trench contact region 57 on the side wall and bottom surface of the trench 65. That is, the source electrode 400 and the pickup electrode (pickup contact) 202 connected to the GND potential are short-circuited at the same potential. Further, the source electrode 400 is in ohmic contact with the n ⁺ type source region 53 via the contact.

The p ⁺ type trench contact region 57 is formed in a normal flat active region, for example, the p ⁺ type contact region 56 used as a source / drain region of a pickup region 202 of a GND potential or a p-channel MOSFET constituting a logic circuit. It is formed using a separate ion implantation mask. For example, after forming a polysilicon pattern, a trench 65 is dug in the region where the p ⁺ type trench contact region 5 is formed, a buffer oxide film is deposited, and a mask for ion implantation into the trench 65 is used to form boron ( ¹¹ B). The impurities are formed at high concentration by quadrant oblique ion implantation. After that, the p ⁺ type contact region 56, which is the source / drain region of the p-channel MOSFET constituting the logic circuit, and the n ⁺ type contact regions 52, 53, which are the source / drain regions of the high withstand voltage n-channel MOSFET 41a, are selectively formed. .. By using boron ( ¹¹ B) as an ion-implanted impurity for the formation of the p ⁺ -type trench contact region 57, it diffuses deeper than the n ⁺ -type contact region 52, which generally uses arsenic ( ⁷⁵ As), in the trench 65. It is formed by laterally diffusing not only to the side wall but also to the bottom of the n ⁺ type source region 53 of the high withstand voltage n-channel MOSFET 41a.

Although not shown, the high withstand voltage n-channel MOSFET 41b shown in FIG. 20 has the same structure as the high withstand voltage n-channel MOSFET 41a shown in FIG. 21. Other configurations of the semiconductor device according to the seventh embodiment of the present invention are the same as those of the semiconductor device according to the first embodiment of the present invention, and duplicate description will be omitted.

According to the semiconductor device according to the seventh embodiment of the present invention, the p ⁺ type trench contact region (high concentration base region) 57 is formed so as to be in contact with the lower surface of the n ⁺ type source region 53 of the high withstand voltage n channel MOSFET 41a. Therefore, when a negative surge voltage is applied to the H- VDD terminal (such as the pickup electrode 203a connected to the H- VDD terminal) via the Vs terminal 110, the forward current of the parasitic body diode 42 is H from the GND terminal. -Excessive flow toward the VDD terminal. After that, when the Vs potential is restored and the voltage of the H— VDD potential is also restored, the parasitic diode 42 is in a reverse recovery state.

At that time, as shown in FIG. 23, holes, which are minority carriers, excessively flow to the bottom of the n ⁺ type source region 53 via the p-type semiconductor layer 1 and the n ^- type withstand voltage region 4, but p in the previous stage. Holes can be quickly extracted due to the existence of the extraction structure of the ⁺ -type trench contact region 57. As a result, even if the Vs potential is restored and the excess reverse recovery current Irr (hole current) of the body diode 42 flows in, the voltage is 0.6 V or more in the p-type base region 61 under the n ⁺ type source region 53. The operation of the parasitic npn bipolar transistor composed of the n ⁺ type source region 53, the p-type base region 61, and the n ^- type withstand voltage region 4 is suppressed without the occurrence of a drop, and the thermal runaway due to the malfunction of the level shift circuit or the parasitic operation is suppressed. It is possible to prevent destruction and the like.

The p ⁺ type trench contact region (p ⁺ type high concentration base region) 57 in contact with the trench 65 of the semiconductor device according to the seventh embodiment of the present invention and the source electrode (trench contact electrode) 400 embedded in the trench 65. The structure is such that the density of the n ⁺ type source region 53 of the semiconductor device according to the fourth embodiment of the present invention shown in FIG. 15 is closer to the universal contact region (51, 52) than the position facing the universal contact region (51, 52). It can also be applied to a high structure at a position not facing 51, 52).

(8th Embodiment)
FIG. 24 is a plan view showing a high withstand voltage n-channel MOSFET 41a of the semiconductor device (HVIC) according to the eighth embodiment of the present invention. In the semiconductor device according to the seventh embodiment of the present invention described above, the n ^- type withstand voltage region 4 and the n-type well of the body diode 42 of the high withstand voltage n-channel MOSFET 41a during the period when the negative surge voltage is applied to the Vs terminal 110. In order to enhance the hole carrier extraction effect in the region 3, it is desirable to expand a high-concentration p ⁺ type region under the n ⁺ source region 53.

However, in an attempt to surround the entire area under the n ⁺ type contact region 53 with the p ⁺ type trench contact region 57, the high concentration p ⁺ type trench contact region 57 is excessively expanded by the excessive ion implantation dose amount and the high acceleration voltage ion implantation. On the contrary, by making the n ⁺ type contact region (n ⁺ type source region) 53 width of the source too narrow, the source contact resistance of the high withstand voltage n-channel MOSFET 41a is increased, and the on-current is significantly reduced. There is a possibility that the value voltage will rise.

Therefore, in the semiconductor device according to the eighth embodiment of the present invention, as shown in FIG. 24, the n ⁺ source region 53 is divided into a plurality of pieces instead of the line shape, and the n + source region 53 is divided between the plurality of n ⁺ source regions 53. Arranged so as to sandwich the p ⁺ type contact area 56. The number of divisions, the size, the interval, etc. of the n ⁺ source area 53 are not particularly limited. Further, a contact of the source electrode 400 is formed so as to straddle the n ⁺ source region 53 and the p ⁺ type contact region 56.

Although not shown, the high withstand voltage n-channel MOSFET 41b also has the same structure as the high withstand voltage n-channel MOSFET 41a shown in FIG. 24. Other configurations of the semiconductor device according to the eighth embodiment of the present invention are the same as those of the semiconductor device according to the seventh embodiment of the present invention, and duplicate description will be omitted.

According to the semiconductor device according to the eighth embodiment of the present invention, holes, which are minority carriers, can be absorbed even in the p ⁺ type contact region 56 sandwiched between the n ⁺ source region 53, and therefore the n ⁺ source region 53. The increase in base resistance can be suppressed and the operation of the parasitic npn bipolar transistor can be suppressed without surrounding the entire lower area with the p ⁺ type trench contact region 57.

Regarding the manufacturing process of the semiconductor device according to the 7th and 8th embodiments of the present invention, the n ^- type pressure resistant region 4, the n-type well region 3, the p-type base region 61 and the p-type junction separation region 63 have undergone a patterning step. It is formed by ion-injecting n-type impurities such as phosphorus or p-type impurities such as boron, and then diffusing to a predetermined diffusion depth in, for example, a high temperature (about 1100-1200 ° C.) diffusion step. Further, the Vs potential region 200 provided in the high-side circuit section, the well region of the low-side circuit section, and the like are, for example, an n ^- type withstand voltage region 4, an n-type well region 3, and a p-type base at a high temperature (about 1100-1200 ° C.). It is formed by diffusing to a predetermined diffusion depth in a diffusion step different from the diffusion step for forming the region 61 and the p-type junction separation region 63.

In the n ⁺ type pickup region 62, for example, an n-type impurity such as arsenic is ion-implanted so as to have a surface concentration of about 1 × 10 ²⁰ / cm ³ , and then a predetermined annealing step is performed, for example, at about 750 to 900 ° C. Formed at depth. The n ⁺ source region 53 and the n ⁺ type contact region 52 of the high withstand voltage n-channel MOSFET 41a are also formed by ion implantation and annealing treatment, similarly to the n ⁺ type pickup region 62.

The p ⁺ type contact region 56 is subjected to a patterning step for forming the p ⁺ region, for example, BF ₂ is ion-implanted so as to have a surface concentration of about 1 × 10 ²⁰ / cm ³ , and then, for example, the n ⁺ type pickup region 62. Each is formed at a predetermined diffusion depth by the annealing step of about 750 to 900 ° C., which is the same as the annealing step of.

The p ⁺ type trench contact region 57 has a trench 65 with a depth of about 0.5 to 5.0 μm and a width of about 0.5 to 5.0 μm in the region adjacent to the n ⁺ source region 53 after forming the polysilicon pattern. Dry etching and digging, depositing a buffer oxide film, and using a mask for ion implantation into the trench groove region, the concentration of boron (B11) impurities on the side wall of the trench is 1 × 10 ¹⁹ to 1 × 10 ²⁰ / cm ³ It is formed by oblique ion implantation in four divisions so as to be about the same, and each has a predetermined diffusion depth by an annealing step of about 750 to 900 ° C., which is the same as the annealing step of the n ⁺ type pickup region 62 and the p ⁺ type contact region 56. It is formed by silicon. It should be noted that 0 ° ion implantation may be used in combination so that boron impurities also enter the bottom surface of the trench when the oblique ion implantation is performed in four divisions.

(9th Embodiment)
FIG. 25 is a cross-sectional view of the semiconductor device (HVIC) according to the ninth embodiment of the present invention, and corresponds to the cross section of the semiconductor device according to the seventh embodiment of the present invention shown in FIG. 21. As shown in FIG. 25, the semiconductor device according to the ninth embodiment of the present invention includes a p ⁺ type trench contact region (p ⁺ type high concentration base region) 57 in contact with the trench 65 and a source electrode embedded in the trench 65. The point of having the trench contact electrode) 400 is the same as that of the semiconductor device according to the seventh embodiment of the present invention shown in FIG.

However, in the semiconductor device according to the ninth embodiment of the present invention, the high withstand voltage n-channel MOSFET 41a has a universal contact region (51, 52) which is a drain region provided on the surface layer of the n-type well region 3. However, it is different from the semiconductor device according to the seventh embodiment of the present invention shown in FIG. The universal contact region (51, 52) is configured such that the p ⁺ type contact region 51 and the n ⁺ type contact region 52 are alternately arranged in contact with each other along the surface of the p-type semiconductor layer 1.

Further, in the semiconductor device according to the ninth embodiment of the present invention, the contact of the pickup region (62a, 64) near the drain region of the high withstand voltage n-channel MOSFET 41a is a universal contact region, which is shown in FIG. 21. It is different from the semiconductor device according to the seventh embodiment of the present invention shown. As shown in FIGS. 11 and 12, in the pickup regions (62a, 64), the n ⁺ type pickup regions 62a and the p ⁺ type contact regions 64 are alternately arranged in contact with each other along the surface of the p-type semiconductor layer 1. It constitutes a universal contact area.

Although not shown, the high withstand voltage n-channel MOSFET 41b also has the same structure as the high withstand voltage n-channel MOSFET 41a shown in FIG. 25. Other configurations of the semiconductor device according to the ninth embodiment of the present invention are the same as those of the semiconductor device according to the seventh embodiment of the present invention, and duplicate description will be omitted.

According to the semiconductor device according to the ninth embodiment of the present invention, the same effect as that of the semiconductor device according to the seventh embodiment of the present invention is obtained. Further, by setting the drain region of the high withstand voltage n-channel MOSFETs 41a and 41b as the universal contact region (51, 52), the hole carrier is universally contacted by the body diode current that flows when a negative surge voltage is input to the Vs terminal 110. Residual carriers can be reduced by efficiently drawing out in the p ⁺ type contact region 51 of the region (51, 52). Therefore, the reverse recovery current Irr (hole current) when the Vs potential is recovered can be reduced, and the operation of the parasitic npn bipolar transistor triggered by the reverse recovery current Irr can be suppressed.

Further, by setting the pickup region (62a, 64) of the H- VDD potential near the drain region 52 of the high withstand voltage n-channel MOSFETs 41a, 41b as the universal contact region, the body diode 42 penetrates the p-type junction separation region 63. The amount of hole carriers flowing into the can be reduced. Therefore, it is possible to prevent the operation of the parasitic npn bipolar transistor due to the reverse recovery phenomenon of the body diode 42 at the time of recovery from the negative surge of the Vs potential.

(Other embodiments)
As mentioned above, the invention has been described by embodiments 1-9, but the statements and drawings that form part of this disclosure should not be understood to limit the invention. This disclosure will reveal to those skilled in the art various alternative embodiments, examples and operational techniques.

For example, as the semiconductor device according to the first to ninth embodiments, a structure in which an n-type diffusion layer such as an n-type well region 3 is formed on the surface layer of the p-type semiconductor layer 1 has been exemplified, but the present invention is not limited thereto. For example, the same effect can be obtained with a structure in which an n-type epitaxial growth layer is grown on the p-type semiconductor layer 1. Further, the same effect is obtained even when the p-type epitaxial growth layer is grown on the p-type semiconductor layer 1 and the n-type embedded layer is provided at the junction between the p-type epitaxial growth layer and the p-type semiconductor layer 1.

Further, as the semiconductor device according to the first to ninth embodiments, a structure in which high withstand voltage n-channel MOSFETs 41a and 41b are provided on the same side of the annular planar pattern of the HVJT303 has been exemplified, but the present invention is not limited thereto. For example, the high withstand voltage n-channel MOSFETs 41a and 41b may be individually provided on the sides of the annular planar pattern of the HVJT 303 facing each other. When this structure is adopted in the second embodiment, the contacts in the pickup region closest to the drain regions of the high withstand voltage n-channel MOSFETs 41a and 41b may be set as universal contact regions, respectively.

Further, although HVIC is exemplified as the semiconductor device according to the first to ninth embodiments, it can also be applied to a semiconductor device other than the HVIC. For example, it is particularly effective for a semiconductor device to which a high voltage of several tens of volts or more is applied.

1 ... p-type semiconductor layer 2 ... p-type well region 3 ... n-type well region 4 ... n ^- type withstand voltage region 41, 41a, 41b ... level shifter 42 ... body diode 51 ... p ⁺ type contact region 52 ... n ⁺ type contact region (N ⁺ type drain region)
53 ... n ⁺ type source region 53a ... facing regions 53b, 53c ... end region 56 ... p ⁺ type contact region 57 ... p ⁺ type trench contact region (high concentration base region)
61 ... p-type base region 62a, 62b, 62c, 62d ... n ⁺ type pickup region 63 ... p-type junction separation region 64 ... p ⁺ type contact region 65 ... trench (groove portion)
71,72,75,76 ... MOSFET
73 ... Level shift resistance 74 ... Diode 101 ... Output unit 102 ... H- VDD pad 103 ... H-OUT pad 104 ... Vs pad 105 ... H-IN pad 106 ... L- VDD pad 107 ... GND pad 110 ... Vs terminal 111 ... High withstand voltage integrated circuit device (HVIC)
112, 113 ... Low voltage power supply 114, 115 ... IGBT
116, 117 ... Reflux diode 118 ... L load 119 ... Detection signal 120 ... H- VDD terminal 131 ... Low side circuit 132 ... Level shift circuit (level up circuit)
133 ... High-side circuit 173 ... Level shift resistance 200 ... Vs potential region 201 ... H- VDD potential region 202, 203, 203a, 203b, 203c, 203d ... Pickup electrode 301 ... High-side circuit region 302 ... Low-side circuit region 303 ... High Pressure-resistant junction termination region (HVJT)
400 ... Source electrode 401 ... Universal electrode 402 ... Gate electrode 501 ... First electrode 502 ... Second electrode

It is a circuit diagram which shows the connection example of the semiconductor device which concerns on 1st Embodiment of this invention. It is a circuit diagram of the semiconductor device which concerns on 1st Embodiment of this invention. It is a top view which shows the main part of the semiconductor device which concerns on 1st Embodiment of this invention. It is sectional drawing seen from the AA'direction of FIG. It is sectional drawing seen from the BB'direction of FIG. It is a top view around the level shifter which concerns on 1st Embodiment of this invention. It is a top view of the universal contact area which concerns on 1st Embodiment of this invention. It is sectional drawing which shows the behavior of an electron and a hole when a negative surge voltage of the semiconductor device which concerns on 1st Embodiment of this invention is applied. It is a top view of the semiconductor device which concerns on a comparative example. 9 is a cross-sectional view taken from the direction of AA'in FIG. It is a top view which shows the main part of the semiconductor device which concerns on 2nd Embodiment of this invention. It is sectional drawing seen from the AA'direction of FIG. It is a top view which shows the main part of the semiconductor device which concerns on 3rd Embodiment of this invention. It is sectional drawing seen from the AA'direction of FIG. It is a top view around the level shifter which concerns on 4th Embodiment of this invention. It is a top view of the semiconductor device which concerns on 5th Embodiment of this invention. It is sectional drawing of the semiconductor device which concerns on 5th Embodiment of this invention. It is a top view of the semiconductor device which concerns on 6th Embodiment of this invention. It is sectional drawing of the semiconductor device which concerns on 6th Embodiment of this invention. It is a top view of the semiconductor device which concerns on 7th Embodiment of this invention. It is sectional drawing seen from the AA'direction of FIG. It is sectional drawing seen from the BB'direction of FIG. It is sectional drawing which shows the behavior of electron and hole at the time of reverse recovery after the negative surge voltage of the semiconductor device which concerns on 7th Embodiment of this invention is applied. It is a top view around the level shifter which concerns on 8th Embodiment of this invention. It is sectional drawing of the semiconductor device which concerns on 9th Embodiment of this invention.

In the semiconductor device according to the first embodiment of the present invention, the width Ws of the n ⁺ type source region 53 of the high withstand voltage n-channel MOSFETs 41a and 41b, which are level shifters, is universal as the drain region of the high withstand voltage n-channel MOSFETs 41a and 41b. Although the width Wd of the contact region (51, 52) is wider than the width Wd of the n ⁺ type source region 53, the width Ws of the n + type source region 53 and the universal contact region (51, 52) are similar to the HVIC according to the comparative examples shown in FIGS. 9 and 10. The width Wd of the above may be substantially the same. In that case, the drain region of the high withstand voltage n-channel MOSFETs 41a and 41b may be the universal contact region (51, 52).

The planar pattern of the pickup region (62a, 64) is the same as the planar pattern of the universal contact region (51, 52) shown in FIG. 7. For example, each of the p ⁺ type contact regions 64 has a rectangular planar shape and is provided in an island shape. The n ⁺ type pickup area 62a is provided so as to surround the p ⁺ type contact area 64 . Other configurations of the semiconductor device according to the second embodiment of the present invention are the same as those of the semiconductor device according to the first embodiment of the present invention, and duplicate description will be omitted.

(Third Embodiment)
FIG. 13 is a plan view showing a main part of the semiconductor device (HVIC) according to the third embodiment of the present invention, and FIG. 14 shows a high withstand voltage n-channel MOSFET 41a seen from the direction of AA'in FIG. It is a sectional view including. In the HVIC according to the third embodiment of the present invention, as shown in FIGS. 13 and 14, the drain region 52 of the high withstand voltage n-channel MOSFETs 41a and 41b is not a universal contact region. It is different from the semiconductor device according to the second embodiment.

Claims (19)

The high-potential side circuit region, the high-potential junction termination structure provided around the high-potential side circuit region, and the low-potential side provided around the high-potential side circuit region via the high-potential junction termination structure. A semiconductor device in which the circuit area is integrated on the same semiconductor chip.
The first conductive type semiconductor layer and
A second conductive type well region located in the high potential side circuit region and provided on the surface layer of the semiconductor layer,
A second conductive type pressure-resistant region having a lower impurity concentration than the well region, which surrounds the well region and is provided in contact with the well region.
A first conductive type base region that surrounds the pressure-resistant region and is provided in contact with the pressure-resistant region.
A second conductive type provided on the surface layer of the base region, which is a carrier supply region of the level shifter included in the level shift circuit for transmitting a signal between the low potential side circuit region and the high potential side circuit region. Carrier supply area and
The carrier receiving region of the level shifter, which is the carrier receiving region provided on the surface layer of the well region or the pressure resistant region.
Equipped with
A semiconductor device characterized in that the carrier receiving region is composed of a first universal contact region in which a first conductive type region and a second conductive type region are provided in contact with each other. A plurality of pickup areas provided on the surface layer of the well area are further provided.
The semiconductor device according to claim 1, wherein the pickup region is composed of a second universal contact region in which a first conductive type region and a second conductive type region are provided in contact with each other. The second universal contact region according to claim 2, wherein the second universal contact region is the pickup region arranged on the plane pattern outside the circuit portion in the high potential side circuit region and inside the carrier receiving region. Semiconductor equipment. The semiconductor device according to claim 2 or 3, wherein the second universal contact region is the pickup region closest to the carrier receiving region. The semiconductor device according to claim 2 or 3, wherein the second universal contact region has a distance of 100 μm or less from the pickup region closest to the carrier receiving region. The second universal contact region according to claim 3, wherein the second universal contact region is the pickup region arranged between the circuit portion in the high potential side circuit region and the carrier receiving region on a plane pattern. Semiconductor device. On a planar pattern, the carrier supply region and the carrier receiving region are provided in parallel with each other.
The semiconductor device according to any one of claims 1 to 6, wherein the width of the carrier supply region is wider than the width of the carrier receiving region. The seventh aspect of claim 7, wherein the density of the carrier supply region at a position facing the carrier receiving region on the plane pattern is lower than the density of the carrier supply region at a position not facing the carrier receiving region. Semiconductor device. The high-potential side circuit region, the high-potential junction termination structure provided around the high-potential side circuit region, and the low-potential side provided around the high-potential side circuit region via the high-potential junction termination structure. A semiconductor device in which the circuit area is integrated on the same semiconductor chip.
The first conductive type semiconductor layer and
A second conductive type well region located in the high potential side circuit region and provided on the surface layer of the semiconductor layer,
A second conductive type pressure-resistant region having a lower impurity concentration than the well region, which surrounds the well region and is provided in contact with the well region.
A first conductive type base region that surrounds the pressure-resistant region and is provided in contact with the pressure-resistant region.
A second conductive type provided on the surface layer of the base region, which is a carrier supply region of the level shifter included in the level shift circuit for transmitting a signal between the low potential side circuit region and the high potential side circuit region. Carrier supply area and
The carrier receiving region of the level shifter, which is the carrier receiving region provided on the surface layer of the well region or the pressure resistant region.
A plurality of pickup areas provided on the surface layer of the well area, and
Equipped with
A semiconductor device characterized in that the pickup region is composed of a universal contact region in which a first conductive type region and a second conductive type region are provided in contact with each other. The semiconductor according to claim 9, wherein the universal contact region is the pickup region arranged on the plane pattern outside the circuit portion in the high potential side circuit region and inside the carrier receiving region. Device. The semiconductor device according to claim 9 or 10, wherein the universal contact region is the pickup region closest to the carrier receiving region. The semiconductor device according to claim 9 or 10, wherein the universal contact region has a distance of 100 μm or less from the pickup region closest to the carrier receiving region. The semiconductor device according to claim 10, wherein the universal contact region is the pickup region arranged between the circuit portion in the high potential side circuit region and the carrier receiving region on a planar pattern. .. The semiconductor device according to any one of claims 2 to 6, 9 to 13, wherein the pickup region is electrically connected to the carrier receiving region via a resistor. The high-potential side circuit region, the high-potential junction termination structure provided around the high-potential side circuit region, and the low-potential side provided around the high-potential side circuit region via the high-potential junction termination structure. A semiconductor device in which the circuit area is integrated on the same semiconductor chip.
The first conductive type semiconductor layer and
A second conductive type well region located in the high potential side circuit region and provided on the surface layer of the semiconductor layer,
A second conductive type pressure-resistant region having a lower impurity concentration than the well region, which surrounds the well region and is provided in contact with the well region.
A first conductive type base region that surrounds the pressure-resistant region and is provided in contact with the pressure-resistant region.
A second conductive type provided on the surface layer of the base region, which is a carrier supply region of the level shifter included in the level shift circuit for transmitting a signal between the low potential side circuit region and the high potential side circuit region. Carrier supply area and
The carrier receiving region of the level shifter, which is the carrier receiving region provided on the surface layer of the well region or the pressure resistant region.
Equipped with
On a planar pattern, the carrier supply region and the carrier receiving region are provided in parallel with each other.
The width of the carrier supply area is wider than the width of the carrier receiving area,
A semiconductor device characterized in that the density of the carrier supply region at a position facing the carrier receiving region on a planar pattern is lower than the density of the carrier supply region at a position not facing the carrier receiving region. The semiconductor device according to any one of claims 1 to 15, further comprising a first conductive type junction separation region provided so as to penetrate the well region and reach the semiconductor layer. A first conductive type high-concentration base region having a higher impurity concentration than the base region, which is provided in contact with the side wall of the trench provided in the surface layer of the base region and in contact with the carrier supply region.
A trench contact electrode embedded in the trench and ohmic contacting the high concentration base region.
The semiconductor device according to any one of claims 1 to 16, further comprising. The semiconductor device according to claim 17, wherein the high-concentration base region is in contact with the lower surface of the carrier supply region. The semiconductor device according to claim 17 or 18, wherein the high-concentration base region is in contact with the bottom surface of the trench.

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