JP7471812B2 - Semiconductor equipment and devices - Google Patents

Description

The present invention relates to semiconductor devices and equipment.

In recent years, solid-state imaging devices have been proposed in which multiple semiconductor components are stacked. The solid-state imaging device described in Patent Document 1 has multiple stacked components, with a pixel unit provided in the first component and a readout unit that reads out signals from the pixel unit in the second component. In addition to the first and second components, a component dedicated to a bypass capacitor is also stacked.

International Publication No. 2017/187738

However, the solid-state imaging device described in Patent Document 1 requires stacking components dedicated to bypass capacitors, which creates the problem of increased manufacturing costs.

The present invention was made in consideration of the above-mentioned problems, and aims to efficiently arrange the capacitance section while suppressing increases in manufacturing costs.

According to one embodiment of the present disclosure, a semiconductor device is provided that includes a first semiconductor component having a first circuit section, and a second semiconductor component having a second circuit section and stacked on the first semiconductor component, the second semiconductor component having a capacitance section as a decoupling capacitance having a first node and a second node connected to the first circuit section, and the first circuit section is a signal processing circuit that processes a signal output from the second circuit section.

According to another embodiment of the present disclosure, a semiconductor device is provided that includes a first semiconductor component having a first circuit section, and a second semiconductor component having a second circuit section and stacked on the first semiconductor component, the second semiconductor component including a capacitance section having a first node and a second node connected to the first circuit section, and the second semiconductor component further including a shield section provided between the second circuit section and the capacitance section.

According to yet another embodiment of the present disclosure, a semiconductor device is provided, comprising a first semiconductor component having a first circuit section, and a second semiconductor component having a second circuit section and stacked on the first semiconductor component, the second semiconductor component having a capacitance section as a decoupling capacitance having a first node and a second node connected to the first circuit section, the capacitance section being configured to include a semiconductor region and a polysilicon electrode formed on the semiconductor region via an insulating film.

According to yet another embodiment of the present disclosure, a semiconductor device is provided, comprising: a first semiconductor component having a first circuit section; and a second semiconductor component having a second circuit section and stacked on the first semiconductor component, the second semiconductor component having a capacitance section having a first node and a second node connected to the first circuit section, the second circuit section being a pixel section including a plurality of pixels, and the capacitance section being disposed outside the pixel section in a plan view.

The present invention makes it possible to efficiently arrange capacitance parts in semiconductor devices while suppressing increases in manufacturing costs.

1 is a schematic diagram of an imaging device according to a first embodiment of the present invention. 1 is a block diagram of an imaging device according to a first embodiment of the present invention. 1 is a cross-sectional view of an imaging device according to a first embodiment of the present invention. FIG. 2 is a cross-sectional perspective view of a shield portion according to the first embodiment of the present invention. 1 is a plan view of a portion of an imaging device according to a first embodiment of the present invention. FIG. 11 is a schematic diagram of an imaging device according to a second embodiment of the present invention. FIG. 11 is a cross-sectional view of an imaging device according to a third embodiment of the present invention. FIG. 13 is a cross-sectional view of an imaging device according to a fourth embodiment of the present invention. FIG. 13 is a diagram for explaining an imaging device according to a fifth embodiment of the present invention. FIG. 13 is a cross-sectional view of an imaging device according to a sixth embodiment of the present invention. FIG. 13 is a block diagram showing a schematic configuration of an imaging system according to a seventh embodiment of the present invention. FIG. 13 is a diagram showing an example of the configuration of an imaging system and a moving body according to an eighth embodiment of the present invention. FIG. 13 is a schematic diagram of a reference voltage circuit according to a ninth embodiment of the present invention. FIG. 13 is a schematic diagram of an inverting amplifier circuit according to a ninth embodiment of the present invention. 13 is a timing chart illustrating an operation of the inverting amplifier circuit according to the ninth embodiment of the present invention. FIG. 13 is a schematic diagram of a reference signal generating circuit according to a ninth embodiment of the present invention. FIG. 13 is a diagram of a comparison circuit according to a ninth embodiment of the present invention. 13 is a timing chart illustrating an operation of a reference signal generating circuit according to a ninth embodiment of the present invention. 13 is a timing chart illustrating an operation of an analog-to-digital conversion unit in the ninth embodiment of the present invention. FIG. 13 is a schematic diagram of a current mirror circuit according to a ninth embodiment of the present invention.

[First embodiment]
The semiconductor device according to the present embodiment can be applied to, for example, an image pickup device having a photoelectric conversion unit, and will be described below by taking an image pickup device as an example.

FIG. 1 is a schematic diagram of an imaging device in this embodiment. The imaging device is a so-called back-illuminated solid-state imaging device, and includes a first semiconductor component 1 and a second semiconductor component 2. The second semiconductor component 2 is stacked on the first main surface (upper surface in the Z direction) of the first semiconductor component 1. Such a semiconductor device is manufactured by bonding a wafer including the first semiconductor component 1 and a wafer including the second semiconductor component 2 at the wafer level, and dicing the bonded wafer. Since they are obtained by dicing, the first semiconductor component 1 and the second semiconductor component 2 can each be called a semiconductor chip. As a manufacturing method that does not involve bonding at the wafer level, a semiconductor chip obtained by dicing a wafer including the first semiconductor component 1 may be stacked on a semiconductor chip obtained by dicing a wafer including the second semiconductor component 2. The first semiconductor component 1 includes, for example, an analog-to-digital conversion unit 11, a memory unit 12, and a signal processing unit 13 as a first circuit unit. The second semiconductor component 2 includes, for example, a pixel unit 21 as a second circuit unit different from the first circuit unit. The pixel section 21 includes a plurality of pixels that generate signals according to incident light, and the plurality of pixels are arranged in a matrix in the X and Y directions. The signal output from the pixel section 21 is output to the analog-to-digital conversion section 11 of the first semiconductor component 1. The analog-to-digital conversion section 11 converts the signal from the pixel section 21 into a digital signal, and the memory section 12 holds the digital signal. The signal processing section 13 processes the digital signal held in the memory section 12. The analog-to-digital conversion section 11 and the memory section 12 constitute a third circuit section, and at least a portion of the analog-to-digital conversion section 11 and the memory section 12 can be arranged to overlap the second circuit section when viewed in a plan view in the Z direction.

The second semiconductor component 2 further includes a capacitance section 22. The capacitance section 22 is connected to, for example, the signal processing section 13 in the first semiconductor component 1. The capacitance section 22 and the signal processing section 13 are electrically connected via joint contacts 24a and 24b made of metal such as Al, Cu, or W. The capacitance section 22 includes a first input node N1 and a second input node N2, and is connected to the signal processing section 13. When the capacitance section 22 is used as a bypass capacitor (decoupling capacitance), the first input node N1 is connected to the power supply line VDD in the signal processing section 13, and the second input node is connected to the ground line GND in the signal processing section 13. When the capacitance section 22 is used as a coupling capacitance, the capacitance section 22 can be connected in series to a desired signal line of the signal processing section 13. Below, the configuration in which the capacitance section 22 includes a bypass capacitor will be mainly described.

The capacitance unit 22 may be formed in a position facing the signal processing unit 13 in the second semiconductor component 2 in a plan view. That is, in a plan view of the imaging device, the capacitance unit 22 and the signal processing unit 13 may be arranged to overlap at least partially. This shortens the wiring between the capacitance unit 22 and the signal processing unit 13, making it possible to reduce the impedance of the power supply line and the ground line. Note that even if the capacitance unit 22 and the signal processing unit 13 are not arranged to overlap in a plan view, it is preferable to make the length of the power supply line and the ground line between the capacitance unit 22 and the signal processing unit 13 as short as possible.

In the second semiconductor component 2, a shield section 23 is formed between the pixel section 21 and the capacitance section 22. The shield section 23 may have a rectangular ring shape surrounding the pixel section 21 in a plan view. The shield section 23 has multiple wirings as described below, and can prevent noise generated in the capacitance section 22 from being mixed into the pixel section 21.

Figure 2 is a block diagram of the imaging device in this embodiment. The imaging device includes a pixel section 21, an analog-to-digital conversion section (AD conversion section) 11, a memory section 12, a signal processing section 13, a vertical scanning section 14, and a capacitance section 22.

The pixel section 21 is provided on the second semiconductor component 2 and includes a plurality of pixels 210 arranged in a matrix. In FIG. 2, three rows and four columns of pixels 210 are shown for the sake of simplicity, but the number of pixels 210 arranged in the row direction and column direction is not particularly limited. In this specification, the row direction refers to the horizontal direction in the drawing, and the column direction refers to the vertical direction in the drawing. Microlenses and color filters may be arranged on the pixels 210. The color filters are, for example, primary color filters of red, blue, and green, and are arranged on each pixel 210 according to the Bayer array. Some of the pixels 210 are light-shielded as OB pixels (optical black pixels). The plurality of pixels 210 may include a ranging row in which focus detection pixels that output pixel signals for focus detection are arranged, and a plurality of imaging rows in which imaging pixels that output pixel signals for generating an image are arranged. A signal line 211 is provided for each column of pixels 210, and a constant current source 212 is electrically connected to the signal line 211.

The pixel 210 includes a photoelectric conversion unit PD, a floating diffusion region FD (Floating Diffusion), a transfer transistor M1, a reset transistor M2, an amplification transistor M3, and a selection transistor M4. The following description shows an example in which the transistors constituting the pixel 210 are N-type MOS transistors. The photoelectric conversion unit PD is composed of, for example, a photodiode, and performs photoelectric conversion by incident light and generates and accumulates electric charges. When the transfer transistor M1 is turned on, it transfers the electric charge of the photoelectric conversion unit PD to the floating diffusion region FD. When the reset transistor M2 is turned on, it resets the electric potential of the floating diffusion region FD to the power supply voltage. The floating diffusion region FD has a predetermined capacitance and generates a voltage according to the electric charge. The amplification transistor M3 operates as a source follower whose source electric potential changes according to the electric potential of the floating diffusion region FD. The selection transistor M4 electrically connects the source of the amplification transistor M3 to a signal line 211. A constant current source 212 that functions as a load of the amplification transistor M3 is connected to the signal line 211. When the selection transistor M4 of the row to be read out is turned on, a voltage (analog signal) corresponding to the charge of the photoelectric conversion unit PD of that row is output to the signal line 211.

Transistors M1 to M4 are not limited to N-type MOS transistors, but may be P-type MOS transistors. The configuration of pixel 210 is also not limited to the example shown in FIG. 2, and various pixels can be used. For example, multiple photoelectric conversion units PD may share one amplification transistor M3, and pixel 210 may be provided with an overflow drain that discharges charge that overflows from the photoelectric conversion unit PD.

The analog-to-digital conversion unit 11 includes an amplifier circuit, a comparator, a ramp signal generating circuit, a counter circuit, and the like. The amplifier circuit amplifies the analog signal output from the pixel 210 to the signal line 211, and inputs it to one input terminal of the comparator. The ramp signal generating circuit generates a ramp signal that changes over time, and inputs it to the other input terminal of the comparator. The comparator compares the analog signal with the ramp signal, and outputs a comparison signal. The counter circuit counts the time from when the ramp signal starts to change to when the comparison signal is inverted, and outputs the count value as digital data.

The memory unit 12 holds the digital data output from the analog-to-digital conversion unit 11. The memory unit 12 can hold the digital data on a row-by-row or frame-by-frame basis. Furthermore, the memory unit 12 can include a scanning circuit that outputs the held digital data as serial data or parallel data.

The signal processing unit 13 includes a digital signal processing circuit, an arithmetic processing circuit, etc., and performs signal processing of the digital data output from the memory unit 12. The signal processing can be, for example, any one or more of noise reduction processing, dynamic range expansion processing, white balance processing, shutter readout processing, and demosaic processing. The digital data output from the signal processing unit 13 is output from the pad electrode SOUT of the second semiconductor component 2 to the outside of the imaging device.

The vertical scanning unit 14 includes a shift register, a gate circuit, etc., and supplies a plurality of control signals to the pixels 210. That is, the vertical scanning unit 14 drives the control signals applied to the gates of the transistors M1, M2, and M4 of the pixels 210, and reads out the pixels 210 row by row.

The capacitance unit 22 is provided in the second semiconductor component 2, and the first input node N1 of the capacitance unit 22 is connected to the power supply wiring VDD of the signal processing unit 13, and the second input node N2 of the capacitance unit 22 is connected to the ground wiring GND of the signal processing unit 13. The power supply wiring VDD and the ground wiring GND are electrically connected to the external pad electrodes VDD and GND of the second semiconductor component 2, and a power supply voltage is supplied from outside the semiconductor device via the external pad electrodes VDD and GND. A power supply control circuit may be provided between the external pad electrodes VDD and GND and each circuit part inside the semiconductor device. The power supply control circuit may control the power supply voltage supplied to each part of the semiconductor device.

Figure 3 is a diagram for explaining the details of the imaging device in this embodiment, and is a cross-sectional view of the imaging device in Figure 1 taken along III-III'. The first semiconductor component 1 includes a first semiconductor substrate 1A and a first wiring layer region 1B, and the second semiconductor component 2 includes a second semiconductor substrate 2A and a second wiring layer region 2B. The first semiconductor component 1 and the second semiconductor component 2 are stacked so that the first main surfaces of the first semiconductor component 1 and the second semiconductor component 2, i.e., the surface of the first wiring layer region 1B and the surface of the second wiring layer region 2B, face each other. Incident light is irradiated onto the second main surface (rear surface) of the second semiconductor substrate 2A.

Transistors M10, M11, and M12 are formed on the first semiconductor substrate 1A. For example, transistor M12 is included in the signal processing unit 13. A P-type well is formed on the first semiconductor substrate 1A, and the source and drain of each of transistors M10, M11, and M12 are formed as N-type semiconductor regions in the P-type well. A gate electrode is formed on the P-type well between the source and drain, with a gate insulating film sandwiched therebetween.

The first wiring layer region 1B is provided on the first semiconductor substrate 1A, and multiple wiring layers are formed via an interlayer insulating film 104 made of an organic material or the like. Different wiring layers are connected to each other by connection parts 25 extending in the Z direction, and the connection parts 25 are further connected to junction contacts 24a, 24b, and 24c on the upper part of the first wiring layer region 1B. In the signal processing unit 13, the power supply wiring VDD is connected to the junction contact 24a, and the ground wiring GND is connected to the junction contact 24b.

The second semiconductor substrate 2A includes P-type wells 201a and 202a implanted with P-type impurities, and an N-type well 203a implanted with N-type impurities. The N-type well 203a is formed between the P-type wells 201a and 202a.

The pixel section 21 is formed in a P-type well 201a. In FIG. 3, the photoelectric conversion section PD, floating diffusion region FD, transfer transistor M1, color filter CF, and microlens ML of the pixel section 21 are shown. The photoelectric conversion section PD includes an N-type region surrounded by the P-type well 201a, and a P-type region is provided above the N-type region (in the -Z direction). This configuration can reduce noise caused by electric charges generated at the interface. A color filter CF and a microlens ML are provided on the second main surface (back surface) of the second semiconductor substrate 2A. Light incident on the back surface of the second semiconductor substrate 2A is incident on the photoelectric conversion section PD via the microlens ML and color filter CF. In this way, by receiving light from the back surface of the second semiconductor substrate 2A, the light receiving area is increased, and a highly sensitive imaging device can be realized.

The floating diffusion region FD includes an N-type region and forms a predetermined capacitance. The gate electrode M1g of the transfer transistor M1 is disposed between the photoelectric conversion unit PD and the floating diffusion region FD, and is formed on the second semiconductor substrate 2A with the gate insulating film M1i sandwiched therebetween. The gate electrode M1g is composed of, for example, a polysilicon electrode or a metal electrode such as Al or Cu, and the gate insulating film M1i is composed of, for example, SiO _2. The source/drain region of the transfer transistor M1 shares the photoelectric conversion unit PD and the floating diffusion region FD. When a voltage is applied to the gate electrode M1g, the charge accumulated in the photoelectric conversion unit PD is transferred to the floating diffusion region FD. The potential of the floating diffusion region FD changes according to the charge, and is output via the amplification transistor M3 and the selection transistor M4 (see FIG. 2). The signal output from the pixel unit 21 can be output to the first semiconductor component 1, for example, via the junction contact 24c.

The capacitance section 22 is formed in a P-type well 202a separated from the pixel section 21. The capacitance section 22 includes a single or multiple bypass capacitors 220. The bypass capacitor 220 in this embodiment has a MOS (Metal-Oxide-Semiconductor) structure, and may be formed, for example, by an N-type MOS transistor. The bypass capacitor 220 includes a gate electrode 220g, a source region 220s, a drain region 220d, a substrate bias section 220a, and a gate insulating film 220i. N-type impurities are injected into the source region 220s and the drain region 220d. The gate electrode 220g is formed of a polysilicon electrode or a metal electrode such as Al or Cu, and is disposed between the source region 220s and the drain region 220d. The gate electrode 220g is formed on the second semiconductor substrate 2A with a gate insulating film 220i sandwiched therebetween. The gate insulating film 220i is formed of SiO ₂ , SiON, SiN, or the like. When SiON or SiN is used for the gate insulating film 220i, a bypass capacitor 220 with a high dielectric constant can be realized.

In addition, an N-type substrate bias section 220a is formed in the P-type well 202a. In the bypass capacitor 220, when a power supply voltage VDD is applied to the gate electrode 220g and a ground voltage GND is applied to the substrate bias section 220a, the source region 220s, and the drain region 220d, a channel region is formed between the source region 220s and the drain region 220d. The gate electrode 220g constitutes one electrode (first input node) of the bypass capacitor 220, and the source region 220s and the drain region 220d constitute the other electrode (second input node) of the bypass capacitor 220.

The substrate bias section 220a, the source region 220s, and the drain region 220d are connected to the ground wiring GND in the second wiring layer region 2B, and the ground wiring GND is connected to the junction contact 24b via the connection portion 25. The junction contact 24b is connected to the ground wiring GND of the signal processing section 13 in the first wiring layer region 1B. Similarly, the gate electrode 220g is connected to the power supply wiring VDD in the second wiring layer region 2B, and the power supply wiring VDD is connected to the junction contact 24a via the connection portion 25. The junction contact 24a is connected to the power supply wiring VDD of the signal processing section 13 in the first wiring layer region 1B. That is, the bypass capacitor 220 in the second semiconductor component 2 is connected to the signal processing section 13 of the first semiconductor component 1.

In FIG. 3, the number of each of the bonding contacts 24a and 24b is only one, but the number of the bonding contacts 24a and 24b may be multiple. This reduces the impedance of the bonding contacts 24a and 24b, the power supply wiring VDD, and the ground wiring GND, and effectively suppresses fluctuations in the power supply wiring VDD.

In addition, although the bypass capacitor 220 in FIG. 3 is configured with an NMOS, it may be configured with a PMOS. That is, by using an N-type well instead of the P-type well 202a of the capacitance section 22, a PMOS bypass capacitor 220 can be formed. Also, an N-type well may be formed in the P-type well 202a, and a PMOS may be further formed in the N-type well.

The shield section 23 is formed in the N-type well 203a between the pixel section 21 and the capacitance section 22. Here, the detailed configuration of the shield section 23 will be described with reference to FIG. 4 in addition to FIG. 3. FIG. 4 is a cross-sectional perspective view of the shield section. The shield section 23 includes a substrate bias section 203b, wiring layers 231, 233, and connection sections 230, 232. The substrate bias section 203b is formed by injecting a high concentration of N-type impurities into the surface of the N-type well 203a. The substrate bias section 203b is disposed between the pixel section 21 and the capacitance section 22 in the XY plan view, and has a predetermined width (Y direction). A plurality of wiring layers 231, 233 are formed in the vertical direction (-Z direction) relative to the substrate bias section 203b. The wiring layers 231, 233 have a predetermined wiring width (Y direction) similar to the substrate bias section 203b. The width of the wiring layers 231, 233 in the Y direction may be the same as the width of the substrate bias section 203b. The substrate bias unit 203b and the wiring layer 231 are connected by a plurality of connection parts 230 extending in the Z direction. The plurality of connection parts 230 are arranged at regular intervals in the X direction. Similarly, the wiring layer 231 and the wiring layer 233 are connected by a plurality of connection parts 232 extending in the Z direction. The plurality of connection parts 232 are arranged at regular intervals in the X direction along the wiring layers 231 and 233. The interval between the connection parts 232 may be the same as the interval between the connection parts 230. A fixed voltage VDD2 is applied to the wiring layers 231 and 233, and the shield unit 23 has a low impedance. The fixed voltage VDD2 may be a power supply voltage VDD, a power supply voltage dedicated to the shield unit 23, or a ground voltage GND.

Since the shield section 23 is provided between the pixel section 21 and the capacitance section 22, it is possible to prevent noise that may occur in the capacitance section 22 from being mixed into the pixel section 21. In addition, the shield section 23 has a lattice shape and extends in the vertical direction (-Z direction) of the second wiring layer region 2B. Therefore, a sufficient shielding effect can be obtained not only in the second semiconductor substrate 2A but also in the second wiring layer region 2B. Note that, to further improve the shielding effect, the number of wiring layers and connection sections that make up the shield section 23 may be increased. Furthermore, the shield sections 23 may be arranged in multiple columns.

FIG. 5 is a plan view of a part of the imaging device in this embodiment. The first semiconductor component 1 and the second semiconductor component 2 are stacked and placed on the package 3. A plurality of pad electrodes 29 are arranged in a row along the sides (edges) of the first semiconductor component 1 and the second semiconductor component 2, and the pad electrodes 29 are connected to the input/output circuit, power supply line, ground line, etc. of the second semiconductor component 2. A plurality of external pad electrodes 30 are arranged in a row on the package 3. The pad electrodes 29 and the external pad electrodes 30 are connected by bonding wires 31, and the external pad electrodes 30 can be connected to a circuit outside the imaging device. In this example, the pad electrodes 29 are arranged in the second wiring layer region 2B of the second semiconductor component 2. And the pad electrodes 29 are connected to the first semiconductor component 1 via a bonding contact. However, the pad electrodes 29 may be arranged in the first wiring layer region 1B of the first semiconductor component 1. The pad electrode 29 may also be arranged on the opposite side of the second wiring layer region 2B from the first semiconductor component 1, and the pad electrode 29 may be connected to the second semiconductor component 2 via a through electrode that penetrates the second semiconductor substrate 2A. The pad electrode 29 may also be arranged on the opposite side of the first wiring layer region 1B from the second semiconductor component 2, and the pad electrode 29 may also be connected to the first semiconductor component 1 via a through electrode that penetrates the first semiconductor substrate 1A.

The bonding wire 31 is made of a glossy material such as gold, aluminum, copper, or palladium, and is prone to reflecting incident light. If the reflected light from the bonding wire 31 enters the pixel section 21, image quality degradation such as ghosting may occur. In order to prevent the reflected light from the bonding wire 31 from entering the pixel section 21, the pixel section 21 is often disposed away from the pad electrode 29, and excess space is provided between the pixel section 21 and the pad electrode 29. In this embodiment, by providing the capacitance section 22 in the excess space generated in the second semiconductor component 2, it is no longer necessary to provide a dedicated semiconductor component for the bypass capacitor 220, and it is possible to suppress an increase in manufacturing costs. In particular, when the pad electrode 29 is disposed on the four sides of the second semiconductor component 2, excess space may occur on the four sides. By providing the capacitance section 22 on the four sides, the capacitance of the bypass capacitor 220 can be further increased, and fluctuations in the power supply voltage VDD can be effectively suppressed. In this way, the size, number, and shape of the capacitance section 22 can be determined according to the excess space of the second semiconductor component 2. For example, a small capacitance section 22 can be placed in an area where there is little excess space, and a large capacitance section 22 can be placed in an area where there is a lot of excess space.

In the imaging device configured as described above, by using the capacitance section as a bypass capacitor, it is possible to effectively suppress fluctuations in the power supply voltage when a large current flows instantaneously through the signal processing section. When the signal processing section is configured with a digital circuit, a large current may flow instantaneously, such as a switching current, causing the power supply voltage to drop. Fluctuations in the power supply voltage may adversely affect other circuits as noise. By providing a bypass capacitor between the power supply line and the ground line, it is possible to supply current from the bypass capacitor to the power supply line, thereby making it possible to suppress fluctuations in the power supply voltage.

As described above, in this embodiment, the capacitance section for the first semiconductor component is provided in the second semiconductor component. This eliminates the need to provide a dedicated semiconductor component for the capacitance section, making it possible to reduce manufacturing costs. In particular, when the semiconductor device is an imaging device, the capacitance section can be efficiently arranged in an area other than the pixel section by utilizing excess space generated around or near the pixel section.

The capacitance section in this embodiment can be used for various purposes, such as not only a bypass capacitor but also a coupling capacitance, but this embodiment is particularly suitable for a bypass capacitor. It is desirable for a bypass capacitor to have as large a capacitance as possible, and in the past, it was necessary to provide a dedicated semiconductor component for the bypass capacitor. According to this embodiment, the surplus space of the second semiconductor component is used to provide a bypass capacitor for the circuit of the first semiconductor component, eliminating the need to provide a dedicated semiconductor component for the bypass capacitor.

In addition, in this embodiment, since the bypass capacitor is provided inside the semiconductor component, the wiring length between the bypass capacitor and the signal processing unit can be shortened compared to when the bypass capacitor is provided outside the semiconductor component. This also reduces the impedance of the wiring, making it possible to more effectively suppress fluctuations in the power supply voltage. If the bypass capacitor were provided outside the semiconductor component, the impedance at high frequencies would increase due to the inductance of the bonding wires and external wiring, and the effect of the bypass capacitor would be reduced. A configuration in which the bypass capacitor is provided inside the semiconductor component is particularly effective in suppressing high-frequency noise in the power supply voltage.

Furthermore, in this embodiment, the bypass capacitor is connected to the signal processing unit via a bonding contact. Since the area of the bonding contact is smaller than the area of the bonding pad, multiple bonding contacts can be provided inside the semiconductor component. As the number of bonding contacts increases, the impedance of the power supply wiring between the bypass capacitor and the signal processing unit decreases. Therefore, compared to when the bypass capacitor is provided outside the semiconductor component, the number of wirings and bonding contacts of the bypass capacitor can be increased, and fluctuations in the power supply voltage can be more effectively suppressed.

In the above embodiment, an example was described in which the bypass capacitor was connected to the signal processing unit, but the circuit unit to which the bypass capacitor is connected is not limited to the signal processing unit. Bypass capacitors can also be connected to circuits in which fluctuations in the power supply voltage in the high frequency band may occur, such as analog-to-digital conversion circuits, parallel-serial conversion circuits for high-speed serial data transmission, transmitter circuits, and memory circuits. In addition, this embodiment may be applied to analog circuits in which a large current may instantaneously flow, without being limited to digital circuits.

[Second embodiment]
6 is a schematic diagram of an image pickup device according to this embodiment. The number of bypass capacitors 220 included in the capacitance section 22 is not limited to one, and may be multiple. The image pickup device according to this embodiment will be described below, focusing on the configuration different from the first embodiment.

In FIG. 6, the capacitance section 22 includes a plurality of bypass capacitors 220, each of which is connected to the signal processing section 13 of the first semiconductor component 1 via a junction contact 24a, 24b. That is, the first input node N1 of the bypass capacitor 220 is connected to the power supply wiring VDD of the signal processing section 13 via the junction contact 24a, and the second input node N2 of the bypass capacitor 220 is connected to the ground wiring GND of the signal processing section 13 via the junction contact 24b.

In this embodiment, the capacitance can be increased by using multiple bypass capacitors connected in parallel. For example, in cases where it is difficult to increase the capacitance of a single bypass capacitor, a bypass capacitor with a large capacitance can be realized by connecting multiple bypass capacitors in parallel. That is, in multiple bypass capacitors, multiple first input nodes N1 may be connected to each other, and multiple second input nodes N2 may be connected to each other.

[Third embodiment]
7 is a cross-sectional view of the imaging device of this embodiment, taken along line III-III' of the imaging device of FIG. 1. The imaging device of this embodiment differs from the first embodiment in the structure of the capacitance section. The following description will focus on the configuration that differs from the first embodiment.

7, the bypass capacitor 221 is formed in the P-type well 202a of the second semiconductor substrate 2A, and includes a substrate bias portion 221a, a semiconductor region 221b, a gate electrode 221g, and a gate insulating film 221i. The semiconductor region 221b is formed by injecting a high concentration of N-type impurities into the P-type well 202a. A gate electrode 221g is formed on the semiconductor region 221b via a gate insulating film 221i. The gate electrode 221g is made of, for example, a polysilicon electrode or a metal electrode such as Al or Cu, and the gate insulating film 221i is made of, for example, SiO ₂ , SiON, SiN, or the like. The substrate bias portion 221a of an N-type region is formed in the P-type well 202a.

The substrate bias section 221a and the semiconductor region 221b are connected to the ground wiring GND in the second wiring layer region 2B, and the ground wiring GND is connected to the junction contact 24b via the connection section 25. The junction contact 24b is connected to the ground wiring GND of the signal processing section 13 in the first wiring layer region 1B. Similarly, the gate electrode 221g is connected to the power supply wiring VDD in the second wiring layer region 2B, and the power supply wiring VDD is connected to the junction contact 24a via the connection section 25. The junction contact 24a is connected to the power supply wiring VDD of the signal processing section 13 in the first wiring layer region 1B. That is, the bypass capacitor 221 in the second semiconductor component 2 is connected to the signal processing section 13 of the first semiconductor component 1.

In this embodiment, too, by providing a capacitive section for the first semiconductor component in the second semiconductor component, it is no longer necessary to provide a dedicated semiconductor component for the capacitive section, making it possible to reduce manufacturing costs.

[Fourth embodiment]
8 is a cross-sectional view of the image pickup device of this embodiment, taken along line III-III' of the image pickup device of FIG. 1. The image pickup device of this embodiment includes a capacitance section having a MIM (Metal-Insulator-Metal) structure. The following description will focus on the configuration that differs from the first embodiment.

8, the capacitance section 22 includes a single or multiple bypass capacitors 222, each of which is composed of two layers of metal wiring 222a, 222b. The metal wirings 222a, 222b face each other in the Z direction and are arranged at a predetermined interval. An interlayer insulating film 204 is interposed between the metal wirings 222a, 222b, and the interlayer insulating film 204 functions as a dielectric. The metal wiring 222a is connected to the junction contact 24a via a connection portion 25 in the second wiring layer region 2B. The junction contact 24a is connected to the power supply wiring VDD of the signal processing unit 13 in the first wiring layer region 1B. Similarly, the metal wiring 222b is connected to the ground wiring GND in the second wiring layer region 2B, and the ground wiring GND is connected to the junction contact 24b via a connection portion 25. The junction contact 24b is connected to the ground wiring GND of the signal processing unit 13 in the first wiring layer region 1B. That is, the bypass capacitor 222 in the second semiconductor component 2 is connected to the signal processing unit 13 of the first semiconductor component 1.

According to this embodiment, the bypass capacitor 222 can be configured using the metal wiring in the second semiconductor component. Note that the metal wiring that configures the bypass capacitor 222 is not limited to two layers, and may be three or more layers. By increasing the number of layers of metal wiring, it is possible to configure a bypass capacitor 222 with a large capacity.

In this embodiment, the capacitance portion 22 is disposed in the second wiring layer region 2B, not on the second semiconductor substrate 2A. Therefore, the region 202b in the second semiconductor substrate 2A that corresponds to the capacitance portion 22 does not necessarily need to be a P-type well, and may be an N-type well. Also, a P-type well may be formed in the region 202b, and the capacitance portion 22 in the first to third embodiments may be further provided in addition to the capacitance portion 22 in this embodiment. In other words, it is possible to form the capacitance portion 22 in each of the second semiconductor substrate 2A and the second wiring layer region 2B, and increase the capacitance of the bypass capacitor.

[Fifth embodiment]
9 is a diagram for explaining the imaging device in this embodiment, and shows a modified example of the capacitance section in the fourth embodiment. The capacitance section in the fourth embodiment is composed of two different layers of metal wiring, but the capacitance section in this embodiment is composed of metal wiring in the same layer. The following mainly describes the configuration different from the fourth embodiment.

In FIG. 9, the bypass capacitor 223 includes metal wirings 223a and 223b formed in the same layer, and the metal wirings 223a and 223b are arranged adjacent to each other at a predetermined interval in a plan view. A concave portion and a convex portion are formed on each of the opposing sides of the metal wirings 223a and 223b. The convex portion of the metal wiring 223a is located in the concave portion of the metal wiring 223b, and the convex portion of the metal wiring 223b is located in the concave portion of the metal wiring 223a. With this configuration, the total length of the opposing sides of the metal wirings 223a and 223b is increased, and the capacitance of the metal wirings 223a and 223b is increased. The metal wirings 223a and 223b are connected to the signal processing unit 13 of the first semiconductor component 1 via joint contacts 24a and 24b (not shown).

As described above, the capacitive section can be constructed using metal wiring in the same layer in the second semiconductor component. In this embodiment, too, there is no need to provide a semiconductor component dedicated to the capacitive section, which makes it possible to reduce manufacturing costs.

Sixth Embodiment
Fig. 10 is a cross-sectional view of the imaging device in this embodiment, taken along line III-III' of the imaging device in Fig. 1. In this embodiment, the front and back of the second semiconductor component 2 are arranged in the opposite direction to those in the first to fifth embodiments, forming a front-illuminated imaging device. The following description will focus on the configurations that differ from those of the first to fifth embodiments.

In FIG. 10, the second main surface (rear surface) of the second semiconductor substrate 2A is bonded to the first wiring layer region 1B, and incident light is irradiated onto the first main surface (front surface) of the second wiring layer region 2B. The first semiconductor component 1 is provided with an analog-to-digital conversion unit 11, a memory unit 12, a signal processing unit 13, and a vertical scanning unit 14, substantially similar to the first to fifth embodiments.

The second semiconductor substrate 2A includes P-type wells 201a, 202a into which P-type impurities are injected. The pixel section 21 is formed in the P-type well 201a, and FIG. 10 shows the photoelectric conversion section PD, floating diffusion region FD, transfer transistor M1, color filter CF, and microlens ML. The color filter CF and microlens ML are arranged on the surface of the second wiring layer region 2B above the photoelectric conversion section PD.

The capacitance section 22 is formed in the P-type well 202a and includes a bypass capacitor 225. The bypass capacitor 225 is configured similarly to the bypass capacitor 221 in the third embodiment, and includes a substrate bias section 225a, a semiconductor region 225b, a gate electrode 225g, and a gate insulating film 225i. The semiconductor region 225b is formed by injecting a high concentration of N-type impurities into the P-type well 202a. A gate electrode 225g is formed on the semiconductor region 225b via a gate insulating film 225i. The gate electrode 225g is composed of, for example, a polysilicon electrode or a metal electrode such as Al or Cu, and the gate insulating film 225i is composed of, for example, SiO ₂ , SiON, SiN, or the like. The substrate bias section 225a can be formed by injecting N-type impurities into the P-type well 202a.

The gate electrode 225g is connected to the metal wiring 205a through a connection in the second wiring layer region 2B. The metal wiring 205a is further connected to the electrode 206a through a connection, and the electrode 206a is connected to the junction contact 24a through the through electrode 208a of the second semiconductor substrate 2A. The junction contact 24a is connected to the power supply wiring VDD of the signal processing unit 13 in the first semiconductor substrate 1A. In addition, the substrate bias unit 225a and the semiconductor region 225b are connected to the metal wiring 205b through a connection in the second wiring layer region 2B. The metal wiring 205b is further connected to the electrode 206b through a connection, and the electrode 206b is connected to the junction contact 24b through the through electrode 208b of the second semiconductor substrate 2A. The junction contact 24b is connected to the ground wiring GND of the signal processing unit 13 in the first semiconductor substrate 1A. The shield unit 23 is provided between the pixel unit 21 and the capacitance unit 22 as in the first to fifth embodiments.

In this embodiment, the capacitive section for the first semiconductor component is provided in the second semiconductor component, eliminating the need to provide a dedicated semiconductor component for the capacitive section, which makes it possible to reduce manufacturing costs.

[Seventh embodiment]
An imaging system according to a seventh embodiment of the present invention will be described with reference to Fig. 11. Fig. 11 is a block diagram showing an example of the configuration of the imaging system according to this embodiment.

The imaging device in the above-described embodiment can be applied to various imaging systems. Examples of imaging systems include digital still cameras, digital camcorders, camera heads, copiers, fax machines, mobile phones, vehicle-mounted cameras, observation satellites, and surveillance cameras. Figure 11 shows a block diagram of a digital still camera as an example of an imaging system.

The imaging system 7 shown in FIG. 11 includes a barrier 706, a lens 702, an aperture 704, an imaging device 70, a signal processing unit 708, a timing generating unit 720, an overall control and calculation unit 718, a memory unit 710, a recording medium control I/F unit 716, a recording medium 714, and an external I/F unit 712. The barrier 706 protects the lens, and the lens 702 forms an optical image of a subject on the imaging device 70. The aperture 704 varies the amount of light that passes through the lens 702. The imaging device 70 is configured as in the above-mentioned embodiment, and converts the optical image formed by the lens 702 into image data. Here, it is assumed that an AD (analog-digital) conversion unit is formed on the semiconductor substrate of the imaging device 70. The signal processing unit 708 performs various corrections and data compression on the imaging data output from the imaging device 70.

The timing generating unit 720 outputs various timing signals to the imaging device 70 and the signal processing unit 708. The overall control/calculation unit 718 controls the entire digital still camera, and the memory unit 710 temporarily stores image data. The recording medium control I/F unit 716 is an interface for recording or reading image data to the recording medium 714, which is a removable recording medium such as a semiconductor memory for recording or reading imaging data. The external I/F unit 712 is an interface for communicating with an external computer, etc. Timing signals, etc. may be input from outside the imaging system, and the imaging system only needs to have at least the imaging device 70 and the signal processing unit 708 for processing the imaging signal output from the imaging device 70.

In this embodiment, the imaging device 70 and the AD conversion unit are provided on separate semiconductor substrates, but the imaging device 70 and the AD conversion unit may be formed on the same semiconductor substrate. Also, the imaging device 70 and the signal processing unit 708 may be formed on the same semiconductor substrate.

Each pixel may include a first photoelectric conversion unit and a second photoelectric conversion unit. The signal processing unit 708 may be configured to process a pixel signal based on the charge generated in the first photoelectric conversion unit and a pixel signal based on the charge generated in the second photoelectric conversion unit, and to obtain distance information from the imaging device 70 to the subject.

[Eighth embodiment]
12(a) and 12(b) are block diagrams of an imaging system related to an in-vehicle camera in this embodiment. The imaging system 8 has the imaging device 80 of the above-mentioned embodiment. The imaging system 8 has an image processing unit 801 that performs image processing on a plurality of image data acquired by the imaging device 80, and a parallax calculation unit 802 that calculates parallax (phase difference of parallax images) from a plurality of image data acquired by the imaging system 8. The imaging system 8 also has a distance measurement unit 803 that calculates a distance to an object based on the calculated parallax, and a collision determination unit 804 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax calculation unit 802 and the distance measurement unit 803 are examples of distance information acquisition means that acquire distance information to an object. That is, the distance information is information related to the parallax, the defocus amount, the distance to the object, and the like. The collision determination unit 804 may use any of these distance information to determine the possibility of a collision. The distance information acquisition means may be realized by dedicated hardware or may be realized by a software module. It may also be realized by a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination of these.

The imaging system 8 is connected to a vehicle information acquisition device 810, and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The imaging system 8 is also connected to a control ECU 820, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the judgment result of the collision judgment unit 804. The imaging system 8 is also connected to an alarm device 830 that issues an alarm to the driver based on the judgment result of the collision judgment unit 804. For example, if the judgment result of the collision judgment unit 804 indicates that there is a high possibility of a collision, the control ECU 820 performs vehicle control to avoid a collision and reduce damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 830 warns the user by sounding an alarm, displaying alarm information on a screen of a car navigation system, etc., or vibrating a seat belt or steering wheel. The imaging system 8 functions as a control means that controls the operation of controlling the vehicle as described above.

In this embodiment, the surroundings of the vehicle, for example the front or rear, are captured by the imaging system 8. FIG. 12(b) shows an imaging system for capturing an image of the area in front of the vehicle (imaging range 850). A vehicle information acquisition device 810, which serves as an imaging control means, sends instructions to the imaging system 8 or imaging device 80 to perform the operations described in the first to seventh embodiments. This configuration can further improve the accuracy of distance measurement.

Although the above describes an example of control to avoid collision with other vehicles, the system can also be applied to control of automatic driving to follow other vehicles, control of automatic driving to avoid going out of lanes, etc. Furthermore, the imaging system is not limited to vehicles such as automobiles, but can be applied to moving bodies (moving devices) such as ships, aircraft, artificial satellites, industrial robots, and consumer robots. In addition, the system can be applied not only to moving bodies, but also to a wide range of equipment that uses object recognition or biometric recognition, such as intelligent transport systems (ITS) and surveillance systems.

[Ninth embodiment]
Next, the semiconductor device according to the present embodiment will be described. The semiconductor device according to the present embodiment can also be applied to a voltage generating circuit that generates a reference voltage such as a constant voltage other than a power supply voltage and a voltage that changes over time. Hereinafter, the circuit constituting the analog-to-digital conversion unit 11 shown in FIG. 2 will be described as an example of the first circuit unit arranged in the first semiconductor component 1.

FIG. 13 is a schematic diagram of a reference voltage circuit in this embodiment. The reference voltage circuit 131 is used, for example, in a column amplifier in the front stage of the analog-to-digital conversion unit 11. The reference voltage circuit 131 includes a differential amplifier 1310 provided in the first semiconductor component 1 and a bypass capacitor (capacitor) 224 provided in the second semiconductor component 2. The inverting input terminal and the output terminal of the differential amplifier 1310 are connected to each other and function as a voltage follower circuit. The differential amplifier 1310 outputs a reference voltage VF equal to the voltage applied to the non-inverting input terminal to a reference voltage line 1311. The reference voltage line 1311 is connected to one electrode (first input node) of the bypass capacitor 224 via a junction contact 24d. The other electrode (second input node) of the bypass capacitor 224 is connected to the ground wiring GND in the second semiconductor component 2 and is connected to the ground wiring GND of the first semiconductor component 1 via a junction contact 24e. A bypass capacitor 224 is provided between the reference voltage line 1311 and the ground wiring GND, reducing the impedance of the reference voltage line 1311 and the ground wiring GND, suppressing fluctuations in the reference voltage VF. Since the reference voltage circuit 131 only needs to supply a small current, it is sufficient to provide a bypass capacitor 224 with a relatively small capacitance in the second semiconductor component 2. Since there is no need to provide a bypass capacitor with a large capacitance outside the chip, manufacturing costs can be reduced and the entire device can be made compact.

Figure 14 is a schematic diagram of an inverting amplifier circuit in this embodiment. The inverting amplifier circuit 132 is provided for each signal line 211 shown in Figure 2, for example, and amplifies the signal of the pixel 210 of each column. It includes a differential amplifier 1320, an input capacitance C0, a feedback capacitance Cf, and a switch 1321. The reference voltage line 1311 shown in Figure 13 is connected to the non-inverting input terminal of the differential amplifier 1320, and a reference voltage VF is applied to the non-inverting input terminal. The signal VIN is input to the inverting input terminal of the differential amplifier 1320 via the input capacitance C0. The feedback capacitance Cf and the switch 1321 are connected between the inverting input terminal and the output terminal of the differential amplifier 1320. The switch 1321 is made of a transistor, and is turned on or off depending on the control signal RES applied to the gate. The differential amplifier 1320 amplifies the signal VIN with a gain depending on the input capacitance C0, the feedback capacitance Cf, and the switch 1321, and outputs a signal VOUT.

Figure 15 is a timing chart showing the operation of the inverting amplifier circuit in this embodiment. At time t1, when the control signal RES becomes high level, the switch 1321 turns on, the output terminal and the inverting input terminal of the differential amplifier 1320 are shorted, and the differential amplifier 1320 operates as a voltage follower. In addition, the non-inverting input terminal and the inverting input terminal become imaginarily shorted, and the voltage of the inverting input terminal becomes equal to the reference voltage VF of the non-inverting input terminal. Therefore, the voltage of the signal VOUT of the differential amplifier 1320 becomes the reference voltage VF. At time t2, the control signal RES becomes low level and the switch 1321 turns off, so that the amplification factor of the differential amplifier 1320 becomes C0/Cf. At times t3 to t4, when the voltage of the input signal VIN decreases by Vd, the voltage of the output signal VOUT increases by Vd x C0/Cf. The output signal VOUT from the inverting amplifier circuit 132 is converted to digital data, for example, by the analog-to-digital converter 11 shown in FIG. 2.

Figure 16 is a schematic diagram of the reference signal generating circuit in this embodiment. The reference signal generating circuit 133 generates a reference signal in a so-called slope-type analog-to-digital conversion section. The reference signal generating circuit 133 includes a current source 1331, a reset switch 1332, and a charging capacitance (capacitance section) 227. The current source 1331 is provided in the first semiconductor component 1 and is composed of transistors and the like. The charging capacitance 227 is provided in the second semiconductor component 2. By providing the charging capacitance 227 in an empty area of the second semiconductor component 2, it is possible to configure the entire device in a small size. One electrode (first input node) of the charging capacitance 227 is connected to the current source 1331 via the junction contact 24f. A current is supplied to the charging capacitance 227 from the current source 1331, and a reference signal ref according to the charge of the charging capacitance 227 is output. The other electrode (second input node) of the charging capacitance 227 is connected to the ground wiring GND of the second semiconductor component 2, and is also connected to the ground wiring GND of the first semiconductor component 1 via the junction contact 24g. The reset switch 1332 is provided in the second semiconductor component 2 and is composed of a transistor. The reset switch 1332 is turned on or off depending on the control signal R_RES applied to the gate. When the reset switch 1332 is turned on, the charge of the charging capacitance 227 is discharged to the ground wiring GND. The reset switch 1332 may be provided in the first semiconductor component 1.

Figure 17 is a diagram of the comparison circuit in this embodiment. The comparison circuit 134 is composed of a differential amplifier and is used in the analog-to-digital conversion section. The reference signal ref is input to the non-inverting input terminal of the comparison circuit 134, and the signal VOUT, which is an analog signal, is input to the inverting input terminal. The comparison circuit 134 outputs a comparison signal CMP that represents the comparison result between the reference signal ref and the output signal VOUT. A counter circuit, not shown, measures the time (count value) until the comparison signal CMP is inverted, and outputs the count value as a digital signal DOUT that corresponds to the output signal VOUT, which is an analog signal.

Figure 18 is a timing chart showing the operation of the reference signal generating circuit in this embodiment. At time t10, the control signal R_RES becomes high level, and the reset switch 1332 is turned on. When the reset switch 1332 is turned on, the charge stored in the charging capacitance 227 is discharged, and the voltage of the reference signal ref of the reference signal generating circuit 133 becomes the GND potential. At times t10 to t11, the control signal R_RES is at a high level, so the reset switch 1332 maintains an on state, and the current supplied from the current source 1331 continues to flow to the ground wiring GND via the reset switch 1332. At time t11, the control signal R_RES becomes low level, and the reset switch 1332 is turned off. When the reset switch 1332 is turned off, the current supplied from the current source 1331 charges the charging capacitance 227. As time passes, the amount of charge stored in the charging capacitance 227 increases, and the voltage of the reference signal ref gradually rises.

Figure 19 is a timing chart showing the operation of the analog-digital conversion unit in this embodiment. At time t20, the reference signal generation circuit 133 starts increasing the voltage of the reference signal ref, and the counter circuit starts counting clock pulses. At time t21, the magnitude relationship between the voltage of the analog signal VOUT and the reference signal ref is inverted, and the comparison signal CMP is inverted from low level to high level. The analog-digital conversion unit stores in memory the count value CNT at the time the comparison signal CMP is inverted. This count value CNT is output as a digital signal DOUT corresponding to the analog signal VOUT.

Figure 20 is a schematic diagram of a current mirror circuit in this embodiment. The current mirror circuit 135 is widely used as a current source circuit. The current mirror circuit 135 includes a current source 1351, transistors 1352, 1353, 1354, and a capacitance 226. The current source 1351 and the transistors 1352, 1353, 1354 are provided in the first semiconductor component 1, and the capacitance 226 is provided in the second semiconductor component 2. One electrode (first input node) of the capacitance 226 is connected to the gates of the transistors 1352, 1353, 1354 via the junction contact 24h. The other electrode (second input node) of the capacitance 226 is connected to the ground wiring GND of the second semiconductor component 2 and to the ground wiring GND of the first semiconductor component 1 via the junction contact 24i. Capacitor 226 is provided between the gates of transistors 1352, 1353, and 1354 and the ground wiring GND, so fluctuations in the gate voltage due to noise, etc. can be suppressed.

As described above, the present invention can also be applied to circuits that generate reference voltages other than power supply voltages, circuits that generate reference signals that change over time, and current mirror circuits. In this embodiment, too, the capacitance outside the chip can be reduced by placing the capacitance that was previously placed outside the chip inside the chip. This makes it possible to reduce costs and the area of the printed circuit board.

[Modified embodiment]
The present invention is not limited to the above-described embodiments, and various modifications are possible. For example, an example in which a part of the configuration of any of the embodiments is added to another embodiment, or an example in which a part of the configuration of any of the embodiments is replaced with another embodiment, is also an embodiment of the present invention.

The present invention can also be realized by supplying a program that realizes one or more of the functions of the above-described embodiments to a system or device via a network or storage medium, and having one or more processors in the computer of the system or device read and execute the program. It can also be realized by a circuit (e.g., an ASIC) that realizes one or more of the functions.

The above-mentioned embodiments are merely examples of the implementation of the present invention, and the technical scope of the present invention should not be interpreted in a limiting manner. In other words, the present invention can be implemented in various forms without departing from its technical concept or main features.

For example, the semiconductor device of the present invention is not limited to imaging devices and can be applied to various devices. For example, the semiconductor device of the present invention can be applied to electronic devices such as cameras, mobile terminals, and general-purpose computers, transportation equipment such as automobiles, ships, and airplanes, communication equipment, office equipment such as copiers, printers, and scanners, display equipment such as displays, medical equipment such as X-ray diagnostic equipment and endoscopes, analytical equipment, and industrial equipment in general, such as semiconductor manufacturing equipment. In addition, devices that can be connected to the semiconductor device of this embodiment can include image processing devices including arithmetic circuits, control devices such as power supply controllers, motor controllers, and robot controllers, storage devices using semiconductor memories, magnetic recording media, and optical recording media, and display devices such as liquid crystal displays and OLED (Organic Light Emitting Diode) displays.

In the above embodiment, an example was described in which the capacitance unit is used as a bypass capacitor (decoupling capacitance), but the capacitance unit may be used for other purposes. For example, the capacitance unit may be used as a coupling capacitor (coupling capacitance) provided between signal lines.

REFERENCE SIGNS LIST 1 First semiconductor component 1A First semiconductor substrate 1B First wiring layer region 13 Signal processing section 2 Second semiconductor component 2A Second semiconductor substrate 2B Second wiring layer region 21 Pixel section 22 Capacitor section 23 Shield section 24 Bonding contact 25 Connection section 29 Pad electrode 30 External pad electrode 31 Bonding wire

Claims (30)

A semiconductor device comprising:
a first semiconductor component having a first circuit portion and including a first wiring layer region;
a second semiconductor component having a second circuit portion, a second wiring layer region and a main surface, and stacked on the first semiconductor component such that the first wiring layer region and the second wiring layer region face each other;
a junction contact portion made of metal and connected to the first wiring layer region and the second wiring layer region;
a pad electrode to which either a power supply voltage or a ground voltage is supplied from outside the semiconductor device;
a capacitance section connected to the pad electrode,
The semiconductor device according to claim 1, wherein at least a portion of the capacitance portion and the junction contact portion overlap each other in a plan view from above the main surface. A semiconductor device comprising:
a first semiconductor component having a first circuit portion and including a first wiring layer region;
a second semiconductor component having a second circuit portion, a second wiring layer region and a main surface, and stacked on the first semiconductor component such that the first wiring layer region and the second wiring layer region face each other;
a junction contact portion made of metal and connected to the first wiring layer region and the second wiring layer region;
a pad electrode to which either a power supply voltage or a ground voltage is supplied from outside the semiconductor device;
a capacitance section connected to the pad electrode;
the second semiconductor component further includes the capacitance section and a shield section provided between the second circuit section and the capacitance section,
The semiconductor device according to claim 1, wherein at least a portion of the shield portion and the junction contact portion do not overlap when viewed from above the main surface. A semiconductor device comprising:
a first semiconductor component having a first circuit portion and including a first wiring layer region;
a second semiconductor component including a second circuit portion, including a first well of a first conductivity type, a second well of the first conductivity type, and a third well of a second conductivity type disposed between the first well and the second well, the second semiconductor component being stacked on the first semiconductor component and including a second wiring layer region and a main surface;
a junction contact portion made of metal and connected to the first wiring layer region and the second wiring layer region;
a pad electrode to which either a power supply voltage or a ground voltage is supplied from outside the semiconductor device;
a capacitance portion connected to the pad electrode and disposed in the third well,
The semiconductor device according to claim 1, wherein at least a portion of the third well and the junction contact portion overlap with each other in a plan view from above the main surface. 4. The semiconductor device according to claim 1 , wherein the second semiconductor component further includes a shield section provided between the second circuit section and the capacitance section. 3. The semiconductor device according to claim 1 , wherein the capacitance section is formed in a well separated from the second circuit section in a semiconductor substrate of the second semiconductor component. 4. The semiconductor device according to claim 1 , wherein the capacitance section has a MOS structure. the capacitance section further comprises a gate electrode, a source region, a drain region, and a substrate bias section;
4. The semiconductor device according to claim 1, wherein a first node of the capacitance section is connected to the gate electrode, and a second node of the capacitance section is connected to the source region, the drain region, and the substrate bias section. 4. The semiconductor device according to claim 1, wherein the capacitance portion comprises a semiconductor region and a polysilicon electrode formed on the semiconductor region via an insulating film, a first node of the capacitance portion being connected to the semiconductor region, and a second node of the capacitance portion being connected to the polysilicon electrode. the capacitance section includes a first metal wiring and a second metal wiring formed in a wiring layer region on a semiconductor substrate of the second semiconductor component;
4. The semiconductor device according to claim 1 , wherein a first node of the capacitance section is connected to the first metal wiring, and a second node of the capacitance section is connected to the second metal wiring. 10. The semiconductor device according to claim 9 , wherein the first metal wiring and the second metal wiring are formed in different wiring layers. 10. The semiconductor device according to claim 9 , wherein the first metal wiring and the second metal wiring are formed in the same wiring layer. 10. The semiconductor device according to claim 9, wherein, in a plan view, each of the first metal wiring and the second metal wiring has a concave portion or a convex portion, and the convex portion of the second metal wiring is located within the concave portion of the first metal wiring. 4. The semiconductor device according to claim 1 , wherein the first semiconductor component includes a third circuit portion that at least partially overlaps the second circuit portion in a plan view. the second circuit unit is a pixel unit including a photoelectric conversion unit,
14. The semiconductor device according to claim 13, wherein the third circuit portion includes at least one of an analog-to-digital conversion portion that converts an analog signal output from the pixel portion into digital data, and a memory portion that holds the digital data. 4. The semiconductor device according to claim 1, wherein a first node of the capacitance section is connected to a power supply line of the first circuit section, and a second node of the capacitance section is connected to a ground line of the first circuit section. the first circuit unit includes a voltage generating circuit that generates a reference voltage;
4. The semiconductor device according to claim 1 , wherein a first node of the capacitance section is connected to a wiring of the reference voltage, and a second node of the capacitance section is connected to a ground line. 3. The semiconductor device according to claim 2 , wherein the first semiconductor component includes a transistor, and in a plan view from above the main surface, at least a portion of the shielding portion overlaps with the transistor. 3. The semiconductor device according to claim 2 , wherein the shield portion includes a plurality of wiring layers and a plurality of connection portions that connect the plurality of wiring layers. 3. The semiconductor device according to claim 2 , wherein a fixed voltage is applied to the shield portion. 3. The semiconductor device according to claim 2 , wherein the capacitance section is formed in a well separated from the second circuit section in a semiconductor substrate of the second semiconductor component. 4. The semiconductor device according to claim 1 , wherein the capacitance portion is disposed between the pad electrode and the second circuit portion in a plan view. 4. The semiconductor device according to claim 1 , further comprising a plurality of the capacitance sections, the plurality of capacitance sections being connected in parallel with each other. 4. The semiconductor device according to claim 1 , wherein the capacitance section and the first circuit section are disposed so as to at least partially overlap each other in a plan view. 4. The semiconductor device according to claim 1 , wherein the capacitance portion is disposed outside a region of the second circuit portions in a plan view. 4. The semiconductor device according to claim 1 , wherein the first circuit portion is a processing circuit. 26. The semiconductor device according to claim 25 , wherein the arithmetic processing circuit performs noise reduction processing. 4. The semiconductor device according to claim 1 , wherein the first circuit portion is an analog-to-digital conversion circuit. 4. The semiconductor device according to claim 1 , wherein the first circuit portion is a digital signal processing circuit that processes digital data. 29. The semiconductor device according to claim 28 , wherein the digital signal processing circuit outputs the digital data to an external device of the semiconductor device. A semiconductor device according to any one of claims 1 to 29 ,
A device connected to the semiconductor device;
An apparatus comprising:

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