JP7455683B2 - Power supply device and image forming device - Google Patents

Description

The present invention relates to a power supply device and an image forming apparatus including the power supply device.

FIG. 8(b) is a cross-sectional view of the vicinity of the image forming section for explaining the image forming operation in the image forming section of the printer 300 shown in FIG. 8(a). A charging voltage Vpr, which is an output voltage of a charging voltage source VPR that supplies a high charging voltage, is applied to the charging roller 102, and the charging roller 102 charges the surface potential of the photosensitive drum 101 to the dark area potential Vd. When the photosensitive drum 101 rotates in the direction of the arrow (clockwise) in FIG. 8B and is irradiated with the laser beam 103 emitted from the exposure section 319, the surface potential of the photosensitive drum 101 changes to the bright area potential. The static electricity is removed to Vl. The photosensitive drum 101 further rotates and comes into contact with the developing roller 104. A developing voltage Vdc is applied to the developing roller 104, and toner 100 is attached to the surface of the developing roller 104. At this time, the bright area potential Vl irradiated with the laser beam 103 is higher than the developing voltage Vdc, so the toner 100 adheres to the surface of the photosensitive drum 101.

Then, the photosensitive drum 101 further rotates and comes into contact with the transfer roller 105 via the sheet 109. A transfer voltage Vtr is applied to the transfer roller 105, and since the transfer voltage Vtr has a higher potential than the bright area potential Vl to which the toner 100 is attached, the toner 100 is peeled off from the photosensitive drum 101 and transferred onto the sheet 109. Attach to. The sheet 109 is conveyed to the left in FIG. 8(b), and is pressurized and heated by the fixing device 314 (FIG. 8(a)). Then, the toner 100 on the sheet 109 is melted and fixed on the sheet 109.

FIG. 9 is a circuit diagram illustrating the configuration of a developing voltage circuit Bias that generates the developing voltage Vdc applied to the developing roller 104. The developing voltage Vdc is generated by the developing voltage circuit Bias, the shunt resistor R0, and the charging voltage source VPR. In the developing voltage circuit Bias shown in FIG. 9, the CPU is supplied with the specified voltage Vb as the power supply voltage, and outputs a PWM signal for controlling the output voltage of the developing voltage Vdc from the output terminal TGT.

In FIG. 9, transistors Tr1 and Tr2 are connected to a specified voltage Va, and a charging voltage source VPR is connected to the collector terminal of transistor Tr2 via a shunt resistor R0. The shunt current Is shown by the broken line flows along a path of specified voltage Va→transistor Tr1→transistor Tr2→shunt resistor R0→charging voltage source VPR→ground (GND). The developing voltage circuit Bias can output a desired developing voltage Vdc to the developing roller 104 by appropriately increasing or decreasing the current value of the shunt current Is using a PWM signal output from the TGT terminal. For example, Patent Document 1 discloses a circuit configuration of the above-mentioned developing voltage circuit. Note that detailed explanations of FIGS. 8 and 9 described above will be given later.

US Patent No. 7877036

FIG. 11 is a cross-sectional view of the image forming section illustrating a state in which the photosensitive drum 101 starts rotating from a stopped state (FIG. 11(a)) to a state in which it starts rotating (FIG. 11(b)). In FIG. 11A, the fan-shaped area from the position where the photosensitive drum 101 contacts the charging roller 102 to the position where the photosensitive drum 101 contacts the developing roller 104 is an area where the surface potential is 0V. Then, the photosensitive drum 101 starts rotating and shifts from the state shown in FIG. 11(a) to the state shown in FIG. 11(b). At this time, if the developing voltage Vdc applied to the developing roller 104 is a negative potential lower than 0V, the toner 100 on the surface of the developing roller 104 will adhere to the photosensitive drum 101 side, which has a higher potential.

As a result, when the attached toner 100 moves to the transfer roller 105 together with the photosensitive drum 101, it adheres to the transfer roller 105 and stains the transfer roller 105. Furthermore, the toner 100 adheres to the back surface (the surface on the transfer roller 105 side) of the sheet conveyed to the transfer roller 105, causing staining of the back surface of the sheet 109. Further, the toner 100 attached to the photosensitive drum 101 at the start of rotation is removed by the cleaning blade 106. However, as the amount of removed toner 100 increases, a problem arises in that the waste toner box 107 that stores the waste toner becomes larger, which in turn causes the image forming apparatus to become larger.

The present invention was made under such circumstances, and an object of the present invention is to prevent toner from adhering to an uncharged area on the photosensitive drum when the photosensitive drum starts rotating.

In order to solve the above-mentioned problems, the present invention includes the following configuration.

(1) A power supply device that supplies a power supply voltage to a load, wherein a first voltage source and an input terminal are connected to the first voltage source, and the voltage input from the first voltage source is applied to the load. a second voltage source connected to an output terminal of the voltage generation section; a control means for controlling the voltage generated by the voltage generation section; bypass means connected to the voltage generation section, the voltage generation section having a first transistor and a second transistor, the first transistor having an emitter terminal connected to the first transistor. the second transistor has a base terminal connected to the bypass means, a base terminal connected to the control means, a collector terminal connected to the emitter terminal of the second transistor, and a base terminal connected to the bypass means; is connected to the output terminal of the voltage generation section, the base terminal of the first transistor and the base terminal of the second transistor are connected via a first resistor, and the base terminal of the second transistor and The control means is connected to the collector terminal via a second resistor, and the control means controls the voltage output from the collector terminal of the second transistor by controlling the current flowing to the base terminal of the first transistor. the bypass means is arranged between the base terminal of the second transistor and the control means, and causes the current flowing to the base terminal of the second transistor to flow through the control means. Device.

(2) a photosensitive drum, a charging means for charging the photosensitive drum to a uniform potential, and an exposure means for forming an electrostatic latent image on the photosensitive drum charged to the uniform potential by the charging means; Developing means for developing an electrostatic latent image on the photosensitive drum with toner to form a toner image; and a transfer means for transferring the toner image formed on the photosensitive drum onto a sheet. 10, wherein the developing means has a developing roller that attaches toner to the electrostatic latent image, and the power source supplies voltage to the developing roller. An image forming apparatus characterized by:

According to the present invention, it is possible to prevent toner from adhering to an uncharged area on the photosensitive drum when the photosensitive drum starts rotating.

Circuit diagram showing the circuit configuration of the developing voltage circuit of Example 1 A diagram explaining the operation of the developing voltage circuit of Example 1 A circuit diagram showing other circuit configurations of the developing voltage circuit of Example 1 Cross-sectional view illustrating the configuration around the image forming unit of Example 2 Circuit diagram showing the circuit configuration of the developing voltage circuit of Example 2 Cross-sectional view illustrating the configuration around the image forming unit of Example 3 Circuit diagram showing the circuit configuration of the developing voltage circuit of Example 3 A sectional view showing the configuration of a conventional image forming apparatus, and a sectional view illustrating the configuration around the image forming unit. Circuit diagram showing the circuit configuration of a conventional developing voltage circuit Circuit diagram showing other circuit configurations of the conventional developing voltage circuit A diagram illustrating the state around the image forming unit when a conventional rotary drum starts rotating. Diagram explaining the operation of a conventional developing voltage circuit

[Image forming device]
A laser beam printer will be described as an example of an image forming apparatus including a power supply device. FIG. 8A shows a schematic configuration of a laser beam printer, which is an example of an electrophotographic printer. The laser beam printer 300 (hereinafter referred to as the printer 300) includes a photosensitive drum 101 as a photosensitive member on which an electrostatic latent image is formed, and a charging roller 102 (charging means) that charges the photosensitive drum 101 to a uniform potential. There is. The printer 300 further includes an exposure unit 319 (exposure unit) that forms an electrostatic latent image on the photosensitive drum 101, and a developing roller 104 that develops the electrostatic latent image formed on the photosensitive drum 101 (on the photosensitive drum) with toner. A developing device (developing means) is provided. Then, the toner image developed on the photosensitive drum 101 is transferred onto a sheet 109 (not shown) as a recording material supplied from the cassette 316 by a transfer roller 105 (transfer means), and the toner image transferred onto the sheet 109 is fixed. The image is fixed in a container 314 and discharged onto a tray 315. The cleaning blade 106 removes toner that has not been transferred to the sheet 109 and remains on the photosensitive drum 101, and the removed toner is accumulated in a waste toner box 107 that stores waste toner. The photosensitive drum 101, charging roller 102, exposure section 319, developing roller 104, and transfer roller 105 constitute an image forming section. The printer 300 also includes a power supply device 500 that supplies a power supply voltage to a load, which will be described later. Note that the image forming apparatus is not limited to that illustrated in FIG. 8A, and may be an image forming apparatus that includes a plurality of image forming sections, for example. Furthermore, the image forming apparatus may include a primary transfer section that transfers the toner image on the photosensitive drum 101 onto an intermediate transfer belt, and a secondary transfer section that transfers the toner image on the intermediate transfer belt onto a sheet.

The printer 300 includes a controller 320 including a CPU that controls the image forming operation by the image forming unit and the conveying operation of the sheet 109. The power supply device 500 includes, for example, a low voltage power supply that supplies power to the controller 320, and a high voltage power supply (voltage source) that supplies high voltage to the charging roller 102, the developing roller 104, and the transfer roller 105.

[Configuration of image forming section]
FIG. 8(b) is a cross-sectional view of the vicinity of the image forming unit for explaining the image forming operation in the image forming unit of the printer 300 shown in FIG. 8(a). A charging voltage Vpr, which is an output voltage of a charging voltage source VPR that supplies a high charging voltage, is applied to the charging roller 102 . The charging voltage Vpr is approximately -1000V. The charging roller 102 charges the surface potential of the photosensitive drum 101 to the dark area potential Vd. The dark potential Vd is approximately -700V. The photosensitive drum 101 rotates in the direction of the arrow (clockwise) in FIG. 8B and is irradiated with the laser beam 103 emitted from the exposure section 319. The surface potential of the photosensitive drum 101 is neutralized to the bright area potential Vl by being irradiated with the laser beam 103. The bright area potential Vl is approximately -100V. The photosensitive drum 101 further rotates and comes into contact with the developing roller 104. A developing voltage Vdc is applied to the developing roller 104. The developing voltage Vdc is approximately -400V. Toner 100 is attached to the surface of the developing roller 104 . The toner 100 is a negatively charged powder. At this time, the bright area potential Vl (approximately -100 V) irradiated with the laser beam 103 is higher than the developing voltage Vdc (approximately -400 V), so the toner 100 adheres to the surface of the photosensitive drum 101.

Then, the photosensitive drum 101 further rotates and comes into contact with the transfer roller 105 via the sheet 109. A transfer voltage Vtr, which is an output voltage of a transfer voltage source VTR that supplies a high-voltage transfer voltage, is applied to the transfer roller 105. The transfer voltage Vtr is approximately +1000V. At this time, since the transfer voltage Vtr (approximately +1000 V) is higher than the bright area potential Vl (approximately -100 V) to which the toner 100 is attached, the toner 100 is peeled off from the photosensitive drum 101 and placed on the sheet 109. Attach to. The sheet 109 is conveyed to the left in FIG. 8(b), and is pressurized and heated by the fixing device 314 (FIG. 8(a)). Then, the toner 100 on the sheet 109 is melted and fixed on the sheet 109. Note that the shunt current Is indicated by the broken line will be explained later.

[Conventional development voltage circuit configuration]
FIG. 9 is a circuit diagram illustrating the configuration of a conventional developing voltage circuit Bias that generates the developing voltage Vdc applied to the developing roller 104. The developing voltage Vdc is generated by the developing voltage circuit Bias, the shunt resistor R0, and the charging voltage source VPR.

In the developing voltage circuit Bias shown in FIG. 9, the CPU, which is the control unit, is supplied with the specified voltage Vb, which is the third voltage source, as the power supply voltage, and receives a pulse signal from the output terminal TGT to control the developing voltage Vdc. Outputs a PWM signal. The output terminal TGT is connected to one end of a resistor R14, and the other end of the resistor R14 is connected to one end of the capacitor C2 and the inverting input terminal (-) of the operational amplifier OP1. The resistor R14 and the capacitor C2 constitute a smoothing section that smoothes the PWM signal output from the TGT terminal of the CPU. The other end of the capacitor C2 is connected (grounded) to the ground (GND). Resistors R12 and R13 are connected in series between the specified voltage Vb and the output developing voltage Vdc. A connection point between the resistor R12 and the resistor R13 is connected to the non-inverting input terminal (+) of the operational amplifier OP1. An output terminal of the operational amplifier OP1, which is a control means, is connected to a non-inverting input terminal (+) via a capacitor C1. Further, the output terminal of the operational amplifier OP1 and the non-inverting input terminal (+) are connected via a capacitor C1.

The pnp transistor Tr1, which is the first transistor, has an emitter terminal connected to a specified voltage Va, which is a first voltage source, and a collector terminal connected to the emitter terminal of the transistor Tr2. The base terminal of the transistor Tr1 is connected to the specified voltage Va via a resistor R10, the base terminal of the transistor Tr2 is connected via a resistor R1 which is a first resistor, and the output terminal of the operational amplifier OP1 is connected via a resistor R11. is connected to. The emitter terminal of the pnp transistor Tr2, which is the second transistor, is connected to the collector terminal of the transistor Tr1. Further, the collector terminal of the transistor Tr2 is connected to the other end of the resistor R2, which is a second resistor whose one end is connected to the base terminal of the transistor Tr2, and to the terminal of the resistor R13 on the opposite side from the connection point with the resistor R12. has been done. Furthermore, the collector terminal of the transistor Tr2 is connected to the output terminal of the developing voltage Vdc and one end of a shunt resistor R0, which is a third resistor. The other end of the shunt resistor R0 is connected to an output terminal of the charging voltage Vpr and a charging voltage source VPR, which is a second power source.

[Operation of conventional developing voltage circuit]
As described above, in FIG. 9, the transistors Tr1 and Tr2 constituting the voltage generation section are connected to a specified voltage Va (for example, +24V DC voltage), and the collector terminal of the transistor Tr2 is connected to the collector terminal of the transistor Tr2 via the shunt resistor R0. A charging voltage source VPR is connected. A shunt current Is (hereinafter also referred to as collector current Is) indicated by a broken line flows along a path of specified voltage Va→transistor Tr1→transistor Tr2→shunt resistor R0→charged voltage source VPR→ground (GND). The developing voltage circuit Bias can output a desired developing voltage Vdc to the developing roller 104 by appropriately increasing or decreasing the current value of the shunt current Is using a PWM signal output from the TGT terminal. As a result, the developing voltage Vdc can be expressed by the following (Equation 1).
Developing voltage Vdc=Vpr+R0×Is...(Formula 1)

A resistor R12 and a resistor R13 connected in series are arranged between the specified voltage Vb (for example, a DC voltage of +3.3V) and the developing voltage Vdc. The divided voltage Vsns divided by the resistors R12 and R13 is input as a reference voltage to the non-inverting input terminal (+) which is the second input terminal of the operational amplifier OP1. On the other hand, the target voltage Vtgt, which is a voltage corresponding to the desired developing voltage Vdc, is input from the capacitor C2 to the inverting input terminal (-), which is the first input terminal of the operational amplifier OP1. The target voltage Vtgt is a DC voltage obtained by smoothing the PWM signal output from the output terminal TGT of the CPU by a resistor R14 and a capacitor C2. The operational amplifier OP1 compares the input voltages input to the inverting input terminal (-) and the non-inverting input terminal (+), and outputs an output voltage Vo according to the comparison result from the output terminal.

When the divided voltage Vsns is higher than the target voltage Vtgt, the output voltage Vo at the output terminal of the operational amplifier OP1 increases. Then, the base current flowing to the base terminal of the transistor Tr1 decreases, and as a result, the collector current Is (also the shunt current Is) flowing to the collector terminal of the transistor Tr1 decreases. When the collector current Is of the transistor Tr1 decreases, the developing voltage Vdc decreases according to the above-mentioned (Formula 1). Then, the divided voltage Vsns obtained by dividing the specified voltage Vb and the developing voltage Vdc by the resistors R12 and R13 decreases.

On the other hand, when the divided voltage Vsns is lower than the target voltage Vtgt, the output voltage Vo at the output terminal of the operational amplifier OP1 decreases. Then, the base current flowing to the base terminal of the transistor Tr1 increases, and as a result, the collector current Is flowing to the collector terminal of the transistor Tr1 increases. When the collector current Is increases, the developing voltage Vdc increases according to the above-mentioned (Formula 1). Then, the divided voltage Vsns obtained by dividing the specified voltage Vb and the developing voltage Vdc by the resistors R12 and R13 increases. In this way, negative feedback is applied to the operational amplifier OP1, and the target voltage Vtgt is always approximately equal to the divided voltage Vsns.

The CPU has a ROM (not shown) that is a nonvolatile memory. The ROM contains a table that associates the on-duty ratio (ratio of on-state in one cycle) of the PWM signal with the developing voltage Vdc for outputting the target voltage Vtgt to the inverting input terminal (-) of the operational amplifier OP1. Stored. Then, the CPU sets the on-duty ratio of the PWM signal output from the TGT terminal so that the desired developing voltage Vdc is output to the developing roller 104. In the developing voltage circuit Bias shown in FIG. 9, the higher the on-duty ratio of the PWM signal corresponding to the target voltage Vtgt, the higher the developing voltage Vdc becomes.

A resistor R1 and a resistor R2 are connected in series between the base terminal of the transistor Tr1 and the output terminal of the developing voltage Vdc. The resistor R1 and the resistor R2 have substantially the same resistance value. Furthermore, a divided voltage obtained by dividing the voltage applied to the base terminal of the transistor Tr1 and the developing voltage Vdc by the resistor R1 and the resistor R2 is applied to the base terminal of the transistor Tr2.

The voltage applied to the base terminal of the transistor Tr1 is lower than the specified voltage Va by the base-emitter voltage of the transistor Tr1. Since the base-emitter voltage is a very small voltage of approximately 0.6V, there is no problem in considering it to be approximately 0V. Therefore, the specified voltage Va is applied to the terminal (upper terminal) of the resistor R1 connected to the base terminal of the transistor Tr1. On the other hand, the developing voltage Vdc is applied to a terminal (lower terminal) connected to the output terminal of the resistor R2 to which the developing voltage Vdc is output. Therefore, the connection point where the resistor R1 and the resistor R2 having substantially the same resistance value are connected is a voltage dividing point between the specified voltage Va and the developing voltage Vdc. As a result, the intermediate voltage between the specified voltage Va and the developing voltage Vdc, that is, (regulated voltage Va + developing voltage Vdc)/2, is applied to the base terminal of the transistor Tr2 connected to the connection point where the resistors R1 and R2 are connected. will be applied. Then, the emitter-collector voltage of the transistor Tr1 and the emitter-collector voltage of the transistor Tr2 become approximately equal. The purpose of using multiple transistors like transistors Tr1 and Tr2 is to distribute the emitter-collector voltage of the transistors to each transistor, thereby making it possible to use transistors with lower breakdown voltages. be.

FIG. 10 is an example of a circuit in which a transistor Tr3 and a resistor R3 are further added to the developing voltage circuit of FIG. In this way, by adding a transistor and a resistor, it is possible to further disperse the emitter-collector voltage. Although FIG. 10 shows an example of a circuit using three transistors, it is also possible to increase the number of transistors to four or more, for example.

[Issues with conventional development voltage circuits]
FIG. 11 is a cross-sectional view of the image forming section illustrating a state in which the photosensitive drum 101 starts rotating from a stopped state (FIG. 11(a)) to a state in which it starts rotating (FIG. 11(b)). In FIG. 11A, the fan-shaped area from the position where the photosensitive drum 101 contacts the charging roller 102 to the position where the photosensitive drum 101 contacts the developing roller 104 has a surface potential of 0V. When the photosensitive drum 101 starts rotating, the state shown in FIG. 11(a) shifts to the state shown in FIG. 11(b). At this time, if the developing voltage Vdc applied to the developing roller 104 is a negative potential lower than 0V, the toner 100 on the surface of the developing roller 104 will adhere to the photosensitive drum 101 side, which has a higher potential. Therefore, in order to prevent the toner 100 from adhering to the photosensitive drum 101, it is conceivable to set the developing voltage Vdc applied to the developing roller 104 to a voltage higher than 0V, but this is difficult with the conventional developing voltage circuit described above. The operation of the conventional developing voltage circuit when the photosensitive drum 101 starts rotating will be described below.

[Operation of the developing voltage circuit when the photosensitive drum starts rotating]
FIG. 12 is a diagram illustrating the circuit operation when the maximum developing voltage Vdc is output from the developing voltage circuit Bias. The circuit diagram in FIG. 12 is similar to the circuit diagram in FIG. 9 described above, and the flow of the current Is shown by the broken line indicates the flow of current during normal operation of the photosensitive drum 101 described in FIG. 9. On the other hand, in FIG. 12, currents Ib1 and Ib2 shown by solid lines indicate the current flows when the photosensitive drum 101 starts rotating.

In FIG. 12,
1) The CPU outputs a PWM signal with a maximum on-duty ratio (100%) from the output terminal TGT. As a result, the target voltage smoothed by the capacitor C1 and input to the inverting input terminal (-) of the operational amplifier OP1 is always approximately the specified voltage Vb (see circled number 1 in FIG. 12).
2) As a result, the voltage Vo output from the output terminal of the operational amplifier OP1 becomes approximately 0V (see circled number 2 in FIG. 12).

3) Since the voltage output from the output terminal of the operational amplifier OP1 becomes approximately 0V, the current Ib1 (indicated by a solid line in the figure) flowing into the base terminal of the transistor Tr1 increases. As a result, the transistor Tr1 becomes saturated, and the emitter-collector voltage Vce1 of the transistor Tr1 becomes approximately 0.3V (see circled number 3 in FIG. 12).
4) As a result, the collector voltage Vc1 output from the collector terminal of the transistor Tr1 becomes the specified voltage Va - the emitter-collector voltage Vce1 (of the transistor Tr1), as shown in the following (Equation 2) (Fig. 12 (see circle number 4).
Collector voltage Vc1=Va-Vce1... (Formula 2)

5) When the transistor Tr1 is turned on, a base current Ib2 (indicated by a solid line in the figure) flows to the base terminal of the transistor Tr2. As a result, the base voltage Vb2 at the base terminal of the transistor Tr2 becomes the collector voltage Vc1 (of the transistor Tr1) - the base-emitter voltage Vbe2 (of the transistor Tr2), as shown in the following (Equation 3) (Fig. 12 (see circled number 5).
Base voltage Vb2=Vc1-Vbe2...(Formula 3)
6) Let the current amplification factor of the transistor Tr2 be hfe2, and let the collector current Is flowing to the collector terminal of the transistor Tr2. As shown in the following (Equation 4), a collector current Is obtained by multiplying the base current Ib2 (of the transistor Tr2) by the current amplification factor hfe2 (of the transistor Tr2) flows through the transistor Tr2 (see circled number 6 in FIG. 12). ).
Collector current Is=hfe2×Ib2...(Formula 4)

7) Since the collector voltage Vc2 of the transistor Tr2 is the developing voltage Vdc applied to the developing roller 104, the base current Ib2 of the transistor Tr2 is expressed by the following (Equation 5) (circled number 7 in FIG. 12). reference).
Base current Ib2=(Vb2-Vdc)/R2...(Formula 5)

The above-mentioned (Formula 1) to (Formula 5) are shown below.
Vdc=Vpr+R0×Is...(Formula 1)
Vc1=Va-Vce1...(Formula 2)
Vb2=Vc1-Vbe2...(Formula 3)
Is=hfe2×Ib2...(Formula 4)
Ib2=(Vb2-Vdc)/R2...(Formula 5)
Then, by using (Formula 1) to (Formula 5) to eliminate the collector current Is from (Formula 1) and solving for the developing voltage Vdc, the following (Formula 6) is obtained.
Developing voltage Vdc=(R2×Vpr+R0×hfe2×(Va-Vce1-Vbe2))
/(R2+R0×hfe2)...(Formula 6)

Generally, the shunt resistance R0 is about 3.3MΩ, the resistance R2 is about 10MΩ, the current amplification factor hfe2 is about 50, the emitter-collector voltage Vce1 is about 0.3V, and the base-emitter voltage Vbe2 is about 0.6V. . Further, the charging voltage Vpr is about -1000V, and the specified voltage Va is about +24V. When these values are substituted into equation (6), the developing voltage Vdc becomes approximately -35V. In other words, the developing voltage Vdc has a negative potential of -35V, which is lower than 0V, which is the surface voltage of the photosensitive drum 101, so the toner 100 on the developing roller 104 will adhere to the photosensitive drum 101 side. .

[assignment]
As described above, the area of the photosensitive drum 101 from the position where it contacts the charging roller 102 to the position where it contacts the developing roller 104 at the start of rotation is an area where the surface potential is 0V. Therefore, when the photosensitive drum 101 starts rotating, the toner 100 from the developing roller 104 adheres to the area where the surface potential is 0V. The toner 100 attached to the photosensitive drum 101 is placed on the downstream side in the rotational direction of the photosensitive drum 101, contacts the photosensitive drum 101, and adheres to a transfer roller 105 to which a positive voltage is applied. As a result, the adhered toner 100 stains the surface of the transfer roller 105, and the toner 100 adheres to the back surface (the surface on the transfer roller 105 side) of the sheet 109 conveyed to the transfer roller 105, causing the back surface of the sheet 109 to be stained. Cause. Furthermore, the toner 100 remaining on the photosensitive drum 101 is removed by a cleaning blade 106. As the amount of toner 100 to be removed increases, a problem arises in that the waste toner box 107 that stores the waste toner 108 becomes larger, which in turn causes the image forming apparatus to become larger.

Next, an embodiment of the developing voltage circuit Bias to which the present invention is applied will be described. The configuration of the image forming apparatus to which the developing voltage circuit of this embodiment is applied and the image forming unit including the developing roller to which the developing voltage outputted from the developing voltage circuit Bias is supplied is shown in FIGS. 8 and 11 described above. This is the same as , and the explanation will be omitted.

[Configuration of development voltage circuit]
FIG. 1 is a circuit diagram showing the circuit configuration of the developing voltage circuit Bias of this embodiment. The circuit configuration shown in FIG. 1 differs from the circuit configuration of the conventional developing voltage circuit Bias shown in FIG. 9 described above in that a diode D1 and a resistor R15, which serve as bypass means, are added. In FIG. 1, the resistor R15 has one end connected to the output terminal of the operational amplifier OP1, one end of the capacitor C1, and one end of the resistor R11, and the other end connected to the cathode terminal of the diode D1. Further, the diode D1 has a cathode terminal connected to the other end of the resistor R15, and an anode terminal connected to one end of the resistor R1, one end of the resistor R2, and the base terminal of the transistor Tr2. Note that the other circuit configurations in FIG. 1 are the same as the circuit configuration in FIG. 9, and will not be described here.

[Operation of developing voltage circuit]
Next, the operation of the developing voltage circuit Bias will be explained separately into the circuit operation when the photosensitive drum 101 starts rotating (starting up) and the circuit operation during normal operation.

[Operation of the developing voltage circuit when starting the photosensitive drum]
As described above, when the photosensitive drum 101 starts rotating, there is a portion on the photosensitive drum 101 where the surface potential reaches the developing roller 104 while remaining at 0 V, like the gray fan-shaped portion shown in FIG. At this time, if the developing voltage Vdc is a negative potential lower than 0V, the toner 100 will adhere to the surface of the photosensitive drum 101, which has a high potential. As a result, the toner adhering to the photosensitive drum 101 may adhere to the transfer roller 105 and stain the transfer roller 105, causing the back side of the sheet 109 to become stained. Further, there is a problem in that the waste toner box 107 in which the adhered toner collected by the cleaning blade 106 is stored becomes larger, which in turn causes the image forming apparatus to become larger.

Therefore, the developing voltage circuit of this embodiment has a configuration that prevents the toner 100 from adhering to the photosensitive drum 101 when the photosensitive drum 101 starts rotating by setting the developing voltage Vdc to a positive voltage higher than 0 V if possible. are doing.

FIG. 2 is a diagram illustrating a circuit operation when the maximum developing voltage Vdc is output from the developing voltage circuit Bias when the photosensitive drum 101 starts rotating. In FIG. 2, currents Ib1 and Ib2 shown by solid lines indicate current flows when the photosensitive drum 101 starts rotating. On the other hand, the flow of current Is indicated by a broken line indicates the flow of current during normal operation of the photosensitive drum 101, which will be described later.

In Figure 2,
1) The CPU outputs a PWM signal with a maximum on-duty ratio (100%) from the output terminal TGT. As a result, the target voltage smoothed by the capacitor C2 and input to the inverting input terminal (-) of the operational amplifier OP1 is always approximately the specified voltage Vb (see circled number 1 in FIG. 2).
2) As a result, the voltage Vo output from the output terminal of the operational amplifier OP1 becomes approximately 0V (see circled number 2 in FIG. 2).

3) Since the voltage output from the output terminal of the operational amplifier OP1 becomes approximately 0V, the current Ib1 (indicated by a solid line in the figure) flowing into the base terminal of the transistor Tr1 increases. As a result, the transistor Tr1 becomes saturated, and the emitter-collector voltage Vce1 of the transistor Tr1 becomes approximately 0.3V (see circled number 3 in FIG. 2).
4) As a result, the collector voltage Vc1 output from the collector terminal of the transistor Tr1 becomes the specified voltage Va - the emitter-collector voltage Vce1 (of the transistor Tr1), as shown in the following (Equation 2) (Fig. 2 (see circle number 4).
Collector voltage Vc1=Va-Vce1... (Formula 2)

5) When the transistor Tr1 is turned on, a base current Ib2 (indicated by a solid line in the figure) flows through the base terminal of the transistor Tr2. As a result, the base voltage Vb2 at the base terminal of the transistor Tr2 becomes the collector voltage Vc1 (of the transistor Tr1) - the base-emitter voltage Vbe2 (of the transistor Tr2), as shown in the following (Equation 3) (Fig. 2 (see circled number 5).
Base voltage Vb2=Vc1-Vbe2...(Formula 3)
6) By using (Formula 2) and eliminating the collector voltage Vc1 (of transistor Tr1) from (Formula 3), the following (Formula 7) is obtained.
Base voltage Vb2=Va-Vce1-Vbe2...(Formula 7)
Generally, the emitter-collector voltage Vce1 is about 0.3V, the base-emitter voltage Vbe2 is about 0.6V, and the specified voltage Va is about +24V. When these values are substituted into (Equation 7), the base voltage Vb2 (at the base terminal of the transistor Tr2) becomes approximately +23.1V. Since the voltage at the cathode terminal of the diode D1 is approximately 0V and the voltage at the anode terminal is 23.1V, the diode D1 becomes conductive. As a result, the base current Ib2 of the transistor Tr2 flows through the path of the base terminal of the transistor Tr2, the diode D1, the resistor R15, and the operational amplifier OP1 (see circled number 6 in FIG. 2).

7) Current Ib2 (indicated by a solid line in the figure) flows from the base terminal of the transistor Tr2, so that the transistor Tr2 is saturated, and the emitter-collector voltage Vce2 of the transistor Tr2 becomes approximately 0.3V (in FIG. 2, (See circled number 7).
8) The developing voltage Vdc at this time is expressed by the following (Equation 8) (see circled number 8 in FIG. 2).
Developing voltage Vdc=Va-Vce1-Vce2...(Formula 8)

Generally, the emitter-collector voltage Vce1 (of the transistor Tr1) is about 0.3V, the emitter-collector voltage Vce2 (of the transistor Tr2) is about 0.3V, and the specified voltage Va is about +24V. When these values are substituted into (Equation 8), the developing voltage Vdc becomes approximately +23.4V. That is, by setting the developing voltage Vdc to +23.4 V, which is higher than the surface voltage of the photosensitive drum 101 of 0 V, it is possible to prevent the toner 100 from adhering to the surface of the photosensitive drum 101.

[Operation of the developing voltage circuit during normal operation of the photosensitive drum]
Next, the operation of the developing voltage circuit Bias during normal operation of the photosensitive drum 101 will be described. Here, the term "normal operation" refers to the operating state of the photosensitive drum 101, excluding the time when the photosensitive drum 101 starts rotating as described above. Specifically, the normal operation refers to the operating state of the photosensitive drum 101 after the area of the photosensitive drum 101 charged by the charging roller 102 has moved to the developing roller 104.

In the developing voltage circuit Bias, as shown in FIG. 2, transistors Tr1 and Tr2 are connected to a specified voltage Va (for example, +24V DC voltage), and a charging voltage is connected to the collector terminal of transistor Tr2 via a shunt resistor R0. source VPR is connected. During normal operation of the photosensitive drum 101, a shunt current Is shown by a broken line in the figure flows along a path of specified voltage Va→transistor Tr1→transistor Tr2→shunt resistor R0→charging voltage source VPR→ground (GND). The developing voltage circuit Bias can output a desired developing voltage Vdc to the developing roller 104 by appropriately increasing or decreasing the current value of the shunt current Is using a PWM signal output from the TGT terminal, and the developing voltage Vdc is as described above. It can be expressed by the following (Equation 1).
Developing voltage Vdc=Vpr+R0×Is...(Formula 1)

A divided voltage Vsns divided by a resistor R12 and a resistor R13 connected in series between the specified voltage Vb and the developing voltage Vdc is input to the non-inverting input terminal (+) of the operational amplifier OP1. On the other hand, the target voltage Vtgt, which is a DC voltage obtained by smoothing the PWM signal output from the output terminal TGT of the CPU by the resistor R14 and the capacitor C2, is input to the inverting input terminal (-) of the operational amplifier OP1.

When the divided voltage Vsns is higher than the target voltage Vtgt, the output voltage Vo of the operational amplifier OP1 increases and the base current of the transistor Tr1 decreases, so that the collector current Is of the transistor Tr1 decreases. As a result, the developing voltage Vdc decreases according to the above-mentioned (Formula 1). Then, the divided voltage Vsns obtained by dividing the specified voltage Vb and the developing voltage Vdc by the resistors R12 and R13 decreases. On the other hand, when the divided voltage Vsns is lower than the target voltage Vtgt, the output voltage Vo of the operational amplifier OP1 decreases, and when the base current of the transistor Tr1 increases, the collector current Is of the transistor Tr1 increases. As a result, the developing voltage Vdc increases according to the above-mentioned (Formula 1). Then, the divided voltage Vsns obtained by dividing the specified voltage Vb and the developing voltage Vdc by the resistors R12 and R13 increases. In this way, negative feedback is applied to the operational amplifier OP1, and the target voltage Vtgt is always approximately equal to the divided voltage Vsns.

Resistors R1 and R2 having approximately the same resistance value are connected in series between the base terminal of the transistor Tr1 and the output terminal of the developing voltage Vdc, and the divided voltage divided by the resistors R1 and R2 is applied to the transistor. It is applied to the base terminal of Tr2. Since it is safe to assume that the base-emitter voltage of the transistor Tr1 is approximately 0V, the specified voltage Va is applied to the terminal (upper terminal) of the resistor R1 connected to the base terminal of the transistor Tr1. On the other hand, the developing voltage Vdc is applied to a terminal (lower terminal) connected to the output terminal of the resistor R2 to which the developing voltage Vdc is output. As a result, the intermediate voltage between the specified voltage Va and the developing voltage Vdc, that is, (regulated voltage Va + developing voltage Vdc)/2, is applied to the base terminal of the transistor Tr2 connected to the connection point where the resistors R1 and R2 are connected. will be applied.

Therefore, during normal operation of the photosensitive drum 101 described above, the voltage on the cathode terminal side of the diode D1 is higher than the voltage on the anode terminal side, and the diode D1 is maintained in a non-conductive state. Therefore, in the circuit in which the diode D1 and the resistor R15 are connected in series, the base current Ib2 of the transistor Tr2 flows when the photosensitive drum 101 starts rotating, but no current flows during the normal operation of the photosensitive drum 101. As a result, when the photosensitive drum 101 starts rotating, the developing voltage Vdc applied to the developing roller 104 can be set to a voltage higher than 0 V, and it is possible to prevent the toner 100 from adhering to the photosensitive drum 101. As a result, the toner 100 that has adhered to the photosensitive drum 101 adheres to the transfer roller 105, and the toner 100 adheres to the back surface (the surface on the transfer roller 105 side) of the sheet conveyed to the transfer roller 105, thereby staining the back of the sheet 109. can be prevented from occurring. Furthermore, since the toner 100 does not adhere to the photosensitive drum 101, it is possible to avoid increasing the size of the waste toner box 107 that stores the adhered toner 100 on the photosensitive drum 101 that is removed by the cleaning blade 106, and the accompanying increase in the size of the image forming apparatus. can do.

Note that the purpose of using multiple transistors like transistors Tr1 and Tr2 in FIG. 2 is to distribute the emitter-collector voltage of the transistors to each transistor, thereby allowing the use of transistors with low breakdown voltages. This is to ensure that. Therefore, for example, by adding a transistor Tr3, a resistor R3, a resistor R16, and a diode D2 to the circuit of FIG. 2, like the developing voltage circuit Bias shown in FIG. 3, the emitter-collector voltage can be further dispersed. Although the number of transistors used in FIG. 3 is three, it is possible to increase the number to four or more, for example.

As described above, according to this embodiment, it is possible to prevent toner from adhering to an uncharged area on the photosensitive drum when the photosensitive drum starts rotating.

In the first embodiment, an example has been described in which the developing voltage Vdc is generated from the charging voltage Vpr of the charging voltage source VPR by using the voltage drop caused by the shunt resistor R0. Embodiment 2 describes an example in which a developing voltage source VDC0 that supplies a high-voltage developing voltage is provided, and a developing voltage Vdc is generated from the output voltage Vdc0 of the developing voltage source VDC0 using a voltage drop caused by a shunt resistor R0. do.

[Configuration of image forming section]
FIG. 4 is a cross-sectional view illustrating the configuration around the image forming section of this embodiment in the image forming section of the printer 300 shown in FIG. 8(a). In the case of the first embodiment, the charging voltage Vpr supplied to the charging roller 102 is supplied from the charging voltage source VPR, and the developing voltage Vdc supplied to the developing roller 104 is also supplied from the charging voltage source VPR via the shunt resistor R0. It was supplied from. On the other hand, in this embodiment, as shown in FIG. 4, the output voltage from the charging voltage source VPR is supplied only to the charging roller 102 as the charging voltage Vpr. On the other hand, the developing voltage Vdc is determined by providing a developing voltage source VDC0, which is a second voltage source that supplies a high-voltage developing voltage, and using the voltage drop caused by the shunt resistor R0 from the developing voltage Vdc0 output from the developing voltage source VDC0. is generated.

[Configuration of development voltage circuit]
FIG. 5 is a circuit diagram showing the circuit configuration of the developing voltage circuit Bias of this embodiment. The circuit configuration of the developing voltage circuit Bias shown in FIG. 5 is the same as the circuit configuration of the developing voltage circuit Bias shown in FIG. Unlike the voltage source VPR in FIG. 5, the difference is that the developing voltage source VDC0 is used in FIG. In the circuit shown in FIG. 5, a developing voltage Vdc is generated from a developing voltage Vdc0 outputted by a developing voltage source VDC0 using a voltage drop caused by a shunt resistor R0.

[Operation of developing voltage circuit]
Next, the operation of the developing voltage circuit of this embodiment will be explained separately into the circuit operation when the photosensitive drum 101 starts rotating (starting up) and the circuit operation during normal operation.

[Operation of the developing voltage circuit when starting the photosensitive drum]
The circuit configuration of the developing voltage circuit Bias of this embodiment shown in FIG. 5 is the same as the circuit configuration of the developing voltage circuit Bias of the first embodiment shown in FIG. Therefore, the circuit operation at the start of rotation of the photosensitive drum 101 (at startup) is the same as in the first embodiment, and the description thereof will be omitted here.

[Operation of the developing voltage circuit during normal operation of the photosensitive drum]
Next, the operation of the developing voltage circuit Bias during normal operation of the photosensitive drum 101 will be described. In the developing voltage circuit Bias of this embodiment, as shown in FIG. 5, the transistors Tr1 and Tr2 are connected to a specified voltage Va (for example, +24V DC voltage), and the collector terminal of the transistor Tr2 is connected via a shunt resistor R0. , are connected to the developing voltage source VDC0. During normal operation of the photosensitive drum 101, a shunt current Is shown by a broken line in the figure flows along a path of specified voltage Va→transistor Tr1→transistor Tr2→shunt resistor R0→developing voltage source VDC0→ground (GND). The developing voltage circuit Bias can output a desired developing voltage Vdc to the developing roller 104 by appropriately increasing or decreasing the current value of the shunt current Is using the PWM signal output from the TGT terminal. It can be expressed by (Equation 9).
Developing voltage Vdc=Vdc0+R0×Is...(Formula 9)

The circuit operation of the developing voltage circuit Bias when the divided voltage Vsns is higher than the target voltage Vtgt and when the divided voltage Vsns is lower than the target voltage Vtgt is the same as in the first embodiment, and the description thereof will be omitted. Further, as in the first embodiment, (specified voltage Va+developing voltage Vdc)/2, which is an intermediate voltage between the specified voltage Va and the developing voltage Vdc, is applied to the base terminal of the transistor Tr2. Therefore, during the normal operation of the photosensitive drum 101 described above, the voltage on the cathode terminal side of the diode D1 is higher than the voltage on the anode terminal side, and the diode D1 is maintained in a non-conductive state.

In this way, in this embodiment as well, as in the first embodiment, in the circuit in which the diode D1 and the resistor R15 are connected in series, when the photosensitive drum 101 starts rotating, the base current Ib2 of the transistor Tr2 flows, and the photosensitive drum 101 The configuration is such that no current flows during normal operation. As a result, when the photosensitive drum 101 starts rotating, the developing voltage Vdc applied to the developing roller 104 can be set to a voltage higher than 0 V, and it is possible to prevent the toner 100 from adhering to the photosensitive drum 101. This can prevent the back surface of the sheet 109 from being stained due to the toner 100 adhering to the back surface of the sheet (the surface on the transfer roller 105 side). Further, since the toner 100 does not adhere to the photosensitive drum 101, the amount of adhered toner 100 on the photosensitive drum 101 that is removed by the cleaning blade 106 when the photosensitive drum 101 starts rotating is reduced. As a result, it is possible to avoid increasing the size of the waste toner box 107 that stores the removed adhered toner 100 and increasing the size of the image forming apparatus.

As described above, according to this embodiment, it is possible to prevent toner from adhering to an uncharged area on the photosensitive drum when the photosensitive drum starts rotating.

In Examples 1 and 2, the circuit configuration was described in which the specified voltage Va applied to the collector terminal of the transistor Tr1 of the developing voltage circuit Bias was a positive voltage of several tens of V (for example, a DC voltage of +24 V). Generally, the withstand voltage of the output terminal of the operational amplifier OP1 used in the developing voltage circuit Bias is several tens of V, and depending on the withstand voltage of the operational amplifier OP1, the voltage of the specified voltage Va can be set as a positive voltage of several tens of V. There is. It is desirable that the breakdown voltage of the output terminal of the operational amplifier OP1 be the same as the specified voltage Va or higher than the specified voltage Va.

On the other hand, when the photosensitive drum 101 starts rotating, there is an area on the photosensitive drum 101, like the fan-shaped area in FIG. 11, where the surface potential remains at 0 V and moves to the developing roller 104. At this time, if the developing voltage Vdc applied to the developing roller 104 is a negative potential lower than 0V, the toner 100 on the surface of the developing roller 104 will adhere to the photosensitive drum side, which has a higher potential. .

As mentioned above, as a countermeasure for this, it is effective to set the developing voltage Vdc as high as possible. If you try to set the developing voltage Vdc to a higher voltage (for example, a positive voltage of plus several tens of V to plus several hundred V), it is necessary to make the specified voltage Va, which is a predetermined voltage, higher. It becomes necessary to increase the withstand voltage of the output terminal. However, this results in an increase in the cost of the circuit. In the third embodiment, a method of setting the specified voltage Va to a high value without increasing the withstand voltage of the output terminal of the operational amplifier OP1 will be described.

[Configuration of image forming section]
FIG. 6 is a cross-sectional view illustrating the configuration around the image forming section of the present embodiment in the image forming section of the printer 300 shown in FIG. 8(a). In the developing voltage circuit Bias of Example 1 shown in FIG. 8(b), the transistor Tr1 was connected to the specified voltage Va. On the other hand, in this embodiment, as shown in FIG. 6, the transistor Tr1 of the developing voltage circuit Bias is connected to the voltage source VE that outputs the voltage Ve. Note that the voltage value of the voltage Ve output from the voltage source VE is, for example, a DC voltage of plus several tens of volts to plus several hundred volts.

[Configuration of development voltage circuit]
FIG. 7 is a circuit diagram showing the circuit configuration of the developing voltage circuit Bias of this embodiment. The circuit configuration of the developing voltage circuit Bias shown in FIG. 7 differs from the developing voltage circuit Bias shown in FIG. 1 of the first embodiment in the following points. That is, the voltage connected to the transistor Tr1 was the specified voltage Va in the first embodiment, but in the third embodiment, the voltage Ve (Ve >Va). In the developing voltage circuit Bias, in the case of the third embodiment, a transistor Tr4, which is a third transistor, and resistors R17 and R18 are connected between the output terminal of the operational amplifier OP1 and one end of the resistor R11 and one end of the resistor R15. The difference is that a configured circuit is added.

In FIG. 7, the resistor R17 has one end connected to the output terminal of the operational amplifier OP1 and one end of the capacitor C1, and the other end connected to one end of the resistor R18 and the base terminal of the transistor Tr4. The other end of the resistor R18 is connected to the emitter terminal of the transistor Tr4. A collector terminal of the transistor Tr4 is connected to one end of a resistor R11 and one end of a resistor R15, and an emitter terminal is connected to GND. Further, the emitter terminal of the transistor Tr1 and one end of the resistor R10 are connected to the voltage source VE. The other circuit configurations are the same as those in FIG. 1 of the first embodiment, and their explanation will be omitted.

[Operation of developing voltage circuit]
Next, the operation of the developing voltage circuit of this embodiment will be explained separately into the circuit operation when the photosensitive drum 101 starts rotating (starting up) and the circuit operation during normal operation.

[Operation of the developing voltage circuit when starting the photosensitive drum]
In FIG. 7, the transistor Tr4 is an npn type transistor that is turned on when the output voltage Vo from the output terminal of the operational amplifier OP1 is at a high level and turned off when it is at a low level. Therefore, in the first embodiment, the CPU outputs the PWM signal with the maximum on-duty ratio (100%) from the output terminal TGT, but in this embodiment, the CPU outputs the PWM signal with the minimum on-duty ratio (0) from the output terminal TGT. %) PWM signal is output. This causes a high level voltage to be output from the output terminal of the operational amplifier OP1. Note that the CPU adjusts the on-duty ratio (1 (on-state ratio in the cycle). Therefore, it is possible to respond by changing the on-duty ratio of the PWM signal without changing the circuit configuration.

In Figure 7,
1) The CPU outputs a PWM signal with the minimum on-duty ratio from the output terminal TGT. As a result, the target voltage input to the inverting input terminal (-) of the operational amplifier OP1 is always approximately 0V. As a result, the voltage Vo output from the output terminal of the operational amplifier OP1 becomes high level. As a result, the transistor Tr4 is turned on.
2) By turning on the transistor Tr4, the current Ib1 flowing to the base terminal of the transistor Tr1 increases, the transistor Tr1 becomes saturated, and the emitter-collector voltage Vce1 of the transistor Tr1 becomes approximately 0.3V. As a result, the collector voltage Vc1 output from the collector terminal of the transistor Tr1 becomes the specified voltage Ve−(the emitter-collector voltage Vce1 of the transistor Tr1).

3) By turning on the transistor Tr1, a base current Ib2 flows to the base terminal of the transistor Tr2. As a result, the base voltage Vb2 at the base terminal of the transistor Tr2 becomes the collector voltage Vc1 (of the transistor Tr1) - the base-emitter voltage Vbe2 (of the transistor Tr2). As a result, the base voltage Vb2 at the base terminal of the transistor Tr2 becomes the specified voltage Ve - the emitter-collector voltage Vce1 (of the transistor Tr1) - the base-emitter voltage Vbe2 (of the transistor Tr2).
Since the voltage at the anode terminal of the diode D1 is higher than the voltage at the cathode terminal, the diode D1 becomes conductive. Therefore, the base current Ib2 of the transistor Tr2 flows through the path of the base terminal of the transistor Tr2, the diode D1, the resistor R15, the transistor Tr4, and the operational amplifier OP1.

4) The current Ib2 flows from the base terminal of the transistor Tr2, so that the transistor Tr2 is saturated, and the emitter-collector voltage Vce2 of the transistor Tr2 becomes approximately 0.3V. The developing voltage Vdc at this time is expressed by the following (Equation 10).
Developing voltage Vdc=Ve-Vce1-Vce2... (Formula 10)

Generally, the emitter-collector voltage Vce1 (of the transistor Tr1) is about 0.3V, the emitter-collector voltage Vce2 (of the transistor Tr2) is about 0.3V, and the specified voltage Ve is from plus several tens of V to plus several hundred V. be. When these values are substituted into (Equation 10), the developing voltage Vdc will be about approximately plus several tens of volts to plus several hundred volts. That is, the developing voltage Vdc is set to a voltage higher than the surface voltage of the photosensitive drum 101, 0V, and it is possible to prevent the toner 100 from adhering to the surface of the photosensitive drum 101.

[Operation of the developing voltage circuit during normal operation of the photosensitive drum]
In the developing voltage circuit Bias, as shown in FIG. 7, pnp transistors Tr1 and Tr2 are connected to a specified voltage Ve (for example, a DC voltage of +several tens of V to +several hundreds of V output from the voltage source VE). ing. Furthermore, a charging voltage source VPR is connected to the collector terminal of the transistor Tr2 via a shunt resistor R0. During normal operation of the photosensitive drum 101, a shunt current Is shown by a broken line in the figure flows along a path of voltage source VE→transistor Tr1→transistor Tr2→shunt resistor R0→charging voltage source VPR→ground (GND). The developing voltage circuit Bias can output a desired developing voltage Vdc to the developing roller 104 by appropriately increasing or decreasing the current value of the shunt current Is using the PWM signal output from the TGT terminal. It can be expressed by (Equation 11).
Developing voltage Vdc=Vpr+R0×Is...(Formula 11)

In addition, as in the case of the first embodiment, the non-inverting input terminal (+) of the operational amplifier OP1 has a voltage divided by a resistor R12 and a resistor R13 connected in series between the specified voltage Vb and the developing voltage Vdc. A divided voltage Vsns is input. On the other hand, the target voltage Vtgt, which is a DC voltage obtained by smoothing the PWM signal output from the output terminal TGT of the CPU by the resistor R14 and the capacitor C2, is input to the inverting input terminal (-) of the operational amplifier OP1. Note that, as described above, in this embodiment, the npn type transistor Tr4 is arranged between the operational amplifier OP1 and the pnp type transistors Tr1 and Tr2. Therefore, the CPU outputs a PWM signal in which the on-duty ratio (ratio of on-time in one cycle) of the PWM signal in the first embodiment becomes the off-duty ratio (ratio of off-time in one cycle) in this embodiment.

When the divided voltage Vsns is higher than the target voltage Vtgt, the output voltage Vo of the operational amplifier OP1 increases and the base current of the transistor Tr1 flowing into the transistor Tr4 decreases, so that the collector current Is of the transistor Tr1 decreases. As a result, the developing voltage Vdc decreases according to the above-mentioned (Equation 11). Then, the divided voltage Vsns obtained by dividing the specified voltage Vb and the developing voltage Vdc by the resistors R12 and R13 decreases. On the other hand, when the divided voltage Vsns is lower than the target voltage Vtgt, the output voltage Vo of the operational amplifier OP1 decreases, the base current of the transistor Tr1 flowing into the transistor Tr4 increases, and the collector current Is of the transistor Tr1 increases. As a result, the developing voltage Vdc increases according to the above-mentioned (Equation 11). Then, the divided voltage Vsns obtained by dividing the specified voltage Vb and the developing voltage Vdc by the resistors R12 and R13 increases. In this way, negative feedback is applied to the operational amplifier OP1, and the target voltage Vtgt is always approximately equal to the divided voltage Vsns.

Note that the circuit operations of the transistors Tr1 and Tr2 of the developing voltage circuit Bias during the normal operation of the photosensitive drum 101 are the same as in the first embodiment, and a description thereof will be omitted here. Thereby, when the photosensitive drum 101 starts rotating, the developing voltage Vdc applied to the developing roller 104 can be set to a voltage higher than 0 V, and it is possible to prevent the toner 100 from adhering to the photosensitive drum 101. As a result, the toner 100 that has adhered to the photosensitive drum 101 adheres to the transfer roller 105, and the toner 100 adheres to the back surface (the surface on the transfer roller 105 side) of the sheet conveyed to the transfer roller 105, resulting in staining of the back side of the sheet 109. can be prevented from occurring. Further, since the toner 100 does not adhere to the photosensitive drum 101, it is possible to avoid increasing the size of the waste toner box 107 that stores the adhered toner 100 on the photosensitive drum 101 that is removed by the cleaning blade 106, and the accompanying increase in the size of the image forming apparatus. be able to.

As explained above, in FIG. 7, the transistor Tr4, whose emitter-collector breakdown voltage is higher than the voltage Ve supplied from the voltage source VE, is inserted between the output terminal of the operational amplifier OP1 and the base terminal of the transistor Tr1. ing. With such a circuit configuration, the voltage applied to the collector of the transistor Tr1 can be set high without increasing the withstand voltage of the output terminal of the operational amplifier OP1. Note that, depending on the voltage Ve supplied from the voltage source VE, the transistors Tr1 and Tr2 are also changed to transistors corresponding to the voltage Ve.

In this embodiment as well, like the developing voltage circuit Bias shown in FIG. 3 of the first embodiment, by adding the transistor Tr3, the resistor R3, the resistor R16, and the diode D2 to the circuit of FIG. It is also possible to disperse the voltage between the two. Also, in this embodiment, as in the second embodiment, a development voltage source VDC0 that supplies a high-voltage development voltage is provided, and the voltage drop from the output voltage Vdc0 of the development voltage source VDC0 due to the shunt resistor R0 is utilized. A developing voltage Vdc can also be generated.

As described above, according to this embodiment, it is possible to prevent toner from adhering to an uncharged area on the photosensitive drum when the photosensitive drum starts rotating.

D1 Diode D1
OP1 operational amplifier OP1
R1 Resistor R1
R2 Resistance R2
Tr1 Transistor Tr1
Tr2 Transistor Tr2
Va Specified voltage Va

Claims (13)

A power supply device that supplies power supply voltage to a load,
a first voltage source;
a voltage generation unit having an input terminal connected to the first voltage source and generating a voltage to be supplied to the load from the voltage input from the first voltage source;
a second voltage source connected to the output terminal of the voltage generation section;
control means for controlling the voltage generated by the voltage generation section;
bypass means connected to the control means and the voltage generation section;
Equipped with
The voltage generation section includes a first transistor and a second transistor,
The first transistor has an emitter terminal connected to the first voltage source, a base terminal connected to the control means, and a collector terminal connected to the emitter terminal of the second transistor,
The second transistor has a base terminal connected to the bypass means, a collector terminal connected to the output terminal of the voltage generation section,
The base terminal of the first transistor and the base terminal of the second transistor are connected via a first resistor,
The base terminal and collector terminal of the second transistor are connected via a second resistor,
The control means controls the voltage output from the collector terminal of the second transistor by controlling the current flowing to the base terminal of the first transistor,
The power supply device is characterized in that the bypass means is disposed between the base terminal of the second transistor and the control means, and causes the current flowing through the base terminal of the second transistor to flow through the control means. The power supply device according to claim 1, wherein the output terminal of the voltage generation section is connected to the second voltage source via a third resistor. The power supply device according to claim 2, wherein the first resistor and the second resistor have the same resistance value. The control means is an operational amplifier,
The operational amplifier generates a voltage according to the result of comparing the input voltages of a first input terminal to which a target voltage corresponding to the voltage to be supplied to the load is input and a second input terminal to which a reference voltage is input. 4. The power supply device according to claim 3, wherein the power supply is output to a base terminal of the first transistor. 5. The power supply device according to claim 4, wherein the output terminal of the operational amplifier is connected to the second input terminal via a capacitor. The power supply device has a third voltage source,
the third voltage source is connected to the collector terminal of the second transistor via a plurality of resistors connected in series;
6. The power supply device according to claim 5, wherein the voltage divided by the plurality of resistors is input to the second input terminal of the operational amplifier. The bypass means includes a diode and a resistor,
an anode terminal of the diode is connected to a base terminal of the second transistor,
A cathode terminal of the diode is connected to one end of the resistor,
The other end of the resistor is connected to the output terminal of the operational amplifier,
The bypass means causes a current flowing through the base terminal of the second transistor to flow through the output terminal of the operational amplifier when the voltage at the base terminal of the second transistor is higher than the output voltage of the operational amplifier. The power supply device according to claim 6. a control unit that outputs a pulse signal corresponding to a target voltage according to the voltage supplied to the load;
a smoothing section that smoothes the pulse signal output from the control section;
Equipped with
The power supply device according to claim 7, wherein the smoothing section outputs a voltage obtained by smoothing a pulse signal corresponding to the target voltage to the first input terminal of the operational amplifier. The power supply device is characterized in that the voltage to be supplied to the load is generated from the voltage of the second voltage source by a voltage drop caused by the current output from the voltage generation unit flowing through the third resistor. The power supply device according to claim 8. When the voltage of the first voltage source is higher than a predetermined voltage, the power supply device connects the output terminal of the operational amplifier, the base terminal of the first transistor, and the other end of the resistor of the bypass means. 10. The power supply device according to claim 9, further comprising a third transistor having a high breakdown voltage between the power supply device and the power supply device. photosensitive drum,
Charging means for charging the photosensitive drum to a uniform potential;
exposure means for forming an electrostatic latent image on the photosensitive drum charged to the uniform potential by the charging means;
a developing means for developing the electrostatic latent image on the photosensitive drum with toner to form a toner image;
a transfer means for transferring the toner image formed on the photosensitive drum to a sheet;
The power supply device according to any one of claims 1 to 10,
Equipped with
The developing means includes a developing roller that attaches toner to the electrostatic latent image,
The image forming apparatus is characterized in that the power supply device supplies voltage to the developing roller. The image forming apparatus according to claim 11, wherein the second voltage source is a voltage source that supplies voltage to the developing roller. The charging means includes a charging roller that charges the photosensitive drum to the uniform potential,
The image forming apparatus according to claim 11, wherein the second voltage source is a voltage source that supplies voltage to the charging roller.

Images