JP7453509B2 - Printed wiring board and printed wiring board manufacturing method - Google Patents

Printed wiring board and printed wiring board manufacturing method Download PDF

Info

Publication number
JP7453509B2
JP7453509B2 JP2020004151A JP2020004151A JP7453509B2 JP 7453509 B2 JP7453509 B2 JP 7453509B2 JP 2020004151 A JP2020004151 A JP 2020004151A JP 2020004151 A JP2020004151 A JP 2020004151A JP 7453509 B2 JP7453509 B2 JP 7453509B2
Authority
JP
Japan
Prior art keywords
layer
insulating substrate
glass plate
opening
printed wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2020004151A
Other languages
Japanese (ja)
Other versions
JP2021111735A (en
Inventor
敬介 清水
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Priority to JP2020004151A priority Critical patent/JP7453509B2/en
Publication of JP2021111735A publication Critical patent/JP2021111735A/en
Application granted granted Critical
Publication of JP7453509B2 publication Critical patent/JP7453509B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Description

本発明は、ガラス板をコア基板に有するプリント配線板、及び、プリント配線板の製造方法に関する。 The present invention relates to a printed wiring board having a glass plate as a core substrate, and a method for manufacturing the printed wiring board.

特許文献1は、大判のガラス板上に絶縁層、導体層を形成し、スルーホールでガラス板の両面を接続し、回路基板を形成した後に、大判のガラス板を個片に切断するプリント配線板の製造方法を開示している。 Patent Document 1 discloses printed wiring in which an insulating layer and a conductive layer are formed on a large glass plate, both sides of the glass plate are connected using through holes to form a circuit board, and then the large glass plate is cut into individual pieces. Discloses a method for manufacturing a board.

特開2019-192722号公報JP2019-192722A

[特許文献1の課題]
特許文献1では、ガラス板上に絶縁層、導体層を形成するため、配線の位置精度を高めることが難しいと考えられる。配線の位置精度を高めるために、絶縁基板の中央に開口を設け、開口内にガラス板を収容することで、絶縁基板に設けたアライメントマークを用いてガラス板上に絶縁層、導体層を形成することが考えられる。しかしながら、この方法は、ガラス板の周囲に枠状の絶縁基板が配置されるため、ガラス板と絶縁基板との熱膨張率の違いで反りが生じる恐れがあると考えられる。
[Issue of Patent Document 1]
In Patent Document 1, since an insulating layer and a conductive layer are formed on a glass plate, it is considered difficult to improve the positional accuracy of wiring. In order to improve the positioning accuracy of the wiring, an opening is created in the center of the insulating substrate and a glass plate is housed in the opening. By using alignment marks provided on the insulating substrate, an insulating layer and a conductive layer are formed on the glass plate. It is possible to do so. However, in this method, since a frame-shaped insulating substrate is placed around the glass plate, there is a possibility that warping may occur due to the difference in coefficient of thermal expansion between the glass plate and the insulating substrate.

本発明に係るプリント配線板は、絶縁基板の矩形の開口にガラス板を収容して成るコア基板と、前記コア基板上に形成された樹脂絶縁層と導体層とから成るビルドアップ層と、を有する。そして、前記絶縁基板は、前記開口の周囲の枠状に形成され、前記絶縁基板の前記開口の角部に枠状の絶縁基板を4分離する4本のスリットが設けられ
前記ガラス板と前記開口の間、及び、前記4本のスリット内は樹脂が充填されている。
The printed wiring board according to the present invention includes a core substrate formed by accommodating a glass plate in a rectangular opening of an insulating substrate, and a build-up layer formed on the core substrate and formed from a resin insulating layer and a conductor layer. have The insulating substrate is formed in a frame shape around the opening, and four slits are provided at corners of the opening of the insulating substrate to divide the frame-shaped insulating substrate into four parts ,
The space between the glass plate and the opening and the inside of the four slits are filled with resin.

本発明に係るプリント配線板は、絶縁基板の矩形の開口にガラス板を収容して成るコア基板と、前記コア基板上に形成された樹脂絶縁層と導体層とから成るビルドアップ層と、を有する。本発明に係るプリント配線板の製造方法では、大判の絶縁基板に矩形の開口と、前記開口の角部にスリットを設けることと、前記開口にガラス板を収容することと、前記ガラス板と前記開口の間、及び、前記4本のスリット内に樹脂を充填することと、前記大判絶縁基板を、前記スリットの端部に沿って裁断し小判の絶縁基板にし、前記スリットによって小判の絶縁基板を4分離すること、有する。
The printed wiring board according to the present invention includes a core substrate formed by accommodating a glass plate in a rectangular opening of an insulating substrate, and a build-up layer formed on the core substrate and formed from a resin insulating layer and a conductor layer. have In the method for manufacturing a printed wiring board according to the present invention, a rectangular opening is provided in a large insulating substrate, a slit is provided at a corner of the opening, a glass plate is accommodated in the opening, and the glass plate and the Filling resin between the openings and in the four slits, cutting the large insulating substrate along the edges of the slits to make an oval insulating substrate, and cutting the large insulating substrate into an oval insulating substrate by the slits. It has 4 separations.

[実施形態の効果]
本発明の実施形態のプリント配線板、プリント配線板の製造方法によれば、絶縁基板の開口にガラス板を収容して導体層が形成されるため、絶縁基板のアライメントマークを用いることで、配線の位置精度を高めることができる。絶縁基板の開口の角部に枠状の絶縁基板を4分離する4本のスリットが設けられている。絶縁基板が枠状では無く、分離した4本の棒状であるため、ガラス板と絶縁基板との熱膨張率の違っていても、絶縁基板に生じる応力が4分割され、絶縁基板からの応力でプリント配線板に反りを生じさせることが無い。
[Effects of embodiment]
According to the printed wiring board and the method for manufacturing a printed wiring board according to the embodiment of the present invention, since a conductor layer is formed by housing a glass plate in an opening of an insulating substrate, wiring position accuracy can be improved. Four slits are provided at the corners of the opening of the insulating substrate to divide the frame-shaped insulating substrate into four sections. Since the insulating substrate is not in the shape of a frame but in the shape of four separate rods, even if the thermal expansion coefficients of the glass plate and the insulating substrate are different, the stress generated on the insulating substrate is divided into four, and the stress from the insulating substrate is divided into four parts. There is no possibility of warping the printed wiring board.

図1(A)は第1実施形態のプリント配線板の断面図であり、図1(B)は平面図である。FIG. 1(A) is a cross-sectional view of the printed wiring board of the first embodiment, and FIG. 1(B) is a plan view. 本発明の第1実施形態に係るプリント配線板の平面図である。FIG. 1 is a plan view of a printed wiring board according to a first embodiment of the present invention. 第1実施形態のプリント配線板の製造工程図である。It is a manufacturing process diagram of the printed wiring board of 1st Embodiment. 第1実施形態のプリント配線板の製造工程図である。It is a manufacturing process diagram of the printed wiring board of 1st Embodiment. 第2実施形態のプリント配線板の製造工程図である。It is a manufacturing process diagram of the printed wiring board of 2nd Embodiment. 第2実施形態のプリント配線板の断面図である。FIG. 3 is a cross-sectional view of a printed wiring board according to a second embodiment.

[第1実施形態]
図1(A)は第1実施形態のプリント配線板10の断面図である。図1(B)はプリント配線板10の平面図であり、図1(A)は図1(B)のA1-A1断面に相当する。プリント配線板10は、第1面FFと第1面FFと反対側の第2面SSとを有するコア基板30とコア基板の第1面FF上に形成されている第1ビルドアップ層55Fとコア基板の第2面SS上に形成されている第2ビルドアップ層55Sとを有する。
[First embodiment]
FIG. 1(A) is a cross-sectional view of a printed wiring board 10 of the first embodiment. FIG. 1(B) is a plan view of the printed wiring board 10, and FIG. 1(A) corresponds to the A1-A1 cross section in FIG. 1(B). The printed wiring board 10 includes a core substrate 30 having a first surface FF and a second surface SS opposite to the first surface FF, and a first buildup layer 55F formed on the first surface FF of the core substrate. It has a second buildup layer 55S formed on the second surface SS of the core substrate.

コア基板30は、図1(B)中に示される開口22aを有する枠状の絶縁基板22と、絶縁基板22の開口22a内に収容され、コア基板の第1面FFと同方向の第1面Fと第1面Fと反対側の第2面Sとを有するガラス板20と、図1(A)中に示される絶縁基板22及びガラス板20の第1面F上の第1絶縁層28Fと、絶縁基板22及びガラス板20の第2面S上の第2絶縁層28Sと、第1絶縁層28F上に形成されている第1導体層34Fと、第2絶縁層28S上に形成されている第2導体層34Sと、第1導体層34Fと第2導体層34Sとを接続するスルーホール導体36とを有する。スルーホール導体36は、ガラス板20に形成された貫通孔25内に充填された第1絶縁層28F、第2絶縁層28S由来の樹脂28内に形成された貫通孔26内に形成されている。絶縁基板22には導体層を形成するためのアライメントマーク24が形成されている。 The core substrate 30 includes a frame-shaped insulating substrate 22 having an opening 22a shown in FIG. A glass plate 20 having a surface F and a second surface S opposite to the first surface F, an insulating substrate 22 shown in FIG. 1(A), and a first insulating layer on the first surface F of the glass plate 20. 28F, a second insulating layer 28S on the second surface S of the insulating substrate 22 and the glass plate 20, a first conductor layer 34F formed on the first insulating layer 28F, and a second insulating layer 28S formed on the second insulating layer 28F. The second conductor layer 34S has a second conductor layer 34S, and a through-hole conductor 36 connects the first conductor layer 34F and the second conductor layer 34S. The through-hole conductor 36 is formed in the through-hole 26 formed in the resin 28 derived from the first insulating layer 28F and the second insulating layer 28S filled in the through-hole 25 formed in the glass plate 20. . Alignment marks 24 for forming a conductor layer are formed on the insulating substrate 22.

第1ビルドアップ層55Fは、コア基板30の第1面Fと第1導体層34F上に形成されている第1樹脂絶縁層50Fと、第1樹脂絶縁層50F上に形成されている第3導体層58Fと、を有する。第1ビルドアップ層55Fは、さらに、第1樹脂絶縁層50Fを貫通する第1ビア導体60Fを有する。第1ビア導体60Fは、第1導体層34Fと第3導体層58Fとを接続する。 The first buildup layer 55F includes a first resin insulating layer 50F formed on the first surface F of the core substrate 30 and the first conductor layer 34F, and a third resin insulating layer 50F formed on the first resin insulating layer 50F. It has a conductor layer 58F. The first buildup layer 55F further includes a first via conductor 60F that penetrates the first resin insulating layer 50F. The first via conductor 60F connects the first conductor layer 34F and the third conductor layer 58F.

第1樹脂絶縁層50Fと第3導体層58F上に開口72Fを有する第1ソルダーレジスト層70Fが形成される。開口72Fから露出する第3導体層58Fに、電子部品を搭載するための第1半田バンプ76Fが形成される。 A first solder resist layer 70F having an opening 72F is formed on the first resin insulating layer 50F and the third conductor layer 58F. First solder bumps 76F for mounting electronic components are formed on the third conductor layer 58F exposed from the opening 72F.

第2ビルドアップ層55Sは、コア基板30の第2面Sと第2導体層34S上に形成されている第2樹脂絶縁層50Sと、第2樹脂絶縁層50Sの上に形成されている第4導体層58Sと、を有する。第2ビルドアップ層55Sは、さらに、第2樹脂絶縁層50Sを貫通する第2ビア導体60Sを有する。第2ビア導体60Sは、第2導体層34Sと第4導体層58Sとを接続する The second buildup layer 55S includes a second resin insulating layer 50S formed on the second surface S of the core substrate 30 and the second conductor layer 34S, and a second resin insulating layer 50S formed on the second resin insulating layer 50S. 4 conductor layers 58S. The second buildup layer 55S further includes a second via conductor 60S that penetrates the second resin insulating layer 50S. The second via conductor 60S connects the second conductor layer 34S and the fourth conductor layer 58S.

第2樹脂絶縁層50Sと第4導体層58S上に開口72Sを有する第2ソルダーレジスト層70Sが形成される。開口72Sから露出する第4導体層58Sに、マザーボード等の回路基板と接続するための第2半田バンプ76Sが形成される。 A second solder resist layer 70S having an opening 72S is formed on the second resin insulating layer 50S and the fourth conductor layer 58S. A second solder bump 76S for connection to a circuit board such as a motherboard is formed on the fourth conductor layer 58S exposed from the opening 72S.

第1実施形態のプリント配線板10は、絶縁基板22の開口22aにガラス板20を収容して第1導体層34F、第2導体層34S、第3導体層58F、第4導体層58Sが形成されるため、絶縁基板22の第1面F側のアライメントマーク24(及び、図示しない第2面側のアライメントマーク)を用いることで、第1導体層34F、第2導体層34S、第3導体層58F、第4導体層58Sの位置精度を高くすることができる。 In the printed wiring board 10 of the first embodiment, a glass plate 20 is accommodated in an opening 22a of an insulating substrate 22, and a first conductor layer 34F, a second conductor layer 34S, a third conductor layer 58F, and a fourth conductor layer 58S are formed. Therefore, by using the alignment mark 24 on the first surface F side of the insulating substrate 22 (and the alignment mark on the second surface side, not shown), the first conductor layer 34F, the second conductor layer 34S, and the third conductor layer The positional accuracy of the layer 58F and the fourth conductor layer 58S can be increased.

第1実施形態のプリント配線板10では、図1(B)に示されるように、絶縁基板22の開口22aの角部に枠状の絶縁基板を4分離する4本のスリット22bが設けられている。図1(A)に示されるように、絶縁基板22の開口22aとガラス板20との間には、第1絶縁層28F、第2絶縁層28S由来の樹脂28が充填されている。同様に、スリット22b内には、第1絶縁層28F、第2絶縁層28S由来の樹脂28が充填されている。第1実施形態のプリント配線板10では、絶縁基板22が枠状では無く、分離した4本の棒状の絶縁基板(子片)22zから成るため、ガラス板と絶縁基板との熱膨張率の違っていても、絶縁基板22に生じる応力が4分割され、絶縁基板22からの応力でプリント配線板10に反りを生じさせることが無い。 In the printed wiring board 10 of the first embodiment, as shown in FIG. 1(B), four slits 22b are provided at the corners of the opening 22a of the insulating substrate 22, dividing the frame-shaped insulating substrate into four parts. There is. As shown in FIG. 1A, the space between the opening 22a of the insulating substrate 22 and the glass plate 20 is filled with resin 28 derived from the first insulating layer 28F and the second insulating layer 28S. Similarly, the slit 22b is filled with resin 28 derived from the first insulating layer 28F and the second insulating layer 28S. In the printed wiring board 10 of the first embodiment, the insulating substrate 22 is not frame-shaped but consists of four separate rod-shaped insulating substrates (child pieces) 22z, so the difference in thermal expansion coefficient between the glass plate and the insulating substrate Even if the insulating substrate 22 is insulated, the stress generated in the insulating substrate 22 is divided into four parts, and the stress from the insulating substrate 22 does not cause the printed wiring board 10 to warp.

[第1実施形態のプリント配線板の製造方法]
図2に示される大判の絶縁基板122が準備され、矩形の開口22aと、開口22aの開口の角部にスリット22bが形成される。図2中の開口22aの断面が図3(A)中に示される。ガラス板20が準備され、絶縁基板122の開口22a内に収容される(図3(B))。ガラス板20は、純粋二酸化珪素(約100%のSiO2)、ソーダ石灰ガラス、ホウケイ酸塩ガラス、アルミノケイ酸塩ガラス、フルオロガラス、リン酸ガラス、又は、カルコゲンガラスから成る。予めブラスト加工等により、ガラス板の表面、裏面がRa(平均粗度)=100nm程度に荒らされる。
[Method for manufacturing printed wiring board of first embodiment]
A large-sized insulating substrate 122 shown in FIG. 2 is prepared, and a rectangular opening 22a and a slit 22b are formed at the corner of the opening 22a. A cross section of the opening 22a in FIG. 2 is shown in FIG. 3(A). A glass plate 20 is prepared and accommodated in the opening 22a of the insulating substrate 122 (FIG. 3(B)). Glass plate 20 is comprised of pure silicon dioxide (approximately 100% SiO2), soda lime glass, borosilicate glass, aluminosilicate glass, fluoroglass, phosphate glass, or chalcogen glass. The front and back surfaces of the glass plate are roughened to Ra (average roughness) of approximately 100 nm by blasting or the like in advance.

絶縁基板122の図示しないアライメントマークを基準としてガラス板20にスルーホール形成用の貫通孔25が形成される(図3(C))。以降の導体層形成にも計測されたアライメントマークの位置が用いられる。絶縁基板122、ガラス板20の第1面F上に第1絶縁層28Fが、第2面S上に第2絶縁層28Sが形成され、図1(B)中に示される絶縁基板22の開口22aとガラス板20との間、4本のスリット22b内、貫通孔25内に、第1絶縁層28F、第2絶縁層28S由来の樹脂28が充填される。そして、第1絶縁層28F、ガラス板20の貫通孔25内の樹脂28、第2絶縁層28Sにスルーホール用の貫通孔26が形成される(図3(D))。上述されたように、ガラス板の表面、裏面が荒らされているため、ガラス板20と第1絶縁層28F、第2絶縁層28Sとの密着性は高い。 A through hole 25 for forming a through hole is formed in the glass plate 20 using an alignment mark (not shown) of the insulating substrate 122 as a reference (FIG. 3(C)). The measured position of the alignment mark is also used in subsequent formation of the conductor layer. A first insulating layer 28F is formed on the first surface F of the insulating substrate 122 and the glass plate 20, and a second insulating layer 28S is formed on the second surface S, and the opening of the insulating substrate 22 shown in FIG. 1(B) is formed. Resin 28 derived from the first insulating layer 28F and the second insulating layer 28S is filled between the glass plate 22a and the glass plate 20, in the four slits 22b, and in the through holes 25. Then, a through hole 26 for a through hole is formed in the first insulating layer 28F, the resin 28 in the through hole 25 of the glass plate 20, and the second insulating layer 28S (FIG. 3(D)). As described above, since the front and back surfaces of the glass plate are roughened, the adhesion between the glass plate 20 and the first insulating layer 28F and the second insulating layer 28S is high.

無電解めっきにより第1絶縁層28F、第2絶縁層28Sの表面、貫通孔26内に無電解めっき膜32が形成される(図3(E))。無電解めっき膜32上に所定パターンのめっきレジスト40が形成され、電解めっきにより、めっきレジスト40から露出する無電解めっき膜32上に電解めっき膜38が形成されると共に、貫通孔26内に電解めっき膜が充填されスルーホール導体36が形成される(図3(F))。めっきレジストが除去され、電解めっき膜38から露出する無電解めっき膜32が除去され、第1導体層34F、第2導体層34Sが形成され、コア基板30が完成する(図3(G))。コア基板30は、ガラス板20の第1面Fと同方向の第1面FFを、ガラス板20の第2面Sと同方向の第2面SSを有する。 An electroless plating film 32 is formed on the surfaces of the first insulating layer 28F and the second insulating layer 28S and inside the through hole 26 by electroless plating (FIG. 3(E)). A plating resist 40 having a predetermined pattern is formed on the electroless plating film 32 , and by electrolytic plating, an electrolytic plating film 38 is formed on the electroless plating film 32 exposed from the plating resist 40 . A plating film is filled to form a through-hole conductor 36 (FIG. 3(F)). The plating resist is removed, the electroless plating film 32 exposed from the electrolytic plating film 38 is removed, the first conductor layer 34F and the second conductor layer 34S are formed, and the core substrate 30 is completed (FIG. 3(G)). . The core substrate 30 has a first surface FF in the same direction as the first surface F of the glass plate 20 and a second surface SS in the same direction as the second surface S of the glass plate 20 .

コア基板30の第1面FF上に第1樹脂絶縁層50Fが、第2面SS上に第2樹脂絶縁層50Sが形成される(図4(A))。第1樹脂絶縁層50Fに、第1導体層34Fに至る開口51Fが形成され、第2樹脂絶縁層50Sに、第2導体層34Sに至る開口51Sが形成される(図4(B))。無電解めっきにより第1樹脂絶縁層50F、第2樹脂絶縁層50Sの表面、開口51F、51S内に無電解めっき膜52が形成され、所定のめっきレジスト(図示されず)が形成され、めっきレジストから露出する無電解めっき膜52上に電解めっき膜56が形成され、開口51F内に第1ビア導体60Fが、開口51S内に第2ビア導体60Sが形成される。めっきレジストが剥離され、電解めっき膜56から露出する無電解めっき膜52が除去され、第3導体層58F、第4導体層58Sが形成される(図4(C))。 A first resin insulating layer 50F is formed on the first surface FF of the core substrate 30, and a second resin insulating layer 50S is formed on the second surface SS (FIG. 4(A)). An opening 51F reaching the first conductor layer 34F is formed in the first resin insulating layer 50F, and an opening 51S reaching the second conductor layer 34S is formed in the second resin insulating layer 50S (FIG. 4(B)). By electroless plating, an electroless plating film 52 is formed on the surfaces of the first resin insulating layer 50F and the second resin insulating layer 50S and in the openings 51F and 51S, and a predetermined plating resist (not shown) is formed. An electrolytic plated film 56 is formed on the electroless plated film 52 exposed from the opening 51F, and a first via conductor 60F is formed in the opening 51F, and a second via conductor 60S is formed in the opening 51S. The plating resist is peeled off and the electroless plated film 52 exposed from the electrolytic plated film 56 is removed to form a third conductor layer 58F and a fourth conductor layer 58S (FIG. 4(C)).

第3導体層58Fと第1樹脂絶縁層50F上に第1開口72Fを有する第1ソルダーレジスト層70Fが形成される。第4導体層58Sと第2樹脂絶縁層50S上に第2開口72Sを有する第2ソルダーレジスト層70Sが形成される。図2中に示されるスリット22bの端部に沿った裁断線22cによって大判の絶縁基板122が切り分けられ、個片(小判)の絶縁基板22にされる(図4(D))。この際に、図1(B)に示されるように、スリット22bによって小判の絶縁基板22は4分離され、4個の棒状の絶縁基板(子片)22zがスリット22b内の樹脂28によって接続される状態となる。。第1ソルダーレジスト層70Fの第1開口72Fに第1半田バンプ76Fが形成され、第2ソルダーレジスト層70Sの第2開口72Sに第2半田バンプ76Sが形成される(図1(A))。 A first solder resist layer 70F having a first opening 72F is formed on the third conductor layer 58F and the first resin insulating layer 50F. A second solder resist layer 70S having a second opening 72S is formed on the fourth conductor layer 58S and the second resin insulating layer 50S. The large insulating substrate 122 is cut along the cutting line 22c along the edge of the slit 22b shown in FIG. 2 to form individual pieces (small) of the insulating substrate 22 (FIG. 4(D)). At this time, as shown in FIG. 1(B), the oval insulating substrate 22 is divided into four parts by the slit 22b, and four rod-shaped insulating substrates (child pieces) 22z are connected by the resin 28 in the slit 22b. The state will be as follows. . A first solder bump 76F is formed in the first opening 72F of the first solder resist layer 70F, and a second solder bump 76S is formed in the second opening 72S of the second solder resist layer 70S (FIG. 1(A)).

第1実施形態のプリント配線板の製造方法では、絶縁基板22が、分離した4本の棒状の絶縁基板(子片)22zから構成されため、ガラス板と絶縁基板との熱膨張率の違っていても、絶縁基板22に生じる応力が4分割され、絶縁基板22からの応力でプリント配線板10に反りを生じさせることが無い。 In the printed wiring board manufacturing method of the first embodiment, the insulating substrate 22 is composed of four separate rod-shaped insulating substrates (child pieces) 22z, and therefore the glass plate and the insulating substrate have different coefficients of thermal expansion. However, the stress generated in the insulating substrate 22 is divided into four parts, and the stress from the insulating substrate 22 does not cause the printed wiring board 10 to warp.

[第2実施形態]
図6は第2実施形態のプリント配線板の断面図である。
第2実施形態のプリント配線板10では、コア基板30がガラス板20とガラス板20の第1面Fに形成された第1導体層34Fと、第2面Sに形成された第2導体層34Sと、第1導体層34F、第2導体層34Sを接続するスルーホール導体36から成る。絶縁基板22の開口22aとガラス板20との間、及び、図示しないスリット内は、第1樹脂絶縁層50F、第2樹脂絶縁層50S由来の樹脂50で充填されている。
[Second embodiment]
FIG. 6 is a sectional view of the printed wiring board of the second embodiment.
In the printed wiring board 10 of the second embodiment, the core substrate 30 includes a glass plate 20, a first conductor layer 34F formed on the first surface F of the glass plate 20, and a second conductor layer formed on the second surface S. 34S, and a through-hole conductor 36 connecting the first conductor layer 34F and the second conductor layer 34S. The space between the opening 22a of the insulating substrate 22 and the glass plate 20 and the inside of the slit (not shown) are filled with resin 50 derived from the first resin insulating layer 50F and the second resin insulating layer 50S.

[第2実施形態のプリント配線板の製造方法]
図5(A)に示されるガラス板20が用意される。ブラスト加工等により、ガラス板20の第1面F、第2面SがRa(平均粗度)=100nm程度に荒らされる。ガラス板20にスルーホール用の貫通孔26が形成される(図5(B))。無電解めっきによりガラス板20の表面、貫通孔26内に無電解めっき膜32が形成される。無電解めっき膜32上に所定パターンのめっきレジスト40が形成され、電解めっきにより、めっきレジスト40から露出する無電解めっき膜32上に電解めっき膜38が形成されると共に、貫通孔26内に電解めっき膜が充填されスルーホール導体36が形成される(図5(C))。めっきレジストが除去され、電解めっき膜38から露出する無電解めっき膜32が除去され、第1導体層34F、第2導体層34Sが形成される(図5(D))。図2を参照し上述された第1実施形態と同様に、開口22a及び開口の4角にスリットの設けられた絶縁基板22の開口22a内に図5(D)に示されるガラス板20が収容される(図5(E))。この際、絶縁基板22に設けられた図示されないアライメントマークを基準にガラス板20の位置合わせが行われる。以降の工程は第1実施形態と同様である。
[Method for manufacturing printed wiring board of second embodiment]
A glass plate 20 shown in FIG. 5(A) is prepared. The first surface F and second surface S of the glass plate 20 are roughened to Ra (average roughness) of approximately 100 nm by blasting or the like. A through hole 26 for a through hole is formed in the glass plate 20 (FIG. 5(B)). An electroless plating film 32 is formed on the surface of the glass plate 20 and inside the through hole 26 by electroless plating. A plating resist 40 having a predetermined pattern is formed on the electroless plating film 32 , and by electrolytic plating, an electrolytic plating film 38 is formed on the electroless plating film 32 exposed from the plating resist 40 . A plating film is filled to form a through-hole conductor 36 (FIG. 5(C)). The plating resist is removed, and the electroless plated film 32 exposed from the electrolytic plated film 38 is removed to form a first conductor layer 34F and a second conductor layer 34S (FIG. 5(D)). Similar to the first embodiment described above with reference to FIG. 2, the glass plate 20 shown in FIG. (Fig. 5(E)). At this time, the glass plate 20 is aligned with reference to alignment marks (not shown) provided on the insulating substrate 22. The subsequent steps are similar to those in the first embodiment.

20 ガラス板
22 絶縁基板
22a 開口
22b スリット
30 コア基板
34F 第1導体層
34S 第2導体層
36 スルーホール導体
20 glass plate 22 insulating substrate 22a opening 22b slit 30 core substrate 34F first conductor layer 34S second conductor layer 36 through-hole conductor

Claims (3)

絶縁基板の矩形の開口にガラス板を収容して成るコア基板と、前記コア基板上に形成された樹脂絶縁層と導体層とから成るビルドアップ層と、を有するプリント配線板であって、
前記絶縁基板は、前記開口の周囲の枠状に形成され、
前記絶縁基板の前記開口の角部に枠状の絶縁基板を4分離する4本のスリットが設けられ
前記ガラス板と前記開口の間、及び、前記4本のスリット内は樹脂が充填されている。
A printed wiring board having a core substrate formed by accommodating a glass plate in a rectangular opening of an insulating substrate, and a build-up layer formed on the core substrate and formed of a resin insulating layer and a conductor layer,
The insulating substrate is formed in a frame shape around the opening,
Four slits are provided at the corners of the opening of the insulating substrate, dividing the frame-shaped insulating substrate into four parts ,
The space between the glass plate and the opening and the inside of the four slits are filled with resin.
請求項のプリント配線板であって、
前記樹脂は、前記絶縁基板及び前記ガラス板の上層の樹脂絶縁層の由来である。
The printed wiring board according to claim 1 ,
The resin is the origin of the resin insulating layer on the insulating substrate and the glass plate.
絶縁基板の矩形の開口にガラス板を収容して成るコア基板と、前記コア基板上に形成された樹脂絶縁層と導体層とから成るビルドアップ層と、を有するプリント配線板の製造方法であって、
大判の絶縁基板に矩形の開口と、前記開口の角部にスリットを設けることと、
前記開口にガラス板を収容することと、
前記ガラス板と前記開口の間、及び、前記4本のスリット内に樹脂を充填することと、
前記大判絶縁基板を、前記スリットの端部に沿って裁断し小判の絶縁基板にし、前記スリットによって小判の絶縁基板を4分離すること、有する。
A method for manufacturing a printed wiring board comprising: a core substrate having a glass plate accommodated in a rectangular opening of the insulating substrate; and a build-up layer formed on the core substrate comprising a resin insulating layer and a conductor layer. hand,
Providing a rectangular opening in a large insulating substrate and a slit at a corner of the opening;
accommodating a glass plate in the opening;
filling a resin between the glass plate and the opening and into the four slits;
The large- sized insulating substrate is cut along the edge of the slit to form a small-sized insulating substrate, and the small-sized insulating substrate is divided into four parts by the slit.
JP2020004151A 2020-01-15 2020-01-15 Printed wiring board and printed wiring board manufacturing method Active JP7453509B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2020004151A JP7453509B2 (en) 2020-01-15 2020-01-15 Printed wiring board and printed wiring board manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2020004151A JP7453509B2 (en) 2020-01-15 2020-01-15 Printed wiring board and printed wiring board manufacturing method

Publications (2)

Publication Number Publication Date
JP2021111735A JP2021111735A (en) 2021-08-02
JP7453509B2 true JP7453509B2 (en) 2024-03-21

Family

ID=77060230

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2020004151A Active JP7453509B2 (en) 2020-01-15 2020-01-15 Printed wiring board and printed wiring board manufacturing method

Country Status (1)

Country Link
JP (1) JP7453509B2 (en)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010114187A (en) 2008-11-05 2010-05-20 Shinko Electric Ind Co Ltd Wiring substrate and method of manufacturing the wiring substrate
JP2014022465A (en) 2012-07-13 2014-02-03 Shinko Electric Ind Co Ltd Wiring board and method of manufacturing the same
JP2014107433A (en) 2012-11-28 2014-06-09 Ibiden Co Ltd Multiple piece forming substrate
JP2014127701A (en) 2012-12-27 2014-07-07 Ibiden Co Ltd Wiring board and method of manufacturing the same
JP2015095654A (en) 2013-11-11 2015-05-18 サムソン エレクトロ−メカニックス カンパニーリミテッド. Printed circuit board and method of manufacturing the same
JP2018133549A (en) 2017-01-17 2018-08-23 京セラ株式会社 Aggregate substrate and manufacturing method thereof
JP2019192722A (en) 2018-04-23 2019-10-31 イビデン株式会社 Printed wiring board and printed wiring board manufacturing method

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010114187A (en) 2008-11-05 2010-05-20 Shinko Electric Ind Co Ltd Wiring substrate and method of manufacturing the wiring substrate
JP2014022465A (en) 2012-07-13 2014-02-03 Shinko Electric Ind Co Ltd Wiring board and method of manufacturing the same
JP2014107433A (en) 2012-11-28 2014-06-09 Ibiden Co Ltd Multiple piece forming substrate
JP2014127701A (en) 2012-12-27 2014-07-07 Ibiden Co Ltd Wiring board and method of manufacturing the same
JP2015095654A (en) 2013-11-11 2015-05-18 サムソン エレクトロ−メカニックス カンパニーリミテッド. Printed circuit board and method of manufacturing the same
JP2018133549A (en) 2017-01-17 2018-08-23 京セラ株式会社 Aggregate substrate and manufacturing method thereof
JP2019192722A (en) 2018-04-23 2019-10-31 イビデン株式会社 Printed wiring board and printed wiring board manufacturing method

Also Published As

Publication number Publication date
JP2021111735A (en) 2021-08-02

Similar Documents

Publication Publication Date Title
US8893380B2 (en) Method of manufacturing a chip embedded printed circuit board
US7935891B2 (en) Wiring board manufacturing method
KR20230092854A (en) Printed circuit board
US20080115349A1 (en) Method of manufacturing a component-embedded printed circuit board
US20120234587A1 (en) Printed wiring board, printed circuit board unit, electronic apparatus and method for manufacturing printed wiring board
WO2006082784A1 (en) Multilayer printed wiring board
US20100126765A1 (en) Multi-layer printed circuit board and manufacturing method thereof
US8945329B2 (en) Printed wiring board and method for manufacturing printed wiring board
JP2014131037A (en) Circuit board and method of manufacturing the same
JP2001320150A (en) Wiring board by stamper and manufacturing method thereof
EP1635625B1 (en) Substrate manufacturing method and circuit board
KR20100077055A (en) Multilayer printed wiring board
TWI734945B (en) Composite substrate structure and manufacturing method thereof
JP7453509B2 (en) Printed wiring board and printed wiring board manufacturing method
JP5660462B2 (en) Printed wiring board
KR101582547B1 (en) Semiconductor package for embedding semiconductor chip and the method for manufacturing the same
JP2009231635A (en) Wiring board and its manufacturing method, semiconductor device, and its manufacturing method
CN110113877A (en) A kind of method of laser cutting method production metal base circuit board
JP6724775B2 (en) Wiring board individualization method and package board
JP2019192722A (en) Printed wiring board and printed wiring board manufacturing method
CN111315109B (en) Composite substrate structure and manufacturing method thereof
KR20150028031A (en) Printed circuit board
KR100704911B1 (en) Electronic chip embedded pcb and method of the same
JP2002237669A (en) Method of forming recognition mark to substrate for kgd
JP3699383B2 (en) Wiring board manufacturing method

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20221221

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20231023

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20231128

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20231219

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20240206

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20240219

R150 Certificate of patent or registration of utility model

Ref document number: 7453509

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150