JP7437979B2 - gaming machine - Google Patents

Description

The present invention relates to a gaming machine that performs a lottery process resulting from a gaming operation and executes an image effect corresponding to the lottery result, and particularly relates to a gaming machine that can stably execute an impressive image effect.

A pinball game machine such as a pachinko machine is equipped with a symbol start opening provided on the game board, a symbol display section that displays a series of symbol variations based on a plurality of displayed symbols, and a big prize opening that opens and closes an opening/closing board. It is composed of Then, when the detection switch provided at the symbol start opening detects the passing of the game ball, the game enters a winning state, and after the game ball is paid out as a prize ball, the displayed symbols are changed for a predetermined period of time in the symbol display section. Thereafter, when the symbols stop in a predetermined manner such as 7, 7, 7, a jackpot state occurs, and the jackpot opening is repeatedly opened to generate a gaming state advantageous to the player.

Whether or not to generate such a gaming state is determined by a jackpot lottery that is executed on the condition that a game ball enters the symbol starting hole, and the symbol fluctuation operation described above is based on the result of this lottery. It has become a thing. For example, if the lottery result is a winning state, a performance action called a reach action is performed for about 20 seconds, and then the special symbols are arranged. On the other hand, even in the case of a losing state, a similar reach action may be executed, and in this case, the player will watch the progress of the performance action while strongly thinking that the player will be in a jackpot state. If the predetermined symbols line up on the stop line at the end of the symbol variation operation, the player is guaranteed a jackpot.

Such a symbol variation operation is normally performed on a liquid crystal display. A liquid crystal display is generally composed of pixels of H dots horizontally and V dots vertically, and each H×V dot pixel is composed of basic pixels of three colors RGB.

Driving of each pixel in a liquid crystal display is executed in synchronization with the operating clock CK (=dot clock DCK) of the device, and the pixel driving of H dots corresponding to one horizontal line is synchronized with the horizontal synchronization signal HS. This is repeated in synchronization, and when driving for V lines is completed, it is configured to return to pixel driving for the first line in synchronization with the vertical synchronization signal VS (see FIG. 40). Therefore, it is necessary to supply the image signal corresponding to the resolution H×V dots, the horizontal synchronizing signal HS, the vertical synchronizing signal VS, and the dot clock DCK from the external device to the liquid crystal display.

Here, in order to smoothly execute the display update operation (frame update) of the liquid crystal display, the pulse width of each synchronization signal HS, Vs and the timing between each synchronization signal HS, Vs and the transmission timing of the image signal are as follows. Certain conditions are required. For example, FIG. 40(g) illustrates an example of drive timing conditions required for a 640×408 dot VGA (Video Graphics Array).

Under the illustrated driving conditions, first, the pulse width PWh of the horizontal synchronization signal HS is equal to 96 operation clocks CK, and the front porch FPh and back port BPh required before and after the horizontal synchronization signal PWh are, respectively. It is defined as 16 operating clocks CK and 48 operating clocks CK.

On the other hand, the pulse width PWv of the vertical synchronization signal VS is 2 lines, and the front porch FPv and back port BPv required before and after the vertical synchronization signal VS are defined as 19 lines and 33 lines, respectively. has been done.

Therefore, in this liquid crystal display, the operation cycle of one line driving operation is 16+96+48+640 (=800) counted by the operation clock CK, and by repeating this in the vertical direction for 10+2+33+480 lines (=525). , the display for one frame on the display screen will be updated.

The above operating cycle is counted by the operating clock CK and is 800 x 525 times. For example, if the operating clock frequency is 25 MHz, the time required to update one frame is 800 x 525/(25 MHz). ×10 ⁶ )=16.8 mS, and the operation cycle is about 1/60 second.

The external control device that controls the liquid crystal display receives a horizontal synchronization signal HS that satisfies the above horizontal conditions (PWh, FPh, BPh) and a horizontal synchronization signal HS that satisfies the above vertical conditions (PWvh, FPvh, BPvh). Image signals corresponding to the number of pixels on the display screen are repeatedly supplied to the liquid crystal display.

JP2017-093633A JP2017-093632A Japanese Patent Application Publication No. 2016-159030 JP 2016-159029 Publication

By the way, in this type of gaming machine, there is a strong demand for making various effects more complex and richer, and in particular, there is a strong demand for image effects using a liquid crystal display. Therefore, the applicant has made various proposals (Cited Documents 1 to 4), including further advancement of image presentation and further improvement of various presentation control operations centered on image presentation control. This is what is desired. Further, it is desired to improve the drive operation of the liquid crystal display so that the control burden of image presentation control can be reduced.

The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a gaming machine in which various performance control operations centering on image performance control are further improved.

In order to achieve the above object, the present invention provides an image generation means that operates based on a system clock derived from the output of a predetermined clock oscillation section to realize image production on a display device, and A gaming machine having a performance control means for controlling the game machine, wherein the image generation means receives a drawing list issued by the performance control means and transfers the drawing list in units of predetermined transfer bits to an analysis circuit that analyzes the drawing list. a data transfer circuit; a drawing circuit that generates necessary image data in a predetermined RAM area based on the drawing list transferred by the data transfer circuit ; and a drawing circuit that reads the image data from the RAM area and performs appropriate image processing when necessary. and a signal output circuit that receives image data output from the display circuit and outputs a differential signal including an LVDS clock, and the data transfer circuit outputs a drawing list. The effect control means includes a transfer port that receives data in units of predetermined acquired bits, and a FIFO buffer having a FIFO structure that accumulates data received by the transfer port, and the effect control means has a total bit length that is determined in units of acquired bits. The drawing list is created to be an integral multiple of the transfer bit unit, and the clock oscillation unit is defined as the supply source of the display clock that defines the operation of the display circuit. a first means; and a second means for appropriately setting a ratio to the output frequency of the clock oscillator to make the period of the display clock correspond to the processing time required for displaying one dot of each pixel of the display device. , comprising third means for distributing image data output from the display circuit into first data and second data for each pixel dot of the display device, and the signal output circuit: The image data distributed by the third means is outputted to the display device via two LVDS paths, and one period of the LVDS clock is twice as long as one period of the display clock. On the other hand, the display device is configured to complete processing for two dots of the pixels in one period of the LVDS clock.

According to the present invention described above, noise resistance is improved by low-speed transmission, and image control operation is improved by cooperatively operating the display devices.

It is a perspective view showing a pachinko machine of a present example. 2 is a front view showing a gaming area of the gaming machine in FIG. 1. FIG. 2 is a block diagram showing the overall circuit configuration of the gaming machine of FIG. 1. FIG. It is a drawing explaining the specifications of a display device. FIG. 2 is a block diagram illustrating the internal configuration of a display device. FIG. 2 is a block diagram showing a slightly more detailed circuit configuration of a production control section for the gaming machine of FIG. 1. FIG. It is a drawing explaining a composite chip that constitutes a production control section. 5 is a block diagram showing the internal configuration of the CPU circuit shown in FIG. 4. FIG. It is a diagram illustrating a memory map of the built-in CPU (performance control CPU) of the CPU circuit. 3 is a diagram illustrating various transfer operation modes (a) to (b) and transfer operation procedures (c) to (e) regarding DMAC; FIG. 3 is a diagram illustrating an index space, an index table, a virtual drawing space, and a drawing area. FIG. 2 is a block diagram illustrating the internal configuration of a data transfer circuit together with related circuit configurations. FIG. 2 is a block diagram illustrating the internal configuration of a display circuit together with related circuit configurations. 3 is a diagram illustrating a data valid signal ENAB output from a VDP circuit. FIG. It is a flowchart explaining power reset operation after CPU reset. 16 is a flowchart illustrating memory section initialization processing that is a part of FIG. 15. FIG. 16 is a flowchart illustrating main control processing and interrupt processing that are part of FIG. 15. FIG. 3 is a flowchart illustrating a CGROM initialization process that is part of the main control process. 12 is a flowchart illustrating a part of processing contents regarding another interrupt processing. It is a flowchart explaining the control operation of production control CPU63 about the case where a preloader is not used. 3 is a diagram illustrating the configuration of a display list. 12 is a flowchart showing DL issuing processing for issuing a display list DL. 23 is a flowchart illustrating the operation when the DMAC is involved in the operation of FIG. 22. FIG. 24 is a flowchart illustrating operations subsequent to the process in FIG. 23. FIG. It is a flowchart explaining the control operation of production control CPU63 about the case where a preloader is used. 26 is a flowchart explaining a part of FIG. 25. FIG. 26 is a flowchart illustrating another part of FIG. 25. 7 is a time chart showing the operation of each part of the VDP in an embodiment that does not use a preloader. 5 is a time chart showing the operation of each part of the VDP in an embodiment using a preloader. FIG. 3 is a block diagram showing the overall circuit configuration of another embodiment. 31 is a block diagram showing a part of FIG. 30 in slightly more detail; FIG. 12 is a flowchart illustrating the operation details of another embodiment. It is a drawing explaining still another example. 7 is a diagram illustrating an example in which setting values are repeatedly set. FIG. 2 is a diagram illustrating a circuit configuration of an embodiment using a built-in audio circuit. 5 is a flowchart illustrating the initial setting operation of the audio circuit. 7 is a diagram illustrating another embodiment of a power reset operation after a CPU reset. FIG. 5 is a time chart showing an example of a memory READ operation and a memory WRITE operation. It is a drawing explaining another example. 1 is a diagram illustrating a method for driving a general display device.

Hereinafter, the present invention will be explained in detail based on Examples. FIG. 1 is a perspective view showing the pachinko machine GM of this embodiment. This pachinko machine GM consists of a rectangular wooden outer frame 1 that is removably attached to an island structure, and an inner frame 3 that is pivotally connected to the outer frame 1 so that it can be opened and closed via a hinge 2 that is fixed to the outer frame 1. It is configured. A game board 5 is removably attached to the inner frame 3 not from the back side but from the front side, and a glass door 6 and a front plate 7 are pivotally attached to the front side of the inner frame 3 so as to be openable and closable, respectively. In this specification, the glass door 6 and the front plate 7 are collectively referred to as a front door member. The inner frame 3 to which the front door member (glass door 6 and front plate 7) is pivotally attached may be referred to as a game frame.

On the outer periphery of the glass door 6, illuminated lamps such as LED lamps are arranged in a substantially C-shape. On the other hand, a total of three speakers are arranged at the upper right and left positions and the lower side of the glass door 6. The two speakers placed at the top are configured to output left and right channels R and L audio, respectively, and the bottom speaker is configured to output bass.

An upper tray 8 for storing game balls for firing is attached to the front plate 7, and a lower tray 9 for storing game balls overflowing or pulled out from the upper tray 8 and a firing handle are attached to the lower part of the inner frame 3. 10 are provided. The firing handle 10 is interlocked with a firing motor, and a game ball is fired by a hammer that operates according to the rotation angle of the firing handle 10.

A chance button 11 is provided on the outer peripheral surface of the upper plate 8. This chance button 11 is provided at a position where it can be operated with the player's left hand, and the player can operate the chance button 11 without removing his right hand from the firing handle 10. This chance button 11 does not function normally, but when the game state becomes the button chance state, the built-in lamp lights up and becomes operable. Note that the button chance state is a game state that is provided as necessary.

Further, a rotary switch type volume switch VLSW is arranged below the chance button 11, and when the player operates the volume switch VLSW, the sound level changes from the silent level (=0) to the highest level (=7). The speaker volume can be adjusted in 8 levels. Note that the volume of the speaker is initially set by a setting switch (not shown) that can be operated only by an attendant, and the initial setting volume is maintained unless the player operates the volume switch VLSW. Furthermore, the abnormality notification sound that informs that an abnormal situation has occurred is emitted at the highest volume regardless of the initial volume setting by the staff member or the volume setting by the player.

On the right side of the upper tray 8, there is provided an operation panel 12 for ball lending operations for the card-type ball lending machine, including a frequency display section that displays the remaining amount on the card as a 3-digit number, and a display section that displays the remaining amount of game balls for a predetermined amount. A ball lending switch for instructing the ball to be borrowed and a return switch for instructing the return of the cards at the end of the game are provided.

As shown in FIG. 2, a guide rail 13 consisting of an outer metal rail and an inner rail is provided in an annular shape on the surface of the game board 5, and a central opening HO is provided approximately in the center thereof. A movable performance element (not shown) is stored in a concealed state below the central opening HO, and when a movable advance notice is given, the movable performance element rises and becomes exposed, thereby achieving a predetermined level of reliability. The preview performance has been realized. Here, the preview performance is a performance that uncertainly informs the player that a jackpot condition advantageous to the player will occur, and the reliability of the preview performance refers to the probability that a jackpot condition will occur.

A main display device DS1 composed of a large liquid crystal color display (LCD) (for example, 1280 pixels horizontally x 1024 pixels vertically) is arranged in the central opening HO, and a small (for example, horizontally 1024 pixels horizontally A movable sub-display device DS2 configured with a liquid crystal color display (480×800 pixels vertically) is arranged. The main display device DS1 is a device that variably displays a specific symbol related to a jackpot state, and also displays a background image, various characters, etc. in an animated manner. This display device DS1 has special symbol display sections Da to Dc in the center and a normal symbol display section 19 in the upper right corner. Then, in the special symbol display sections Da to Dc, a ready-to-reach effect that makes the player expect a jackpot state may be executed, and in the special symbol display sections Da to Dc and around them, appropriate preview effects and the like are executed.

The sub-display device DS2 normally displays image information in a stationary state with its display screen tilted at an angle that is easy for the player to view. However, at the time of a predetermined preview performance, the tilt angle is changed to an angle that is easy for the player to see, and the predetermined preview image is displayed while moving to the left side in the figure.

That is, the sub-display device DS2 of the embodiment functions not only as a mere display device but also as a movable presentation body that executes a preview presentation. Here, the reliability of the preview performance by the sub-display device DS2 is set to be high, and the player pays attention to the moving operation of the sub-display device DS2 with great anticipation.

By the way, in the game area where the game balls fall and move, there are a first symbol starting opening 15a, a second symbol starting opening 15b, a first big winning opening 16a, a second big winning opening 16b, a normal winning opening 17, and a gate 18. is installed. Each of these winning holes 15 to 18 has a detection switch inside, and can detect the passage of a game ball.

Above the first symbol starting port 15a, a production stage 14 is arranged so that a prize can be won in the first symbol starting port 15 after the game ball that enters from the introduction port IN moves in a seesaw shape or a roulette shape. There is. Then, when a game ball enters the first symbol starting hole 15, the special symbol display sections Da to Dc start varying operations.

The second symbol start opening 15b is configured to be opened and closed by an electric tulip equipped with a pair of right and left opening/closing claws, and when the stop symbol after the fluctuation of the normal symbol display section 19 displays a winning symbol, a predetermined symbol is displayed. The opening/closing claw is opened for a certain amount of time or until a predetermined number of game balls are detected.

The normal symbol display section 19 displays normal symbols, and when a game ball passing through the gate 18 is detected, the normal symbol changes for a predetermined period of time and is extracted at the time when the game ball passes through the gate 18. The stop symbol determined by the random number for lottery is displayed and stopped.

The first big prize opening 16a is configured with a sliding board that advances and retreats in the front and back direction, and the second big winning opening 16b is configured with an opening/closing plate whose lower end is pivoted and opens forward. . Although the operation of the first big winning hole 16a and the second big winning hole 16b is not particularly limited, in this embodiment, the first big winning hole 16a corresponds to the first symbol starting hole 15a, and the second big winning hole 16b is configured to correspond to the first symbol starting port 15b.

That is, when a game ball enters the first symbol starting hole 15a, the special symbol display sections Da to Dc start varying operations, and then, when predetermined jackpot symbols are aligned in the special symbol display sections Da to Dc, the first jackpot is activated. A special game is started, and the sliding board of the first big prize opening 16a is opened forward to facilitate winning of game balls.

On the other hand, when the predetermined jackpot symbols are aligned in the special symbol display sections Da to Dc as a result of the fluctuating motion started by the winning of the game ball into the second symbol start opening 15b, a special game as a second jackpot is started, and the second jackpot is started. The opening/closing plate of the two major winning openings 16b is opened to facilitate winning of game balls. The gaming value of the special game (jackpot state) varies depending on the jackpot symbols arranged, but which gaming value is given is determined in advance based on the lottery result according to the winning timing of the game ball. It is determined.

In a typical jackpot state, after the opening/closing board of the big prize opening 16 is opened, the opening/closing board closes after a predetermined time has elapsed or when a predetermined number (for example, 10) of game balls have won. Such an operation is continued up to, for example, 15 times at maximum, and is controlled to be advantageous to the player. In addition, if the stopped symbol after the change of the special symbol display parts Da to Dc is a specific symbol among the special symbols, there is a benefit that the game after the end of the special game will be in a high probability state (probability variable state). Granted.

FIG. 3(a) is a block diagram showing the overall circuit configuration of the pachinko machine GM that implements each of the above-described operations. Further, FIG. 3(b) is a circuit diagram showing the circuit configuration of the power supply monitor unit MNI arranged on the payout control board 25, and FIG. 3(c) is a circuit diagram showing the specifications of the main display device DS1 used in this embodiment. FIG.

First, the specifications of the main display device DS1 used in the embodiment will be explained based on FIG. 3(c). As explained earlier, this display device DS1 is a liquid crystal color display of 1280 horizontal pixels x 1024 vertical pixels, but the odd number pixels (ODD) and even number pixels (EVEN) adjacent to each other in the left and right direction are separated by separate LVDS (Low Voltage The signal is received by the receiving unit RV (RVa+RVb) through the Differential Signaling (Differential Signaling) transmission line. Therefore, in this embodiment, in accordance with this specification, the ODD signal is transmitted via the first transmission line LVDS1, and the EVEN signal is transmitted via the second transmission line LVDS2 (Fig. 3 (bottom right of (a)).

Further, in this display device DS1, the operating clock CK (see FIG. 7) that defines the internal operation of the display device DS1 is specified to have a frequency in the range of 40 MHz to 70 MHz (typical value=54 MHz). This operating clock CK corresponds to the LVDS clock CLK to be described later, but in the following, for convenience of explanation, it is assumed that the frequency of the operating clock CK is a typical value of 54 MHz. In addition, a configuration will be described in which the update time FR (Frame Rate) required for updating one frame of image is approximately equal to 1/60 seconds at the operating clock CK of 54 MHz.

As a specification, this display device DS1 aligns two pixels adjacent in the left and right direction of the display screen based on the ODD signal received from the first transmission path LVDS1 and the EVEN signal received from the second transmission path LVDS2. It is configured to simultaneously process the data using the operating clock CK. As a result, the pixel data of 1280 pixels in one horizontal line is updated in an operation time of 640/54MHz = 11.85 μS, and by repeating this operation for 1024 lines, an image of 1280 x 1024 pixels for one frame is created. The display will be updated. Note that the image is updated line by line in a non-interlaced manner, such as from the first line to the second line, . . . , to the 1024th line.

However, as shown in FIG. 3(c), the specifications of the display device DS1 include providing a standby time (blank period) of 204 clocks as a typical value in the horizontal direction, and a typical value of 204 clocks in the vertical direction. It is specified that a waiting time (blank period) for 42 lines is provided. Therefore, the actual screen update cycle FR that takes these blank periods into consideration is (204+640) x (42+1024)/54MHz≒16.66mS in calculations based on the above-mentioned typical values, so the frame rate FR is approximately 1/ It becomes 60Hz.

Note that for each of the horizontal waiting time WTh and the vertical waiting time WTv, an allowable range with respect to a typical value is defined, and in reality, a value different from the above-described typical value can be selected. However, since the frame rate FR=1/60 seconds, it is necessary to accurately set the horizontal/vertical wait time WTh/WTv so that (WTh+640)×(WTv+1024)/54MHz=1/60 seconds. .

On the other hand, in this display device DS1, while it is not particularly necessary to receive the horizontal synchronizing signal HS and the vertical synchronizing signal VS, it is required to transmit the H-level data valid signal ENAB when transmitting the ODD signal and the EVEN signal. That is, the data valid signal ENAB needs to be at active level (H) at the timing when a significant signal (ODD/EVEN signal) is being transmitted to the transmission paths LVDS1 and LVDS2.

Therefore, in this embodiment, based on the specifications of the main display device DS1 described above, the production control board 23 and the main display device DS1 are connected by dual link transmission of the LVDS clock CLK with a frequency of 54 MHz (= 1/2 of the dot clock DCK). LVDS connection is made via the network (Fig. 5, Fig. 13(a)). Further, the VDP circuit 52 of this embodiment provides a horizontal blank period WTh and a vertical blank period WTv that satisfy the specifications of the main display device DS1, and also provides a data valid signal when outputting image data (ODD/EVEN signal). ENAB is set to active level (H level).

That is, the data valid signal ENAB is configured to be at H level only during the horizontal display period THd of the horizontal synchronization period TH, as shown in FIG. 4(b). Therefore, the data valid signal ENAB is always at the L level during the vertical synchronization period TV except for the vertical display period TVd. Note that the horizontal blank period WTh and the vertical blank period WTv adopt values different from their respective typical values (WTh=204/WTv=42), but the specific design values are based on FIG. will be described later.

In any case, the data valid signal ENAB is repeatedly transmitted as a discrete DE signal in each operating cycle of the LVDS clock CLK via the differential signal line RA2/RB2. The data valid signal ENAB shown in FIG. 4(b) and FIG. 4(c) is a demodulated DE signal that is discrete data transmitted by LVDS, and is a signal in which the discrete DE signal is made continuous on the time axis. It is. Note that on the differential signal line RA2/RB, the vertical synchronization signal VS and the horizontal synchronization signal HS are also repeatedly transmitted following the DE signal (data valid signal ENAB), but the main display used in the embodiment The device DS1 does not utilize these synchronization signals VS and HS.

However, in the display device DS1, transmission of the horizontal synchronization signal HS and the vertical synchronization signal VS is not prohibited at all. However, the internal operations specified by these synchronization signals are not executed. In other words, the horizontal line feed timing of the display line is determined by the falling timing of the data valid signal ENAB or the operating clock CK (corresponding to the LVDS clock CLK) after the rising timing of the data valid signal ENAB, regardless of the received horizontal synchronizing signal HS. (in the example, 640 pieces = 1280/2), etc., is determined to be the optimal timing for the internal circuit of the display device DS1 (downward arrow in FIG. 4(b)).

This point also applies to the vertical line feed timing after displaying one frame of image, and the internal circuit of the display device DS1 is determined based on the number of consecutive data valid signals ENAB of a predetermined pulse width (1024 in the embodiment). (downward arrow in FIG. 4(c)), and is not affected by the received vertical synchronization signal VS. In this way, in this embodiment, since there is no need to transmit the horizontal synchronizing signal HS and vertical synchronizing signal VS to the display device DS1, the pulse widths PWh/PWv of the synchronizing signals HS and VS, the front port FPh/FPv, There is no need to optimally set backport BPh/BPv, and the control burden on the production control section 23 and VDP circuit 52 is greatly reduced.

Furthermore, as for the internal operations of the display device DS1, horizontal line feed and vertical line feed operations are executed at optimal timings based on its own internal configuration, thereby eliminating the possibility of unnatural display operations. Incidentally, in the case of a display device that operates based on the horizontal synchronizing signal HS or vertical synchronizing signal VS received from the outside, the pulse width of the synchronizing signals HS and VS, the front porch period before and after the synchronizing signals HS and VS, If the back porch period is inappropriate, normal display operation may be impaired.

By the way, in FIG. 4(a), the first differential signal LVDS1 using the differential signal lines RA0 to RA3 and RACLK transmits odd-numbered pixels (ODD signal on A side), and the differential signal LVDS1 uses the differential signal lines RA0 to RA3 and RACLK. The second differential signal LVDS2 using lines RB0 to RB3 and RBCLK transmits even-numbered pixels (B-side EVEN signal). In this way, in this embodiment, by transmitting two types of ODD signals and EVEN signals through the dual link transmission path, the frequency of the dot clock DCK can be reduced to 1/2, and the noise resistance is improved accordingly. It has excellent performance and can also increase transmission distance.

On the other hand, the main display device DS1 has a built-in conversion reception unit RV for the ODD signal and EVEN signal transmitted through the dual link transmission line, and restores the RGB signal from the two LVDS signals (ODD signal and EVEN signal). An image of one frame (1280×1024 dots) is displayed. As explained above, since each RGB signal is composed of 8 bits, a full-color image with a gradation of 2 ⁸ × 2 ⁸ × 2 ⁸ is displayed on the main display device DS1.

FIG. 5 is a block diagram showing the internal configuration of the display device DS1 together with related parts of the VDP circuit 52. As shown in the figure, the ODD signal is transmitted to the LVDS-parallel converter RVa via the first LVDS line (A side), and the EVEN signal is transmitted to the LVDS-parallel converter RVa via the second LVDS line (B side). It is transmitted to parallel converter RVb. Of the 8-bit RGB data transmitted on the differential lines SA0/SB0, image data R0 to R5, G0 are extracted, and image data G1 to G5, B0 are extracted from the differential lines SA1/SB1. ~B1 is poured out.

Also, image data B2 to B5, DE signal, VS signal, and HS signal are output from differential line SA2/SB2, and image data G6 to G7, R6 to R7, B6 to B7 is dispensed. Here, the DE signal is nothing but the data valid signal ENAB. Further, as described above, the extracted VS signal and HS signal are not used.

Next, the LVDS clock CLK of the differential line RACLK/RBCLK is supplied to a PLL circuit, thereby generating an operation clock CK having the same frequency as the LVDS clock CLK, 54 MHz. This operation clock CK defines the internal operation of the liquid crystal controller LCD_CTL, and the liquid crystal controller LCD_CTL generates image data corresponding to two RGB pixels (8 bits x 3 x 2) adjacent in the left and right direction of the liquid crystal panel LCD. are processed all at once in synchronization with one operation clock CK.

Therefore, processing of pixels of 1280 (=640×2) dots in the horizontal direction is completed in a processing time of 11.85 μS (=640/54 MHz) corresponding to 640 operation clocks CK. Note that one pixel is composed of basic pixels of three colors RGB, and the image data of each basic pixel of three colors RGB is 1 byte long and has a gradation of 2 ⁸ × 2 ⁸ × 2 ⁸ , so The entire image data of all pixels (1280 dots) in one line has a length of 3×1280 bytes.

As shown in Figure 5, the liquid crystal controller LCD_CNT controls ON/OFF of the source driver SDV, which drives 1280 source signal lines with drive signals of 2 ⁸ (=256) gradations, and the 1024 gate signal lines. The gate driver GDV is controlled appropriately. Specifically, the liquid crystal controller LCD_CNT performs an image update operation at a frame rate FR=1/60Hz by operating each part appropriately based on the DE signal extracted from the LVDS transmission line and the operation clock CK. It has been realized. As confirmed earlier, the DE signal corresponds to the data valid signal ENAB output by the VDP circuit 52.

In the case of this embodiment, the source driver SDV is configured by arranging 10 driver elements each having 384 output terminals. As explained earlier, one line of all pixels (1280 dots) of a liquid phase panel LCD is composed of basic pixels of three colors RGB, and there are a total of 3 x 1280 pixels, so 10 driver elements are required to drive these. becomes. Note that these ten driver elements are sequentially supplied with image data DAT from the liquid crystal controller LCD_CNT, and transferred as appropriate based on the start signal SP and transfer clock DCLK. Then, in synchronization with the latch signal LT, the analog-converted drive signal is supplied to the 3840 source signal lines. As explained above, the time required for all pixels (1280 dots) in one line of the liquid crystal panel LCD to be updated is 11.85 μS (=640/54 MHz).

On the other hand, the liquid crystal controller LCD_CNT updates the gate signal line to be driven by supplying the gate start signal GS and the gate clock signal GCLK to the gate driver GDV. Here, the gate driver GDV is configured by arranging four driver elements each having 256 output terminals.

Note that the update timing of the gate signal line is defined based on the fall timing of the DE signal and the operation clock CK, and the horizontal line feed period of the gate signal line is counted using the operation clock CK, and the typical value calculation is 640 + 204. This is used as a clock (see FIG. 3(c)). Further, based on the number of DE signals (1024), the gate signal line to be driven is reset to the initial state, the gate start signal GS is outputted at the optimum timing, and the output of the gate clock signal GCLK is restarted. The vertical line feed cycle of the gate signal line is counted using the operation clock CK, and according to a typical value calculation, it is 42+1024 clocks (see FIG. 3(c)). However, as explained above, in this embodiment, the display device DS1 is operated with a design different from the typical value (see FIG. 14).

The main display device DS1 has been described in detail above, but the sub display device DS2 operates in the same way as shown in FIG. 40 based on the horizontal synchronization signal HS and vertical synchronization signal VS received from the VDP circuit 52. . However, it is also preferable that the sub-control device DS2 be configured to operate based on the data valid signal ENAB without being based on the horizontal synchronizing signal HS or the vertical synchronizing signal VS. Note that the data valid signal ENAB is transmitted to the sub-display device DS2 not in the form of a discrete DE signal but as a continuous signal ENAB (see the lower right part of FIG. 13(a)).

Next, returning to FIG. 3(a), the overall circuit configuration of the pachinko machine GM will be described. As shown in Fig. 3(a), this pachinko machine GM consists of a power supply board 20 that receives AC 24V and outputs various DC voltages (35V, 12V, 5V) along with AC 24V, and a main unit that centrally handles game control operations. Based on the control board 21, the production interface board 22 equipped with the circuit element SND for audio production, and the control command CMD received from the main control board 21, lamp production, audio production, and image production are performed in a unified manner. A game is played by controlling the payout motor M based on the control command CMD' received from the production control board 23, the liquid crystal interface board 24 located between the production control board 23 and the display devices DS1 and DS2, and the main control board 21. It is mainly composed of a payout control board 25 that pays out balls, and a firing control board 26 that fires game balls in response to operations by the player.

Note that the presentation interface board 22, the presentation control board 23, and the liquid crystal interface board 24 are directly connected to a male connector and a female connector without going through a wiring cable. Therefore, even if the circuit configuration of each electronic circuit becomes complex and sophisticated, the storage space of the entire board can be minimized, and the noise resistance can be improved by minimizing the connection lines.

As shown in the figure, the control command CMD' output from the main control board 21 is transmitted to the payout control board 25. On the other hand, the control command CMD output by the main control board 21 is transmitted to the performance control board 23 via the performance interface board 22. Here, the control commands CMD and CMD' are both 16 bits long, but are transmitted in parallel in two parts each having a length of 8 bits.

The main control board 21 and the payout control board 25 are equipped with a computer circuit including a one-chip microcomputer. Further, the production control board 23 is equipped with a composite chip 50 in which computer circuits such as a VDP circuit (Video Display Processor) 52 and a built-in CPU circuit 51 are built-in. Therefore, in this specification, the circuits mounted on the control boards 21, 25, 23, the production interface board 22 and the liquid crystal interface board 24, and the operations realized by the circuits are collectively referred to in terms of functionality. , the main control section 21, the production control section 23, and the payout control section 25. Note that the production control section 23 and the payout control section 25 serve as sub-control sections for the main control section 21.

Further, this pachinko machine GM is roughly divided into a frame side member GM1 surrounded by a broken line in FIG. 3(a) and a board side member GM2 fixed to the back side of the game board 5. The frame side member GM1 includes an inner frame 3 to which a glass door 6 and a front plate 7 are pivotally attached, and a wooden outer frame 1 on the outside thereof, and regardless of model changes, the game hall can be used for a long time. Fixedly installed. On the other hand, the panel side member GM2 is replaced in response to the model change, and a new panel side member GM2 is attached to the frame side member GM1 in place of the original panel side member. In addition, all except the frame side member 1 are board side members GM2.

As shown in the broken line frame in FIG. 3(a), the frame side member GM1 includes a power supply board 20, a backup power supply board 33, a payout control board 25, a firing control board 26, a frame relay board 36, and a motor/ A lamp drive board 37 is included, and these circuit boards are each fixed at a proper position on the inner frame 3. On the other hand, on the back side of the game board 5, a main control board 21, an effect control board 23 are fixed together with display devices DS1, DS2 and other circuit boards. The frame side member GM1 and the panel side member GM2 are electrically connected by central connection connectors C1 to C3 that are centrally arranged at one location.

The power supply board 20 generates three types of DC voltages (35V, 12V, 5V) based on the AC voltage AC24V distributed from the game hall, and connects each DC voltage to the performance interface via the central connection connector C2. Power is distributed to the face board 22. Moreover, three types of DC voltages (35V, 12V, 5V) are distributed to the payout control board 25 along with the AC voltage AC24V. The DC voltage (35V, 12V, 5V) distributed to the payout control board 25 is configured to be distributed to the main control board 21 together with the backup power supply BAK via the central connection connector C1.

The DC 35V is used as a driving power source for the ball feeding solenoid and the firing solenoid, and as a driving power source for the electromagnetic solenoid that opens and closes the electric tulip (variable prize winning device) and the big prize opening 16 in connection with the firing operation of the game ball. In addition, the DC 12V is used as the drive power for the LED lamps and motors controlled from each control board, and as the power supply voltage for the digital amplifier, while the DC 5V is used for the one-chip microcomputer on the dispensing control board 25 and the main control board 21. It is used as the power supply voltage for the logic elements mounted on each control board. In addition, the level of the DC 5V is lowered by the DC/DC converter on the production interface board 22, and the lowered voltages at various levels are used as the power supply voltage for various computer circuits (composite chip 50, audio processor 27, etc.). used.

The backup power supply BAK is a DC5V direct current power supply for retaining data in the built-in RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 25 after the power is cut off, and is realized by, for example, an electric double layer capacitor. In this embodiment, a dedicated backup power supply board 33 is provided, and the electric double layer capacitor disposed on the backup power supply board 33 is configured to be charged during gaming operations by a DC voltage of 5V received from the payout control board 25. has been done.

On the other hand, after the power is cut off, the backup power supply BAK retains the data in the built-in RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 25, so the main control unit 21 and the payout control unit 25 are The gaming operation can be resumed after the power is turned on. Note that an electric double layer capacitor capable of retaining the stored contents of the built-in RAM of each one-chip microcomputer for at least several days is arranged on the backup power supply board 33.

By the way, in this embodiment, unlike the conventional equipment configuration, the power supply abnormality signal ABN indicating an abnormal drop in the AC voltage AC24V is configured to be generated not in the power supply board 20 but in the power supply monitor unit MNT of the payout control board 25. has been done. As shown in FIG. 3(b), the power supply monitor unit MNT includes a full-wave rectifier circuit that rectifies the AC 24V received from the power supply board 20, a photodiode D that emits light when energized upon receiving the output of the full-wave rectification circuit, and the power supply board 20. A phototransistor TR that is powered by a DC voltage of 5V received from the photodiode D and turns on based on the light emission of the photodiode D, and an output section that outputs an H-level detection signal ABN (power supply abnormality signal) based on the ON operation of the phototransistor TR. It is composed of the following. Note that the photodiode D and the phototransistor TR constitute a photocoupler PH.

In the above configuration, after the power is turned on, the photocoupler PH is quickly turned on, so that the power abnormality signal ABN becomes a normal level (H). However, after that, when the AC power drops abnormally for some reason (normally the power is cut off), the photocoupler PH changes to the OFF state, and the power abnormality signal ABN changes to an abnormal level (L). This power supply abnormality signal ABN is transmitted to the one-chip microcomputer of the payout control board 25, and is also transmitted to the one-chip microcomputer of the main control board 21 via the central connection connector C1. Therefore, each one-chip microcomputer that receives the power supply abnormality signal ABN at the abnormal level executes a backup process of storing necessary information in its own built-in RAM. As explained above, since the information in the built-in RAM is maintained by the backup power supply BAK, the gaming operation that was in place before the power was cut off can be resumed after the power is turned on.

As shown in FIG. 3(a), the production interface board 22 is equipped with an audio circuit SND such as an audio processor 27, and the production control board 23 is equipped with computer circuits such as a VDP circuit 52 and a built-in CPU circuit 51. A composite chip 50 is mounted thereon. Hereinafter, the built-in CPU circuit may be abbreviated as a CPU circuit.

The performance interface board 22 is equipped with reset circuits RST3 and RST4 that detect a rise in the power supply voltage and generate various reset signals RT3 and RT4 when the power is turned on. First, the reset circuit RST3 generates a reset signal RT3 based on the DC voltages 12V and 5V distributed from the power supply board 20. Then, the reset signal RT3 resets the power of only the audio memory 28 and is transmitted to the production control board 23 as it is.

As shown in FIG. 6(a), the reset signal RT3 transmitted to the production control board 23 is ANDed with the output of the WDT (Watch Dog Timer) circuit 58 at the AND gate G1, and is sent to the CPU circuit as the system reset signal SYS. 51 and the VDP circuit 52 (see FIGS. 6(a) and 6(d)).

After the power is turned on, the reset signal RT3 generated by the reset circuit RST3 maintains the L level for a predetermined time as a power reset signal, and then rises to the H level. However, if one or more of the DC voltage 12V or 5V drops after that (usually when the power is cut off), the system reset signal SYS also drops to L level in response to the level drop of the reset signal RT3. Therefore, the CPU circuit 51 and the VDP circuit 52 of the production control board 23 become inactive.

This system reset signal SYS also changes based on the output of the WDT circuit 58 (which is at H level during normal operation), so when the reset signal RT3 is at H level, the output of the WDT circuit 58 may change due to program runaway or the like. Corresponding to the fall to the L level, the system reset signal SYS also changes to the L level, abnormally resetting the CPU circuit 51 and the VDP circuit 52 (see FIG. 6(d)).

On the other hand, the reset circuit RST4 generates the reset signal RT4 based on 3.3V generated by dropping the 5V distributed from the power supply board 20. This reset signal RT4 resets the power of the audio processor 27 as a power reset signal when the power is turned on.

As shown in the figure, the reset circuit RST4 is also supplied with the system reset signal SYS sent back from the production control board 23, so when the CPU circuit 51 or the VDP circuit 52 is abnormally reset, it is synchronized with the abnormal reset of these circuits. Then, the audio processor 27 is also abnormally reset. As a result, the audio performance returns to its initial state along with the image performance and lamp performance, and there is no risk that unnatural audio performance will continue.

Next, the payout control board 25, which is the frame side member GM1, and the main control unit 21, which is the board side member GM2, are each equipped with reset circuits RST1 and RST2, and when the power is turned on, a power reset signal is generated, and each The computer circuitry is configured to be power reset.

In this way, in this embodiment, the reset circuits RST1 to RST4 are arranged in the main control section 21, the payout control section 25, and the production interface board 22, respectively, and the system reset signal SYS is transmitted between the circuit boards. Never transmitted. That is, since there is no wiring cable for transmitting the system reset signal SYS, there is no possibility that the computer circuit will be abnormally reset due to noise superimposed on the wiring cable.

However, the reset circuits RST1 and RST2 provided in the main control unit 21 and the payout control unit 25 each have a built-in watchdog timer, and do not receive periodic clear pulses from the CPUs of the respective control units 21 and 25. In this case, each CPU is forced to reset.

In addition, the main control unit 21 is provided with an initialization switch SW that can be operated by a staff member, so that when the power is turned on, a RAM clear signal CLR indicating whether or not the initialization switch SW is turned on is output. It is configured. This RAM clear signal CLR is transmitted to the one-chip microcomputers of the main control section 21 and the payout control section 25, and determines whether or not to initialize all areas of the built-in RAM of the one-chip microcomputers of each control section 21, 25. ing.

In addition, as explained earlier, the one-chip microcontroller of the main control unit 21 and the payout control unit 25 receives the power supply abnormality signal ABN from the power supply monitor MNT arranged in the payout control unit 25, so that it and starts the necessary termination processing.

As shown in FIG. 3(a), the main control unit 21 receives a prize ball count signal indicating the payout operation of game balls, a status signal CON related to an abnormality in the payout operation, and an operation start signal BGN from the payout control unit 25. is being received. The status signal CON includes, for example, an out-of-supply signal, an insufficient dispense error signal, and a lower tray full signal. The operation start signal BGN is a signal that notifies the main control section 21 that the initial operation of the payout control section 25 has been completed after the power is turned on.

In addition, the main control section 21 receives switch signals from detection switches built into each of the winning holes 16 to 18 on the game board, and also drives solenoids such as electric tulips. The solenoids and detection switches are configured to operate with power supply voltage VB (12V) distributed from the main control unit 21. In addition, each switch signal indicating the winning status of the symbol starting port 15 is converted into a TTL level or CMOS level switch signal by an interface IC that operates with power supply voltage VB (12V) and power supply voltage Vcc (5V). After that, it is transmitted to the main control section 21.

As explained earlier, the production interface board 22 receives DC voltages of various levels (5V, 12V, 35V) from the power supply board 20 via the central connection connector C2 (see FIGS. 3(a) and 3). 6(a)). The DC voltage of 12V is the power supply voltage for the digital amplifier 29, and is also used as a driving voltage for LED lamps and the like. Further, the DC voltage of 35V is used as a drive voltage for a solenoid that is distributed to appropriate locations on the gaming slot and moves the movable object back and forth.

On the other hand, the DC voltage of 5V is supplied as a power supply voltage to circuit elements at various locations on the production interface board 22, and is also supplied to two DC/DC converters DC1 and DC2 to generate 3.3V and 1.0V ( (See FIG. 6(a)). The generated DC voltages of 3.3V and 1.0V are supplied to the audio processor 27 as power supply voltages for I/O (input/output) and chip core, respectively. Further, the DC voltage of 3.3V becomes the basic voltage of the power supply reset signal RT4 generated by the reset circuit RST4.

The DC voltage 5V distributed to the performance interface board 22 is distributed to the performance control board 23 together with 3.3V generated by the DC/DC converter DC1. The DC voltage of 3.3V distributed to the performance control board 23 is supplied to the composite chip 50, PROM 53, and CGROM 55 as a power supply voltage.

As shown in FIG. 6(a), two DC/DC converters DC3 and DC4 are arranged on the production control board 23, and based on the DC voltage 5V supplied to each, 1.5V and 1.05V is being generated. Here, the DC voltage of 1.05V is the power supply voltage for the chip core of the composite chip 50, and the DC voltage of 1.5V is the power supply voltage for I/O (input/output) with the DRAM 54. Therefore, the DC voltage of 1.5V is also supplied to the DRAM 54 as a power supply voltage.

As shown in FIG. 3(a), the production interface board 22 receives the control command CMD and the strobe signal STB from the main control unit 21, and transfers them to the production control board 23. More specifically, as shown in FIG. 6(a), the control command CMD and strobe signal STB are transferred to the composite chip 50 (CPU circuit 51) of the production control board 23 via the input buffer 40. . Here, the strobe signal STB is a received interrupt signal IRQ_CMD, and the performance control CPU 63 obtains the control command CMD based on an interrupt processing program (interrupt handler) activated in response to the received interrupt signal IRQ_CMD.

As shown in FIG. 6(a), the input buffer 44 of the production interface board 22 receives the switch signals of the chance button 11 and the volume switch VLSW from the frame relay boards 35 and 36, and sends each switch signal to the CPU of the production control board 23. It is transmitted to the circuit 51. Specifically, a 3-bit length of the encoder output indicating the contact position (0 to 7) of the volume switch VLSW and a 1-bit length indicating the ON/OFF state of the chance button 11 are transmitted to the CPU circuit 51.

Further, the performance interface board 22 is connected to a lamp drive board 30 and a motor lamp drive board 31, and is also connected to a lamp drive board 37 via frame relay boards 35 and 36. As shown, an output buffer 42 is arranged corresponding to the lamp drive board 30, and an input buffer 43a and an output buffer 43b are arranged corresponding to the motor lamp drive board 31. Note that in FIG. 6A, for convenience, the input buffer 43a and the output buffer 43b are collectively referred to as the input/output buffer 43. The input buffer 43a receives the outputs SN0 to SNn of the origin sensor for grasping the current position of the movable performance object (rotational position of the performance motors M1 to Mn), and transmits the output to the CPU circuit 51 of the performance control board 23. There is.

The lamp drive board 30, the motor lamp drive board 31, and the lamp drive board 37 are equipped with driver ICs of the same type, and the production interface board 22 receives serial signals from the production control board 23 and connects them to each driver IC. is being transferred to. Specifically, the serial signals are a lamp (motor) drive signal SDATA and a clock signal CK, and the drive signal SDATA is transmitted to each driver IC in a clock synchronized manner, and the drive signal SDATA is transmitted to each driver IC in a clock synchronized manner, and is used to perform lamp performances using a large number of LED lamps and illuminated lamps. , an accessory performance is executed by the performance motors M1 to Mn.

In the case of this embodiment, the lamp performance is executed by three systems of lamp groups CH0 to CH2, and the lamp drive board 37 receives the lamp drive signal SDATA0 of CH0 via the frame relay boards 35 and 36 as a clock. It is received in synchronization with signal CK0. Note that the series of lamp drive signals SDATA0 transmitted as serial signals are outputted from the driver IC to the lamp group CH0 at the timing when the operation control signal ENABLE0 changes to the active level, thereby updating the lighting state all at once.

The above points are the same for the lamp drive board 30, and the driver IC of the lamp drive board 30 receives the lamp drive signal SDATA1 of the lamp group CH1 in synchronization with the clock signal CK1, and the operation control signal ENABLE1 is at the active level. At the timing when the lamp group CH1 changes, the lighting states of the lamp group CH1 are updated all at once.

On the other hand, the driver IC mounted on the motor lamp drive board 31 drives the lamp group CH2 in response to a lamp drive signal transmitted in a clock synchronous manner, and also receives a motor drive signal transmitted in a clock synchronous manner. It drives a group of performance motors M1 to Mn composed of a plurality of stepping motors. Note that the lamp drive signal and the motor drive signal are a series of serial signals SDATA2, which are serially transmitted in synchronization with the clock signal CK1, and the driver IC that receives these signals determines the timing at which the operation control signal ENABLE2 changes to the active level. Then, the driving states of the lamp group CH2 and the motor groups M1 to Mn are updated.

Next, the audio circuit SND will be explained. As shown in FIG. 6(a), the production interface board 22 includes an audio processor (speech synthesis circuit) 27 that reproduces audio signals based on instructions received from the CPU circuit 51 (production control CPU 63) of the production control board 23. , an audio memory 28 that stores compressed audio data that is the original data of the audio signal to be reproduced, and a digital amplifier 29 that receives the audio signal output from the audio processor 27.

The audio processor 27 includes a WDT circuit that automatically resets the set value of the internal circuit to a default value (initial value) when the internal circuit malfunctions, and an audio control register SRG. Then, the audio processor 27 accesses the audio memory 28 based on the operation parameters (set values based on audio commands) received from the performance control CPU 63 in the audio control register SRG, and reproduces and outputs the necessary audio signals. .

As shown in FIG. 6A, the audio processor 27 and the audio memory 28 are connected by a 26-bit audio address bus and a 16-bit audio data bus. Therefore, the audio memory 28 can store 1 Gbit (=2 ²⁶ ×16) of data.

The audio control register SRG is divided into register bank 1 to register bank 6, each of which is specified by a register number from 00H to FFH. Therefore, the predetermined setting operation is realized by specifying the register bank and then writing the 1-byte length operation parameter into the audio control register SRG of the predetermined register number (1-byte length). Ru.

In the case of this embodiment, the register numbers (00H to FFH) of the audio control register SRG correspond to the address space CS3 of the production control CPU 63. For example, the operation parameter YYH is set in the audio control register SRG with register number XXH. In this case, the performance control CPU 63 writes XXH to the zero address of the address space CS3, and then writes YYH to the first address. That is, the performance control CPU 63 writes XXH and YYH to the data bus in this order. Note that in this specification, the subscript H and the prefix symbol 0X/0x indicate that the numerical value is expressed in hexadecimal.

In addition, in this specification, address spaces CS0 to CS7 refer to external memory for the CPU circuit 51, which can specify the memory type, including whether or not it is volatile, and the data bus width (8/16/32 bits). meaning (excluding internal memory). These address spaces CS0 to CS7 are selected by different chip select signals CS0 to CS7, and are configured to be settable so that the READ/WRITE control signal that functions during READ/WRITE access can be optimized in accordance with the memory type. Note that this setting operation is executed for the bus state controller 66.

FIG. 6(e) illustrates the setting operation to the audio register SRG by the production control CPU 63, and shows the contents of the 2-bit length address bus A1-A0 and the 1-byte length data bus D7-D0. There is. In this embodiment, the chip select signal CS3 is set at power-on so that it automatically becomes active when accessing the address space CS3, but this point will be described later with respect to FIGS. 8 and 15.

In any case, in the case of this embodiment, the compressed audio data stored in the audio memory 28 is phrase compressed data specified by a 13-bit phrase number NUM (000H to 1FFFH), and a series of background A maximum of 8192 types (=2 ¹³ ) of one piece of music (BGM), a group of performance sounds (notice sounds), etc. are stored, each corresponding to a phrase number NUM. This phrase number NUM is specified by the set value (operation parameter) of the voice command transmitted from the production control CPU 63 to the voice control register SRG of the voice processor 27.

As described above, the power of the audio memory 28 having the above configuration is reset by the reset signal RT3, and the power of the audio processor 27 is reset by the reset signal RT4. As shown in FIG. 6(c), after the power is turned on, the reset signal RT4 rises to H level after a predetermined assertion period ASRT (L level period), but in this embodiment, after that, the internal circuit of the audio processor 27 is configured to function automatically and perform initialization sequence processing. Note that this initialization sequence processing is an internal operation executed in a predetermined procedure, and the production control CPU 63 cannot access the audio register SRG during the operation of the initialization sequence processing.

When the initialization sequence processing, which is an internal operation, is completed, the interrupt signal IRQ_SND to the CPU circuit 51 changes to L level, and the CPU circuit 51 (performance control CPU 63) executes the interrupt processing program based on the interrupt signal IRQ_SND. Then, the interrupt signal IRQ_SND is returned to the H level based on a predetermined command, the details of which will be described later with reference to FIG. 17(c).

As shown in FIG. 6(a), the data bus and address bus of the CPU circuit 51 of the production control section 23 also extend to the clock circuit (real time clock) 38 and production data memory 39 mounted on the liquid crystal interface board 24. I'm reading. The clock circuit 38 is connected to the lower 4 bits of the address bus and the lower 4 bits of the data bus of the CPU circuit 51, and when the clock circuit 38 is selected by the chip select signal CS4, the CPU circuit 51 The internal register (having an address value) can be accessed arbitrarily.

The performance data memory 39 is a memory element SRAM (Static Random Access Memory) that can be accessed at high speed, and is connected to the 16 bits of the address bus of the CPU circuit 51 and the lower 16 bits of the data bus, and is connected to the chip select signal CS4. In the state where the chip is selected, game performance information and other information stored in the SRAM (performance data memory) 39 is accessed by the CPU circuit 51 as appropriate. Note that in the address space CS4 selected by the chip select signal CS4, addresses 0 to 15 are numbered to the clock circuit 38, and therefore are not used by the SRAM 39.

The clock circuit 38 and the performance data memory 39 are driven by a secondary battery (not shown), and this secondary battery is appropriately charged by the power supply voltage from the power supply board 20 during the game operation. Therefore, even after the power is cut off, the timekeeping operation of the clock circuit 38 continues, and the game performance information stored in the performance data memory 39 is permanently stored and held (imparted with non-volatility). Note that the clock circuit (RTC) 38 is configured to be able to output an interrupt signal IRQ_RTC to the CPU circuit 51 (RTC interrupt). These RTC interrupts include alarm interrupts that can specify the date, day of the week, hour, minute, and second, and timer interrupts that are activated after a predetermined time has passed. Utilizes alarm interrupts to update gaming performance information.

As shown on the right side of FIG. 6(a), the production control board 23 includes a composite chip 50 that includes a CPU circuit 51 and a VDP circuit 52, and a control memory (PROM) 53 that stores a control program for the CPU circuit 51. It is equipped with a DRAM (Dynamic Random Access Memory) 54 that can access a large amount of data at high speed, and a CGROM 55 that stores a large amount of CG data required for production control.

As will be described later with reference to FIG. 9, the control memory (PROM) 53 is located in the address space CS0 selected by the chip select signal CS0 in this embodiment. Further, a DRAM (Dynamic Random Access Memory) 54 configured with DDR (Double-Data-Rate 3) is positioned in an address space CS5 selected by a chip select signal CS5.

FIG. 7(a) is a circuit block diagram illustrating the composite chip 50 constituting the production control section 23, including related circuit elements. As shown in the figure, the composite chip 50 of the embodiment includes a CPU circuit 51 that issues a display list DL at predetermined time intervals, and a CPU circuit 51 that generates image data based on the issued display list DL to drive the display devices DS1 and DS2. A VDP circuit 52 is built-in. The CPU circuit 51 and the VDP circuit 52 are connected through a CPU IF circuit 56 that relays mutual transmission and reception data.

Note that although the VDP circuit 52 has a built-in audio circuit SND that performs the same function as the audio processor 27, the audio circuit SND is not utilized in the first embodiment to be described. However, if the audio circuit SND built into the VDP circuit 52 is utilized as in the embodiment described last, the audio memory 28 and the audio processor 27 are not required.

First, the CPU circuit 51 receives the oscillation output (for example, 100/3 MHz) of the oscillator OSC1 at the HCLKI terminal, and multiplies the frequency (for example, by 8) to obtain a CPU operating clock of about 266.7 MHz (Fig. 13 (see (b)). Here, the oscillator OSC1 is configured to output a spread spectrum wave, thereby taking measures against EMI (Electromagnetic Interference) to prevent radio interference/electromagnetic interference.

Incidentally, in the case of this embodiment, the CPU operating clock can be generated based on the output of an oscillator OSC2, which will be described later, instead of the oscillator OSC1, and the oscillator OSC1 can be made unnecessary. However, in a configuration in which a single oscillator is used, the frequency multiplication ratio of the PLL circuit is the same fixed value (for example, 5) as in the case of the system clock described below, so the frequency of the CPU operating clock is The frequency is 200MHz (=40MHz×5), which is the same as the system clock.

Although such a configuration has the advantage that the built-in CPU circuit 51 and the VDP circuit 52 have a common operating cycle, it goes against the desire to speed up the CPU operation as much as possible. That is, since the VDP operation cannot be made faster than a certain level, it is not possible to reliably meet the demand for faster CPU operation. Therefore, in this embodiment, two oscillators are provided in order to optimize the respective operating cycles of the VDP circuit 52 and the CPU circuit 51. Further, by providing a separate oscillator OSC1, the above-mentioned EMI countermeasures can be improved.

To explain the VDP circuit 52 based on the above, the VDP circuit 52 receives the oscillation output (40 MHz) of the oscillator OSC2, which is different from the oscillator OSC1, at the PLLREF terminal, multiplies the frequency using a PLL (Phase Locked Loop) circuit, and then , is used as the system clock for the VDP circuit 52. The frequency multiplication ratio of the PLL circuit is fixedly defined by the setting value to a predetermined setting terminal, and in this embodiment, since the setting value to the setting terminal (3-bit PLLMD terminal) is a fixed value of 5, the VDP The system clock of the circuit 52 is 200 MHz (=40 MHz×5) (see FIG. 13(b)).

Furthermore, in this embodiment, the dot clocks DCK _A to DCK _C that define the operations of the display circuits 74A to 74C and the DDR clock of the external DRAM 54 are also generated based on the oscillation output (40 MHz) of the oscillator OSC2. There is. That is, the output (40 MHz) of the oscillator OSC2 functions as a reference clock for the entire VDP circuit 52.

As will be described later with reference to FIGS. 13 and 14, since the display circuits 74A to 74C normally drive display devices with different specifications, the dot clocks DCK _A to DCK that define the operation of each display circuit 74A to 74C are _C needs to correspond to the specifications of the display device to be driven. Based on this need, in this embodiment, the display circuits 74A to 74C receive any of the output clocks (DCLKAI to DCLKCI) of the dedicated oscillation circuits DCLKA to DCLKC and use them as dot clocks DCK _A to DCK _C. It is configured so that it can also be used.

When this configuration is utilized, there is no need to design multiplication ratios or frequency division ratios or set processing to VDP register RGij, which will be described later, and the frequencies of dot clocks DCK _A to DCK _C can be easily optimized. . That is, a dedicated oscillation circuit DCLKA with an oscillation frequency _FDOT1 is provided corresponding to the dot clock frequency _FDOT1 of the main display device DS1, and a dedicated oscillation circuit DCLKA with an oscillation frequency _FDOT2 is provided corresponding to the dot clock frequency _FDOT2 of the sub display device DS2. It is also possible to provide an oscillation circuit DCLKB.

However, when adopting such a configuration, dedicated oscillation circuits are required corresponding to the number of display devices, and the equipment configuration becomes complicated. Therefore, in this embodiment, in order to simplify the equipment configuration, the dot clocks DCK _A /DCK _B of the display circuits 74A/74B are generated based on the oscillation output (40 MHz) of the oscillator OSC2. Specifically, as shown in FIG. 13(b), for the display circuit 74A that drives the main display device DS1, the oscillation output (40 MHz) of the oscillator OSC2 is subjected to predetermined multiplication processing (×108) and frequency division processing (1 /40), a dot clock DCK _A with a frequency of 108 MHz is generated.

Similarly, for the display circuit 74B that drives the sub-display device DS2, the frequency F is increased by subjecting the oscillation output (40 MHz) of the oscillator OSC2 to predetermined multiplication processing (×108) and frequency division processing (1/160). A dot clock DCK _B of _dot = 27 MHz is generated. Designing these multiplication ratios and frequency division ratios is somewhat complicated, and it is easier to provide a dedicated oscillation circuit, but in this example, we focused on simplifying the equipment configuration, and has not been established.

In any case, the dot clocks DCK _A to DCK _C are individually set for each display circuit 74A to 74C, but when these dot clocks DCK _A to DCK _C are collectively referred to as "display clocks" in this specification, It is sometimes referred to as "DCK". Furthermore, in the following description, the dot clocks DCK _A and DCK _B may be abbreviated as "dot clocks DCK" for convenience.

Note that in this embodiment, since a low-speed LVDS output configuration is not adopted, the LVDS clock CLK of the LVDS signal outputted via the display circuit 74A also undergoes the same generation process as the dot clock DCK _A , and has a frequency of 108 MHz. It is said that However, in this embodiment, since a dual link transmission path is adopted, the actual frequency of the LVDS clock CLK is 54 MHz, as explained in connection with FIG. 4. Note that when a single link transmission path is adopted, the frequency of the LVDS clock CLK is 108 MHz.

As described above, in this embodiment, the oscillation output (40 MHz) of the oscillator OSC2 is utilized as a reference clock for the system clock, dot clock DCK, and DDR clock. Therefore, in consideration of this importance, the oscillator OSC2 is operated at the same power supply voltage of 3.3V as the VDP circuit 52, and the reference clock is set on the condition that the output enable terminal OE is at H level (=3.3V). It is configured to output oscillation. If the power supply voltage of 3.3V drops below a predetermined level, normal performance operation cannot be expected after that, so a non-maskable interrupt (NMI) is generated.

Further, the composite chip 50 is provided with an HBTSL terminal, and based on the logic level of the HBTSL terminal, it is determined whether the boot program (initial setting program) to be executed after power-on (CPU reset) is stored in the CGROM 55 (HBTSL =H), or whether it is stored in a memory other than that (HBTSL =L). As shown in the figure, in this embodiment, HBTSL is set to L level, and the zero address of the address space CS0 of the production control CPU 63 is allocated to a location other than the CGROM. Specifically, the address space CS0 is set to the control memory 53. is assigned to.

On the other hand, when the HBTSL terminal is set to H level (see broken line), address zero of the address space CS0 of the production control CPU 63 is assigned to the CGROM 55. In this case, the memory type and bus width (64/32/16 bits) of the CGROM 55 are respectively specified based on the input values to the 2-bit long HBTBWD terminal and the 4-bit long HBTRMSL terminal. Note that these points will be further described later based on FIG. 37.

Next, regarding the CPU circuit 51 and the VDP circuit 52, the CPU IF circuit 56 that relays mutual transmission and reception data will be described. As shown in FIG. 7(a), the CPUIF circuit 56 includes a control memory (PROM) 53 that non-volatilely stores control programs and necessary control data, and a work memory (RAM) 57 having a storage capacity of about 2 Mbytes. are connected to each other, and each is configured to be accessible from the CPU circuit 51. As explained above, the control memory (PROM) 53 is located in the address space CS0 selected by the chip select signal CS0, and the work memory (RAM) 57 is located in the address space CS6 selected by the chip select signal CS6. It is being

The work memory (RAM) 57 has a DL buffer BUF that temporarily stores a display list DL in which a series of instruction commands for specifying one frame each of the display devices DS1 and DS2 is written. In the case of this embodiment, the series of instruction commands includes texture loading commands such as the TXLOAD command for reading and decoding (expanding) image materials (textures) from the CGROM 55, and the VRAM area (index) to be decoded (expanded). texture setting commands such as the SETINDEX command, which has functions such as specifying a space in advance, and primitive drawing commands such as the SPRITE command, which places the decoded (expanded) image material at a predetermined position in the virtual drawing space. , environment setting commands such as the SETDAVR command and SETDAVF command for specifying the drawing area to be actually drawn on the display device among images drawn in the virtual drawing space by drawing commands, and the index table IDXTBL for managing the index space. Contains index table control commands (WRIDXTBL) related to

Note that FIG. 11(c) shows a virtual drawing space (horizontal X direction ±8192: vertical Y direction ±8192), a drawing area that can be set arbitrarily in the virtual drawing space, and output to display devices DS1 and DS2. The relationship between the actual drawing areas in the frame buffers FBa and FBb that temporarily store image data is illustrated.

Next, the CPU circuit 51 is a circuit that has the same performance as a general-purpose one-chip microcomputer, and is connected to a production control CPU 63 that centrally controls image production based on the control program in the control memory 53. A watchdog timer (WDT) that forcibly resets the CPU, a built-in RAM 59 that has a storage capacity of about 16 kbytes and is used as a work area for the CPU, and a DMAC (Direct Memory Access) that realizes data transfer without going through the CPU 63. A serial input/output port (SIO) 61 having a plurality of input ports Si and an output port So, a parallel input/output port (PIO) 62 having a plurality of input ports Pi and output ports Po, It is configured to include an operation control register REG, etc., in which set values are set to control the operation. However, in this embodiment in which an external WDT circuit 58 is provided, the watchdog timer (WDT) built into the CPU circuit 51 is not utilized.

In this specification, for convenience, the expression "input/output port" is used, but in the production control section 23, the input/output port includes an input port and an output port that operate independently. This point also applies to the input/output circuit 64p and input/output circuit 64s described below.

The parallel input/output port 62 is connected to an external device (the production interface board 22) through the input/output circuit 64p, and the production control CPU 63 inputs the 3-bit encoder output of the volume switch VLSW and the chance output via the input circuit 64p. The switch signal of the button 11, the control command CMD, and the interrupt signal STB are received. The 3-bit encoder output and 1-bit switch signal are supplied to the parallel input/output port (PIO) 62 via the input/output circuit 64p.

Similarly, the received control command CMD is supplied to the parallel input/output port (PIO) 62 via the input/output circuit 64p. Further, the strobe signal STB is supplied to the interrupt terminal of the production control CPU 63 via the input/output circuit 64p, thereby starting the reception interrupt process. Therefore, the performance control CPU 63, which has grasped the control command CMD based on the reception interrupt processing, uniformly controls the audio performance, lamp performance, motor performance, and image performance corresponding to this control command CMD through a performance lottery or the like. I will do it.

Although not particularly limited, in this embodiment, an SMC section (Serial Management Controller) 78 of the VDP circuit 52 is used for lamp effects and motor effects. The SMC unit 78 is a composite controller that includes an LED controller and a motor controller, and is configured to output serial signals in a clock synchronous manner. Further, the Motor controller is configured to be able to output a latch pulse at any timing based on a set value to a predetermined control register 70, and is also configured to be able to input a serial signal in a clock synchronized manner.

Therefore, in this embodiment, the motor drive signal and the LED drive signal are outputted from the SMC section 78 in synchronization with the clock signal, while the latch pulse is outputted as the operation control signal ENABLE at an appropriate timing. . Further, it is configured to serially input the origin sensor signals SN0 to SNn from the effect motor groups M1 to Mn in a clock synchronized manner.

As explained in connection with FIG. 6(a), the clock signals CK0 to CK2, the drive signals SDATA0 to SDATA2, and the operation control signals ENABLE0 to ENABLE2 are sent to the predetermined drive boards 30, 31, 37. Further, the origin sensor signals SN0 to SNn are serially inputted from the motor lamp drive board 31 to the SMC unit 78 via the input/output buffer 43.

However, in this embodiment, it is not essential to use the SMC section 78. That is, since the CPU circuit 51 has a built-in general-purpose serial input/output port SIO 61, these can be used to perform lamp effects and motor effects.

Specifically, as shown by the broken line in FIG. 7(a), in the configuration shown by the broken line, the clock signals CK0 to CK2, Drive signals SDATA0 to SDATA2 are output, and operation control signals ENABLE0 to ENABLE2 are output via the input/output circuit 64p. For convenience, it is expressed as an input/output port or an input/output circuit, but what actually functions is an output port or an output circuit.

Here, the serial output port SO is configured to include a 16-stage FIFO register. Then, the DMAC circuit 60 receives an operation start instruction from the production control CPU 63 (see ST18 in FIG. 20(b)), starts up, and sequentially inputs the necessary drive data from the lamp/motor drive table (see FIG. 20(b)). It is configured to read the data and transfer it by DMA to the FIFO register of the serial output port SO. The drive data accumulated in the FIFO register is serially output from the serial output port SO in a clock synchronous manner. Note that the DMAC circuit has multiple (for example, 7) DMA channels, but the third DMA channel with lower priority transfers the lamp drive data by DMA, and the first DMA channel with the highest priority transfers the motor drive data. It is configured to perform DMA transfer of data.

The operation control register REG built into the CPU circuit 51 is an 8-bit, 16-bit, or 32-bit long register whose register number (address value) is numbered after 0xFF400000, and can be accessed by WRITE/READ from the production control CPU 63 as appropriate. (See Figure 9). Therefore, the operation control register REG may be set to an unreasonable value due to noise or the like.

However, for example, the composite chip 50 can be abnormally reset by intentionally executing infinite loop processing and activating the external WDT circuit 58. In this case, the value of the operation control register REG is returned to the same default value (initial value) as after the power is turned on, and the value of the VDP register RGij of the VDP circuit 52 is also returned to the default value (initial value). This will resolve the abnormal condition.

FIG. 6(b) is a circuit configuration related to this reset operation, and is a diagram illustrating a reset mechanism that is characteristic of this embodiment. Note that in this specification, the VDP register expressed as RGij is not the operation control register REG built into the CPU circuit 51, but any one of the control register group 70 (see FIG. 9) that controls the internal operation of the VDP circuit 52. means. Furthermore, the system control circuit 520 shown in FIG. 6(b) means an internal control circuit of the VDP circuit 52 that functions based on the set value to the VDP register RGij (any of the control register group 70 in FIG. 9). (See FIG. 6(a)). Note that the VDP register RGij is located in the address space CS7 selected by the chip select signal CS7 in the address map of the production control CPU 63.

To explain the reset mechanism based on the above, as shown in FIG. 6(b), the composite chip 50 receives the internal circuit through three OR gates G2 to G4 that receive the logically inverted system reset signal SYS bar. is configured to be resettable. However, in this embodiment, as shown by the broken line, the built-in WDT is not enabled, so the input terminal and output terminal of OR gate G2 are directly connected.

In any case, a pattern check circuit CHK is provided between the CPU circuit 51 and the VDP circuit 52, and the pattern check circuit CHK receives a predetermined keyword string (a code string for reset) from the parallel input/output port (PIO) 62. ) is configured to output a reset signal RST.

The internal circuit of the composite chip 50 is divided into three parts: (1) the CPU circuit 51, (2) the display circuit 74 of the VDP circuit 52, and (3) the circuit other than the display circuit in the VDP circuit 52. It is configured to receive reset signals from the first to third reset paths from the gates G2 to G4.

First, the OR gate G2, whose input and output terminals are directly connected, is associated with the first reset path, and is configured so that the entire CPU circuit 51 is system reset based on the system reset signal SYS bar. Further, the OR gate G3 is related to the second reset path, and can reset the entire VDP circuit 52 based on OR logic upon receiving the system reset signal SYS bar and the reset signal RST from the pattern check circuit CHK. It is composed of

This second reset path is used not only for the power reset operation when the power is turned on, but also for the performance control CPU 63, which detects a predetermined abnormality, to reset the entire VDP circuit 52 to the initial state. Specifically, if it is determined that a serious abnormality has occurred based on a predetermined status register RGij indicating the internal operation of the VDP circuit 52, a reset signal RST is generated from the pattern check circuit CHK. , the entire VDP circuit 52 is abnormally reset. Note that the display circuit 74 is abnormally reset via the OR gate G4 via the second reset path→the third reset path.

On the other hand, the internal circuits built into the VDP circuit 52 are configured so that they can be individually reset when necessary via a fourth reset path. Internal circuits that can be reset individually include the index table IDXTBL, data transfer circuit 72, preloader 73, display circuit 74, drawing circuit 76, SMC circuit 78, and audio circuit SND shown in FIG. 12 is included.

The method of realizing the individual reset operation is as described at the bottom of FIG. 6(b). For example, the display circuit 74 writes the first reset value to a predetermined VDP register RGij (system command register). As a result, it is reset via the fourth reset path 4A→the third reset path.

In addition, each internal circuit (72, 73, 74, 76, SND, ...) of the VDP circuit 52 (1) sets a setting value that specifies the target circuit in the first VDP register RGij (reset RQ register). After writing, (2) the second reset value is written in a predetermined VDP register RGij (system command register) to be individually reset (fourth reset path 4B). Although not used in this embodiment, the audio circuit SND can be reset not only by resetting via the fourth reset path 4B but also by writing a reset value to a predetermined VDP register (circuit setting command register). 4 reset path 4C).

Since this embodiment has the above configuration, not only the entire VDP circuit 52 automatically returns to the initial state when the power is turned on or a program runs out of control, but also each part is returned to the initial state as necessary to prevent abnormal situations. recovery can be achieved. For example, when the drawing circuit 76 freezes with no READ/WRITE access to the built-in VRAM 71 for a certain period of time, the drawing circuit 76 is individually initialized via the fourth reset path 4B (see FIG. 20(d)). (See ST16a). The same applies to the preloader 73 and the data transfer circuit 72, and in the event of a predetermined abnormality, the preloader 73 is initialized via the fourth reset path 4B (see ST27 in FIG. 27), and the preloader 73 is initialized via the fourth reset path 4B. The data transfer circuit 72 is initialized (see ST27 in FIGS. 22 and 27).

In addition, regarding the display circuit 74, if an underrun abnormality continues in which display data cannot be generated in time at the display timing of every 1/60 seconds, the fourth reset path 4A or the fourth reset path 4B is activated. The display circuit 74 is individually initialized via the process (see ST10c in FIG. 20). Note that these individual reset operations will be further described later with respect to the program processing described from FIG. 20 onwards.

The reset mechanism characteristic of this embodiment has been described above. When any of the reset paths 1 to 4 functions and the internal circuit of the composite chip 50 is reset, the VDP register RGij corresponding to the internal circuit is reset. The setting value returns to the same default value after power-on.

Next, returning to the internal configuration of the CPU circuit 51, description of the characteristic circuit configuration will be continued. FIG. 8 is a block diagram showing the internal configuration of the CPU circuit 51 in slightly more detail. The CPU circuit 51 is configured to include many characteristic circuits in addition to the built-in RAM 59, DMAC circuit 60, SIO 61, PIO 62, and WDT described above.

First, the CPU circuit 51 implements the Harvard architecture by separately having a CPU fetch bus for instructions and a CPU memory access bus for data. Therefore, the fetch operation in which the CPU core (performance control CPU) 63 reads instructions from the memory does not conflict with the memory access operation, and high-speed processing is achieved by making the fetch operations consecutive.

Further, the CPU core 63 is configured to include a plurality of (for example, 15) register banks RB0 to RB14, and is configured to be able to select whether or not to use them. In an operating state in which the use of register bank RBi is permitted, at the start of interrupt processing, the register values (each 32 bits long) of the CPU's built-in registers (for example, 19) are automatically saved to an empty register bank RBi. be done.

Further, when a predetermined return instruction is executed at the end of interrupt processing, for example, 19 pieces of saved data are automatically returned to the corresponding built-in registers. Therefore, there is no need to execute the PUSH instruction 19 times at the start of interrupt processing and the POP instruction 19 times at the end of the interrupt processing, as in the normal configuration, and high-speed processing is realized.

Further, the CPU circuit 51 of the embodiment realizes Harvard cache operation by providing an instruction cache memory 67, an operand cache memory 89, and a cache controller 69. By utilizing this data, we aim to further speed up program processing. Note that by providing the bus bridge 65, a controller for the peripheral bus (1), a controller for the peripheral bus (2), and a controller for the peripheral bus (3), the internal bus and the peripheral bus (1) are provided. ), peripheral bus (2), and peripheral bus (3) as appropriate.

Next, in the circuit configuration of FIG. 8, the bus state controller 66 operates based on the appropriate setting value to the operation control register REG, and performs memory READ operations with various memory devices connected to the CPU circuit 51. This is the part that optimizes WRITE operations. The memory READ operation and the memory WRITE operation are executed, for example, at the operation timing illustrated in FIG. The operation timing of WRITE data written to the WRITE data bus (32Bit) and control signals such as chip select signals CS0 to CS7 is based on the setting value to the operation control register REG and corresponds to the characteristics of each memory device. As appropriate.

Since the READ data bus and WRITE data bus are provided separately, high-speed operation according to the Harvard architecture described above is realized. In this specification, the address bus (28Bit), READ data bus (32Bit), and WRITE data bus (32Bit) are referred to as internal buses shown in FIG. 8, peripheral buses (1) to peripheral buses (3), etc. It is sometimes collectively referred to as an external bus to distinguish it from the external bus.

FIG. 9 illustrates the address spaces CS0 to CS7 selected by the chip select signals CS0 to CS7, and illustrates the address map for the performance control CPU 63 accessed via the bus state controller 66. . First, each address space CS0 to CS7 is defined to have a maximum of 64 Mbytes (=0x4000000H=67108864).

As explained above, the address spaces CS0 to CS7 refer to external memories for the CPU circuit 51, which can specify the memory type, including whether or not it is volatile, and the data bus width (8/16/32 bits), respectively. do. In this embodiment, as shown in FIG. 8(b) and FIG. The SRAM 39 is located in address space CS4, the external DRAM (DDR) 54 is located in address space CS5, the work memory 57 is located in address space CS6, and the VDP register RGij is located in address space CS7. Note that a description of the address spaces CS1 and CS2 will be omitted.

By the way, as confirmed from FIG. 9, address spaces CS0 to CS7 are reserved not only for address values 0x00000000 to 0x1FFFFFFF (cache valid space) but also for address values 0x20000000 to 0x3FFFFFFF (cache invalid space). This means that when address bit A29=1, the cache is disabled based on the internal operation of the CPU circuit 51, while when address bit A29=0, the cache is enabled, so that the utilization of the cache function can be arbitrarily selected. This is how it was done.

Therefore, in this embodiment, even if the value of bit A29 of the total 32 bits of address information (bits A31 to A0) is 1 or 0, the remaining 31 bits (bits A31 to A30 and bits A28 to A0) If the values are the same, they point to the same location in the same memory. For example, whether the address 0x18000000 is accessed by READ or the address 0x38000000 is accessed by READ, the same data will be read from address zero of the work memory 57. Note that when the address 0x18000000 is accessed by READ, the read data is stored in the cache, and FIG. 8(b) illustrates the access operation to enable/disable the cache.

However, it is also possible to disable the cache operation of the instruction cache and/or operand cache based on the set value to a predetermined operation control register REG. However, in this embodiment, after the power is turned on, cache operations are enabled for the instruction cache and operand cache, and then the cache operations are disabled by accessing the cache invalid space as necessary.

Continuing with the explanation of the memory map in FIG. 9, the area after address 0x40000000 is an internal memory space in which the bus state controller 66 does not function, and addresses 0xF0000000 to 0xFF3FFFFF are allocated to the address array space of the cache. Furthermore, addresses 0xFF400000 to 0xFFF7FFFF and addresses 0xFFFC0000 to 0xFFFFFFFF are allocated to built-in peripheral modules, and specifically, to the operation control register REG of the CPU circuit. Note that the address range of the built-in RAM 59 is 0xFFF80000 to 0xFFFBFFFF.

Continuing with the explanation of the internal configuration of the CPU circuit 51, the compare match timer CMT and the multi-function timer unit MTU count external signals supplied to the CPU circuit 51, or count by multiplying or dividing the internal clock. This circuit counts clocks and generates an interrupt signal when the count reaches a predetermined value. Although not particularly limited, in this embodiment, the multi-function timer unit MTU is utilized to generate a 1 mS interrupt signal and a 20 μS interrupt signal.

Next, the interrupt controller INTC receives internal interrupts from the VDP circuit 52, DMAC circuit 60, multi-function timer unit MTU, etc., and external interrupts such as IRQ_CMD, IRQ_SND, and IRQ_RCT, based on predefined priorities. This is a circuit that starts interrupt processing (interrupt handler). Here, IRQ_CMD is a command reception interrupt signal for receiving the control command CMD, IRQ_SND is an end interrupt signal indicating that the audio processor 27 has finished the initialization sequence, and IRQ_RCT is an alarm interrupt signal.

In this embodiment, the command reception interrupt IRQ_CMD has the highest level of interrupt priority, and the order of priority is as follows: 20 μS interrupt → 1 mS interrupt → interrupt from the VDP circuit (IRQ0, IRQ1, IRQ2, IRQ3) → DMAC interrupt → IRQ_SND → The order is IRQ_RCT (see Figure 17(d)). All of these are maskable interrupts, and the non-maskable interrupt NMI is output to the performance control CPU 63 when the reference clock is not output from the oscillator OSC2, as described above.

In any interrupt processing, the register values (each having a length of 32 bits) of the plurality of built-in registers of the CPU are automatically saved to one of the vacant register banks RBi. Then, when a predetermined return instruction is executed at the end of the interrupt processing, the saved data is automatically returned to the corresponding built-in register.

Next, the DMAC circuit 60 will be explained. The DMAC circuit 60 of the embodiment performs data transfer from a transfer source (Source) to a transfer destination (Destination) in a predetermined DMA transfer mode every predetermined data transfer unit based on the set value in a predetermined operation control register REG. This is a circuit that repeats data transfer a predetermined number of times. Note that a plurality of channels DMAC0 to DMACn having the same internal configuration are prepared and can operate in parallel. However, the priority is determined (channel 0>...>channel n), and during parallel operation in the channel arbitration operation mode, the operation of DMACi with a higher priority is prioritized by channel arbitration at a predetermined timing.

As for the utilization of the DMAC circuit 60, for example, in an embodiment in which the serial output port SO functions (see the broken line in FIG. 9(a)), the operation control register REG of the CPU circuit 51 contains the start address of the lamp/motor drive table. (the leading value of the transfer source address), the address of the input register of the serial output port SO (fixed value of the transfer destination address), the data transfer unit (8 bits), and the number of transfers are specified. Then, the DMAC circuit 60 receives an operation start instruction from a predetermined operation control register REG, and DMA transfers the drive data to a predetermined transfer destination address while updating the transfer source address. When all DMA transfers are completed, a DMAC interrupt (operation end interrupt) is generated.

This point is almost the same in the embodiments (FIGS. 23 and 27(c)) in which the DMAC circuit 60 issues the display list DL. That is, the production control CPU 63 stores the start address of the transfer source (DL buffer BUF), the address of the transfer destination (transfer port TR_PORT), the DMA transfer mode, and the data transfer unit in a predetermined operation control register REG of the CPU circuit 51. Then, the number of transfers and other conditions will be set. Note that these points will be further described later with respect to FIG.

By the way, in general, DMA transfer modes include a cycle steal transfer mode in which the DMA operation does not occupy the memory bus, such as releasing the bus control right in the middle of a DMA transfer unit operation (R operation/W operation), and a cycle steal transfer mode in which the DMA operation does not occupy the memory bus. In burst transfer (pipeline transfer) mode, in which bus control is not released until the specified number of transfers is completed, such as continuous operation or W operation, and while a DMA transfer request (demand) received from another device is active. A demand transfer mode in which DMA operation continues may be considered. However, the DMAC circuit 60 of this embodiment functions in a cycle-steal transfer mode in which a memory release period of at least one cycle is provided between read access activation (R operation) and write access activation (W operation) during DMA transfer. By doing so, the operation of the production control CPU 63 is prevented from being hindered.

FIG. 10 is a diagram illustrating cycle steal transfer operation (a1) and pipeline transfer (a2). As shown in FIG. 10(a1), the DMAC circuit 60 functioning in the cycle-steal transfer mode operates with at least one cycle between read access activation (R) and write access activation (W) of one data transfer. In this vacant cycle, the production control CPU 63 can use the bus. As is clear from the comparison between FIGS. 10(a1) and 10(a2), in pipeline transfer, the bus is not released to the CPU until one cycle (one operand transfer) is completed, whereas cycle stealth In the transfer mode, the bus is released to the CPU every time a read access is made, so there is no significant delay in the operation of the CPU.

For example, in an embodiment in which the DMAC circuit 60 is used when issuing the display list DL to the VDP circuit 52, the data transfer unit of one cycle (one operand) is set to 32 x 2 bits, and the display list DL is stored. While appropriately increasing the source address of the built-in RAM 59 (+8 for each operand transfer), the DMA transfer operation is performed for the transfer port register TR_PORT (see FIG. 12) of the data transfer circuit 72 specified by the fixed address. is running.

As described later, in the embodiment, by adding a required number of NOP (no operation) commands to the display list DL, the total data size is set to a fixed value (for example, 4 x 64 = 256 bytes, or an integer thereof). By repeating one operand transfer of 32 bits x 2 times 32 times (or an integral multiple thereof), issuing the display list DL is completed. Note that even if the drawing circuit 76 executes the NOP command, virtually no change occurs.

Furthermore, when classifying the operation modes in terms of DMA transfer conditions, there are generally single operand transfers (see Figure 10 (b1)), continuous operand transfers (see Figure 10 (b2)), and non-stop transfers (see Figure 10 (b3)). ).

Here, single-operand transfer means, as shown in FIG. 10 (b1), that one operand is transferred repeatedly every time a DMA transfer request is given, and when the byte count that counts the number of transferred bytes reaches zero. This means the operating mode in which a DMA interrupt request occurs. Next, continuous operand transfer means an operation mode in which DMA transfer is repeated with one DMA request until the byte count becomes zero, as shown in FIG. 10(b2).

In these continuous operand transfers (b2) and single operand transfers (b1), channel arbitration is performed every time one operand transfer is completed, and the current channel (channel arbitration operation mode). Therefore, in this embodiment, a single operand transfer method is adopted for issuance of the display list DL to the VDP circuit and DMA transfer of lamp drive data and motor drive data. During parallel operation, for example, the optimal channel DMACi is used to arbitrate the priority channels of motor data>display list DL>lamp data.

On the other hand, nonstop transfer is an operation mode in which channel arbitration is not performed, and as shown in FIG. 10 (b3), DMA transfer is continuously repeated until the byte count reaches zero with one DMA request. It will be done. In this embodiment, in the memory section initialization process (SP8 in FIG. 15) when the power is turned on, programs and data are transferred by DMA using non-stop transfer.

Since the CPU circuit 51 has been explained above, the VDP circuit 52 will be explained next. An external DRAM (Dynamic Random Access Memory) 54 having a storage capacity of , a main display device DS1, and a sub display device DS2 are connected. Note that the DRAM 54 is preferably configured with DDR3 (Double-Data-Rate3 SDRAM).

Although not particularly limited, in this embodiment, the CGROM 55 is composed of a flash SSD (solid state drive) composed of a NAND flash memory with a storage capacity of about 62 Gbit, and the compressed data required by serial transmission is is configured to obtain. Therefore, the problem of skew (difference in transmission speed between bit data) that inevitably occurs in parallel transmission is eliminated, and extremely high-speed transmission operation becomes possible. Although not particularly limited, in this embodiment, the CGROM 55 is accessed at high speed using the HSS (High Speed Serial) method based on SerialATA.

Note that regardless of whether or not an HSS method is adopted that is compliant with SerialATA, NAND flash memory is mechanically more stable than hard disks and can be accessed at high speed; however, since it is a sequential access memory, Compared to DRAM and SRAM (Static Random Access Memory), it has a problem in random access. Therefore, in this embodiment, by executing a preload operation in which a group of compressed data (CG data) is read out to the DRAM 54 prior to the drawing operation, smooth random access to the CG data during the drawing operation is realized. ing. Incidentally, the access speed becomes slower in the order of built-in VRAM>external DRAM>CGROM.

Specifically, the VDP circuit 52 includes a control register group 70 in which various operating parameters that define the operation of the VDP (Video Display Processor) can be set by the production control CPU 63, and a control register group 70 that controls the image data to be displayed on the display devices DS1 and DS2. A built-in VRAM (video RAM) 71 of approximately 48 Mbytes used during generation, a data transfer circuit 72 that executes data transmission and reception between each part inside the chip and data transmission and reception with the outside of the chip, and a source and destination of the built-in VRAM 71. An index table IDXTBL that can specify address information, a preloader 73 that can execute a preload operation that performs READ access to the CGROM 55 prior to a drawing operation, and a graphics decoder that decodes (decodes and expands/expands) compressed data read from the CGROM 55. (GDEC) 75, a drawing circuit 76 that appropriately combines decoded (expanded) still image data and moving image data to generate one frame worth of image data for each of the display devices DS1 and DS2, and an operation of the drawing circuit 76. As a part, there is a geometry engine 77 that generates a three-dimensional image by appropriate coordinate transformation, and three systems that can read image data of frame buffers FBa and FBb generated by the drawing circuit 76 and execute appropriate image processing in parallel. (A/B/C) display circuits 74A to 74C, an output selection section 79 that appropriately selects and outputs the outputs of the three systems (A/B/C) display circuits 74, and an image output by the output selection section 79. An LVDS section 80 that converts data into an LVDS signal, an SMC section 78 capable of transmitting and receiving serial data, a CPUIF section 81 that relays data transmission and reception with the CPUIF circuit 56, and a CG bus IF section 82 that relays data reception from the CGROM 55. , a DRAMIF section 83 that relays data transmission and reception with the external DRAM 54, and a VRAMIF section 84 that relays data transmission and reception with the built-in VRAM 71 (see FIG. 7(a)). Note that an audio circuit SND is also built-in.

FIG. 7B shows the relationship between the CPUIF section 81, CG bus IF section 82, DRAMIF section 83, and VRAMIF section 84, and the control register group 70, CGROM 55, DRAM 54, and built-in VRAM 71. As shown in the figure, the CG data acquired from the CGROM 55 is transferred to the preload area of the external DRAM 54 as, for example, preload data via the data transfer circuit 72 and the DRAMIF section 83.

However, the preload operation described above is not an essential operation, and the data transfer destination is not limited to the external DRAM 54, but may be the built-in VRAM 71. Therefore, for example, in an embodiment in which a preload operation is not performed, CG data is transferred to the built-in VRAM 71 via the data transfer circuit 72 and the VRAMIF section 84 (FIG. 7(b)).

By the way, in this embodiment, the built-in VRAM 71 stores the expansion area of the compressed data read from the CGROM 55 and image data that specifies each ARGB information (32 bits = 8 x 4) of W x H display pixels of the display device. A frame buffer area for storing depth information of each display pixel, a Z buffer area for storing depth information of each display pixel, etc. are required. Note that in the ARGB information, A means 8-bit α plane data, and RGB means 8-bit data of three primary colors.

Here, each of the above-mentioned areas of the built-in VRAM 71 is accessed indirectly based on various instruction commands (such as the above-mentioned textures and SPRITE) written in the display list DL by the production control CPU 63, but the READ/WRITE access In this case, it is troublesome to specify the destination address and source address of the built-in VRAM 71 one by one. Therefore, in this embodiment, in the initial processing after resetting the CPU, a one-dimensional or two-dimensional logical address space (hereinafter referred to as index space) required for drawing operation is secured, and an index number is assigned to each index space. This allows access based on index numbers.

Specifically, after the CPU is reset, the built-in VRAM 71 is roughly divided into three types of memory areas, and a required number of index spaces are secured in each memory area. Then, by constructing an index table IDXTBL (see FIG. 11(a)) that stores index spaces and index numbers in a linked manner, subsequent operations based on the index numbers are realized.

This index space must be (1) added after initial processing, or (2) released. Therefore, when the addition/release production control CPU 63 operates, there is a flag that can determine whether or not the timing is such that the addition/release processing is possible, and whether or not the addition/release processing has actually been completed. Area FG is provided in index table IDXTBL. The built-in VRAM 71 is roughly divided into three types of memory areas: two AAC areas (a1, a2), a page area (b), and an arbitrary area (c), which will be explained below. The index table IDXTBL is divided into three sections corresponding to (a1,a2)(b)(c) (FIG. 11(a)). As shown in the figure, in this embodiment, the first AAC area (a1) and the second AAC area (a2) are secured as the AAC area (a), but this is not particularly limited, and only one of them can be used. But it's okay. In the following description, the first and second AAC areas (a1, a2) may be collectively referred to as AAC area (a).

In the case of this embodiment, the built-in VRAM 71 has (a) an index space and an AAC area to which index numbers are automatically assigned by internal processing and has a memory cache function, and (b) a two-dimensional space of, for example, 4096 bits x 128 lines. As a unit space, it is configured so that it can be divided into a page area where index space can be secured within an integral multiple of the page area, and (c) an arbitrary area where the start address (space start address) STx and horizontal size Hx can be arbitrarily set. (See Figure 11(b)). However, in order to smooth the internal operation of the VDP circuit 52, the space start address STx of the index space arbitrarily set in the arbitrary area (c) has its lower 11 bits set to 0, and the predetermined bits (2048 bits = 256 bytes). It needs to be a unit.

After the CPU is reset, the maximum value of the address space required for each and the area start address (lower 11 bits = 0) are defined, and the AAC area (a1), the second AAC area (a2), and the page area ( b) is secured, and the remaining memory area becomes the arbitrary area (c). In order to smooth the internal operation of the VDP circuit 52, the maximum value of the address space of the AAC area is specified in units of 2048 bits, and the maximum value of the address space of the page area is an integral multiple of the above-mentioned unit space of 4096 bits x 128 lines. It is said that

Next, the required number of index spaces are set in each area (a1, a2), (b), and (c) thus secured. Note that when using the arbitrary area (c), in order to smooth the internal operation of the VDP circuit 52, the horizontal size Hx of the index space that handles two-dimensional data can be arbitrarily set as a multiple of 256 bits; Its vertical size is a fixed value (for example, 2048 lines).

In any case, index spaces and index numbers are automatically assigned to the first and second AAC areas (a1, a2) by the VDP circuit 52, so for example, by using the SETINDEX command, which is a texture setting command, If you specify the decoding destination as the AAC area (a), in the TXLOAD (texture load) command that reads CG data from the CGROM55, you only need to specify the source address of the CGROM55 and the horizontal and vertical size after expansion (decoding). It turns out. Therefore, in this embodiment, still images (textures) such as characters that appear temporarily during preview presentations and I-stream moving images are decoded in the AAC area (a).

This AAC area (a) is all provided with a memory cache function, so for example, if the same texture from the CGROM 55 is read out to the AAC area (a) multiple times, from the second time onwards, The decoded data cached in the AAC area (a) can be used, and redundant READ access and decode processing can be suppressed. However, if the AAC area (a) is used up, old data will be automatically destroyed, so in this embodiment, when using the AAC area (a), the first AAC area (a1) is used as a general rule. Only a specific texture to be used repeatedly is acquired in the second AAC area (a2).

Examples of textures that are repeatedly used include, for example, characters that repeatedly appear during predetermined preview performances, background images when a background screen is constructed from still images, and the like. In such a case, use the SETINDEX texture setting command to set the decoding destination to the second AAC area (a2), and use the TXLOAD command to decode the textures such as characters and background images to the second AAC area (a2). After that, the decoding results are protected by not using the second AAC area (a2).

Then, if you use the SETINDEX command to specify the decoding destination as the second AAC area (a2) and then execute the same TXLOAD command that re-acquires the acquired textures, the acquired textures will hit the cache. , the time required for READ access to the CGROM 55 and decoding processing can be eliminated. As will be described later, such a cache hit function is also exhibited by preload data that is read ahead into the preload area, but the preload data that cache hits in the preload area is compressed data before decoding, whereas AAC It is significant that the cache hit in the area is the expanded data after decoding.

By the way, texture is a concept that generally refers to the texture and feel of the surface of an object, but in this specification, it refers to sprite image data that makes up a still image, image data that makes up one frame of a video, and the like. , is used as a concept that includes not only image data pasted onto drawing primitives such as triangles and squares, but also image data after decoding. When copying image data within the built-in VRAM 71 (hereinafter referred to as moving for convenience), set the source image data as a texture using the SETINDEX command, which is a texture setting command, and then use the SPRITE command. will be executed.

Note that by executing the SPRITE command, the source image data of the movement source is formally drawn in the virtual drawing space shown in FIG. 11(c), but the drawing in the virtual drawing space that is actually drawn on the display device is If you set the correspondence between the area and the index space that serves as the frame buffer in advance using environment setting commands (SETDAVR, SETDAVF) or texture setting commands (SETINDEX), you can, for example, use the SPRITE command to access the virtual drawing space. By drawing, the source image data of the movement source is drawn in a predetermined index space (frame buffer) (see FIG. 11(c)).

In any case, in this embodiment, the built-in VRAM 71 is roughly divided into an AAC area (a1, a2), a page area (b), and an arbitrary area (c), and an appropriate number of index spaces is secured for each area. Each index space is identified by an independent index number for each area (a), (b), and (c). The index number is, for example, 1 byte long, and is set in the range of 0 to 255 for the page area (b) (excluding the AAC area (a) that is automatically assigned by the internal circuit) and the arbitrary area (c). The control CPU 63 can freely assign index numbers.

Therefore, in this embodiment, as shown in FIG. 11(a), a pair of frame buffers FBa are secured in an arbitrary area (c) for the display device DS1, and index numbers 255, 255, 254 is given. That is, as the frame buffer FBa for the main display device DS1, an index space 255 and an index space 254 are secured, which are switched and used in a toggle manner. Although not particularly limited, the index spaces 255 and 254 have a horizontal size of 1280, corresponding to the number of pixels in the horizontal direction of the display device DS1. Note that since each pixel is specified by 32 bits of ARGB information, the horizontal size 1280 means 32×1280=40960 bits (a multiple of 256 bits).

Further, another pair of frame buffers FBb are secured in the arbitrary area (c) for the display device DS2, and index numbers 252 and 251 are given to both of the double buffer structures. That is, the index space 252 and the index space 251 are secured as the frame buffer FBb for the sub display device DS2. The index spaces 252 and 251 have a horizontal size of 480, corresponding to the number of pixels in the horizontal direction of the display device DS2. In this case as well, each pixel is specified by 32 bits of ARGB information, so the horizontal size 480 means 32×480=15360 bits (a multiple of 256 bits).

Note that frame buffers FBa and FBb are secured in the arbitrary area (c) because they can be set to any horizontal size as a multiple of 32 bytes (=256 bits=8 pixels). This is because, as described above, if the number of horizontal pixels is made equal to the number of horizontal pixels of the display devices DS1 and DS2, the secured area will not be wasted. On the other hand, the page area (b) can only be set in a horizontal/vertical size that is an integral multiple of the unit space of 128 pixels x 128 lines.

However, the two-dimensional index space secured in the arbitrary area (c) has a fixed vertical size (for example, 2048 lines). Therefore, in the frame buffer FBa, only an area of horizontal size 1280×vertical size 1024 becomes a valid data area for main display device DS1. This point is the same for the sub-display device DS2, and in the frame buffer FBb, only an area of horizontal size 480×vertical size 800 is an effective data area for the sub-display device DS2 (FIG. 11(c), FIG. 20 (see (e)).

The above points will be discussed further later, but in any case, the double buffers (255/254, 252/251) of the frame buffers FBa and FBb are used alternately as a drawing area for the drawing circuit 76, and The double buffers (255/254, 252/251) are used alternately as display areas for display circuits 74A and 74B. In this embodiment, a missing number (253) occurs because the Z buffer for storing depth information of display pixels is not used. However, if the Z buffer is used, index numbers 253 and 250 in arbitrary area (c) are used. Index spaces 253 and 250 serve as Z buffers for display device DS1 and display device DS2.

Furthermore, in this embodiment, when an additional index space (memory area) is secured in the arbitrary area (c) where frame buffers FBa and FBb are secured, an index number starting from 0 is assigned. . Although not limited in any way, in this embodiment, a work area for a preview effect in which a effect image composed of characters and other still images appears on a part of the display screen in an appropriate rotational posture as necessary. Index space (0) is secured in arbitrary area (c).

However, the use of the work area is not essential, and an index space as a work area may be secured in the page area (b) instead of the arbitrary area (c). By using the page area (b), it is possible to secure an index space that is a multiple of the square unit space of horizontal size 128 (=4096 bits) x vertical size 128, which is suitable for handling small-sized performance images.

By the way, in this embodiment, the background image is also composed of moving images, and the image presentation is realized almost only by moving images. In particular, during variable performance, a large number (usually 10 or more) of moving images are being drawn at the same time. All of these videos are stored in the CGROM 55 in a compressed state as a series of video frames, but there are two types of videos: I-stream video consisting only of I frames, and IP stream video consisting of I-frames and P-frames. It is divided into Here, the I frame (Intra coded frame) means a frame in which an input image is compressed as it is, independent of other screens. On the other hand, a P frame (Predictive coded frame) means a frame for which forward predictive coding is performed, and an I frame or a P frame located in the temporal past is required.

Therefore, in this embodiment, the IP stream video is expanded to the page area (b) instead of the AAC area (a) where there is a concern that old data may be destroyed. That is, a large number of index spaces (IDX ₀ to IDX _N ) are secured in the page area (b) where index spaces with dimensions that are multiples of horizontal size 128 x vertical size 128 can be secured, and a series of video frames is The same index space IDXi corresponding to MVi is always used for decoding. That is, the moving image MV1 is expanded into the index space IDX1, the moving image MV2 is expanded into the index space IDX2, and the moving image MVi is expanded into the index space IDXi in the same manner.

To explain the video MVi more specifically, after specifying in advance with the SETINDEX command that "the decoding destination of the IP stream video MVi is the index space (i) of the index number i in the page area (b)", A TXLOAD command is executed to acquire one frame of the IP stream video MVi.

Then, one video frame (any one of a series of video frames) on the CGROM 55 specified by the TXLOAD command is first acquired into the AAC area (a), and then processed by the automatically activated GDEC (graphics decoder) 75. , one frame of the acquired video is decoded and developed in the index space (i) of the page area (b).

On the other hand, in this embodiment, I-stream videos are treated the same as still images, and the SETINDEX command specifies that "the decoding destination of the I-stream video MVj is the first AAC area (a1)". Execute the TXLOAD command. As a result, the video frame is acquired in the first AAC area (a1), and then the automatically activated GDEC 75 develops decoded data in the first ACC area (a1). As explained above, the index space for AAC area (a) is automatically generated, so there is no need to specify an index number. Note that the expansion volume required for the index space, that is, the horizontal size and vertical size of the decoded texture (video frame), is determined by the TXLOAD regardless of whether the expansion destination is the AAC area (a) or the page area (b). Specified by command.

By the way, the IP stream video MVi and the I stream video MVj are generally composed of N video frames (I frames and P frames). Therefore, the TXLOAD command specifies, for example, the Source address of the CGROM 55 in which the k-th (1≦k≦N) video frame is stored, and the horizontal and vertical sizes after expansion. Although not limited in any way, in an embodiment in which still images are hardly used, most of the 48 Mbytes of the address space of the built-in VRAM 71 (approximately 30 Mbytes) is allocated to the page area (b). In an example in which still images are hardly used, only the first AAC area (a1) is secured as the AAC area, the second AAC area (a2) is not secured, and the cache hit function of the AAC area described above is It is not used either.

Note that in order to speed up the decoding process of compressed video data, it is also possible to provide a dedicated GDEC (graphics decoder) circuit. If a dedicated GDEC circuit is built into the VDP circuit 52, in the decoding process of compressed video data composed of N compressed video frames, it is sufficient to instruct the GDEC circuit to specify the start address of the compressed video data. There is no need to specify the start address for each of the N compressed video frames.

However, if a plurality of such dedicated GDEC circuits are built in for each compression algorithm, the internal configuration of the VDP circuit 52 becomes even more complicated. Therefore, in this embodiment, software GDEC is used to realize decoding processing of data such as IP stream moving images, I stream moving images, still images, and other α values by software processing corresponding to each compression algorithm. Note that the processing time difference between hardware processing and software processing does not matter much, and the processing time that becomes a problem is exclusively the access (READ) time from the CGROM 55.

Next, returning to FIG. 7A and continuing the explanation, the data transfer circuit 72 transfers the resources (storage medium) inside the VDP circuit and the external storage medium between them as a transfer source port or a transfer destination port. This is a circuit that executes a data transfer operation in a DMA (Direct Memory Access) manner. FIG. 12 is a block diagram showing the internal configuration of this data transfer circuit 72 together with related circuit configurations.

As shown in FIG. 12, the data transfer circuit 72 is configured to transmit and receive data to and from the CGROM 55, DRAM 54, and built-in VRAM 71 via an integrated connection bus ICM having a router function. Note that the CGROM 55 and DRAM 54 are accessed via the CG bus IF section 82 and the DMA IF section 83.

On the other hand, the CPU circuit 51 issues the display list DL to the drawing circuit 76 and the preloader 73 via the transfer port register TR_PORT built in the data transfer circuit 72. Note that the CPU circuit 51 and the data transfer circuit 72 are bidirectionally connected, but when the display list DL is issued, the transfer port register TR_PORT is used as a data write port that accepts one unit of data that constitutes the display list DL. Function. Note that the writing unit (one unit data length) of the transfer port register TR_PORT is 32 bits, corresponding to the FIFO structure of the CPU bus control unit 72d.

As shown in the figure, the production control CPU 63 can write access to the transfer port register TR_PORT via the CPUIF section 81, while when utilizing the DMAC circuit 60, the DMAC circuit 60 directly accesses the transfer port register TR_PORT. WRITE access. Then, a series of instruction commands written to the transfer port register TR_PORT (in other words, instruction command strings that make up the display list DL) are transferred in 32-bit units to a CPU bus that has a built-in FIFO buffer with a FIFO structure (32 bits x 130 stages). The control unit 72d is configured to automatically accumulate the information.

Further, this data transfer circuit 72 executes data transmission and reception operations on the transmission path of 3 channels ChA to ChC, and has a ChA control circuit 72a (N=130 A ChB control circuit 72b (N=1026 stages), and a ChC control circuit 72c (N=130 stages).

Then, the instruction command string (display list DL) accumulated in the CPU bus control unit 72d is sent to the drawing circuit 76 or It is transferred to the preloader 73. As shown by the arrow, the display list DL is transferred from the CPU bus control unit 72d to the drawing circuit 76 via the FIFO buffer of the ChB control circuit 72b, and transferred to the preloader 73 via the FIFO buffer of the ChC control circuit 72c. It is configured to be

In this embodiment, the ChB control circuit 72b and the ChC control circuit 72b are specialized for the transfer operation of the display list DL, and the data accumulated in the FIFO buffer of the CPU bus control section 72d is transferred to the ChB control circuit 72b. 72b or the FIFO buffer of the ChC control circuit 72c, they are transferred to the drawing circuit 76 or the display list analyzer of the preloader 73 as part of the display list DL, respectively.

The drawing circuit 76 then starts a drawing operation based on the transferred display list DL. On the other hand, the preloader 73 executes a necessary preload operation based on the transferred display list DL. Through the preload operation, the CG data in the CGROM 55 is read in advance into the preload area secured in the DRAM 54, and a display list DL (hereinafter referred to as rewrite list DL') in which the source address of the texture has been changed is secured in the DRAM 54 in relation to the TXLOAD command, etc. The data is saved in the DL buffer area BUF'.

On the other hand, the ChA control circuit 72a and the connection bus access arbitration circuit 72e function for data transfer between storage media such as the CGROM 55, the DRAM 54, and the built-in VRAM 71. Further, when accessing the built-in VRAM 71 where address information of the index table IDXTBL is required, the IDXTBL access arbitration circuit 72f functions. To be more specific, the ChA control circuit 72a, for example, (a) transfers the compressed data of the CGROM 55 to the built-in VRAM 71, or (b) preloads (read ahead) the compressed data of the CGROM 55 and transfers it to the external DRAM 54. It functions when (c) pre-read data in the preload area is transferred to the built-in VRAM 71.

Here, the ChA control circuit 72a is configured to be able to operate in parallel with the ChB control circuit 72b and the ChC control circuit 72c, and the operations (a) to (c) described above are the display list DL issuing operation ( ST8 in FIG. 20, PT11 in FIG. 25) and the transfer operation of the rewrite list DL' (PT10 in FIG. 25) can be executed in parallel. Furthermore, the ChB control circuit 72b and the ChC control circuit 72c can also be executed simultaneously; for example, the process of step PT10 in FIG. 25 in which the ChB control circuit 72b functions and the process in step PT11 in which the ChC control circuit 72c functions are performed in parallel. It is possible to do this by However, since there is only one transfer port register TR_PORT, when either one (72b/72c) is using transfer port register TR_PORT, the other (72c/72b) cannot access transfer port register TR_PORT. I can't.

Note that during the operation of the ChA control circuit 72a, the connection bus access arbitration circuit 72e arbitrates data transmission with each storage element (CGROM 55, DRAM 54) via the integrated connection bus ICM. On the other hand, the IDXTBL access arbitration circuit 72f arbitrates data communication with the built-in VRAM 71 by controlling the ChA control circuit 72a based on the index table IDXTBL. In the case of the embodiment in which the preloader 73 functions, the rewrite list DL' stored in the DL buffer area BUF' of the DRAM 54 is transferred to the drawing circuit 76 via the connection bus access arbitration circuit 72e and the ChB control circuit 72b. (See FIG. 26(b)).

As described above, the data transfer circuit 72 of this embodiment is configured to transfer data between a data transfer source arbitrarily selected from various storage resources (Resources) and a data transfer destination arbitrarily selected from various storage resources (Resources). This enables high-speed data transfer between the two. As confirmed from FIG. 12, the storage resources on which the data transfer circuit 72 functions include not only the built-in VRAM 71 but also external devices via the CPU IF section 56, CG bus IF section 82, and DRAM IF section 83.

Then, like the amount of data to be acquired at one time from the CGROM 55 (memory sequential READ), the amount of data transferred to and from an external device where the ChA control circuit 72a functions is controlled by the display system where the ChB control circuit 72b or the ChC control circuit 72c functions. This is huge compared to the list DL, and the amount of data transferred is greatly different from each other.

It may be possible to configure the unit data amount and total transfer data amount for these various data transfers to be finely configurable, but this would complicate the control operations inside the VDP and prevent smooth transfer operations. inhibited. Therefore, in this embodiment, the minimum data amount Dmin for data transfer is uniquely defined, and the total transfer data amount is limited to be an integral multiple of the minimum data amount DTmin, thereby achieving a high-speed and smooth data transfer operation. It has been realized. Although not particularly limited, in the data transfer circuit 72 of the embodiment, the minimum data amount Dmin (unit data amount) is 256 bytes, and the total transfer data amount is limited to an integral multiple of this.

Therefore, the instruction command string of the display list DL stored in the FIFO buffer of the CPU bus control unit 72d every 32 bits is transferred to the ChB control circuit 72b or the ChC control circuit 72b at the timing when the total amount reaches the minimum data amount Dmin. will be stored in each FIFO buffer.

The display list DL is composed of a series of instruction commands. In this embodiment, the command length of the display list DL is an integer N times 32 bits, corresponding to the write unit (32 bits) of the transfer port register TR_PORT. It consists of only (N>0) instruction commands. Therefore, the drawing circuit 76 and preloader 73 that receive the instruction command of the display list DL via the data transfer circuit 72 can quickly and smoothly start the command analysis process (DL analyze). Note that the command length of 32 bits, which is an integer N times, does not necessarily mean that all of the bits are significant bits, but also includes non-significant bits (don't care bits).

Next, the preloader 73 will be explained. As outlined above, the preloader 73 interprets the display list DL transferred from the data transfer circuit 72 (ChC control circuit 72b), and loads the CG data on the CGROM 55 referred to by the TXLOAD command into the DRAM 54 in advance. This is the circuit that transfers the data to the preload area. Furthermore, regarding this TXLOAD command, the preloader 73 stores in the DL buffer BUF' of the DRAM 54 a rewrite list DL' in which the reference destination of the CG data is rewritten to the address after transfer. Note that the DL buffer BUF' and the preload area are secured in advance during initial processing after the CPU is reset (ST3 in FIG. 20).

Then, at the start of the drawing operation of the drawing circuit 76, the rewrite list DL' is sent to the display list analyzer (DL analyzer) of the drawing circuit 76 via the connection bus access arbitration circuit 72e of the data transfer circuit 72 and the ChB control circuit 72b. ) will be forwarded to. Then, the drawing circuit 76 executes a drawing operation based on the rewriting list DL'. Therefore, based on the TXLOAD command or the like, CG data that should originally be acquired from the CGROM 55 is acquired from the preload area of the DRAM 54 as preload data that has been read in advance into the preload area. In this case, the preload data can be used repeatedly unless overwritten and erased, and the preload data that hits the cache in the preload area is repeatedly reused.

In this embodiment, since the preload area is set in the external DRAM 54 having sufficient storage capacity, the cache hit function described above functions effectively. Furthermore, since the storage capacity of the external DRAM 54 is large, multiple preloading is possible, for example, in which multiple frames of CG data are preloaded at once. That is, regarding the operation period of the preloader 73, the operation period of a series of preload operations including the pre-read operation of CG data is appropriately set within the range of an integral multiple of the operation period δ during intermittent operation of the VDP circuit 52. multiple preload is realized.

However, in the following description, for convenience, an embodiment without multiple preloading will be described, so the preloader 73 of the embodiment completes the preloading operation for one frame during one operation cycle (δ). As will be described later with reference to FIG. 20, in this embodiment, the operating cycle δ of the VDP circuit 52 during intermittent operation is 1/30 seconds, which is twice the cycle of the vertical synchronizing signal of the display device DS1.

Next, the drawing circuit 76 sequentially analyzes the instruction command strings of the display list DL and rewriting list DL' transferred via the data transfer circuit 72, and cooperates with the graphics decoder 75, geometry engine 77, etc. This is a circuit that draws an image for one frame of each display device DS1, DS2 in a frame buffer formed in the VRAM 71.

As described above, in the embodiment in which the preloader 73 functions, the reference destination of the CG data in the rewrite list DL' is not the CGROM 55 but the preload area set in the DRAM 54. Therefore, sequential access to CG data generated during execution of drawing by the drawing circuit 76 can be quickly executed, and even high-resolution moving images with rapid movement can be drawn without problems. That is, according to this embodiment, it is possible to perform complex and sophisticated image rendering while utilizing an inexpensive SATA module as the CGROM 55.

Incidentally, regardless of whether or not the preloader 73 is activated, even if data garbled occurs during transfer of the display list DL or rewrite list DL', the drawing circuit 76 will not be able to detect this. Furthermore, the drawing circuit 76 may freeze due to the influence of noise, and READ/WRITE access to the built-in VRAM 71 may stop abnormally. Therefore, in this embodiment, when the drawing circuit 76 detects an unreasonable instruction command (a bit arrangement that cannot be analyzed) or when there is no READ/WRITE access to the built-in VRAM 71 for a certain period of time, a drawing abnormality interrupt is generated. (drawing abnormal interrupts are enabled). Note that this point will be discussed later with respect to FIG. 20(d).

Next, as explained with reference to FIG. 11, the frame buffer FB secured in the arbitrary area (c) of the VRAM 71 is a double buffer divided into a drawing area and a reading area, and the usage of the two areas is alternately switched. and use it. Further, in this embodiment, since two display devices DS1 and DS2 are connected, two frame buffers FBa/FBb are secured as shown in FIG. 11. Therefore, the drawing circuit 76 draws one frame of image data in the drawing area (writing area) of the frame buffer FBa for the display device DS1, and also draws the image data for one frame in the drawing area (writing area) of the frame buffer FBa for the display device DS2. Then, one frame of image data will be drawn. Note that when image data is written in the drawing area, the display circuit 74 reads out the image data in the other reading area (display area) and outputs it to each of the display devices DS1 and DS2.

The display circuit 74 is a circuit that reads image data from the frame buffers FBa and FBb, performs final image processing, and outputs the data (see FIG. 13(a)). The final image processing includes, for example, a scaler scaling process that enlarges/reduces the image, a subtle color correction process, and a dithering process that minimizes the quantization error of the entire image. A digital RGB signal (24 bits in total) that has undergone these image processes is usually output together with a horizontal synchronizing signal HS, a vertical synchronizing signal VS, and the like.

As shown in FIG. 13(a), in this embodiment, three systems of display circuits A/B/C that execute the above operations in parallel are provided, and each display circuit 74A to 74C corresponds to The image data of the frame buffers FBa/FBb/FBc are read out and the final image processing described above is executed. However, in this embodiment, since there are two display devices, the frame buffer FBc is not secured and the display circuit 74C does not function.

Here, when checking the specifications of the main display device DS1, the main display device DS1 connects odd pixels (ODD) and even pixels (EVEN) adjacent in the left and right direction through separate LVDS (Low Voltage Differential Signaling) transmission paths. It is necessary to receive it at the receiver RV (RVa+RVb). In addition, the frequency of the operating clock CK of the main display device DS1 needs to be approximately 40 to 70 MHz (typical value 54 MHz), and horizontal/vertical It is necessary to set the waiting time WTh/WTv in the direction. Furthermore, at the timing of outputting image data (ODD/EVEN signal) to the main display device DS1, it is necessary to output a data valid signal ENAB at an active level.

Therefore, the display circuit 74A needs to output a signal that satisfies all the specifications described above. FIGS. 14(a) to 14(e) illustrate various signals output from the display circuit 74A. First, it is necessary to determine the frequency of the dot clock (LVDS clock) DCK. In this embodiment, since the main display device DS1 is operated with the operating clock CK of a typical value of 54 MHz, the frequency of the (VDP The designed dot clock DCK (in the circuit 52) is set to 108 MHz (=54×2).

This is because in the display panel LCD (see Figure 14(f)), which has 1280 dots horizontally and 1024 lines vertically, two pixels adjacent to each other on the left and right are processed at once in synchronization with the 54MHz operating clock CK. This is because it is equivalent to operating with a 108 MHz dot clock DCK.

Various operating parameters that define the operation of the display circuit 74A are defined based on the dot clock DCK having a frequency of 108 MHz. First, it is necessary to set the horizontal/vertical standby time WTh/WTv so that (WTh+640)×(WTv+1024)/54MHz≒1/60 seconds, but the operating parameters WTh, WTv for the display circuit 74A are , (WTh+1280)×(WTv+1024)/108MHz≈1/60 seconds.

Furthermore, regarding the horizontal/vertical standby time WTh/WTv, it is also necessary to consider the allowable range according to the specifications of the display device DS1. Therefore, in this embodiment, the horizontal standby time WTh is counted using the 108 MHz dot clock DCK and is set to 382 clocks, and the vertical standby time WTv is set to 59 lines. Therefore, the time required to update one frame of image is (382+1280)×(59+1024)/108 MHz=16.666 mS, and the frame rate FR is 1/60 second.

This relationship defines the update period FR [seconds] of the display device DS1, and using the frequency F _dot of the dot clock DCK, the number of horizontal synchronization cycles THc, and the number of vertical synchronization lines TVl, which will be described later, FR=THc×TVl/F _dot . Here, if the update cycle FR is too long, abnormalities such as flickering may occur.On the other hand, if the update cycle FR is too short, the display device cannot perform normal update processing, so 0.95/60<FR[ seconds]<1.05/60.

Corresponding to this setting, the data valid signal ENAB is at L level during the standby time WTh (=382/108MHz) corresponding to 382 clocks in the image update operation of each line, and then at the active level corresponding to 1280 clocks. The section (=1280/108 MHz) is at the active level (H) (FIG. 14(c)). As shown in FIG. 14(d) and FIG. 14(e), during the active period of the data valid signal ENAB, the image is updated at a predetermined time (11.85 μS = 1280/108 MHz) for 1280 dots per line. Image data is output to complete the operation. That is, 1280 pixel data are output in synchronization with 1280 dot clocks DCK. Note that since a full-color image with a gradation level of 2 ⁸ × 2 ⁸ × 2 ⁸ is displayed on the display device DS1, pixel data of one pixel has a length of 3 × 8 bits.

Incidentally, in this embodiment, the vertical synchronizing signal VS and the horizontal synchronizing signal HS are outputted, although they are not necessary in the main display device DS1. The vertical synchronization signal VS is output within the vertical standby time WTv, and the horizontal synchronization signal HS is output within the horizontal standby time WTh. Note that each operation cycle is shown in FIGS. 14(a) and 14(b) for convenience of understanding. In addition, in FIG. 14(f), circles are shown at the top left and bottom right vertices of the rectangular frame specified by TH×TV (=1083×1662 clocks), indicating “start of display operation” and “start of display operation”. The mark "O" means "V blank start" which defines the operation cycle of the display circuit 74A, which starts every 1/60 seconds. Since the 1083 x 1662 clock that defines the display operation corresponds to 1/60 second, the elapsed time from "start of display operation" to "end of display operation" (operation cycle of display circuit 74A) is 1/60 second. It is. Note that "V blank start" will be described later based on FIG. 20.

Continuing the explanation by returning to FIG. 13, the output selection section 79 of the embodiment divides the output signal of the display circuit 74A into dual links that divide the 108 MHz dot clock DCK by two, and divides the output signal of the display circuit 74A into two links, respectively. , is transmitted to the LVDS unit 80b (see FIG. 13(a) and FIG. 5). Each LVDS section 80a, 80b converts the image data (digital RGB signal of 24 bits in total) into first and second LVDS signals, and sends a pair of signals to which a clock signal (54MHz=108/2) is transmitted. In addition, all five pairs of differential signals LVDS1 and LVDS2 are output to the main display device DS1 via two paths (see FIG. 13(a) and FIG. 4).

As explained above, in the main display device DS1, the ODD signal for one pixel and the EVEN signal for one adjacent pixel are processed at the same timing, so the actual frequency of the operating clock CK is This corresponds to the 108 MHz dot clock DCK output by the circuit 74A.

The display circuit 74A that generates an image to be transmitted to the main display device DS1 has been described above, but the display circuit 74B generates image data to be transmitted to the sub display device DS2. The digital RGB signal output by the display circuit 74B is supplied to the digital RGB section 80c via the output selection section 79, and is transmitted to the sub-display device DS2 together with the vertical synchronization signal VS and the horizontal synchronization signal HS.

Note that, along with the synchronization signals VS and HS, the data valid signal ENAB is also transmitted via the digital RGB section 80c, but each of these signals is transmitted as a continuous signal rather than as a discrete value as in the case of the LVDS transmission line. Of course, this is true (see FIG. 13(a)).

Incidentally, in the case of this embodiment, each display circuit 74A to 74B is provided with underrun counters URCNTa to URCNTc that count underrun abnormalities in which display data is not generated in time for the display timing (FIG. 14). reference). The counter values of the underrun counters URCNTa to URCNTc are configured to be automatically added for each VBLANK when an underrun abnormality occurs.

Next, the SMC unit 78 (Serial Management Controller) is a composite control controller incorporating an LED controller and a Motor controller. Then, it outputs the LED drive signal and motor drive signal in synchronization with the clock signal to the LED/motor driver (driver IC with built-in shift register) mounted on the external board, and also outputs latch pulses at appropriate timing. Configured to enable output.

Regarding the internal circuit of the VDP circuit 52 and its operation, the contents of the operation to be executed by the internal circuit are defined by the operation parameters (setting values) set in the control register group 70 by the production control CPU 63, and the execution of the VDP circuit 52. The state can be specified by reading the operation status value of the control register group 70. The control register group 70 refers to a large number of VDP registers RGij mapped to an address space of about 1 Mbyte (0 to FFFFFH) on the memory map of the production control CPU 63. A WRITE (setting) operation for operation parameters and a READ operation for operation status values are executed (see FIG. 7(b)).

The control register group 70 (VDP register RGij) includes a "system control register" in which initial setting values related to system operations such as interrupt operations are written, and a register that defines the AAC area (a) and page area (b) in the built-in VRAM. , "Index table register" related to constructing or changing the index table IDXTBL, and "Data transfer" in which setting values related to data transfer processing by the data transfer circuit 72 between the production control CPU 63 and the internal circuit of the VDP circuit 52 are written. a "GDEC register" that specifies the execution status of the graphics decoder 75, a "drawing register" in which instruction commands and setting values regarding the drawing circuit 76 are written, and setting values relating to the operation of the preloader 73 are written. A "preloader register", a "display register" into which setting values related to the operation of the display circuit 74 are written, an "LED control register" into which setting values relating to the LED controller (SMC section 78) are written, and a motor controller (SMC section 78). 78), and a "sound control register SRG" into which setting values related to the audio circuit SND are written. However, in this embodiment, the audio circuit SND is not utilized.

In any case, in the following description, one or more registers RGij included in the control register group 70 may be referred to by the above-mentioned individual names or collectively as VDP registers RGij, but in any case, The performance control CPU 63 controls the internal operation of the VDP circuit 52 by writing appropriate setting values into a predetermined VDP register RGij. Specifically, the effect control CPU 63 realizes a predetermined image effect based on a display list DL that is updated at appropriate time intervals and a set value to a predetermined VDP register RGij. In this embodiment, since the performance control CPU 63 is in charge of the lamp performance and motor performance, the VDP register RGij also includes the LED control register and the motor control register.

Next, a unified performance control operation of image performance, audio performance, motor performance, and lamp performance realized by the composite chip 50 incorporating the above-described CPU circuit 51 and VDP circuit 52 will be explained.

In the case of this embodiment, the operation of the composite chip 50 is started by a power-on reset operation (see FIG. 15(a)) due to power-on or abnormal reset, and initial setting processing (SP1 to SP1) by an initial setting program (boot program) Pinit. After SP9), the process is configured to proceed to main control processing (SP10) by the production control program Main and the interrupt processing program (vector handler) Vopt. Regarding the main control processing, the processing contents of the introduction part are described in FIG. 17(a), and the processing contents of the main part are described in FIG. 20(a). Note that the process in step SP27 in FIG. 17 includes the processes in steps ST1 to ST3 in FIG. 20(a).

Based on the above, the power-on reset operation will be explained based on FIG. 15(a). When the system reset signal SYS maintains the L level for a predetermined period (assertion period) such as when the power is turned on, all operation control registers REG and all VDP registers RGij are automatically set to predetermined default values. After that, when the system reset signal SYS changes to H level (negate level), in this embodiment, 32-bit data from the first address of the address space CS0 is first set in the program counter PC of the production control CPU 63, The 32-bit data following this is configured to be set in the stack pointer SP. Note that in FIG. 9 and FIG. 16(c), the top area of the memory that stores the initial values of the program counter PC and stack pointer SP is called a vector table VECT.

As shown in FIG. 15(b), in this vector table VECT, vector numbers for specifying priorities, interrupt factors, etc., and address information are stored in correspondence. The smaller the vector number, the higher the priority. For example, vector number 11 is a non-maskable interrupt (NMI), and the start address of the interrupt processing program to be executed at the time of the NMI interrupt is stored as address information. has been done. Vector number 64 is an internal interrupt (VDP_IRQ0) from the VDP, and the start address of the interrupt processing program to be executed at the time of the VDP_IRQ0 interrupt is stored as address information.

The interrupt priorities are as shown in Figure 17(d), so the columns for vector numbers smaller than vector number 64 contain information about the control command reception interrupt IRQ_CMD, the 20μS timer interrupt, and the 1mS timer interrupt in the interrupt processing program. Each starting address is stored. On the other hand, in the columns of vector numbers greater than vector number 64, the start addresses of interrupt processing programs (IRQ_SND, IRQ_RTC, etc.) having lower priority than VDP_IRQ 1 are stored.

Further, in the vector table VECT, vector number 0 and vector number 1 define setting values that should be automatically set to the program counter and stack pointer of the CPU at the time of power-on reset. As shown in FIG. 15(b), in this embodiment, 4-byte data "***" is set in the program counter PC as an internal operation during power-on reset (reset assertion period), and 4-byte data "***" is set in the program counter PC. ++++" is set in the stack pointer SP. Note that "＊＊＊＊" is the start address value of the initial setting program Pinit (SP1 to SP9 in FIG. 15) that is non-volatilely stored in the address space CS0, and "++++" is the start address value that is reserved in the built-in RAM 59. In addition, it is the address value of the top or end of the stack area that functions in the LIFO (Last-In First-Out) method.

Note that in this embodiment, since the register bank RBi is effectively utilized, the stack area is not consumed during interrupt processing, and a large memory capacity is not required. That is, in this embodiment, the stack area is used exclusively for function processing and subroutine processing.

As a result of the above operations, the production control CPU 63 will then execute the initial setting program Pinit written after the address value "*****". However, the memory READ operation of the address space CS0 is executed based on the default value (initial value) of the operation control register REG that defines the operation of the bus state controller 66 (FIG. 8). The initial value of this operation control register REG is a value that is automatically set during the reset assertion period (the period shown in FIG. 6(d) when the system reset signal SYS maintains the L level), and the address space CS0 is It is set to the slowest READ access operation (default access operation) so that READ access can be performed without problems even when configured with memory devices.

Therefore, in order to change this default access operation to an optimal access operation, an optimal value is first set in a predetermined operation control register REG that defines the operation of the bus state controller 66 (FIG. 8) for the address space CS0 ( SP1). In other words, the bus width and In addition to setting the presence or absence of page access, the chip select signal CS0, READ control signal, WRITE control signal, and other operation timings are optimally set (see FIG. 38).

As a result of the above settings, the processes after step SP2 are executed by optimally reading the program stored in the address space CS0 into the memory. Therefore, next, in order to optimize the READ/WRITE access operation when accessing the VDP register RGij, the production control CPU 63 performs predetermined operation control that defines the operation of the bus state controller 66 (FIG. 8) with respect to the VDP register RGij. An optimum value is set in register REG (SP2).

As explained above, in this embodiment, the VDP register RGij is located in the address space CS7 of the production control CPU 63, so a predetermined value is set in order to optimally set the operation timing of the chip select signal CS7 and other control signals. A predetermined value is written to the operation control register REG.

Subsequently, the register value of a specific VDP register RGij is read, and it is determined whether the value is a predetermined value (device code) (SP3). This is a confirmation judgment that the system clock of the VDP circuit 52 has been stabilized. That is, the VDP circuit 52 operates based on the oscillation output of the oscillator OSC2 supplied to the PLLREF terminal, but this VDP circuit 52 does not normally process commands from the CPU circuit 51 (that is, settings to the VDP register RGij, etc.). This is a determination as to whether or not it can be accepted.

Then, if it is confirmed that the system clock has been stabilized by the device code reading process (SP3), normal operation of the VDP circuit 52 can be expected, so the setting process for the predetermined VDP register RGij is executed (SP4). ~SP6). Specifically, first, the endian setting (big/little) and data bus width when accessing the VDP register RGij from the performance control CPU 63 are set (SP4).

In this embodiment, the most significant bit of the setting value is set to big endian, which is stored in the most significant bit of the VDP register RGij, and the data 32 bus width is set to 32 bits, but these settings If the value is the same as the default value, these setting processes can be omitted (the following processes are the same).

Next, the interrupt significance level (H/L) is set for the internal interrupts (VDP_IRQ0, VDP_IRQ1, VDP_IRQ2, VDP_IRQ3) from the VDP circuit to the CPU circuit, and the clock signal ( A setting is made to make the DDR (DRAM 54) function based on the reference clock (SP4). Note that the reference clock of the oscillator OSC2 is supplied to the PLLREF terminal, as described in connection with FIG. 7(a).

Next, address spaces CS1 to CS6 are defined to realize the memory map shown in FIG. 9 (SP5). As explained above, the address space CS3 is assigned to the internal register of the audio processor 27, the address space CS4 is assigned to the internal register of the RTC 38 and the address space of the SRAM 39, and the address space CS5 is assigned to the external DRAM (DDR). 54, and the address space CS6 is assigned to the work memory 57 of the built-in CPU.

Note that since it is fixedly stipulated that the VDP register RGij is allocated to the address space CS7, there is no need to define the address space CS7. Furthermore, it is fixedly stipulated in advance that the address space CS0 is from address 0x000000000 on the memory map of the CPU circuit 51, and based on this stipulation, whether the address space CS0 is secured in the CGROM 55 or in other memory Whether it is given to a device is determined by the H/L level of the HBTSL terminal.

As described above, in this embodiment, the HBTSL terminal is set to L, indicating that the address space CS0 is defined in addition to the CGROM 55. Since the specific bus width and optimal access operation for the control memory 53 other than the CGROM 55 have already been set in step SP1, the process in step SP5 is not necessary for the address space CS0 as well.

Next, for the address spaces CS1 to CS6 defined in the process of step SP5, a predetermined value is written to a predetermined operation control register REG regarding the bus width and the presence or absence of page access when accessing each address space CSi (SP6 ). Further, in order to optimally set the chip select signal CSi and others, a predetermined value is written into a predetermined operation control register REG (SP6). These processes have the same contents as those in steps SP1 and SP2, and the chip select signal CSi, READ control signal, WRITE Control signals and other operation timings are set optimally.

Subsequently, a clear signal is output to the WDT circuit 58 to avoid abnormal reset (SP7). This is done in consideration of the fact that the WDT circuit 58 automatically starts operating after power is turned on, and the same process is repeated thereafter. Note that the process of step SP9 is stored in the control memory 53 as a subroutine SP7, but the subroutine SP7 of the control memory 53 is called until the end of step SP9, and after the end of step SP9, the process is stored in the external DRAM 54. Another transferred subroutine SP7' is called and executed.

Next, among the programs and data stored in the address space CS0, the vector handler Vopt (interrupt processing program) shown in FIGS. 15(b) and 16(c), the error recovery processing program Piram, the production control program MainB, The variable D with initial value and the constant data C are transferred to the external DRAM 54 or built-in RAM 59 (SP8). Note that the variable D with an initial value means initial value data stored in a predetermined variable area. This memory section initialization process (SP8) is a process to transfer programs and data in order to speed up the performance control process, and is a process to avoid accessing the ROM, which has poor access speed.

Then, settings are made to use the register bank RBi (SP9). Therefore, thereafter, register banks RB0 to RB14 function during interrupt processing, speeding up interrupt processing and easing stack area consumption.

The above processing is realized by executing the "initial setting program Pinit" stored in the control memory 53, which is the address space CS0 (see FIG. 16(c)). When the execution of this initial setting program Pinit is completed, the main control processing by the production control program Main is subsequently executed (SP10). Here, execution of the main control process means execution of the "effect control program Main" transferred from the control memory 53 to the external DRAM 54 by the transfer process of step SP8 (see FIG. 15(b)).

The specific contents of the main control process (production control program Main) will be explained based on FIG. 17(a) and FIG. 20(a), but prior to that, the memory section initialization process (SP8) I will explain about it. As shown in FIG. 16A, in the memory section initialization process (SP8), first, the DMACs of a plurality of channels are initialized to a stopped state. Note that this process is just a formal process to be sure.

When the above processing is completed, the DMACi of the predetermined channel is activated, and the vector handler Vopt (interrupt processing program) stored in the control memory 53 is transferred to the built-in RAM 59 using a non-stop transfer method (see FIG. 10 (b3)). Perform DMA transfer. In this embodiment, since the interrupt processing program Vopt is transferred to the built-in RAM 59, even when an abnormality occurs in the external DRAM 54, appropriate abnormality handling processing can be performed.

The subsequent processing is also the same, and is executed in a non-stop transfer manner using DMACi of a predetermined channel, and the error recovery processing program Piram is DMA-transferred to the built-in RAM 59 (SP62). In this embodiment, since the error recovery processing program Piram is transferred to the built-in RAM 59, the peripheral circuits can be reliably reset to the reset state in the error recovery processing. For example, if the error recovery processing program Piram is transferred to an external DRAM 54 other than the built-in RAM 59, the external DRAM 54 cannot be reset during error recovery processing.

Next, the production control program Main is DMA-transferred to the external DRAM 54 (SP63), and the constant data C is DMA-transferred to the external DRAM 54 (SP64). The constant data includes lottery data used in the performance lottery, lamp drive data and motor drive data in various drive data tables shown in FIG. 20(b). Further, the variable D having an initial value is DMA transferred to the external DRAM 54 (SP65), but both of these are executed in a non-stop transfer method using DMACi of a predetermined channel.

Finally, clear data is written at the beginning of variable area B of the external DRAM (SP66). Assuming that this start address is ADb, in the subsequent DMA transfer process, after initializing the transfer source address as ADb and the transfer destination address as ADb+1, each address value ADb, ADb+1 is incremented, and the clear data is By diffusing the variable area B, clearing processing of variable area B is executed (SP67).

The processes of steps SP61 to SP66 and step SP67 described above are all similar operations and are as shown in FIG. 16(b). That is, first, regarding the DMACi of a predetermined channel, the DMA transfer conditions are (1) cycle steal transfer mode, (2) nonstop transfer method, and (3) the address values of Source and Destination are updated by increment. SP68).

Next, the initial values of the transfer source Source address and transfer destination Destination address are set (SP69), the transfer size is set, and interrupts are disabled (SP70), and the DMA transfer operation is started (SP71). ). Note that the settings in steps SP68 to SP71 are all realized by setting operations in a predetermined operation control register REG.

In this memory section initialization process, interrupts at the end of DMA transfer are disabled (SP70), so after starting the DMA transfer operation, the status flag of the predetermined operation control register REG is set by repeated READ access. Then, it waits for the DMA transfer to end (SP72). However, taking into account the processing time until the end of the operation, a clear signal is repeatedly output to the WDT circuit 58 (SP73). Then, at the end of the DMA transfer, DMACi is set to be stopped based on a setting operation to a predetermined operation control register REG.

Next, the operation contents of the main control process will be explained based on FIGS. 17 to 20. As explained above, regarding the main control processing, the processing contents of the introduction part (SP20 to SP27) are shown in FIG. 17(a), and the processing contents of the main part (ST4 to ST14) are shown in FIG. Described in a). Note that the process in step SP27 in FIG. 17 includes the processes in steps ST1 to ST3 in FIG. 20(a).

As shown in FIG. 17A, in the main control process (introduction part), first, the bus width and ROM device type of the CGROM 55 are specified (SP20). Specifically, as shown in FIG. 18(a), a predetermined VDP register RGij (for example, CG bus Status register) that specifies the operating state of the CG bus that controls the interface with the CGROM 55 is accessed (SP80). ), it is determined whether operation settings can be made for the CG bus (SP81).

Here, if the value of the CG bus Status register is 1, it means that the internal circuit of the CG bus is in a reset operation, and it means that the set value to the VDP register RGij cannot be accepted. Therefore, after confirming that the value of the CG bus Status register has changed from 1 to 0 (SP81), for each device section (SPA0 to SPAn) that can be defined corresponding to the memory devices that make up the CGROM, ( 1) Operation parameters such as enable/disable of each device section SPAi, (2) ROM device type, and (3) data bus width are set in a predetermined VDP register RGij (SP82).

As shown in FIG. 17(a), in this embodiment, the CGROM 55 can be divided into multiple areas (device sections). For example, each device section (SPA0 to SPAn) has a memory device, a data bus width are configured so that they can be selected. As a memory device, for example, (1) a SATA module (AHSI/F) employed in this embodiment, (2) a memory element that adopts a parallel I/F (Interface) format, and (3) a memory element that adopts a sequential I/F format. Although it is broadly classified into memory elements, etc., it is possible to specifically select a memory device for each broadly classified memory device, and also to arbitrarily define data bus width and the like.

Next, predetermined operation parameters are set in a predetermined VDP register RGij in order to optimize the memory READ operation with the memory device selected for each device section (SPA0 to SPAn) (SP83). The operating parameters include setting values that define the operating timing of the chip select signal and other control signals (such as the READ control signal). Further, when a memory element adopting a sequential I/F format is selected, the output timing of the address latch, the number of read clocks, etc. are also specified in order to realize the operation shown in FIG. 18(b).

Therefore, the CGROM 55 can also be configured by combining different types of memory devices. However, in this embodiment, the CGROM 55 is configured using only SATA modules, and only the device section (SPA0) is enabled, and the other device sections (SPA1 to SPAn) are disabled.

In any case, when the setting processing in steps SP82 and SP83 is completed, a predetermined value is written into a predetermined VDP register RGij in order to make the setting processing effective (SP84). This is done in consideration of the fact that it takes a predetermined time for the internal circuit of the CG bus to be able to operate in response to the setting processing in steps SP82 and SP83. (See SP80) becomes 0.

Therefore, after that, the CG bus Status register is repeatedly accessed by READ (SP85), and the process is finished after confirming that the value of the Status register returns from 1 to 0 (SP86). Note that, regardless of the predetermined number of determinations, if the value of the Status register does not return from 1 to 0, the process of step SP66 may be terminated. However, in that case, since the game process starts in a state where the CGROM cannot be accessed normally, the WDT circuit 58 is activated at some timing thereafter, and the composite chip 50 is placed in an abnormal reset state. In this case, the power-on reset operation will be executed again.

On the other hand, after the process of step SP20 in FIG. 17 is successfully executed, the built-in circuits of the CPU circuit 51, such as the interrupt controller INTC, the DMAC circuit 60, and the multi-function timer unit MTU, are individually initialized by software processing. (SP21).

Next, after starting a predetermined timer measurement operation for the multi-function timer unit MTU (SP22), for internal interrupts and internal interrupts, a permission setting value is written to a predetermined operation control register REG to set the interrupt permission state. (SP23).

As a result, various interruptions shown in FIG. 17(d) may occur thereafter. Normally, at this timing, the audio processor 27 has finished its initialization sequence, so the end interrupt signal IRQ_SND should have fallen to the L level, as shown in FIG. 6(c). Therefore, the interrupt process shown in FIG. 17(c) is activated, and the production control CPU 63 initializes the error flag ERR to 1, performs READ access to the address space CS3 (SP30), and outputs the predetermined audio of the audio processor 27. The value of register SRG is acquired and it is determined whether the initialization sequence has ended normally (SP31).

If the initialization sequence does not end normally, the production control CPU 63 writes a reset command to a predetermined audio register SRG of the audio processor 27 (SP32), and initializes it to 1. The current error flag ERR is set to 2 (SP33). This error flag ERR defines whether or not to execute the audio processor initialization process (SP26), and error flag ERR=1 is the execution condition for step SP26.

On the other hand, in response to receiving the reset command, the audio processor 27 starts the initialization sequence again with the end interrupt signal IRQ_SND = H level, and when the initialization sequence is finished, the end interrupt signal IRQ_SND is Lower it to L level. As a result, the process of FIG. 17(c) is re-executed.

The above describes an exceptional case where the initialization sequence does not end normally, but normally, following step SP31, the process of step SP32 is executed, and the production control CPU 63 inputs the information to the predetermined audio register SRG. By writing a predetermined value, the end interrupt signal IRQ_SND is returned from L level to H level (SP34).

Finally, by writing a predetermined value into a predetermined audio register SRG, READ/WRITE access to all audio registers SRG is permitted (SP35). As a result of this processing, necessary setting processing can be executed in the subsequent audio processor initialization processing (SP26).

An example of a Maskable Interrupt corresponding to the interrupt permission setting in step SP23 has been described above, but a non-maskable interrupt based on stopping the oscillation of the oscillator OSC2 can be activated at any timing. As explained earlier, the operating clock (CPU system clock) for circuits other than the built-in CPU (production control CPU 63) is generated by frequency-multiplying the output clock of the oscillator OSC2 using a PLL (Phase Locked Loop). If the oscillation of the VDP circuit 52 is stopped, normal operation of the VDP circuit 52 is impossible thereafter.

On the other hand, the operating clock of the performance control CPU 63 is generated by multiplying the output clock of the oscillator OSC1 by a PLL, and the program processing can be continued. Furthermore, the interrupt processing program is stored in the built-in RAM 59. Therefore, the production control CPU 63 notifies the occurrence of an abnormal situation by sound or a lamp (SP28), and continues to output a clear signal to the WDT circuit 58 (SP29). The abnormality notification is, for example, a voice notification saying, "An abnormal situation has occurred. Please contact the staff immediately." Note that the reason why the clear signal is continued to be output to the WDT circuit 58 is to avoid an abnormal reset operation. That is, in the event of a serious abnormality in which the oscillator OSC1 stops operating, it is considered that the device cannot be expected to return to normal even if the abnormality reset process is repeated.

Since FIG. 17(b) and FIG. 17(c) have been described above, the explanation will be continued by returning to FIG. 17(a). In step SP24, in order to protect the program area of the external DRAM, the necessary area is set to write-protection. Next, the clock circuit 38, which is powered by a battery when the power is cut off, is checked for normal operation when the power is cut off, and alarm interrupt settings are reset just in case (SP25).

Then, on the condition that the error flag ERR=1, necessary setting values are written into the built-in register (audio register SRG) of the audio processor 27 and initialization processing is executed (SP26). Note that when the error flag ERR=0, the process waits for a predetermined time until the error flag ERR=1, but if the limit time is exceeded, the process shifts to an infinite loop process to start the WDT circuit 58.

Next, initialization processing of the VDP circuit 52 is executed by writing necessary setting values into the VDP register RGij (SP27). Note that the process of step SP27 includes the processes of ST1 to ST3 in FIG.

Although the embodiment in which the termination interrupt signal IRQ_SND is received from the audio processor has been described above, it is also preferable to omit the interrupt processing in FIG. 17(c). FIG. 19 shows a modified embodiment, in which a 1 ms timer interrupt signal generated by the multi-function timer unit MTU is used instead of the end interrupt signal IRQ_SND.

FIG. 19 shows a part of the 1ms timer interrupt processing, and realizes four stages of operation based on the value of the operation management flag FLG (0/1/2/3) whose initial state is zero. are doing. Note that the IRQ_SND output terminal of the audio processor 27 is left open, and the IRQ_SND input terminal of the CPU circuit 51 is fixed at H level.

In the 1 mS timer interrupt process, first, if it is determined in the process of step SP42 that the operation management flag FLG=0, it is confirmed that the initialization sequence of the audio processor 27 has ended normally (SP43). If the process has ended normally, a predetermined value is written to a predetermined audio register SRG to clear the interrupt signal (IRQ_SND) (SP46), and the operation management flag FLG is set to 1 (SP47). Note that the processing in steps SP43 and SP46 is the same as the processing in steps SP31 and SP34 in FIG. 17(c).

On the other hand, if the initialization sequence has not ended normally, a reset command is written to a predetermined audio register SRG to cause the audio processor 27 to start the initialization sequence (SP44) and set the operation management flag FLG to zero. Return (SP45). Note that the process at step SP44 corresponds to the process at step SP32 in FIG. 17(c).

Normally, the operation management flag FLG is set to 1 after the processing in step SP47, so in the next 1ms timer interrupt, access to all audio registers is permitted by writing a predetermined value to a predetermined audio register (SP48 ) and set the operation management flag FLG=2 (SP49). The process at step SP48 corresponds to the process at step SP35 in FIG. 17(c).

Next, in the 1ms timer interrupt with the operation management flag FLG=2, the necessary setting value is written to the built-in register (sound register SRG) of the audio processor 27, as in step SP26 in FIG. 17(a). Initialization processing is executed (SP50) and the operation management flag FLG is set to 3.

The operation management flag FLG=3 means a normal voice control state, and the voice control is advanced by setting necessary operation parameters in the necessary voice register SRG (SP52).

The above is a method of confirming the normal completion of the initialization sequence of the audio processor 27 using the interrupt processing caused by the interrupt signal (IRQ_SND) (SP31 in FIG. 17(c)), and a method of confirming the normal completion of the initialization sequence of the audio processor 27 using the 1mS timer interrupt processing (FIG. 19). SP43) has been described, but the method is not limited to these methods in any way. For example, as part of the process of step SP26 in FIG. 17, it is also suitable to determine whether the initialization sequence of the audio processor 27 has ended normally.

The introduction section of the main control process (SP20 to SP27 in FIG. 17) has been described above, and the operation of the main body section of the main control process will now be explained based on FIG. As shown in FIG. 20, the operations of the production control CPU 63 include a main control process (a), a timer interrupt process (b) that starts every 1 mS, and a reception interrupt process (not shown) that starts in response to the control command CMD. , VBLANK interrupt processing (c) that starts in response to the VBLANK signal that occurs at the start timing of V blank (vertical retrace period) of display device DS1, and drawing abnormality interrupt processing (c) that occurs when the operation freezes or when an unreasonable instruction command is detected. d). Note that a description of the 20 μS interrupt processing will be omitted.

In the reception interrupt processing, the control command CMD received from the main control unit 21 is stored in a predetermined reception buffer so that it can be referenced in the main control processing (ST13), and the processing ends. In addition, in the VBLANK interrupt processing (FIG. 20(b)), the interrupt counter VCNT is incremented for each VBLANK interrupt (ST15), and at the start timing of the main control processing, the interrupt counter VCNT is incremented for 1/30 seconds based on the value of the interrupt counter VCNT. After understanding the operation start timing, the interrupt counter VCNT is cleared to zero (ST4).

On the other hand, as shown in FIG. 20(b), the timer interrupt process includes a process for advancing lamp effects and motor effects (ST18), and a sensor signal acquisition process for obtaining origin sensor signals SN0 to SNn signals, chance button signals, etc. (ST19) is included. Lamp effects and motor effects are controlled based on a performance scenario that centrally manages all performance operations, and when the performance start time managed by the performance counter EN is reached, the motor drive table and motor performance are updated in the performance scenario update process (ST11). A lamp drive table is now identified.

After that, the motor effect will proceed based on the specified motor drive table, and the lamp effect will proceed based on the specified motor drive table. As described above, there are some embodiments in which the DMAC circuit (first and second DMA channels) 60 functions during the operation of step ST18. Note that the motor effect progresses every 1 mS, but the lamp effect progresses at an appropriate timing longer than 1 mS.

On the other hand, as shown in FIG. 20(d), in the drawing abnormality interrupt processing, the status register RGij indicating the operating state of the drawing circuit 76 is read accessed to identify the cause of the interrupt. Specifically, it is determined whether (1) the drawing abnormality interrupt is due to the detection of an abnormal instruction command (bit corruption) or (2) the drawing abnormality interrupt is due to an abnormal operation (freeze) of the drawing circuit 76 (ST16a). If the drawing abnormality interrupt is based on the detection of an abnormal instruction command, the drawing circuit 76 is initialized by writing a predetermined value into a predetermined system control register RGij (ST16b). This operation is nothing but the individual reset operation of the reset path 4B shown in FIG. 6(b).

Next, after confirming the normal completion of the individual reset operation using a predetermined status register RGij, a group of operating parameters that define the operation of the drawing circuit 76 are reset to the predetermined drawing register RGij, and the process ends (ST16c). . After adjusting the stack area for storing the return address (a release process for erasing the return address after interrupt processing), the process proceeds to step ST13 (ST16c).

On the other hand, in the case of a drawing abnormality interrupt due to an abnormal operation of the drawing circuit 76, the WDT circuit 58 is activated and the entire composite chip 50 is reset by shifting to infinite loop processing (ST16d). Note that if you do not want to reset the CPU circuit 51, you may output a predetermined keyword string to the pattern check circuit CHK and reset only the VDP circuit 52 using the reset signal RST (see FIG. 6(b)). . In this case, after confirming that the reset operation of the VDP circuit 52 has completed normally, the process proceeds to steps ST4 and ST13. In addition, in order to avoid overlooking the control command CMD as much as possible, it is better to proceed to step ST13 from step ST4, including in other cases.

When the entire composite chip 50 is reset, the previous effects disappear and the effect control completely returns to the initial state (power-on state), but when resetting only the VDP circuit 52, the reset operation of the VDP circuit 52 Although there is a predetermined waiting time until the process is completed, a series of production controls can be continued. Note that since the performance control CPU 63 controls the image performance, lamp performance, and audio performance in a unified manner, there is no possibility that unnatural deviations will occur in each performance.

Next, the main control process (a) will be described for an embodiment in which the preloader does not function. As shown in FIG. 20(a), the main control process includes an introduction initial process (ST1 to ST3) that is executed after the CPU is reset, and a steady process (ST4 to ST14) that is repeatedly executed every 1/30 seconds. It is divided into Note that the initial processing (ST1 to ST3) is a part of the introduction part of the main control processing, and the steady processing means the main part of the main control processing.

Since the steady processing is started at the timing when the interrupt counter VCNT becomes VCNT≧2 (ST4), the operation cycle δ of the steady processing is 1/30 seconds. This operating cycle δ is nothing but the actual operating cycle δ of the VDP circuit 52 which operates intermittently under the control of the performance control CPU 63. Note that the reason for setting the judgment condition as VCNT≧2 is to take into consideration the possibility that the steady processing (ST4 to ST14) may be abnormally prolonged and the timing of VCNT=2 may be missed; however, in the case where VCNT=3 It is designed to prevent this from occurring.

Continuing the explanation of the main control processing (FIG. 20(a)) based on the above, in this embodiment, in the initial processing, the built-in VRAM 71 with a storage capacity of 48 Mbytes is used as an ACC area (a) having an appropriate storage capacity. , a page area (b) and an arbitrary area (c) (ST1). Specifically, for the ACC area (a1, a2) and the page area (b), each area start address and required total data size are set in a predetermined index table register RGij (ST1). Then, the secured ACC area (a1, a2) and the remaining area not included in the page area (b) become an arbitrary area (c).

Here, the lower 11 bits of the first and second ACC areas (a1, a2) and page area (b) must be 0, but they can be arbitrarily selected in units of 2048 bits. Yes (selection for every 256 addresses, assuming 1 address = 1 byte). Further, the total data size is also arbitrarily selected within the range of an integral multiple of the unit size. Although not particularly limited, the unit size of the ACC area (a) is 2048 bits, and the unit size of the page area (b) is 512 kbits.

In this way, in this embodiment, certain conditions are set for the area settings of the ACC area (a1, a2) and the page area (b), but this is to ensure that the built-in VRAM 71, which has a limited memory capacity, is wasted as much as possible. This is to eliminate the area and to smoothen the internal operation of the VDP circuit 52. In other words, if the storage capacity of the built-in VRAM 71 is increased recklessly, there are concerns that manufacturing costs will rise and the chip area becomes larger. On the other hand, if free area setting that completely eliminates waste areas is allowed, internal processing will become faster. This is because it becomes complicated and the processing time for VRAM access cannot be shortened. Note that it is for the same reason that certain restrictions are placed on securing the index space, which will be explained below.

Continuing the explanation based on the above, following the processing in step ST1, necessary index spaces IDXi are secured for the page area (b) and arbitrary area (c) (ST2). Specifically, by setting necessary information in a predetermined index table register RGij, the index space IDXi of each area (b) and (c) is secured.

For example, when providing index space IDXi in page area (b), multiple information of arbitrary horizontal size Hx and arbitrary vertical size Wx (vertical and horizontal multiple information for unit space) ) is set in a predetermined index table register RGij (ST2).

As explained earlier, the index space IDXi of page area (b) has a unit space of 128 lines in horizontal size x 128 lines in vertical size, and since 1 pixel is specified by 32 bits of information, the horizontal size Hx and vertical size Based on the setting of the size Wx, an index space IDXi of data size (bit length)=32×128×Hx×128×Wx is secured. Note that the start address (space start address) of the index space IDXi in page area (b) is automatically assigned internally.

Furthermore, when an index space IDXi is provided in an arbitrary area (c), an arbitrary start address (space start address) STx and multiple information of an arbitrary horizontal size Hx are set in a predetermined manner corresponding to an arbitrary index number i. is set in the index table register RGij (ST2). Here, "arbitrary" is based on a predetermined condition, and the horizontal size Hx is arbitrarily determined in units of 256 bits, the lower 11 bits of the start address STx are 0, and arbitrarily determined in units of 2048 bits. As explained earlier, the vertical size of the arbitrary area is fixed to 2048 lines, so based on the setting of the horizontal size Hx, an index of data size (bit length) = 2048 x Hx is created after the start address STx. This means that space has been secured.

Specifically, as the frame buffer FBa of the main display device DS1, a pair of index spaces of horizontal size 1280×vertical lines 2048 are set in one or more predetermined index table registers RGij with each index number specified. As the frame buffer FBb of the sub-display device DS2, a pair of index spaces of horizontal size 480×vertical lines 2048 are set in one or more predetermined index table registers RGij with each index number specified. If the number of horizontal pixels of the display device does not match an integral multiple of 256 bits/32 bits, the horizontal size of each index space should be larger than the number of horizontal pixels of the display device, and 256/32=8. Set it to a value that is an integer multiple of , to minimize wasted memory space.

As described above, by setting the necessary size information and address information in the predetermined index table register RGij for the page area (b) and arbitrary area (c), the required number of index spaces IDXi is generated. (ST2). Corresponding to this setting process (ST2), an index table IDXTBL that specifies address information and size information of each index space IDXi is automatically constructed. As shown in FIG. 11(a), the index table IDXTBL stores the start address of each index space IDXi together with other necessary information, and is used for data transfer within the VDP circuit 52, external storage resources (Resource), etc. ) is referenced when acquiring data from (see Figure 12). Incidentally, since the index space IDXi in the AAC area (a) is automatically generated and automatically deleted when necessary, the setting process in step ST2 is not necessary.

As shown in FIGS. 11(a) and 11(b), a pair of frame buffers FBa and FBb are secured in the arbitrary area (c), and index numbers are assigned to each pair. In an embodiment that does not use the Z buffer, a pair of index spaces 255 and 254 assigned index numbers 255 and 254 are secured as the frame buffer FBa. Furthermore, a pair of index spaces 252 and 251 to which index numbers 252 and 251 are assigned are secured as the frame buffer FBb. In this embodiment, a work area with index number 0 (index space 0) is also secured in the arbitrary area (c).

Further, in this embodiment, a necessary number of index spaces IDXi, which serve as decoding areas for IP stream moving images, are secured in the page area (a), and an index number i is assigned thereto. However, initially, only the index space IDX ₀ is reserved for the background video (IP stream video). Then, depending on the need for image production (variable production and preview production), the index space IDXj of the page area (a) is increased based on the setting process to the index table register RGij and the instruction command of the display list DL. Thereafter, when it is no longer needed, the index space IDXj is released. That is, FIG. 11(a) shows the index table IDXTBL during steady operation.

The index space of the ACC area (a) is automatically generated when necessary based on the instruction command written in the display list DL, and the index table IDXTBL contains the start address of the automatically generated index space IDXj. and other necessary information will be automatically set. In this embodiment, this AAC area (a) is used as a decoding area for still images and other textures.

The above operation of securing the index space is realized exclusively by setting the index table register RGij included in the control register group 70, but following the processing of steps ST1 and ST2, setting the index table register RGij included in the control register group 70, By executing the necessary setting operation (ST3), steady operation (intermittent operation) of the VDP circuit 52 shown in FIGS. 28 and 29 is enabled.

In this embodiment, the necessary setting processing (ST3) includes at least the processing shown in Table 1 (SS30 to SS43). Note that steps SS30 to SS43 can be executed in any order without any limitation on the order of processing, regardless of the order of explanation below.

In this embodiment, first, a predetermined system control register RGij is set to construct a dual link transmission path for the main display device DS1 (SS30). As a result of this setting, the output of the display circuit 74A is supplied to the LVDS section 80a and the LVDS section 80b in a state in which the dot clock DCK is divided into two, an ODD signal and an EVEN signal.

Next, for the display circuit 74A and the display circuit 74B, a predetermined system control register RGij is set to generate the dot clocks DCK _A and DCK _B based on the 40 MHz reference clock (output of the oscillator OSC2). Then, the multiplication ratio and frequency division ratio for this reference clock are appropriately defined for each display circuit (SS32).

The dot clock DCK is set separately for the display circuit 74A and the display circuit 74B, and the frequency of the dot clock DCK _A for the main display device DS1 applied to the display circuit 74A is set to 108 MHz, as described above. . On the other hand, the frequency of the dot clock _DCKB for the sub-display device DS2 applied to the display circuit 74B is set to 27 MHz, corresponding to 480 pixels horizontally by 800 pixels vertically.

Further, a predetermined system control register RGij is set to synchronize the start of operation of the display circuit 74B with the start of operation of the display circuit 74A (SS33).

Next, by writing predetermined operating parameters (number of lines and number of pixels) into a predetermined display register RGij that defines the operation of the display circuit 74, the number of display lines and the number of horizontal pixels for each display device DS1 and SD2 is determined. Set (SS34). In the case of this embodiment, the number of horizontal pixels of the main display device DS1 is 1280 dots, and the number of display lines is 1024. Further, the number of horizontal pixels of the sub-display device DS2 is 480 dots, and the number of display lines is 80. As a result of the setting process in step SS34, the vertical and horizontal dimensions of the valid data area (broken line in FIG. 20(e)) to be accessed by the display circuits 74A, 74B for READ access are specified in each frame buffer FBa, FBb. .

Next, by writing predetermined operating parameters (THc, WTh) into a predetermined display register RGij that defines the operation of the display circuit 74, the number of cycles THc of the horizontal period TH and A horizontal standby time WTh is set (SS35). In addition, by writing predetermined operating parameters (TVl, WTv) into a predetermined display register RGij, the number of vertical period TV lines TVl and vertical standby time WTv are set for each display device DS1, SD2 (SS36 ).

As explained with reference to FIG. 14, for the main display device DS1, the number of cycles THc of the horizontal period TH is set to 1662, and the number of lines TVl of the vertical period TV is set to 1083. Further, the horizontal standby time WTh=382 lines and the vertical standby time WTv=59 lines are set. On the other hand, for the sub display device DS2, for example, the number of cycles THc of the horizontal period TH is set as 519, the number of lines TVl of the vertical period TV is set as 867, the horizontal standby time WTh is set as 39, and the vertical standby time WTv is set as 67 lines. be done. Note that THc-WTh=519-39=480 and TVl-WTv=867-67=800, which match the number of pixels of the sub display device (480 horizontally x 800 vertically).

In any case, the frequency F _dot (=108 MHz) of the dot clock DCK is determined by the processing in step SS32, and the number of cycles THc (= 1662) and the number of lines TVl (=1083) of the vertical period TV, the display period of one frame is determined to be THc×TVl/F _dot . Specifically, the display period of one frame is 1083×1662/108 MHz=16.667 mS, and the frame rate FR is determined to be 1/60 second.

For the sub display device DS2, for example, based on the frequency F _dot of the dot clock DCK = 27 MHz, the number of cycles THc of the horizontal period TH = 519, and the number of lines TVl of the vertical period TV = 867, It is determined that 27MHz=16.66mS.

In this embodiment, in response to the above-described determination process, the display circuit 74 enters the V blank start state every 1/60 seconds, and the display operation shown in FIG. 14 is repeated. In addition, in FIG. 14, the start timing of the display operation and the end timing of the display operation indicated by the circle mark indicate the V blank start timing.

Based on this V blank start timing, a horizontal reference point TH0 (=horizontal reference time) and a vertical reference point (=vertical reference time) TV0 in the operation of the display circuit 74 are defined, and the display circuit 74 waits without outputting image data corresponding to each pixel of the display device until the horizontal standby time WTh elapses from the horizontal reference point TH0. Similarly, the display circuit 74 is configured to wait without outputting image data corresponding to each pixel of the display device until a vertical standby time WTv elapses from the vertical reference point TV0.

Furthermore, since the display circuit 74B operates in synchronization with the display device 74A (SS33), the start and end timings of the display operation for the sub display device DS2 are also the same as the timings for the main display device DS1. Therefore, the frame period (519×867/27) for the sub display device DS2 is set shorter than the frame period (1083×1662/108) for the sub display device DS2, so that at the start of V blanking, the frame period (519×867/27) for the sub display device DS2 is The update process is set to complete.

Next, in this embodiment, regarding the sub display device DS2, the pulse width of the horizontal periodic signal HS and the number of cycles from the V blank start timing of the pulse rising edge are set in a predetermined display register RGij (SS37). Further, regarding the sub display device DS2, the pulse width of the vertical periodic signal VS and the number of cycles from the V blank start timing of the pulse rising edge are set (SS38).

As explained above, the main display device DS1 does not require the horizontal synchronization signal HS or the vertical synchronization signal VS, so the above processing (SS37 to SS38) for the main display device DS1 is unnecessary. However, if the setting processing of steps SS37 to SS38 is omitted, the default value set at the power reset will function, so the display device 74A will actually output the horizontal synchronizing signal HS and the vertical synchronizing signal VS. It turns out.

According to the default value, for example, a horizontal synchronizing signal HS with a pulse width of 40 clocks that becomes active level 16 clocks after the V blank start timing is output, and a pulse width that becomes active level in synchronization with the V blank start timing. A vertical synchronization signal VS for three lines is output.

In this operation, a horizontal synchronizing signal HS with horizontal front porch HPv=16, pulse width PWh=40, and horizontal back porch BPv=326 is output to the main display device DS1 during horizontal standby time WTh=382 clocks. , which also means that a vertical synchronizing signal VS with vertical front porch HPv=0, pulse width PWv=3, and vertical back porch BPv=56 is output during the vertical standby time WTv=59 lines. However, as described above, these synchronization signals are ignored in the main display device.

Note that in order to prevent the synchronization signals HS and VS based on default values from being output, a configuration may be adopted in which a predetermined system control register RGij is set so as not to output the horizontal synchronization signal HS and the vertical synchronization signal VS. When such a mask setting is provided, the output terminal of the horizontal synchronization signal HS and the output terminal of the vertical synchronization signal VS of the VDP circuit 52 can maintain a fixed value of H level or L level.

Subsequently, a predetermined system control register RGij is set to permit V blank interrupts (SS39). As a result, in this embodiment, the VBLANK start interrupt shown in FIG. 20(c) occurs corresponding to the VBLANK start timing that occurs every 16.667 mS=1/60 seconds. This V blank interrupt timing defines the start timing of the steady processing (ST5 to ST14) of the production control CPU 63, and also means the start timing of the display period for the display circuits 74A and 74B (the end timing of the immediately preceding display period). .

Next, a predetermined operating parameter (address value) is written into a predetermined display register RGij, and the vertical display start position and horizontal display start position are specified for each frame buffer FBa, FBb (SS40). As a result, the valid data area whose vertical and horizontal dimensions were specified in the process of step SS34 is determined on the frame buffers FBa and FBb. Here, the vertical display start position and the horizontal display start position are relative address values in each index space, and in the example shown in FIG. 20(e), the display start position is (0,0).

Here, the "display area" means an index space (frame buffer FBa, FBb) from which the display circuits 74A, 74B should read image data in order to drive the display devices DS1, DS2, and each has a double buffer structure. This means either one of the double buffers in frame buffers FBa and FBb. However, display circuits 74A and 74B actually read image data only from the "valid data area" specified in step SS34 and step SS40 in display area (0) or display area (1).

Next, the display register RGij (DSPAINDEX) related to the display circuit 74A that drives the main display device DS1 and the display register RGij (DSPBINDEX) related to the display circuit 74B that drives the sub display device DS2 are each set to have a "display area (0)". and "display area (1)" to define each display area (SS41).

Although not limited in any way, in this embodiment, for the frame buffer FBa, the index space 254 with the index number 254 in the VRAM arbitrary area (c) is defined as the "display area (0)", and the index space 254 in the VRAM arbitrary area (c) is defined as the "display area (0)". 255 is defined as a "display area (1)" (SS41).

Regarding the frame buffer FBb, the index space 251 with index number 251 in the VRAM arbitrary area (c) is defined as the "display area (0)", and the index space 252 with index number 252 in the VRAM arbitrary area (c) is defined as the "display area (0)". 1)” (SS41). Note that there is no particular limitation on defining the "display area" in the initial processing (ST3), and the display circuit 74 can toggle the index space (display area) to which the image data should be accessed at each operation cycle δ. You may switch.

In this embodiment, after the initial settings including the above processing (SS30 to SS41) are completed, the set value to the predetermined system control register RGij is set to the first register so that it will not be changed due to noise or the like. A predetermined prohibition value is set in the seed prohibition setting register RGij (first prohibition setting SS42).

Here, the setting values that will be prohibited from being written in the future include (1) setting values related to the display clock DCK of display devices DS1 and DS2, (2) setting values related to the LVDS sampling clock, and (3) settings values of the output selection circuit 79. Setting values related to selection operations, (4) synchronization relationship between the plurality of display devices DS1 and DS2 (the display circuit 74B is dependent on the operation cycle of the display circuit 74A), etc. are included. Note that although there is a software process for canceling the first prohibition setting, it is not used in this embodiment. However, it is also suitable to use it as needed.

Next, by setting a predetermined prohibition value in the second type of prohibition setting register RGij, writing is prohibited for the initial setting type VDP register RGij (second prohibition setting SS43). Here, the registers set to be prohibited include the VDP register RGij related to steps SS30 to SS42.

On the other hand, by setting a predetermined prohibition value in the third type prohibition setting register RGij, it is also possible to prohibit settings for a large number of VDP registers, including the VDP registers related to the setting processing of steps ST1 to ST3. 3 prohibition setting). However, in principle, this is not used in this embodiment. In any case, the second prohibition setting and the third prohibition setting can be canceled arbitrarily by writing a cancellation value to a predetermined cancellation register RGij, and the setting value cannot be changed during normal operation. is also possible.

The initial setting process in steps ST1 to ST3 described above is executed based on the initial value setting table SETTABLE (see FIG. 34) that associates the register address value of the VDP register RGij with the set value to that register RGij. be done. Since the initial setting process has been explained above, next, before explaining the steady process (ST4 to ST14), the steady operation (intermittent operation) of the VDP circuit 52 controlled by the production control CPU 63 will be explained as shown in FIG. 28(a) and This will be briefly explained based on FIG. 29(b).

The intermittent operation of the VDP circuit 52 is as shown in FIGS. 28 and 29, and in an embodiment that does not use the preloader 73, the display list DLi completed by the production control CPU 63 is as shown in FIG. 28(a). At the operation cycle (T1), it is issued to the drawing circuit 76, and the drawing circuit 76 completes the image data in the frame buffers FBa and FBb by a drawing operation based on the display list DLi. Then, the image data completed in the frame buffers FBa and FBb is outputted by the display circuit 74 to the display devices DS1 and DS2 in the next operation cycle T1+δ, based on the subsequent drawing operations of the display devices DS1 and DS2. , becomes the display screen that the player senses.

On the other hand, in the embodiment using the preloader 73, as shown in FIG. , interprets the display list DLi, performs the necessary prefetch operation, and rewrites a part of the display list DLi to complete the rewrite list DL'. Note that the prefetched CG data and rewrite list DL' are stored at appropriate locations in the DRAM 54.

Next, in the next operation cycle (T1+δ), the drawing circuit 76 acquires the rewriting list DL' from the DRAM 54, and completes the image data in the frame buffers FBa and FBb by a drawing operation based on the rewriting list DL'. . Then, the image data completed in the frame buffers FBa and FBb is further outputted by the display circuit 74 to the display devices DS1 and DS2 in the next operation cycle (T1+2δ), so that the image data can be displayed on the subsequent display devices DS1 and DS2. Based on the movement, a display screen is created that the player senses.

The intermittent operation of the VDP circuit 52 has been schematically explained above, but in order to realize the operations shown in FIGS. is repeatedly referred to and waits until the operation start timing is reached. When the operation start timing (one-by-one V blank start timing) is reached, the interrupt counter VCNT is cleared to zero (ST4).

After that, the steady operation is started, but in this embodiment, it is first determined whether or not the operation start condition for starting the steady operation is satisfied (ST5). Note that this determination timing is the timing of T1, T1+δ, T1+2δ, . Note that the display timing of the display device DS2 is set at the time of initial setting (ST3) so as to be subordinate to the display timing of the display device DS1.

Since the operation start condition determined by the start timing of the vertical blanking period (VBLANK) differs depending on whether or not the preloader 73 is used, an example (FIG. 20) in which the preloader 73 is not used will be described first. In this case, the circuit configuration and program are originally designed so that the internal operation of the VDP proceeds as shown in the time chart of FIG. 28(a). That is, based on the display list DL1 completed in the operation cycle (T1), the drawing circuit 76 is supposed to finish the drawing operation during the operation cycle (T1 to T1+δ). However, it cannot be said that there are cases where the drawing operation is not completed during the operation cycle (T1+2δ to T1+3δ), for example, like the display list DL3 completed in the operation cycle (T1+2δ) in FIG. 28(a). Furthermore, regarding the display circuit 74, there is a possibility that an underrun abnormality occurs in which display data is not generated in time for the display timing.

The determination process in step ST5 takes this situation into consideration, and the production control CPU 63 accesses the status register RGij (a type of control register group 70) that indicates the operating state of the drawing circuit 76, and at the timing of step ST5, The drawing circuit 76 determines whether the necessary operations have been completed and whether there is an underrun abnormality. Note that the presence or absence of an underrun abnormality is determined based on underrun counters URCNTa to URCNTc. Furthermore, in an embodiment that does not utilize the preloader 73, for example, at timing T1+δ in FIG. 28(a), the status information of the drawing register related to the drawing circuit 76 is read accessed, and the drawing operation based on the display list DL1 is completed. Check.

If the operation start condition is not satisfied (abnormality/nonconformity), an abnormality flag ER that counts the number of abnormalities is incremented, and steps ST6 to ST8 are skipped. The abnormality flag ER is determined together with other serious abnormality flags ABN in the processing of steps ST9 and ST10, and on the premise that the serious abnormality flag ABN is in the reset state, if the number of consecutive abnormalities is not large (ER≦2), Similar to the normal time, performance command analysis processing is executed (ST13).

In the case of underrun abnormality, steps ST6 to ST8 are similarly skipped. Then, by writing a predetermined clear value into a predetermined system control register RGij, the display clock DCK (frequency) and the display circuit 74 are initialized (ST10c). After confirming that the initialization process has completed successfully, the frequency of the display clock DCK and the values of a group of system control registers RGij that define the operation of the display circuit 74 are reset to the specified values (ST10c). , performs production command analysis processing (ST13).

In the performance command analysis process (ST13), it is determined whether or not a control command CMD is received from the main control board 21, and if a control command CMD is received, the control command CMD is analyzed and necessary processing is executed. (ST13). Here, the necessary processing includes a process for preparing to start a new variable effect based on a control command CMD that instructs the start of a variable effect, and a process for starting error notification based on a control command CMD indicating the occurrence of an error. Subsequently, a clear pulse is output to the WDT circuit (ST14), and the process returns to step ST4.

Above, we have explained the case where there is a slight underrun abnormality or the operation start condition is not met and the abnormality flag ER is ER≦2. In such a case, the display circuit 74 The process of toggling the display area to be read out (ST6) and the process of creating a display list (ST7) are skipped, and the production scenario does not proceed (see ST8 to ST12). This is to prevent image data from incomplete frame buffers FBa and FBb from being output. Therefore, for example, in the operation cycle (T1+3δ) of FIG. 28(a), image rendering does not proceed and a frame drop occurs in which the original screen (screen based on DL2) is redisplayed.

Here, in order to avoid frame drops, a configuration may be considered in which the process waits until the operation start condition is satisfied. However, there are many control processes (ST6 to ST12) to be executed by the production control CPU 63, and it is necessary to secure time for each process, so in this embodiment, if the operation start conditions are not met, frames are dropped. There is.

However, even if a frame drop occurs, the progress of the image presentation will only be delayed by about 1/30 to 2/30 seconds compared to the lamp effect and motor effect that proceed due to interrupt processing (Figure 20(b)). Yes, the player does not notice this. Moreover, when a frame is dropped, the production scenario processing (ST11) including the processing to update the production counter EN and the audio progression processing (ST12) are also skipped, so the reach production, preview production, and accessories that will be started afterwards are also skipped. There is no fear that the start timings of image effects, audio effects, lamp effects, motor effects, etc. will be shifted in the effects.

In other words, in the production scenario, the start timing of image production, audio production, lamp production, and motor production, as well as the content of production to be executed thereafter, are centrally managed. Since the timing is controlled, the various performances will not go out of sync. For example, if there is a performance action that combines an explosion sound, an explosion image, a moving object, and a lamp flash action, each of the above performance actions will start correctly in synchronization even after a frame drop occurs. Ru.

Although relatively minor abnormalities have been explained above, when the serious abnormality flag ABN is set, when the number of consecutive abnormalities is large (ER>2), or when an underrun abnormality occurs repeatedly, step ST10 is performed. After the determination, an infinite loop state is established (ST10b). As a result, the timekeeping operation of the WDT circuit 58 progresses, and the composite chip 50 including the performance control CPU 63 is abnormally reset. After that, the initial processing (ST1 to ST3) is re-executed, thereby preventing the occurrence of an abnormal situation. It is hoped that the root cause will be resolved.

Note that this reset operation is executed by activating the WDT circuit 58, so the entire composite chip 50 including the CPU circuit 51 enters the reset state (FIG. 6(b)). Therefore, in order to avoid resetting the CPU circuit 51, the performance control CPU 63 outputs a predetermined keyword string (for example, three pieces of 1-byte data) to the pattern check circuit CHK, and outputs a reset signal RST to the VDP circuit 52. is also suitable (see ST100 in FIG. 34). In this case as well, after confirming that the reset operation of the VDP circuit 52 has completed normally (ST101), the process proceeds to steps ST4 and ST13.

In any case, when this abnormality occurs, the audio circuit SND is also abnormally reset, so that the image effect, sound effect, lamp effect, and motor effect all return to their initial states. However, these reset operations have no effect on the main control section 21 or the payout control section 25, so there is no possibility that situations such as the disappearance of the jackpot state or the disappearance of prize balls will occur.

Although abnormal situations have been explained above, in reality, the above-mentioned abnormalities almost never occur, even in minor cases, and after the processing in step ST5, the settings in the predetermined display register RGij (DSPACTL /DSPBCTL) Based on the display circuit 74A and the display circuit 74B, the display areas of the frame buffers FBa and FBb storing the image data to be read out are toggled (ST6). As explained earlier, "display area (0)" and "display area (1)" are defined in advance in the initial process (ST3), so in the process of step ST6, frame buffers FBa and FBb are Specify whether the "display area" is display area (0) or display area (1).

By executing this step ST6, the display circuit 74A alternately displays image data from the index space 254 (display area (0)) and the index space 255 (display area (1)) at every operation cycle δ. The data will be read out and the display device DS1 will be driven. Similarly, the display circuit 74B alternately reads image data from the index space 251 (display area (0)) and the index space 252 (display area (1)) at every operation cycle δ, and displays the sub display device DS2. It will be driven. As described above, the actual READ access of the display circuit 74 is limited to the valid data area in the display area (0)/display area (1).

In any case, in this embodiment, since the "display area" is switched every operation cycle, the display circuits 74A, 74B display the image data completed by the drawing circuit 76 in the immediately previous operation cycle on the display devices DS1, DS2. This will start output processing to. However, since the process of step ST5 starts from the start of the vertical blanking period (V blank) of the main display device DS1, the image data output process actually starts after the vertical blanking period is completed. will be done. In FIG. 28(a), the arrow shown in the display circuit column indicates the operation cycle of this output processing.

When the process of step ST6, which has the above significance, is completed, the production control CPU 63 subsequently completes the display list DL specifying the image data that the display circuit 74 should output to the display device in the next operation cycle. (ST7). Although not particularly limited, in this embodiment, a list buffer area (DL buffer BUF) of the RAM 59 is secured, and the display list DL is completed there (see FIG. 12).

The display list DL is configured by listing a series of instruction commands in an appropriate order, and is configured to end with an EODL (End Of DL) command. In this embodiment, in order to realize smooth operation of the data transfer circuit 72, the drawing circuit 76, and the preloader 73, all instruction commands including the EODL command are divided into commands whose command length is 32 bits multiplied by an integer N (N>0). It is limited to only instruction commands. Note that, as described above, the instruction command composed of N times an integer of 32 bits may also include a don't care bit.

In this way, the display list DL of the embodiment is composed of only instruction commands whose command length is an integer N times (N>0) of 32 bits, so the data volume value (total amount of data) of the entire display list DL is: It is always an integral multiple of the minimum unit of command length (32 bits = 4 bytes). Furthermore, in this embodiment, in consideration of the minimum data amount Dmin of the data transfer circuit 72, the data volume value of the display list DL is set to be an integral multiple (1 or more) of the minimum data amount Dmin, and the value of the instruction command. It is adjusted to be an integral multiple of the minimum unit (4 bytes). For example, if Dmin=256 bytes, the data volume value of the display list DL is adjusted to either 256 bytes, 512 bytes, etc.

Here, it is preferable to adjust the value to 256 bytes or 512 bytes depending on the complexity of the presentation content, but in this embodiment, there are two display devices, and the sub display device DS2 is The data volume value of the display list DL is always adjusted to 256 bytes in consideration of not executing very complicated image effects.

However, this method is not limited in any way, and in the case of three or more display devices, or in the case of a gaming machine that executes complex image production including the sub-display device DS2, the method is adjusted to 512 bytes or 768 bytes. be done. Also, during normal performances, the data volume value of the display list DL is adjusted to 256 bytes, and only when performing special performances, the data volume value of the display list DL is adjusted to 512 bytes or 768 bytes. is also suitable.

However, in the case of this embodiment, the data volume value of the display list DL is adjusted to a predetermined byte length (256 bytes) in each operation cycle δ. The adjustment method is the simple method (A) of filling in a 32-bit long NOP (No Operation) command to fill in the missing area after a 32-bit long EODL command, or after filling in the missing area with a 32-bit long NOP command. A standard method (B) is considered in which a 32-bit long EODL command is written at the end. Note that the data volume value (total amount of data) of the display list DL is terminated with the EODL command without any adjustment, and when the data transfer circuit 72 operates, dummy data is additionally transferred and the data volume value (total amount of data) of the display list DL is terminated by an integral multiple of the minimum data amount Dmin. A non-adjustment method (C) is also conceivable to ensure the transfer amount of .

Here, when adopting the standard method (B), the command counter CNT is first initialized to the specified value (64-1 corresponding to 256 bytes), and each time a significant instruction command is written to the DL buffer area BUF. Next, a method can be considered in which the command counter CNT is appropriately decremented, and once a series of significant instruction commands have been written, NOP commands are written until the command counter CNT reaches zero, and finally the EODL command is written. In the case of this embodiment, the instruction command is limited to those whose command length is an integer N times (N>0) of 32 bits, so the above process is easy, and the subtraction process of the command counter CNT is performed by an integer The subtraction process corresponds to N.

On the other hand, when adopting the simple method (A), it is sufficient to first fill the entire list buffer area (DL buffer BUF) with NOP commands when creating the display list DL. Seems to be excellent. In addition, from the viewpoint of simplicity, the no-adjustment method (C) also seems to be superior. However, in this embodiment, the standard method (B) is basically adopted, and the actual amount of data from the beginning of the display list DL to the EODL command, that is, the amount of data up to the EODL command, is always the same as that of the data transfer circuit 72. is adjusted to be an integral multiple of the minimum data amount Dmin.

This takes into consideration the example that utilizes the preloader 73, and if the simple method (A) or non-adjustment method (C) is adopted, the actual data amount of the display list DL up to the EODL command will be random. This is because a problem occurs when the rewrite list DL' rewritten by the preloader 73 is transferred to the DRAM 54 or when the rewrite list DL' is transferred from the DRAM 54 to the drawing circuit 76. Note that when transferring the rewrite list DL' to the DRAM 54, the ChA control circuit 72a of the data transfer circuit 72 functions, and when transferring the rewrite list DL' to the drawing circuit 76, the ChB control circuit 72b functions (see FIG. ), in either case, only the rewrite list DL' up to the EODL command is transferred.

The advantages of the standard method (B) for adjusting the data volume value of the display list DL have been explained above, but in an embodiment that does not use the preloader 73, the issued display list DL is only processed by the drawing circuit 76. Therefore, the use of the simple method (A) and the no-adjustment method (C) is not prohibited in any way.

However, in the following explanation, the details of the display list DL will be explained based on FIG. 21 on the premise that the standard method (B) is adopted in principle regardless of whether or not the preloader 73 is used.

Although not particularly limited, in this embodiment, first, the instruction command string (L11 to L16) regarding the main display device DS1 is written in the display list DL, and then the instruction command string (L17 to L20) regarding the sub display device DS2 is written. I am trying to write it down. Further, standard method (B) is adopted to adjust the data volume value of the display list DL to a fixed length (256 bytes). Note that FIG. 21 actually shows the procedure in which the production control CPU 63 writes an instruction command into the list buffer area of the RAM 59 and the operation of the drawing circuit 76 based on the display list DL.

As shown in FIG. 21, at the beginning of the display list DL, an environment setting instruction command (SETDAVR) is written to set the upper left base point address (X, Y) on the index space IDX for the frame buffer FBa of the display device DS1. (L11). As explained with reference to FIG. 11(a), in this embodiment, a pair of frame buffers FBa are secured in the arbitrary area (c) for the display device DS1. Then, normally, by setting the base point address (X, Y) = (0, 0) corresponding to the effective data area for the display circuit 74, the drawing circuit 76 uses the starting position of the frame buffer FBa. .

In FIG. 11(c), the actual drawing area on the lower left side is labeled L11, which means that the actual drawing area on the frame buffer FBa is moved to the base point address (0, 0, 0) means that it is specified as starting from position. However, the vertical and horizontal dimensions of the actual drawing area and the index number specifically specifying the actual drawing area are still undetermined, and are determined by an instruction command (SETINDEX) L13, which will be described later. Note that the instruction command L11 also specifies whether or not to use the Z buffer.

Next, use the environment setting instruction command (SETDAVF) to set the upper left base point coordinates (Xs, Ys) and lower right diagonal point coordinates (Xe, Ye) on the virtual drawing space, and set the W x H dimension. A drawing area is defined (L12). Here, the virtual drawing space is a virtual two-dimensional space of ±8192 in the X direction and ±8192 in the Y direction, which can be drawn by a drawing instruction command (SPRITE command, etc.) (see FIG. 11(c)). .

This instruction command L12 (SETDAVF) divides the virtual drawing space into a drawing area where the drawing content is actually reflected on the display device DS1 and other non-drawing areas. Further, the instruction command L12 (SETDAVF) associates the actual drawing area whose start position (base point address) is defined by the instruction command L11 with the drawing area in the virtual drawing space.

In other words, the instruction command L12 defines a W×H actual drawing area starting from the base address, which corresponds to the drawing area in the virtual drawing space, in the frame buffer FBa (the index space is undetermined). It turns out. Therefore, the drawing area specified by the instruction command L12 needs to be equal to or smaller than the horizontal size of the frame buffer FBa. Usually, the drawing area and the actual drawing area are defined to have the same dimensions as the effective data area for the display circuit 74 (FIG. 20(e)).

After the drawing circuit 76 executes the instruction commands L11 and L12, of the drawing contents drawn in the virtual drawing space, only those included in the drawing area are reflected in the actual drawing area of the frame buffer FBa. become. Therefore, the drawing contents of the portion that protrudes from the drawing area or the portion described as a work area in FIG. 11(c) are not reflected in the frame buffer as they are. Note that when securing a work area in the virtual drawing space, a non-drawing area of the virtual drawing space is used.

Next, in the current operation cycle, the drawing circuit 76 specifies where the drawing content to be drawn should be drawn based on the display list DL to be completed from now on (L13). Specifically, for the frame buffer FBa of the display device DS1 with the double buffer configuration, an index space IDX that is a "write area" for the drawing content based on the current display list DL is specified (L13). Specifically, the SETINDEX command, which is a texture setting command, confirms that (1) the frame buffer FBa is secured in an arbitrary area, and (2) the arbitrary area of the index space IDX _N , which is the "write area" An index number N on the area is specified.

For example, when N=255 is specified by this instruction command L13, the actual drawing area corresponding to the drawing area defined on the virtual drawing space is specified in the frame buffer FBa with a double buffer structure. This means that the index space IDX ₂₅₅ is defined.

In the case of this embodiment, the index number of the frame buffer FBa is 255 or 254 (FIG. 11(a)), and either one is specified by toggling (L13). Note that this index number is the index number of the display area other than (0)/(1) specified in step ST6 of the main control process. For example, in the process of step ST6, if the display area (0) is specified for the display circuit 74, the display area (1) becomes the "write area" for the drawing circuit 76.

As described above, after the correspondence between the actual drawing area (W×H logical space) and the drawing area (W×H virtual space) is generally defined by the instruction command L11 and the instruction command L12, By the instruction command L13 (SETINDEX) that specifically specifies the index space IDX, the W×H virtual space is associated with the W×H logical space in the specific index space IDX.

In other words, the content that will be virtually drawn in the W×H virtual space based on a series of instruction commands will be based on the internal VDP that defines the correspondence between the virtual space and the real address of the built-in VRAM 71. Based on the conversion table, the image data is stored in the built-in VRAM 71 (frame buffer).

Subsequently, an instruction command for executing a frame buffer clearing process of filling the specified index space IDX with black, for example, is written as a "write area" (L14, L15). This is nothing but a process of erasing the image data written to the frame buffer FBa two operation periods ago.

Specifically, the SETFCOLOR command, which is a type of environment setting command, is used to select, for example, black color, and the RECTANGLE command, which is a primitive drawing command, is used to specify that a rectangular area should be filled. Note that the RECTANGLE command specifies the XY coordinates of the upper left end point and lower right end point of the drawing area set in the virtual drawing space (virtual space corresponding to frame buffer FBa) (see Figure 11(c)). .

The drawing preparation process is completed by the above processing, so next, instruction commands for drawing an appropriate texture, such as a still image or one frame of a moving image, in the virtual drawing space will be listed. Typically, first, the index space IDX to which the texture is to be expanded is specified using a texture setting SETINDEX command, and then a TXLOAD command, which is a texture loading instruction command, is written to select a predetermined value to be read from the CGROM 55. The texture is written in the display list DL so as to be developed in a predetermined index space IDX.

As explained above, in this embodiment, the background video is composed of an IP stream video. So, for example, for a background video, specify the index space IDX in which it should be developed as index space IDX ₀ of page area (b) using the texture setting SETINDEX command, and then write the texture loading TXLOAD command. do. Note that in the TXLOAD command, it is necessary to specify the start address of the CGROM 55 (texture source address) and the data size (horizontal x vertical) after expansion for the video frame to be loaded this time.

When the above TXLOAD command is executed in the VDP circuit 52, one video frame (texture) of the background video is first acquired into the AAC area (a), and then automatically activated by the GDEC 75, the page area ( b) is expanded to the index space IDX ₀ . Next, this one video frame will be drawn in the virtual drawing space. In this case, you can use the SETINDEX command (texture setting system) to set "index space IDX ₀ of page area (b) is the texture to be processed later", but it is also possible to set the texture to be processed after the TXLOAD command. In this case, the description of this SETINDEX command can be omitted.

In any case, in a state where it is specified that "index space IDX ₀ of page area (b) is the texture to be processed later," next, set parameters for α blend processing, etc. Describe appropriate instruction commands for the inter-rendering calculation system. Note that the α blend process is related to the process of making an image already written in the drawing area (frame buffer FBa) transparent/semi-transparent with an image that will be overwritten from now on. Therefore, in the drawing operation of the first image, as in the moving image frame of the background moving image, it is not necessary to use the instruction command of the inter-drawing calculation system.

Next, use the SPRITE command, which is a primitive drawing instruction command, to move the "texture in index space IDX ₀ of page area (b) (one video frame of the background video)" to the appropriate location in the virtual drawing space (rectangular Destination area). Write the SPRITE command to draw. Note that the SPRITE command requires specifying the upper left end point and lower right end point of the Destination area of the virtual drawing space.

This Destination area is the whole or part of the drawing area (virtual space defined on the virtual drawing space) that is previously associated with the actual drawing area (FBa) by the instruction commands L11 and L12. However, since a background moving image is normally drawn on the entire display screen, the Destination area in such a case is the entire drawing area or more. Note that the case where the Destination area is larger than the entire drawing area is, for example, when the background video is zoomed in.

With the above processing, the drawing of the video frames of the background video has been completed.Next, list the instruction commands such as texture loading type, texture setting type, inter-rendering calculation type, and primitive drawing type commands in the appropriate order. A display list DL is configured to draw various textures over the background video. As explained earlier, a large number of moving images are required during variable production. The command (NEWPIX) will be described.

For example, regarding the second IP stream video, after securing additional index space IDX ₁ in page area (b) using the NEWPIX command, specifying this index space IDX ₁ (SETINDEX), and Instructs to expand one frame of the video (TXLOAD) and places the expanded texture at the appropriate location in the drawing area (SPRITE). Normally, the Destination area in this case is part of the drawing area.

The same goes for the following. After securing the index space IDX _k one after another using the NEWPIX command, if multiple IP streams are drawn in the drawing area while executing the appropriate α blending process, the content drawn in the drawing area is , are sequentially accumulated as image data in the frame buffer FBa, which is an actual drawing area. When a plurality of N IP stream videos are rendered, a plurality of N index spaces are functioning in the page area (b).

Then, when a series of variable effects has been completed, use the DELPIX command to release the index space IDX that is deemed unnecessary among the many index spaces IDX ₁ to IDX _k secured in the page area (b). All you have to do is delete the unnecessary index space IDX.

Note that when drawing still images or I-stream videos, specify that these textures should be decoded in the AAC area (a) using the SETINDEX command, and then execute the TXLOAD command to decode the AAC area. The texture acquired in (a) is then developed in the ACC area (a) by the automatically activated GDEC 75. The expanded texture can then be drawn at the appropriate location in the drawing area using the SPRITE command. Note that the first AAC area (a1) or the second AAC area (a2) is used depending on whether or not to utilize the cache hit function.

In the explanation so far, each texture is directly drawn in the drawing area of the main display device DS1, but the operation is not necessarily limited to this. For example, if an appropriate drawing area is provided without overlapping the drawing area already secured for the display device DS1 (FIG. 11(c)) and this drawing area is associated with the work area of the built-in VRAM 71, an intermediate drawing area can be created. By constructing a drawing area, it is possible to complete an appropriate effect image. Here, the reason why the drawing area for the display device DS1 is not overlapped is that for the overlapping area, the later association setting is given priority, and the drawing content for that area is not reflected in the frame buffer FBa.

As shown in FIG. 11(c), the work area of this embodiment is index space IDX ₀ in the arbitrary area (c). Then, at the production timing using this work area, an instruction command is first issued to associate the drawing area for the effect image (see FIG. 11(c)) with the work area (actual drawing area of index space IDX ₀ ). Write down the columns (SETDAVR, SETDAVF, SETINDEX). As shown in FIG. 11(c), the rendering area for the effect image is secured in an area that is not included in the rendering area for the main display device DS1.

Thereafter, it is sufficient to list instruction commands similar to the instruction command string L16 regarding the frame buffer FBa to complete an appropriate effect image in the index space _IDX0 . In the case of this embodiment, since the effect image is composed of a still image, an instruction command (SETINDEX) is written so that the decoded data is developed in the first AAC area (a1), and then in the index space IDX _0. A primitive drawing instruction command (SPRITE) will be used that sets the destination to a suitable location in the drawing area. Note that such an operation is repeated once or multiple times depending on the content of the performance.

Then, after positioning the index space IDX ₀ that has completed the effect image as a texture (SETINDEX), the effect image (texture) of the index space IDX ₀ is drawn at the appropriate location in the drawing area of the main display device DS1 using the SPRITE command. Just do it. In such a case, it is conceivable to decompose the effect image in the index space IDX ₀ into triangular drawing primitives, rotate them at an appropriate angle, and then draw them in the drawing area. Note that the rotation angle of the texture is associated with, for example, the reliability of the preview performance.

The instruction command sequence (L11 to L16) for completing one frame of the main display device DS1 has been described above, but the instruction command sequence (L17 to L12) for completing one frame of the sub display device DS2 has also been described. The same is true. That is, specify the starting XY coordinates of the frame buffer FBb, define (L17) (usually A drawing area is defined (L18).

By the way, in this embodiment, after the generation of image data for the main display device DS1 is completed, the process shifts to generation processing for the sub display device DS2, so that the drawing area for the sub display device DS2 is the same as that for the main display device DS1. You can freely set the drawing area without any problem even if it overlaps with the drawing area of . Therefore, when developing a display list DL generation program, for example, when pasting an appropriate texture to a newly set drawing area using the SPRITE command, settings such as the operation parameters (Destination area) of the SPRITE command, etc. It can be standardized to some extent.

When the definition of such an arbitrary drawing area is completed (L18), next, for the frame buffer FBb of the display device DS2 with the double buffer configuration, an index space is created which becomes the "writing area" of the drawing content based on the current display list DL. Specify IDX (L19). The index number of this index space IDX is the index number of the frame buffer FBb that does not correspond to the display area (0)/(1) specified in step ST6 of the main control process.

Thereafter, the instruction command strings L20 to L22 for the sub display device DS2 are listed in the same manner as the instruction command strings L14 to L16 for the main display device DS1. Furthermore, it is also possible to use the effect image completed in the index space IDX ₀ .

As described above, in this embodiment, the instruction commands L11 to L22 that make up the display list DL are all limited to those whose command length is an integral multiple of 32 bits. As explained earlier, the data volume value (total amount of data) of the display list DL in this embodiment is adjusted to a fixed length (256 bytes), and the required number of NOP commands (L23) as dummy commands are added. After that, it is terminated with the EODL command (L24). That is, the embodiment shown in FIG. 21 adopts the standard method (B) described above.

However, even when using the standard method (B), it is not always essential to fix the total amount of data in the display list DL to 256 bytes in all operation cycles. That is, in another embodiment, if the total amount of data in the display list DL excluding the NOP command exceeds 256 bytes (for example, during a special performance period), the total amount of data in the display list DL may be increased by adding the NOP command. and adjusted to 512 bytes or more N×256 bytes. As described above, when standard method (B) is adopted, the last of N×256 bytes is terminated with the EODL command.

The configuration of the display list DL has been described in detail above, and the production control CPU 63 issues the completed fixed byte length display list DL to the VDP circuit (ST7 to ST8). FIG. 22 is a flowchart illustrating a DL issuing process (ST8 in FIG. 20) in which the production control CPU 63 directly accesses the transfer port register TR_PORT of the transfer circuit 72 by WRITE and issues the display list DL to the drawing circuit 76. Note that the transfer port register TR_PORT is a type of data transfer register RGij that defines the operation contents of the data transfer circuit 72.

In order to implement the DL issuing process, it is first necessary to set necessary setting values in a plurality of data transfer registers RGij that define the operation contents of the data transfer circuit 72. Specifically, the transfer operation mode of the data transfer circuit 72 and the transmission route inside the data transfer circuit 72 are specified to a predetermined data transfer register RGij. Although the setting contents are not particularly limited, here, the data transfer operation is executed while checking the remaining capacity of the FIFO buffer regarding the CPU bus control section 72d and the transfer from the CPUIF section 56 via the ChB control circuit 72b. Set (ST20). Note that in the following description, the ChB control circuit 72b may be abbreviated as "transfer circuit ChB" for convenience.

Next, the total transfer size is set in a predetermined data transfer register RGij. As explained above, in this embodiment, the total amount of data in the display list DL is adjusted to an integral multiple of 256 bytes, so that value is set. Note that the total amount of data=256×N is also an integral number N times the minimum data amount Dmin of the data transfer circuit 72. Usually, the multiple N is 1 or 2, but in the following explanation, it will be assumed that N=1.

Here, since the transfer port register TR_PORT (hereinafter sometimes abbreviated as transfer port) is a 32-bit register, the production control CPU 63 executes a register WRITE operation for the transfer port TR_PORT every 32 bits. It turns out. Therefore, the value of the management counter CN for managing the number of register WRITEs is initialized to 64 (ST21). Note that when adopting the non-adjustment method (C), at this timing, a data transfer amount that is an integral multiple of the minimum data amount Dmin is determined and the management counter CN is set.

Since the initial settings are completed through the above processing, next, the data transfer operation via the transfer circuit ChB is set to the start state (ST22), and the settings are made to the predetermined drawing register RGij that defines the operation of the drawing circuit 76. Based on the value, a drawing operation is started (ST23). As a result, the rendering circuit 76 (display list analyzer) can quickly and smoothly analyze the instruction command string for which the performance control CPU 63 performs a register WRITE operation on the transfer port TR_PORT.

Note that the fact that the instruction commands listed in the display list DL are limited to instruction commands whose command length is an integral multiple of 32 bits also contributes effectively to quick and smooth Analyze processing. Timings t1, t2, t3, and t4 in FIG. 28(a) indicate the operation timings of step ST23. Note that since the display list DL issuing process (ST8) ends quickly, the time span required for the issuing process is not shown in FIGS. 28 to 29.

Subsequently, it is confirmed whether the settings in step ST22 worked (ST24). This is because the initial setting of each part of the data transfer circuit 72 takes more processing time than the register WRITE operation (setting operation) by the production control CPU 63, so subsequent instructions are not given to the data transfer circuit 72 in an incomplete state. This is because there is no If the operation does not start even after waiting for a predetermined period of time, the serious abnormality flag ABN is set and the DL issuing process ends (ST25). As a result, the WDT circuit 58 then functions and the composite chip 50 is abnormally reset (ST10).

In addition, in order to avoid resetting the CPU circuit 51, the performance control CPU 63 may output a predetermined keyword string to the pattern check circuit CHK and reset only the VDP circuit 52 abnormally based on the reset signal RST. As mentioned above.

However, normally, the setting in step ST22 is completed quickly, so next, after confirming that the FIFO buffer (32 bits x 130 stages) of the CPU bus control unit 72d is not full (ST26) , writes instruction commands to the transfer port TR_PORT line by line in order from the first line configuring the display list DL (ST28).

Then, while decrementing the management counter CN (ST29), the processes of steps ST26 to ST29 are repeated until the management counter CN becomes zero (ST30). In the case of this embodiment, since the minimum data amount Dmin is defined in the data transfer circuit 72, the data transfer operation is executed at the timing when the minimum data amount Dmin is accumulated in the FIFO buffer, and the data transfer operation is performed intermittently. This is a typical transfer operation.

In any case, in this embodiment, the DL issuing process (ST28) is quickly completed, but in the unlikely event that the settings in the VDP register RGij become inconsistent due to the influence of noise, etc. In the determination, the FIFO buffer full state may not be resolved even after waiting for a predetermined period of time. In such a case, initialization data is set in a predetermined VDP register RGij to initialize the drawing circuit 76 and data transfer circuit 72, and then the serious abnormality flag ABN is set to start the DL issuing process. Finish (ST27).

By the way, at this timing, the data transfer circuit 72 and the drawing circuit 76 have already started operating and have completed some processing, so the contents of the drawing register RGij are used for the initialization process of the drawing circuit 76. In the maintained state, (1) all internal parameters that may be set by the display list DL are set to their initial values, (2) all internal control circuits are set to their initial states, (3) This includes initializing the GDEC 75 and (4) initializing the cache state of the AAC area. Similarly, the initialization processing of the data transfer circuit 72 includes initialization processing of the entire data transfer up to that point, such as clearing the FIFO buffer. As a result, the status information indicating the operating state of the data transfer circuit 72 changes to a predetermined value (a value indicating that the entire data transfer is being initialized).

Note that in the initialization process of step ST27 described above, the contents of the drawing register RGij are maintained, but the contents of a predetermined drawing register may be initialized. The predetermined drawing registers that are cleared to initial values include (a) an execution control register that sets the start of drawing execution (see ST23 in FIG. 22), (b) a status register that indicates the execution status of the drawing circuit 76, and ( c) Contains a status register that identifies the position of the display list currently being processed.

In any case, as a result of setting the serious abnormality flag ABN, the WDT circuit 58 and the production control CPU 63 function, and either the composite chip 50 or the VDP circuit 52 is abnormally reset (ST10a), so the drawing circuit 76 Processing to initialize the data transfer circuit 72 is not necessarily essential. On the other hand, when the drawing circuit 76 and data transfer circuit 72 are initialized, abnormality recovery can be expected as a result, so the process returns to step ST20 and the DL issuing process is restarted without setting the serious abnormality flag ABN. It is also suitable to carry out.

This point is the same in the process of step ST25, and it is preferable to initialize the data transfer circuit 72 and the drawing circuit 76 and then return to the process of step ST20 without setting the serious abnormality flag ABN. However, in such a case, the number of times the DL issuing process is re-executed is counted, and if the number of re-executing times exceeds the limit value, the serious abnormality flag ABN is set and the DL issuing process is ended.

FIG. 22(b) is a diagram illustrating a normal operating state for confirmation. As shown in the figure, the issued display list DL is analyzed by the drawing circuit 76 (display list analyzer) in the order of the listed instruction commands, and operations based on each instruction command are executed. This operation is executed in parallel with the display list DL issuance process and the data transfer operation of the data transfer circuit 72 (ST26 to ST30).

For example, by executing the instruction command (TXLOAD), the necessary texture is read from the CGROM 55 and acquired in the AAC area (a), and then the GDEC 75 is automatically started and decoding is performed. The subsequent data is developed into a predetermined index space. Also, depending on the instruction command, the geometry engine 77 and others function, but in any case, the image data corresponding to the display list DL is completed in the frame buffers FBa and FBb by the cooperation of each part of the drawing circuit 76. That will happen.

Next, the case where the display list DL is issued via the DMAC circuit 60 will be explained based on FIG. 23. Although not limited in any way, of the first to fourth DMA channels built into the DMAC circuit 60, the third DMA channel will be used.

In the embodiment of FIG. 23, first, a clear value is set in a predetermined data transfer register RGij and a predetermined drawing register RGij, respectively, and the data transfer circuit 72 and the drawing circuit 76 are initialized (ST20). This process is the same as the error process in step ST27 of FIG. 22, and the internal circuit of the data transfer circuit 72 including the FIFO buffer is initialized, and the status bit of the data transfer register indicating the progress state of data transfer is set to the initial value. The bit indicating that the entire data transfer is being initialized becomes a predetermined value.

The same applies to the drawing circuit 76, and the above-mentioned (1) setting the internal parameters to initial values, (2) setting the internal control circuit to the initial state, (3) initializing the GDEC 75, and (4) ) Includes processing to initialize the cache state of the AAC area. Further, in the initialization process of the drawing circuit (ST20 in FIG. 23), the above-described predetermined drawing register RGij may be initialized. Note that in the process of FIG. 22, such initialization process may be executed first.

In the process of FIG. 23, next, it is confirmed that the initialization process has been completed normally by reading a predetermined status register RGij that specifies the operating states of the data transfer circuit 72 and the drawing circuit 76 (ST21). If initialization is not possible, a serious abnormality flag ABN is set and the process ends (ST22). However, such a situation almost never occurs in reality.

Next, the transfer operation mode of the data transfer circuit 72 and the transmission route inside the data transfer circuit 72 are set in a predetermined data transfer register RGij. Although the setting contents are not particularly limited, here, it is set that the transfer protocol from the CPU IF section 56 to the ChB control circuit 72b and the transfer protocol to the CPU bus control section 72d follows the settings for the DMAC circuit 60 (ST23). ).

Next, the total transfer size is set in a predetermined data transfer register RGij. As in the case of FIG. 22, the total amount of data=256. Note that when adopting the non-adjustment method (C), the total transfer size that is an integral multiple of the minimum data amount Dmin is determined and set at this timing. Next, the drawing operation of the drawing circuit 76 is started based on the set value to a predetermined drawing register RGij (ST25). Timings t1, t2, t3, and t4 in FIG. 28(a) are also the operation timings of step ST25. Then, after starting the operation of the DMAC circuit 60 (ST26), the data transfer operation of the data transfer circuit 72 is started (ST27).

The processing for starting the operation of the DMAC circuit 60 is as shown in FIG. ST40). The detailed operation is the same as the process shown in FIG. 24, and is divided into a process for prohibiting DMAC transfer (ST53) and a subsequent standby process (ST54).

The reason for providing such processing is that (1) in other embodiments, the DMAC circuit 60 (third DMA channel) may be used in the main control processing or timer interrupt processing (FIG. 20); and (2) In other embodiments in which the process of step ST5 in FIG. 20 is not provided, the DMAC circuit 60 that has started issuing the display list DL may not be able to complete the DL issuing operation within its operation cycle (δ). This takes into consideration things that could happen.

In the above-mentioned exceptional situation, if new setting values (such as contradictory setting values) are additionally set for the DMAC circuit 60 in operation, normal DMA operation will not be guaranteed at all, and serious troubles may occur. Although this is a concern, by providing the process in step ST40, normal operation based on the subsequent set values is ensured. In other words, even in the modified embodiment in which the present embodiment is partially modified, normal DMA operation can be realized thereafter regardless of the preceding trouble.

After executing the process of step ST40, which has the above-mentioned significance, next, the operating conditions of the DMAC circuit 60 are set (ST41). Specifically, as shown in FIG. 8, the cycle steal transfer mode is selected and one operand transfer is 32-bit transfer x 2 times. In addition, the Source address is the address of the list buffer area (DL buffer BUF) of the RAM 59, so it should be recognized as increasing sequentially, while the Destination address is the transfer port TR_PORT, so it should be a fixed value. .

Next, the start address of the DL buffer BUF of the RAM 59 is set in a predetermined operation control register REG that defines the operation of the DMAC circuit 60 (ST42), and the address of the transfer port TR_PORT, which is the transfer destination address, is set (ST43). ). Further, after setting the total transfer size, that is, the total data amount of the display list DL to 256 bytes (ST44), the DMA operation of the DMAC circuit 60 is started (ST45).

By the way, the explanation so far has been based on the assumption that the actual bit lengths of the instruction commands are all integral multiples of 32 bits. However, since the structure of the display list DL and the instruction command is not necessarily limited, such a case will be described below.

For example, when the total data amount X of the display list DL is an arbitrary value X that is not an integral multiple of 32 bits, including the case where the above-mentioned non-adjustment method (C) is adopted, in the process of step ST44, this arbitrary value is adjusted to an appropriate transfer amount MOD, and then the total transfer size setting process is executed. Here, the appropriate transfer amount MOD is defined based on the settings for one-operand transfer and the minimum data amount Dmin (bytes) of the data transfer circuit 72.

Specifically, if the one-operand transfer setting is N bytes x M times, the transfer amount MOD is adjusted to a value that is an integral multiple of N x M (bytes) and an integral multiple of Dmin (bytes). be done. For example, if N×M=8×4 and Dmin=256, the arbitrary value X (=300) bytes is adjusted to the transfer amount MOD (=512) bytes.

As described above, including the general theory, the DMA operation of the DMAC circuit 60 starts with a cycle steal transfer operation as shown in FIG. In this case, each 32 bits are transferred to the transfer port TR_PORT. The transferred data is then transferred to the drawing circuit 76 via the transfer circuit ChB.

In order to realize such an operation, in this embodiment, following the process in step ST45, the data transfer circuit 72 starts a transfer operation and ends the process (ST27). Thereafter, the data transfer circuit 72 receives the instruction command string of the display list DL from the DMAC circuit 60 using the minimum data amount Dmin as one unit, and transfers this to the drawing circuit 76. Then, the drawing circuit 76 executes a drawing operation based on the instruction command of the display list DL. Therefore, after the process in step ST27, the production control CPU 63 can start the process in step ST11 in FIG. You can also control lamp effects and motor effects.

FIG. 23(c) illustrates the contents of this operation. Prior to DMA transfer, the operation of the drawing circuit is started (ST25), and the display list analyzer of the drawing circuit 76 quickly and smoothly executes Analyze processing, and other operations such as the GDEC 75 and the geometry engine 77 are performed. Based on this, image data for one frame is generated in frame buffers FBa and FBb for each display device DS1 and DS2.

By the way, the configuration of FIG. 23 in which the DL issuing process ends with the process of step ST27 is not necessarily limited. For example, as shown in FIGS. 30 and 31, when the audio effects, lamp effects, and motor effects are controlled by another CPU, after the processing in step ST27, the DMAC circuit 60 and the data transfer circuit 72 operate normally. It is preferable to check. FIG. 24 is an operation following step ST27 in FIG. 23, and is a flowchart illustrating normal operation confirmation processing.

First, referring to a predetermined status register, it is confirmed that the transfer operation of the DMAC circuit 60 has been completed normally (ST50). Also, it is confirmed that the data transfer circuit 72 has finished the transfer operation (ST51). Normally, the DL issuing process shown in FIG. 23 is completed through such a route.

On the other hand, even if you wait for a certain period of time. If the operation of the DMAC circuit 60 has not been completed, or if the data transfer circuit 72 has not completed its transfer operation, a clear value is set in a predetermined VDP register RGij for the drawing circuit 76 and the data transfer circuit 72. Then, the DL issuing process is initialized (ST52). This is an operation based on the fact that the display list DL issuance process has not been completed normally, and specifically, the content is the same as the error process in step ST27 in FIG. 22 and the initial process in step ST20 in FIG. be.

That is, in this case as well, since the drawing circuit 76 has already started operating and has completed some processing, the initialization process of the drawing circuit 76 includes (1) the possibilities set by the display list DL; (2) set all internal control circuits to their initial states; (3) initialize the GDEC 75; (4) initialize the cache state of the AAC area. It includes becoming

Next, a new DMA transfer operation is prohibited (ST53), and the process waits for the transfer operation of one operand in progress to be completed (ST54). As described above, in this embodiment, two 32-bit transfers are used as one operand, in order to avoid sudden initialization of the DMAC circuit 60 in operation.

When this preparatory work is completed, a clear value is set in a predetermined operation control register REG that defines the operation of the DMAC circuit 60, and the DMAC circuit 60 is initialized (ST52). Then, the serious abnormality flag ABN is set and the DL issuing process is completed. In this case, since abnormality recovery can be expected through the processing in steps ST52 and ST55, it is also preferable to return to step ST20 in FIG. 23 and re-execute the DL issuing process without setting the serious abnormality flag ABN. be. However, it is necessary to count the number of times the DL issuance process (ST23 to ST27) is re-executed, and if the number of re-executions exceeds the limit value, it is necessary to set the serious abnormality flag ABN and finish the DL issuance process.

Next, the main control process when using the preloader 73 will be explained based on FIG. 25. The process in FIG. 25 is similar to the process in FIG. 20, but first, the content of start condition determination (ST5') is different. That is, in the embodiment using the preloader, at the start of each operation cycle, the status information of the drawing circuit 76 and the preloader 73 is read accessed to confirm that the drawing operation based on the display list DL1 has been completed, and that the drawing operation based on the display list DL2 has been completed. It is confirmed that the preload operation based on is completed (ST5').

As shown in the time chart of FIG. 29(a), the preloader 76 performs a prefetch operation (preload operation) during the operation cycle (T1 to T1+δ), for example, based on the display list DL1 issued in the operation cycle (T1). You should have finished. Further, the drawing circuit 76 should have finished the drawing operation based on the display list DL1 during the operation cycle (T1+δ to T1+2δ), for example, based on the operation start command instructed at the operation cycle (T1+δ).

Therefore, in (ST5'), the status information of the VDP register RGij regarding the drawing circuit 76 and the preloader 73 is read accessed to confirm the above-mentioned normal operation. In FIG. 29(a), normal operation is confirmed at the determination timings of operation cycles T1, T1+δ, T1+2δ, and T1+4δ, but a state in which the preload operation is not completed is shown at the determination timing of operation cycle T1+3δ. .

When such an abnormality occurs, the abnormality flag ER is incremented (ER=ER+1) and the process proceeds to step ST9. Therefore, as in the case of the embodiment of FIG. 20, frame drops occur. That is, since the display area switching process (ST6) is skipped, the same screen is displayed again. The operating period (T1+3δ to T1+4δ) shown in FIG. 28(a) indicates the operating state.

Further, in the determination in step ST5', if the start condition is not satisfied, the drawing circuit 76 is not instructed to start the drawing operation based on the rewrite list DL' (PT10), so the drawing circuit 76 is inactive. Also, no new display list is generated. Note that in FIG. 29A, timings t0, t2, and t4 indicate the operation timings of the drawing operation start instruction (PT10), more precisely, the timings of step ST26 in FIG. 26.

The case where the determination in step ST5' is non-conformity has been described above, but in a normal case, after the display areas of frame buffers FBa and FBb are toggled (ST6), the rewriting list DL is sent to the drawing circuit 76. A drawing operation based on ' is started (PT10). The specific contents are as shown in FIG. 26, and the drawing circuit 76 receives data from the DL buffer BUF' of the external DRAM 54 via the data transfer circuit 72 (transfer circuit ChB) under the control of the performance control CPU 63. The rewriting list DL' is acquired and the drawing operation is executed.

Prior to explaining the flowchart of FIG. 26 that implements this operation, the operation of the preloader 73 will be confirmed. The preloader 73 performs a pre-read operation (preload) of the CGROM 55 based on the display list DL acquired one operation cycle ago. has been completed, and the pre-read data has already been stored in the preload area secured in the external DRAM 54. In addition, for the texture load command (TXLOAD) listed in the display list DL, its Source address is rewritten to the address of the preload area and stored in the DL buffer BUF' of the external DRAM 54 as the rewrite list DL'. ing.

Note that in this rewriting process, there is no change in the total amount of data in the display list DL, and the total amount of data in the rewriting list DL' is the same as that in the display list DL. Further, the display list DL is created using the standard method (B), and the last of the rewrite list DL' is an EODL command, as in the case of the display list DL.

Based on the above, referring to FIG. 26, the production control CPU 63 first sets clear values in a predetermined data transfer register RGij and a predetermined drawing register RGij, and then controls the data transfer circuit 72 and the drawing circuit 76. Initialize (ST20). This process has the same content as the process of ST20 in FIG. 23. Next, it is confirmed that this initialization process has been completed normally (ST21), and if the initialization is not completed even after a predetermined period of time has elapsed, the serious abnormality flag ABN is set and the process is terminated (ST21). ST22).

Normally, the initialization of the data transfer circuit 72 and the drawing circuit 76 is completed normally, so next, the transmission route inside the data transfer circuit 72 is set to a predetermined data transfer register RGij (ST23). Specifically, data is set to be transferred from the external DRAM 54 to the drawing circuit 76 via the ChB control circuit 72b (ST23). Next, the start address of the DL buffer BUF' of the external DRAM 54 in which the rewrite list DL' is stored is set in a predetermined data transfer register RGij (ST24).

Further, for this rewrite list DL', the total transfer size is set in a predetermined data transfer register RGij (ST25). As explained above, the total amount of data in the rewriting list DL' is the same as the total amount of data in the display list DL, and specifically, for example, 256 bytes.

Next, the drawing operation of the drawing circuit 76 is started based on the set value to a predetermined drawing register RGij (ST26). Timings t1, t2, t3, and t4 in FIG. 28(a) are also the operation timings of step ST26. Then, based on the set value to a predetermined data transfer register RGij, the operation of the data transfer circuit 60 is started, and the process ends (ST27). Thereafter, the effect control CPU 63 does not particularly involve in the operation of the data transfer circuit 72 or the drawing circuit, and shifts to display list generation processing (ST7) to be executed in the next operation cycle.

On the other hand, the drawing circuit 76, which starts operating at the timing of step ST26, executes a drawing operation based on the rewrite list DL', and generates image data based on the rewrite list DL' in the frame buffers FBa and FBb. In this operation, the drawing circuit 76 exclusively performs READ access to the preload area without performing READ access to the CGROM 55, so that the series of drawing operations can be quickly completed.

The processing contents of step PT10 have been explained above, so to continue the explanation by returning to FIG. It is created based on the standard method (B) (ST7). For example, in the operation cycle (T1) shown in FIG. 29(a), the display list DL to be referred to by the drawing circuit 76 is created in the next cycle, the operation cycle (T1+δ).

Next, the production control CPU 63 issues the created display list DL to the preloader 73 instead of the drawing circuit 76 (PT11). The specific contents of the operation are as shown in FIG. First, regarding the embodiment in which the preloader 73 is not used (FIG. 20), the effect control CPU 63 issues the display list DL directly to the drawing circuit 76 (FIG. 22), and the case in which the display list DL is issued via the DMAC circuit 60. The case of issuing (FIG. 23) is shown, but almost the same operation is shown in FIGS. 27(b) and 27(c), except that the issuing destination is the preloader 73 in FIG. .

FIG. 27(a) is a flowchart explaining the operation of FIG. 27(b), and is almost the same as the flowchart of FIG. 22. However, it is set that the data transfer operation is to be performed from the CPUIF section 56 via the ChC control circuit 72c, and the remaining capacity of the FIFO buffer of the CPU bus control section 72d is checked (ST20). In addition, in the following description, the ChC control circuit 72c may be abbreviated as "transfer circuit ChC" for convenience.

Next, the total transfer size (for example, 256 bytes adjusted by the standard method (B)) is set in a predetermined data transfer register RGij, and the management counter CN is initialized to 64 (ST21). Next, the data transfer operation via the transfer circuit ChC is set to the start state (ST22), and the preload operation is started based on the set value to the preload register RGij that defines the operation of the preloader 73 (ST23).

As a result, after that, the preloader 73 executes the necessary analysis processing for each instruction command that the production control CPU 63 writes to the transfer port TR_PORT, and when it detects an instruction command (TXLOAD) to read the CGROM 55. , the texture is preloaded and stored in the preload area of the DRAM 54. In addition, the rewrite list DL' in which the source address of the texture has been changed is stored in the DL buffer area BUF' of the DRAM 54.

Note that timings t1, t3, and t5 in FIG. 29(a) actually indicate the operation timings of step ST23 in FIG. 27. However, also in this embodiment, if some abnormality occurs during the display list DL issuance process, the process of step ST25 or step ST27 is executed. Specifically, the operations of the data transfer circuit 72 and the preloader 73 are initialized, and the display list DL issuance processing (ST20 to ST30) is re-executed to the extent possible. The initialization process of the preloader 73 includes erasing the incomplete rewrite list DL' and clearing the preload area in which new preload data is stored.

Although the cases in which the preloader 73 is used and the cases in which it is not used have been described above in detail, the specific operation contents are not particularly limited. FIG. 28(b) shows an embodiment in which the display list generated by the production control CPU 63 is issued to the drawing circuit 76 not with the generated operation cycle but with a delay of one operation cycle δ. In such an embodiment, the drawing circuit 76 can use almost the entire time of one operating period (δ), reducing the possibility of frame drops.

Further, FIG. 29(b) shows an embodiment in which the display list generated by the production control CPU 63 is issued to the preloader 73 not with the generated operation cycle but with a delay of one operation cycle. In this case, the preloader 73 can use almost the entire time of one operation period (δ) to perform the predoze operation, so that the possibility of dropping frames is reduced in this case as well.

In addition, in the explanation so far, the composite chip 50 is used, but it is not necessarily necessary to integrate the production control CPU 63 and the VDP circuit 52 into one element. Furthermore, in the above embodiment, the entire performance control is controlled by a single CPU (performance control CPU 63), but the upstream CPU and the downstream performance control CPU 63 cooperate with each other to control the performance. Control operations may also be performed.

FIGS. 30-31 are block diagrams illustrating such an embodiment. As shown in the figure, in this embodiment, the upstream performance control CPU controls the audio performance, lamp performance, and motor performance. On the other hand, the CPU circuit 51 on the downstream side controls only the image presentation based on the control command CMD' received from the presentation control CPU.

In the case of adopting such a configuration, the CPU circuit 51 does not need to execute the process of step ST12 in FIG. 20(a) and the process of FIG. A list DL can be generated, and more complex and advanced image effects such as 3D (Dimension) can be realized. In such a case, the display list becomes large, but in that case, the total amount of data in the display list DL is adjusted to 512 bytes or more (N x 256 bytes) by adding a dummy command. .

Further, since the operation of the downstream side CPU circuit 51 is specialized for image production control, it is also possible to confirm that the drawing operation is completed after the display list DL is issued. The lower part of FIG. 22 shows an example of operation control in this case, and if the drawing operation is not completed even after the limit time is exceeded, the serious abnormality flag ABN is set and the process ends (ST32). Note that since the downstream CPU circuit 51 only performs image rendering control, it may simply wait for the completion of the drawing operation in an infinite loop.

When adopting such a configuration, the start condition determination (ST5) in FIG. 20(a) can be repeated for a predetermined period of time. Even with this configuration, if the delay in completing the drawing operation is not too long, the only problem that occurs is that there is a delay in switching between the display area (0) and the display area (1). That is, as in the operation cycle T1+3δ shown in FIG. 32(a), in one operation cycle in which the display operation is repeated twice, frames are dropped only in the first half, and normal frames are displayed in the second half.

This point is the same when using a preloader, and the start condition determination (ST5') in FIG. 25(a) can be repeated for a predetermined period of time. If there is a slight delay, frames are dropped only in the first half, and normal frames are displayed in the second half, as shown in the operation cycle T1+3δ shown in FIG. 32(b). However, if the completion of the drawing operation is significantly delayed, a complete frame drop will occur, similar to the operation cycle T1+3δ in FIG. 28(a), and if this situation continues, the WDT circuit 58 will It will start. This point is the same even when the preloader is not used.

Furthermore, when the control operation of the CPU circuit 51 is specialized for image production control, in an embodiment that employs DMA transfer, as shown in the lower part of FIG. The completion of the operation of the DMAC circuit 60 and the completion of the operation of the DMAC circuit 60 are determined (ST50' to ST52'). If any of the operations does not end normally, the operations of the data transfer circuit 72 and the drawing circuit 76 are initialized, and the same processes as steps ST53 to ST55 (ST55' to ST57') are executed. Ru. Note that in this case as well, it is preferable to re-execute the DL issuing process a predetermined number of times.

An embodiment has been described above in which an index space of a horizontal size completely matching the number of horizontal pixels of each display device is constructed as frame buffers FBa and FBb of the main display device DS1 and sub display device DS2. FIG. 33(a) shows this relationship for confirmation, and shows that the drawing area (W×H) in the virtual drawing space and the effective data area (actual drawing area W×H) in the index space are , both show cases where the number of horizontal/vertical pixels matches the number of horizontal/vertical pixels of the display device.

In such a correspondence relationship, the drawing operation in the virtual drawing space by the display list DL is not necessarily limited to the drawing area (W×H), so for example, as shown by the left inclined line in the upper part of FIG. 33(a), , by temporally moving the drawing position of the drawing image (W'×H') that exceeds the drawing area (W×H), the actual drawing area W×H shown by the right-slanted line at the bottom of FIG. 33(a) It becomes possible to move the drawing content vertically/horizontally/diagonally as appropriate.

Further, in order to perform such an effect, for example, as shown in FIG. 33(b), an index space with a horizontal size W larger than the number of horizontal pixels of the display device may be provided. In this case, the drawing area W×H in the virtual drawing space defined by the instruction command L12 (SETDAVF) of the display list DL is larger than the actual drawing area w×h corresponding to the number of horizontal/vertical pixels of the display device. Set. Note that in the lower part of FIG. 33(b), the actual drawing area w×h is indicated by a right-sloping line.

The vertical and horizontal dimensions of the actual drawing area w×h are specified as the number of display lines and the number of horizontal pixels of the display device in the process of step SS30 in FIG. 20, and the upper left end point of the actual drawing area w×h is In step SS31 of 20, the vertical/horizontal display start position is set in a predetermined display register.

On the other hand, the base point address (X, Y) in the index space is set in a predetermined drawing register by the display list instruction command L11. As explained above, specifically, the upper left base point address on the index space IDX is defined as (0,0), for example, by the environment setting instruction command L11 (SETDAVR). If the upper left end point of the actual drawing area w x h is moved appropriately in the steady processing, the drawing contents of the actual drawing area W x H shown by the right-slanted line at the bottom of FIG. 33(b) can be changed vertically, horizontally, and diagonally. will be moved accordingly.

As explained with reference to FIG. 20, the VDP register RGij related to steps SS30 to SS32 is set to be write-prohibited after the initial setting (second prohibition setting SS34), but at the timing of executing the above effect, a predetermined write is disabled. This prohibition setting is canceled by writing a cancellation value to the VDP register RGij.

By the way, in the above embodiment, the first type and the second type of prohibition setting registers are utilized to uniformly set a predetermined system control register RGij and a predetermined initial setting VDP register RGij to a write-protected state. (see SS33 and SS34 in FIGS. 20 and 25) to prevent the values set in these registers from being changed thereafter due to the influence of noise or the like. However, it is also preferable to repeat the setting process at predetermined time intervals for the set value of the important system control register RGij without performing such a write prohibition setting.

FIG. 34 is a diagram illustrating the processing in such a case, and the setting values to be set in the initial setting process (ST3) are summarized in the setting value table SETTABLE stored in the control memory 53 (PROGMROM). . Although the explanation is omitted in step ST3 of FIG. 20, (a) executing the initial setting process based on the initial value setting table SETTABLE, and (b) the contents of the initial value setting table SETTABLE are as follows. , the embodiment of FIG. 20 is also substantially the same as described below.

In any of the embodiments, the set value table SETTABLE is composed of a plurality of sets (N sets) each including a register address value of the VDP register RGij and a set value for the register RGij. Although not particularly limited, the register address value is fixed to 16 bits long, and the setting value is fixed to 32 bits long, and each has a fixed length, so the data capacity of the initial value setting table SETTABLE is 6 x N bytes (=48t ×Nbit) length, and there are N VDP registers RGij.

However, in the embodiment of FIG. 20, the initial value setting table SETTABLE is accessed only once, and all N VDP registers RGij are initialized only once, whereas in the embodiment of FIG. The N VDP registers RGij are divided into N1 VDP registers RGij, which are initialized only once, and N2 VDP registers RGij, which are repeatedly initialized every 1/30 seconds after the first initialization. It is classified.

In the embodiment of FIG. 34, the setting values that are repeatedly initialized include (1) setting values for DMA transfer operation, (2) setting values for VRAM, (3) setting values for interrupts, and (4) display values. Setting values regarding the circuit 74 and (5) setting values regarding the drawing circuit 76 are included.

(1) Setting values related to DMA transfer operation are, for example, setting values that are prerequisites for the operating conditions specified in step ST41, and are fixed regardless of the difference in operating conditions in FIG. 23(c) or FIG. 27(c). These are the basic settings that are applied. Specifically, (a) how much of the FIFO buffer (N stages) built in the DAMC circuit 60 must be released to make a transfer request to the transfer source (for example, 1/2 stage of the total); b) Contains setting values such as whether to perform handshake operation with the transfer destination and transfer source (for example, No).

Furthermore, (2) the VRAM setting value includes the refresh cycle of the refresh operation. By operating the built-in VRAM 71 at this refresh cycle, spontaneous discharge of stored data is prevented. Next, (3) setting values related to interrupts include values that specify the error type that causes the interrupt request and the output terminal of the interrupt signal (internal terminal of the built-in CPU); for example, (a) when the drawing circuit 76 If it freezes, a drawing abnormality interrupt will be generated to the CPU circuit 51 (interrupt enabled state, see FIG. 20(d)); (b) When the display device DS1 starts VBLANK, a VBLANK start interrupt will be generated to the CPU circuit 51. It includes setting values such as what will occur (see FIG. 20(c)).

Note that this embodiment uses a composite chip 50 in which a CPU circuit 51 and a VDP circuit 52 are integrated, but if they are separate chips, the output terminal from which the VDP circuit 52 outputs an interrupt signal is connected to the CPU circuit. 51 external interrupt input terminal.

(4) Setting values related to the display circuit include (a) horizontal/vertical start position of each frame buffer (refer to SS31), (b) setting values related to the horizontal synchronization signal of each display device, (c) setting values for each display device. (d) setting values for the scaler, (e) setting values for the number of horizontal pixels and display lines of each display device (SS30), etc.

(5) The setting values regarding the drawing circuit 76 include the setting value of the freeze time until a drawing abnormality interrupt occurs. This setting value is set, for example, as an integral multiple of the period of the vertical synchronization signal. As explained in FIG. 20(d), if the drawing circuit 76 does not access the VRAM during the freeze period defined here, the drawing circuit 76 is individually reset (ST16b), and the operating parameters for the drawing circuit 76 are It is reset (ST16c).

As mentioned above, in this embodiment, important setting values are repeatedly reset at predetermined intervals, so even if the bits of the setting values become garbled due to the influence of noise, etc., the abnormality can be immediately corrected. will be recovered. Furthermore, in this embodiment, unlike the embodiment shown in FIG. 20, the first type and second type inhibition setting registers RGij are not set to a write-protected state, so there is no need to go through a somewhat complicated prohibition release process. , the rewriting process can be executed freely.

As described above, in the embodiment so far, (1a) the operation of the drawing circuit 76 is in a frozen state after a predetermined freeze time has elapsed, or (1b) the drawing circuit 76 detects an unreasonable instruction command in the display list DL. , a configuration in which a drawing abnormal interrupt occurs from the drawing circuit 76 of the VDP circuit 52 to the CPU circuit 51 has been described (see FIG. 20(d)). When a drawing abnormality interrupt occurs, a configuration is adopted in which the cause of the interrupt is determined (ST16a in FIG. 20(d)), and processing is executed according to the determination result (ST16c to ST16d).

However, according to the inventor's experiments, even under harsh operating conditions with a lot of noise, abnormal drawing interrupts almost never occur. Therefore, in order to reduce the control burden, it is necessary to uniformly shift to infinite loop processing without providing the interrupt cause determination processing (ST16a) (see FIG. 25(b)), or to shift to the pattern check circuit CHK (see FIG. 6(b)) is also suitable (see ST17a in FIG. 25(c)).

In this case, either the WDT circuit 58 is activated after a predetermined period of time and the entire composite chip 50 is reset, or only the VDP circuit 52 is immediately reset (see FIG. 6(b)). reference). Note that when the VDP circuit 52 is reset based on the reset keyword output processing (ST17a), after confirming that the reset operation has completed normally and arranging the stack area for storing the return address (ST17b), For example, the process will proceed to step ST4 or ST13.

In addition, in this embodiment, an abnormality determination process (ST5 in FIGS. 20 and 25) is provided to determine whether the operation of the drawing circuit 76 is completed every 1/30 seconds. Alternatively, a drawing abnormality interrupt process (FIG. 25(d)) may be provided that does not execute anything. As shown in FIG. 25(d), in this configuration, when a drawing abnormality interrupt occurs, the IRET (Interrupt Return) command is immediately executed and the process returns to the main control process, so that the frozen state of the drawing circuit 76 can continue as it is. become. However, in this embodiment, the number of dropped frames is counted by the abnormality flag ER in the process of step ST5 in FIGS. The configuration in (d) is substantially the same as the configurations in FIG. 25(b) and FIG. 25(c).

Furthermore, in order to further reduce the control burden, it is also preferable to set the VDP circuit 52 to a drawing abnormality interrupt disabled state at the time of initial setting (see step ST3 in FIGS. 20 and 25). In addition, when adopting a configuration in which the default state at power-on is a state in which drawing abnormal interrupts are disabled, (a) write a predetermined system control register RGij that should set a permission value that specifies permission/prohibition of abnormal interrupts; Either the prohibited state is set, or (b) the prohibited value is repeatedly written to the system control register RGij at predetermined time intervals.

At first glance, this configuration seems superior to the configurations in FIG. 25(b) and FIG. 25(b). However, for all models of gaming machines of this type, (a) drawing abnormal interrupts are uniformly set to a disabled state, rather than (b) uniformly set to an enabled state and then changed for each model. It is better to select either the configuration shown in FIG. 20(d) or any of the configurations shown in FIGS. 25(b) to (d) from the viewpoint of generalization of the control program. Note that in the former configuration (a), it is necessary (complicated) to change the initial setting routine (see step ST3 in FIGS. 20 and 25) for each model.

In addition, as a further modified embodiment, it is also suitable to utilize the audio circuit SND built in the composite chip 50. FIG. 35 is a block diagram showing such an embodiment. As is clear from comparing FIG. 35 with FIG. 6, this embodiment eliminates the need for the audio processor 27 and audio memory 28, and also eliminates the need for the data bus (8 bits) and address bus (2 bits) of the CPU circuit 51. Therefore, external wiring to the audio circuit is not required. Furthermore, since there is no transmission line for the underflow signal UF, the possibility that the composite chip is erroneously and abnormally reset due to noise superimposed on this UF transmission line is also avoided.

Furthermore, in this embodiment, in response to eliminating the audio memory 28, the audio data to be stored in the audio memory 28 is stored in the CGROM 53. FIG. 36(d) shows the storage contents of the CGROM 53. The CGROM 53 includes sound ROM header information, phrase header information HD, a large number of phrase data PH obtained by compressing a group of audio data, and an audio circuit. A large number of sound commands SCMD that define the operation of the SND are permanently stored.

As shown in the figure, the sound ROM header information is stored starting from the first address SNDst, and subsequently, phrase header information HD of data size HDvl is stored starting from the first address HDst. Further, phrase data PH of data size PHvl is stored from the first address PHst, and sound command SCMD of data size SCMDvl is stored from the first address SCMDst.

Here, the sound ROM header information specifically includes the start address HDst of the phrase header HD area, the data size HDvl of the phrase header HD area, the start address PHst of the phrase data area PH, and the start address PHst of the phrase data area PH. It means the data size PHvl, the start address SCMDst of the sound command area SCM, and the data size SCMDvl of the sound command area SCMD. These pieces of information are acquired by the internal circuit of the audio circuit SND when the power is turned on (see step SD4).

Furthermore, the phrase header information HD and the phrase data PH are transferred to the external DRAM 54 when the power is turned on, thereby speeding up subsequent READ access (step SD6). As described above, in this embodiment, the audio processor 27 and the audio memory 28 are eliminated to reduce the size and manufacturing cost, and while it is inexpensive and easy to increase the capacity, the CGROM 53 has a slow access speed. Overcoming weaknesses.

Based on the above, the initial setting process when the power is turned on will be explained based on FIG. 36(a). Note that these processes are executed as part of the process of step ST3 in FIGS. 20 and 25.

As explained with reference to FIG. 6(b), when the power is turned on or during an abnormal reset when the WDT 58 is activated, the audio circuit SND is hardware reset through the reset path 2 (step SD1). Further, when the production control CPU 63 detects an abnormality in the audio circuit SND, the audio circuit SND is hardware reset via the reset path 4B or 4C (step SD1). Note that the audio circuit SND may be hardware reset together with other circuits (72, 73, 74, . . . ) by the effect control CPU 63 operating the pattern check circuit CHK (step SD1).

In any of these cases, next, the production control CPU 63 confirms that the reset operation has been completed normally (step SD2), and then first sets the start address SNDst of the sound data area to the system control of the audio circuit SND. It is set in register RGij (step SD3). Next, by setting a predetermined value in a predetermined system control register, the sound ROM header information HD is stored in the internal circuit. Note that the sound ROM header information HD includes the six elements (HDst, HDvl, PHst, PHvl, SCMDst, SCMDvl) described above, as shown in FIG. 36(c).

Then, it is confirmed that the processing up to this point has operated normally, and if by any chance it cannot be completed normally, the audio circuits are individually reset using the reset path 4B or 4C. However, normally, since normal completion can be confirmed, the data transfer circuit 72 is then used to transfer the phrase header information HD and the phrase data PH to the external DRAM 54 (step SD6). Note that the data transfer circuit 72 is appropriately designated with the top address BGN of the transfer destination, the top address HDst of the transfer source, the total amount of transfer data HDvl+FDvl, etc.

Next, after setting in a predetermined system control register RGij that the phrase header information HD and phrase data PH exist in the external DRAM 54 instead of the CGROM 55 (step SD7), the group of phrase data PH transferred to the external DRAM 54 is set. The data start address BGN (sound RAM start address) is set in a predetermined system control register (step SD8). Thereafter, by completing other initial setting processing (step SD9), voice control operations become possible.

As explained earlier, the sound ROM header information, that is, the six pieces of information (HDst, HDvl, PHst, PHvl, SCMDst, SCMDvl) are stored in the internal circuit of the audio circuit SND (step SD4), and then , the production control CPU 63 can instruct necessary information such as phrase data in a relative value to the sound RAM start address BGN, and the audio circuit SND that receives this instruction converts the relative address value into an absolute address value. Then, the necessary audio processing will be performed. Since audio data such as phrase data is read-accessed not from the CGROM 55 but from the external DRAM 54, even complex and highly advanced audio effects can be smoothly realized.

Although various embodiments have been described in detail above, the present invention is not limited to pinball game machines, spinning drum game machines, etc., and the present invention is not limited to specific descriptions. For example, the power-on reset operation shown in FIG. 15 is activated based on the information of the vector table VECT secured from address 0x00000000 onward in the control memory 53. It is also preferable to place the vector table VECT in . FIGS. 37(a) and 37(b) illustrate address maps in such a case, and the address space CS0 of the production control CPU 63 is secured in a part (head area) of the CGROM 55.

Note that the main body of the CGROM 55 is not accessed by the performance control CPU 63 (access is not possible) and is accessed exclusively from the VDP circuit 52, so it is not located in the address space CSi. As explained above, the main body of the CGROM 55 can be composed of a plurality of memory devices, and in such a case, it is divided into device sections SPA0 to SPA1 by the process of step SP20 in FIG. 17(a). This enables optimal READ access that matches the characteristics of the memory device.

In any case, when the HBTSL terminal is set to H level, the memory type and bus width (64/32/16 bits) of the CGROM55 are set to 2-bit long HBTBWD terminal. It must be specified in advance based on a fixed input value to the 4-bit long HBTRMSL terminal.

In this embodiment, following the vector table VECT, bus parameters for optimizing READ access from the CGROM 55 must be stored in the top area of the CGROM 55. Although not essential, it is also suitable to store obfuscation parameters for deciphering the performance control program when it is obfuscated to make illegal analysis difficult.

When such a configuration is adopted, after the power is reset, the following operations 1 to 4 are automatically executed during the reset assertion period without going through program processing. First, the bus width of the address space CS0 is specified based on the input value to the HBTRMSL pin, and the memory type is automatically specified based on the input value to the BTBWD pin, and each is set in a predetermined VDP register RGij. (Movement 1). The types of memory in this case are roughly divided into memory devices that use a parallel I/F (Interface) format and memory devices that use a sequential I/F format.

Next, the obfuscation parameters stored in the CGROM 55 are loaded, and information necessary for canceling the obfuscation is automatically set in the internal circuit (operation 2). Furthermore, the bus parameters stored in the CGROM 55 are automatically acquired into the VDP register RGij (operation 3). Note that this operation 3 corresponds to the program processing of step SP63 in FIG. 18, and is automatically executed by the internal circuit.

Finally, in order to implement the bus parameters set in operations 1 to 3, the internal circuit automatically executes an operation corresponding to the program processing in step SP64 in FIG. 18 (operation 4). Then, at the timing when the bus parameter settings are implemented, the values of the program counter PC and stack pointer SP are automatically set based on the information in the vector table, and the execution of the boot program (initial setting program) is started. Ru.

According to the configuration shown in FIG. 37(a), the program processing at step SP1 in FIG. 15(a) is also unnecessary, and operations 1 to 4 are automatically executed, so that the program processing burden is greatly reduced. . Also in this case, programs and data after the vector handler Vopt are transferred to an appropriate RAM area based on the operation of the initial setting program Pinit.

Note that the programs and data after the vector handler Vopt do not necessarily need to be stored in the top area of the CGROM 55, and may be stored in the control memory 53, for example (FIG. 37(b)). Further, the programs and data after the vector handler Vopt do not necessarily need to be transferred to the RAM area, and if they are not transferred, the memory section initialization process (SP8 in FIG. 15) in the initialization setting program is unnecessary.

Further, it is not necessary to make the V blank timing and the transmission end timing of significant image data necessarily coincide with each other. That is, there is no need to end the transmission of image data at the timing of the lower left end point (circle mark) of the display area shown in FIG. 14(f). In short, it is sufficient to satisfy the specifications of the standby time WTh/WRv and the horizontal/vertical synchronization signals HS/Vs required by the display device.

FIG. 39(a) is a drawing for explaining such an embodiment, and shows, for example, the operation of the display circuit 74A. In this embodiment as well, the frequency F _dot of the dot clock DCK is defined as 108 MHz in accordance with the specifications of the main display device DS1. In addition, in order to match the frame rate FR to 1/60 seconds, it is necessary to set THc×TVl/F _dot = 1/60, and here, as in the case of FIG. 14(f), the horizontal synchronization cycle The number THc is 1662 clocks, and the number TVl of vertical synchronization lines is 1083 lines.

Further, in the illustrated embodiment, the horizontal synchronizing signal HS and the vertical synchronizing signal VS are outputted in accordance with the specifications of the display device so that it can be used with general display devices. In the illustrated example, the pulse width of the horizontal synchronizing signal HS is 100 clocks, the horizontal front porch FPh is designed to be 110 (=10+100) clocks, and the horizontal back porch BPh is designed to be 172 clocks. Further, the pulse width of the vertical synchronizing signal VS is designed to be 10 lines, the vertical front porch FPv is designed to be 20 (=10+10) lines, and the vertical back porch BPv is designed to be 291 lines.

However, in the embodiment shown in FIGS. 39(a) and 39(b), the vertical standby time WTv is set to 49 lines and the horizontal standby time WTh is set to 372 clocks in order to finish the output operation before the V blank start timing indicated by the circle. . Therefore, according to this embodiment, the V blank start timing will arrive after the time for 10 lines (154 μS) has elapsed after the image update process for one frame is completed, and the image update process can be performed reliably under any operating conditions. (see FIG. 39(b)).

Such an operation works particularly well in a display circuit that operates incidentally in synchronization with another display circuit, for example, the display circuit 74B or the display circuit 74C that accompanies the operation of the display circuit 74A. 39(c) to 39(e) are drawings for explaining this point, and illustrate a case where the V blank period T2 in the display circuit 74B is longer than the V blank period T1 in the display circuit 74A (T1 <T2).

In such a case, if the V blank period T1 in the display circuit 74A is operated in conjunction with the display circuit 74A, the V blank will start before the output of image data in the display circuit 74B is completed, and the image There is a risk that defects or unnatural display operations may occur (FIG. 39(d)). On the other hand, if the display circuit 74B were operated independently, it would not be possible to match the operation timing of the drawing circuit which is synchronized with the operation of the display circuit 74A.

Therefore, when the V blank period T2 of the display circuit 74B accompanying the operation of the display circuit 74A is longer than the V blank period T1 of the display circuit 74A, the display device In B, the standby time (vertical blank period) may be set short so that there is sufficient margin time after outputting the image data. In this case, unless the standby time is set extremely short, a normal liquid crystal display device can perform display operations without problems.

Note that, for example, even if the V blank period T3 of the display circuit 74B associated with the operation of the display circuit 74A is shorter than the V blank period T1 of the display circuit 74A, an extra standby period occurs after the V blank period T3. As long as the overall standby time is not extremely long, display operations can be realized without any problems.

Although the embodiments of the present invention have been described in detail above, the specific contents of the description do not limit the present invention in any way. For example, in the embodiments, the dual link transmission path has been mainly described, but in order to simplify the equipment configuration, it is also suitable to employ a single link transmission path.

In the case of a single link transmission path, if the frequency of the dot clock DCK is 108 MHz, the frequency of the LVDS clock CLK is also 108 MHz. In this case as well, it is preferable that the dot clock DCK and the LVDS clock CLK have the oscillator OSC2 as a common source and are generated in the same generation process.

Further, unlike the above-mentioned embodiments, it is advantageous to use a single oscillator OSC2 as a common source for supplying the system clock of the VDP circuit 52 and the CPU operation clock of the CPU circuit 51 in order to simplify the circuit configuration. It is suitable for If a configuration is adopted in which the multiplication ratios of the PLL circuits are commonly set based on the setting value of a common setting terminal (3-bit PLLMD terminal), frequency setting processing becomes unnecessary and is even more effective.

In this case, although it is somewhat contrary to the desire to speed up the CPU operating clock, it is preferable to adopt the system clock with the highest frequency allowed by the internal circuit of the VDP circuit 52 and use the same frequency as the CPU operating clock. .

For example, if the oscillation frequency of the oscillator OSC2 is 40MHz, by setting the setting value to the setting terminal (3-bit PLLMD terminal) to 5, the system clock and CPU operation clock can be commonly set to 200MHz (=40MHz x 5). can. According to this configuration, the oscillator OSC1 is not required, which not only simplifies the circuit configuration but also eliminates the somewhat complicated setting process for the VDP register. Note that there is also an advantage that the operating cycles of the VDP circuit 52 and the CPU circuit 51 match.

GM Gaming machines DS1, DS2 Display device 52 Image generation means 51 Performance control means DL Drawing list 76 Drawing circuit 74 Display circuit DCK Display clock SS31 First means SS32 Second means ODD First data EVEN Second data SS30, 80 Third means OSC2 clock oscillation section

Claims (1)

A gaming machine comprising an image generation means that operates based on a system clock derived from an output of a predetermined clock oscillation section to realize an image effect on a display device, and an effect control means that controls the operation of the image generation means. hand,
The image generating means includes a data transfer circuit that receives the drawing list issued by the effect control means and transfers the drawing list in units of predetermined transfer bits to an analysis circuit that analyzes the drawing list, and a drawing list transferred by the data transfer circuit. a drawing circuit that generates necessary image data in a predetermined RAM area based on the image data, a display circuit that reads out the image data in the RAM area, performs appropriate image processing when necessary, and outputs the image data, and the display circuit outputs the image data. a signal output circuit that receives image data and outputs a differential signal including an LVDS clock ; the data transfer circuit includes a transfer port that receives a drawing list in units of predetermined acquired bits; a FIFO buffer having a FIFO structure for accumulating received data, and the effect control means has a total bit length that is an integral multiple of the acquired bit unit, and a FIFO buffer that has a FIFO buffer that stores data received by the transfer bit unit. A drawing list is created so that it is an integer multiple,
a first means for specifying that the clock oscillation unit is a supply source of a display clock that specifies the operation of the display circuit;
a second means for appropriately setting a ratio to the output frequency of the clock oscillation unit to make the period of the display clock correspond to the processing time required for displaying one dot of each pixel of the display device;
comprising third means for distributing image data output from the display circuit into first data and second data for each pixel dot of the display device,
The signal output circuit outputs the image data distributed by the third means to the display device via two LVDS paths,
One period of the LVDS clock is twice as long as one period of the display clock, and the display device is configured to complete processing for two dots of the pixel in one period of the LVDS clock. A gaming machine that has

Images