JP7436108B2 - Shift register unit, gate drive circuit, display device and driving method - Google Patents

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to Chinese Patent Application No. 201810966800.7 filed with the Chinese Patent Office on August 23, 2018, the entire contents of which are incorporated into this application by reference.

The present invention relates to display technology, and more specifically to a shift register unit, a gate drive circuit, a display device, and a drive method.

In display panels, particularly for organic light emitting diode (OLED) based display panels, the driving circuit is usually integrated into a gate integrated circuit (gate IC). When designing a gate IC chip, the cost of the chip mainly depends on the area of the chip. Existing OLED gate driving circuits include three sub-circuits: a sensing unit circuit, a scanning unit circuit, and a connecting circuit or gating circuit for outputting signals from both the sensing unit circuit and the scanning unit circuit. Including, the gate IC becomes a very complicated circuit structure, which is difficult to meet the increasingly strict requirements for producing narrow frame high resolution OLED display panels. Therefore, improvements in circuit design are required for shift register units forming gate drive circuits of display panels.

In one aspect, the present disclosure provides a shift register unit. The shift register unit includes a first subunit including a first input circuit coupled to a first output circuit via a first node. The first input circuit is configured to control a voltage level at the first node in response to a first input signal, and the first output circuit is configured to control a voltage level at the first node in response to a voltage level at the first node. The signal is configured to output a signal and a first output signal. The shift register circuit further includes a second subunit including a second input circuit coupled to a second output circuit via a second node. The second input circuit is configured to control a voltage level at the second node in response to the first input signal, and the second output circuit is configured to control a voltage level at the second node in response to the first input signal. It is configured to output two output signals.

Optionally, the shift register unit is coupled to the first node and the second node and configured to receive a selection control signal to control respective voltage levels of the first node and the second node. further comprising a blank input subunit configured to.

Optionally, the blank input subunit includes a common input circuit, a first transmission circuit, and a second transmission circuit. The common input circuit is configured to control a voltage level at a third node and to control a voltage level at a fourth node in response to the selection control signal. The first transmission circuit is connected to the first node and the fourth node and configured to control the voltage level of the first node in response to the voltage level of the fourth node or the first transmission signal. be done. The second transmission circuit is connected to the second node and the fourth node and configured to control the voltage level of the second node in response to the voltage level of the fourth node and the second transmission signal. be done.

Optionally, the common input circuit further includes a selection control circuit and a third input circuit. The selection control circuit is configured to control the voltage level of the third node using a second input signal in response to the selection control signal, and to maintain the voltage level of the third node. The third input circuit is configured to control the voltage level of the fourth node in response to the voltage level of the third node.

Optionally, the selection control circuit includes a first transistor and a first capacitor. The first transistor has a gate terminal configured to receive the selection control signal, a first terminal configured to receive the second input signal, and a second transistor connected to the third node. It has a terminal. The first capacitor has a first terminal connected to the third node.

Optionally, the third input circuit includes a gate coupled to the third node, a first terminal configured to receive a first clock signal, and a second terminal coupled to the fourth node. a second transistor having a terminal;

Optionally, the first transmission circuit includes a third transistor, and the second transmission circuit includes a fourth transistor. The third transistor has a gate terminal coupled to the fourth node, a first terminal configured to receive a first voltage, and a second terminal coupled to the first node. The fourth transistor has a gate terminal coupled to the fourth node, a first terminal configured to receive the first voltage, and a second terminal coupled to the second node.

Optionally, the first input circuit includes a fifth transistor, and the first output circuit includes a sixth transistor, a seventh transistor, and a second capacitor. The fifth transistor has a gate terminal configured to receive the first input signal, a first terminal configured to receive a first voltage, and a second terminal coupled to the first node. and has. The sixth transistor has a gate terminal connected to the first node, a first terminal configured to receive the second clock signal as a shift register signal, and configured to output the shift register signal. and a second terminal. The seventh transistor has a gate terminal connected to the first node, a first terminal configured to receive a third clock signal as the first output signal, and a first terminal configured to output the first output signal. and a second terminal configured to. The second capacitor has a first terminal connected to the first node and a second terminal connected to the second terminal of the seventh transistor.

Optionally, the second input circuit includes an eighth transistor, and the second output circuit includes a ninth transistor and a third capacitor. The eighth transistor has a gate terminal configured to receive the first input signal, a first terminal configured to receive the first voltage, and a second transistor connected to the second node. It has a terminal. The ninth transistor has a gate terminal connected to the second node, a first terminal configured to receive a fourth clock signal as the second output signal, and a first terminal configured to output the second output signal. and a second terminal configured to. The third capacitor has a first terminal connected to the second node and a second terminal connected to the second terminal of the ninth transistor.

Optionally, the first sub-unit further includes a first control circuit, a first reset circuit, a second reset circuit, a shift register output terminal, and a first output terminal. The first control circuit is configured to control a voltage level at a fifth node in response to a voltage level at the first node and a second voltage. The first reset circuit is configured to reset the voltage level at the first node, the shift register output terminal, and the first output terminal in response to the voltage level at the fifth node. The second reset circuit is configured to reset the voltage level at the first node, the shift register output terminal, and the first output terminal in response to the voltage level at the sixth node.

Optionally, the second sub-unit further includes a second control circuit, a third reset circuit, a fourth reset circuit, and a second output terminal. The second output terminal is configured to output the second output signal. The second control circuit is configured to control the voltage level at the sixth node in response to the voltage level at the second node and a third voltage. The third reset circuit is configured to reset the voltage level at the second node and the second output terminal in response to the voltage level at the sixth node. The fourth reset circuit is configured to reset the voltage level at the second node and the second output terminal in response to the voltage level at the fifth node.

Optionally, the blanking input subunit is coupled to the fourth node, the fifth node, and the sixth node, and is configured to blank the input subunit in response to a voltage level at the fifth node or the sixth node. The method further includes a common reset circuit configured to reset the voltage levels of the four nodes.

Optionally, the common reset circuit includes a tenth transistor and an eleventh transistor. The tenth transistor has a gate terminal connected to the fifth node, a first terminal connected to the fourth node, and a second terminal configured to receive a fourth voltage. The eleventh transistor has a gate terminal connected to the sixth node, a first terminal connected to the fourth node, and a second terminal configured to receive the fourth voltage.

Optionally, the first control circuit includes a twelfth transistor and a thirteenth transistor. The first reset circuit includes a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor. The second reset circuit includes a 17th transistor, an 18th transistor, and a 19th transistor. The twelfth transistor has a gate terminal and a first terminal both configured to receive the second voltage, and a second terminal coupled to the fifth node. The thirteenth transistor has a gate terminal connected to the first node, a first terminal connected to the fifth node, and a second terminal configured to receive a fourth voltage. The fourteenth transistor has a gate terminal connected to the fifth node, a first terminal connected to the first node, and a second terminal configured to receive the fourth voltage. The fifteenth transistor has a gate terminal coupled to the fifth node, a first terminal coupled to the shift register output terminal, and a second terminal configured to receive the fourth voltage. . The sixteenth transistor has a gate terminal coupled to the fifth node, a first terminal coupled to the first output terminal, and a second terminal configured to receive a fifth voltage. The seventeenth transistor has a gate terminal connected to the sixth node, a first terminal connected to the first node, and a second terminal configured to receive the fourth voltage. The eighteenth transistor has a gate terminal coupled to the sixth node, a first terminal coupled to the shift register output terminal, and a second terminal configured to receive the fourth voltage. . The nineteenth transistor has a gate terminal connected to the sixth node, a first terminal connected to the first output terminal, and a second terminal configured to receive the fifth voltage. .

Optionally, the second control circuit includes a 20th transistor and a 21st transistor. The third reset circuit includes a twenty-second transistor and a twenty-third transistor, and the fourth reset circuit includes a twenty-fourth transistor and a twenty-fifth transistor. The twentieth transistor has a gate terminal and a first terminal both configured to receive the third voltage, and a second terminal coupled to the sixth node. The twenty-first transistor has a gate terminal connected to the second node, a first terminal connected to the sixth node, and a second terminal configured to receive a fourth voltage. The twenty-second transistor has a gate terminal connected to the sixth node, a first terminal connected to the second node, and a second terminal configured to receive the fourth voltage. The twenty-third transistor has a gate terminal coupled to the sixth node, a first terminal coupled to the second output terminal, and a second terminal configured to receive a fifth voltage. The twenty-fourth transistor has a gate terminal connected to the fifth node, a first terminal connected to the second node, and a second terminal configured to receive the fourth voltage. The twenty-fifth transistor has a gate terminal connected to the fifth node, a first terminal connected to the second output terminal, and a second terminal configured to receive the fifth voltage. .

Optionally, the first sub-unit further includes a third output terminal configured to output a third output signal. The second subunit further includes a fourth output terminal configured to output a fourth output signal. The first reset circuit and the second reset circuit are configured to reset the voltage level at the third output terminal. The third reset circuit and the fourth reset circuit are configured to reset the voltage level at the fourth output terminal.

Optionally, the first subunit further includes a third control circuit and a fourth control circuit. The third control circuit is configured to control the voltage level of the fifth node in response to the first clock signal, and the fourth control circuit is configured to control the voltage level of the fifth node in response to the first input signal. The node is configured to control a voltage level of the node. The second subunit further includes a fifth control circuit and a sixth control circuit. The fifth control circuit is configured to control the voltage level of the sixth node in response to the first clock signal, and the sixth control circuit is configured to control the voltage level of the sixth node in response to the first input signal. The node is configured to control a voltage level of the node.

Optionally, the first subunit further includes a fifth reset circuit and a sixth reset circuit. The fifth reset circuit is configured to reset a voltage level at the first node in response to a display reset signal, and the sixth reset circuit is configured to reset a voltage level at the first node in response to a full-scale reset signal. configured to reset the voltage level of. The second subunit further includes a seventh reset circuit and an eighth reset circuit. The seventh reset circuit is configured to reset the voltage level at the second node in response to the display reset signal, and the eighth reset circuit is configured to reset the voltage level at the second node in response to the full-scale reset signal. configured to reset the voltage level at the node;

Optionally, the shift register unit further includes a common leakage prevention circuit, a first leakage prevention circuit, and a second leakage prevention circuit. The common leakage prevention circuit is connected to the first node and the seventh node and configured to control the voltage level at the seventh node in response to the voltage level at the first node. The first leakage prevention circuit is connected to the seventh node, the first reset circuit, the second reset circuit, the fifth reset circuit, and the sixth reset circuit, and is responsive to a voltage level of the seventh node. The first node is configured to prevent leakage from occurring in the first node. The second leakage prevention circuit is connected to the seventh node, the third reset circuit, the fourth reset circuit, the seventh reset circuit, and the eighth reset circuit, and is connected to the voltage level at the seventh node. The second node is configured to responsively prevent leakage from occurring at the second node.

In another aspect, the present disclosure provides a gate drive circuit that includes a plurality of shift register units cascaded in series. Each of the plurality of shift register units is a shift register unit as described herein, and includes a first sub-unit in an odd number of stages each controlled by a voltage level of a first node and a second node; including a pair with a second subunit in an even stage of. The voltage levels of the first node and the second node are controlled by a first transmission circuit and a second transmission circuit, respectively, which are both connected from a common input circuit. The first subunit of each shift register unit outputs the shift register signal as a first input signal to drive both the first subunit and the second subunit in the next shift register unit, or outputs a display reset signal. and drives both the first subunit and the second subunit in the previous shift register unit.

In yet another aspect, the present disclosure provides a display device including a gate drive circuit as described herein and a plurality of subpixel units arranged in an array. A first output signal and a second output signal respectively output from a first output circuit and a second output circuit of each one shift register unit in the gate driving circuit are respectively provided to sub-pixel units in different rows of the array. Ru.

In yet another aspect. The present disclosure provides a method of driving the shift register unit described herein. The method includes inputting a first input signal to a first input circuit of a first subunit of the shift register unit and a second input circuit of a second subunit of the same shift register unit. The method further includes controlling a voltage level of a first node of the first sub-unit based on the first input signal by driving the first sub-unit. The method further includes coupling a first output circuit to the first node. Further, the method includes controlling the first output circuit to output a shift register signal and a first output signal in response to the voltage level of the first node by driving the first subunit. , controlling a voltage level of a second node of the second sub-unit based on the first input signal by driving the second sub-unit. Additionally, the method includes coupling a second output circuit to the second node. The method also includes controlling the second output circuit to output a second output signal in response to the voltage level of the second node by driving the second sub-unit.

Optionally, controlling the voltage level of the first node by driving the first sub-unit uses a blank input circuit having a common input circuit to control the voltage level of the second input signal and the first clock signal. to determine voltage levels at a third node and a fourth node, and using a first transmission circuit to control the voltage level at the first node in response to the voltage level at the fourth node. include. controlling the voltage level of the second node by driving the second subunit is responsive to the voltage level of the fourth node using the blanking input circuit further comprising a second transmission circuit. The method includes controlling a voltage level of the second node.

Optionally, controlling the first output circuit by driving the first sub-unit includes controlling the shift register output terminal and the first output terminal using at least a first reset circuit and a second reset circuit. The method includes resetting a voltage level and controlling a second clock signal output as a shift register signal and a third clock signal output as the first output signal in response to the voltage at the first node. Driving the second subunit to control the second output circuit includes resetting the voltage level at the second output terminal using at least a third reset circuit in response to the voltage level at the second node. and controlling a fourth clock signal output as the second output signal.

The following drawings are merely examples for illustrative purposes of the various disclosed embodiments and are not intended to limit the scope of the invention.

FIG. 2 is a block diagram of a shift register unit according to an embodiment of the present disclosure.

FIG. 3 is a block diagram of a shift register unit according to another embodiment of the present disclosure.

FIG. 2 is a block diagram of a blank input subunit of a shift register unit according to an embodiment of the present disclosure.

FIG. 3 is a circuit diagram of a blank input subunit according to an embodiment of the present disclosure.

FIG. 3 is a circuit diagram of a blank input subunit according to an embodiment of the present disclosure.

FIG. 2 is a circuit diagram of a blank input subunit including a leak-proof structure according to an embodiment of the present disclosure.

FIG. 3 is a block diagram of a shift register unit according to yet another embodiment of the present disclosure.

FIG. 3 is a block diagram of a shift register unit according to yet another embodiment of the present disclosure.

9A and 9b are circuit diagrams of a first subunit and a second subunit, respectively, of a shift register unit according to an embodiment of the present disclosure. 9A and 9b are circuit diagrams of a first subunit and a second subunit, respectively, of a shift register unit according to an embodiment of the present disclosure.

FIG. 3 is a circuit diagram of three types of first input circuits of a shift register unit according to an embodiment of the present disclosure.

11A and 11B are circuit diagrams of respective first and second subunits of a shift register unit according to another embodiment of the present disclosure. 11A and 11B are circuit diagrams of respective first and second subunits of a shift register unit according to another embodiment of the present disclosure.

FIG. 2 is a circuit diagram of a shift register unit with anti-leakage circuitry according to some embodiments of the present disclosure. FIG. 2 is a circuit diagram of a shift register unit with anti-leakage circuitry according to some embodiments of the present disclosure. FIG. 2 is a circuit diagram of a shift register unit with anti-leakage circuitry according to some embodiments of the present disclosure.

13A and 13B are circuit diagrams of respective first and second subunits of a shift register unit according to yet another embodiment of the present disclosure. 13A and 13B are circuit diagrams of respective first and second subunits of a shift register unit according to yet another embodiment of the present disclosure.

FIG. 1 is a schematic diagram of a gate drive circuit according to an embodiment of the present disclosure.

15 is a timing diagram for operating the gate drive circuit of FIG. 14 according to an embodiment of the present disclosure. FIG.

15 is a timing diagram for operating the gate drive circuit of FIG. 14 according to another embodiment of the present disclosure. FIG.

FIG. 3 is a schematic diagram of a gate drive circuit according to another embodiment of the present disclosure.

18 is a timing diagram for operating the gate drive circuit of FIG. 17 according to an embodiment of the present disclosure. FIG.

FIG. 3 is a schematic diagram of a gate drive circuit according to another embodiment of the present disclosure.

20 is a timing diagram for operating the gate drive circuit of FIG. 19 according to an embodiment of the present disclosure. FIG.

FIG. 3 is a signal diagram of simulated voltage signals at circuit nodes and output terminals of a gate drive circuit according to an embodiment of the present disclosure.

FIG. 1 is a schematic diagram of a display device according to an embodiment of the present disclosure.

Next, the present disclosure will be described more specifically with reference to the following embodiments. It should be noted that the following description of some embodiments is presented herein for purposes of illustration and description only. It is not intended to be exhaustive or limited to the precise form disclosed.

In the detailed description that follows, numerous specific details are set forth in order to provide a more thorough understanding of the disclosure. However, it will be apparent to those skilled in the art that the present disclosure may be practiced without necessarily being limited to these specific details. In other instances, well-known structures and circuits are shown in block diagram form, rather than in detail, in order to avoid obscuring the present invention.

The reader's attention is directed to all papers and documents filed contemporaneously with this specification and disclosed to the public herein, the contents of all such papers and documents being incorporated herein by reference. It will be done. All features disclosed in this specification (including any appended claims, abstract and drawings) may, unless stated otherwise, be replaced by alternative features serving the same, equivalent or similar purpose. . Thus, unless stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.

Further, elements in a claim that do not explicitly recite "means" for performing a particular function or "steps" for performing a particular function are defined as "means for performing a particular function" or "steps" for performing a particular function as specified in 35 U.S.C. should not be construed as a "means" or "step" clause. In particular, the use of "step" or "act" in the claims herein is not intended to invoke the provisions of 35 U.S.C. 112(6).

It is noted that "first," "second," and similar words, as used in this disclosure, do not indicate order, quantity, or importance, but are used to distinguish between different components. . Similarly, words such as "comprising" or "include" or "comprising" or "a" or "an" as well as "coupled" or "connected" refer to physical or mechanical It is not limited to connections, but may include electrical connections, whether direct or indirect. "Top", "bottom", "left", "right", etc. are used only to indicate relative positional relationships; if the absolute position of the object changes, the relative positional relationship may change accordingly.

In general, the words "a", "a", "said" and "the" and the terms "comprising" and "including" are intended to include only the steps and elements identified; and elements do not constitute an exclusive list; the method or apparatus may also include other steps or elements.

When compensating a sub-pixel unit of an OLED display panel, in addition to setting a pixel compensation circuit for internal compensation in the sub-pixel unit, external compensation may also be performed by setting a sensing transistor. When external compensation is performed, a gate driving circuit formed of a shift register unit needs to provide driving signals for each of the scanning transistor and sensing transistor in the sub-pixel unit of the display panel. For example, a scan drive signal for the scan transistor is provided during a display period of one cycle for displaying one frame of an image, and a sense drive signal for the sense transistor is provided during a blank period of the cycle.

In the external compensation method, the sensing driving signal output by the gate driving circuit is sequentially scanned row by row. For example, during a blank period of a cycle for displaying a first frame, a sensing drive signal is output to a sub-pixel unit of a first row of the display panel, and during a blank period of a cycle for displaying a second frame, a sensing drive signal is output to a sub-pixel unit of a second row of the display panel. Another sensing drive signal is output to the sub-pixel units of the row, and so on. Therefore, by outputting a sensing drive signal for a corresponding row of sub-pixel units for each frame, sequential compensation for each row of the display panel is completed.

Accordingly, the present disclosure provides, among other things, gate drive circuits that can be cascaded in series to output a scan drive signal during a display period of one cycle for displaying one frame and output a sense drive signal during a blank period of said cycle. A shift register unit, display device, and driving method configured to form a shift register unit, display device, and driving method are provided that substantially avoid one or more problems due to limitations and weaknesses of the related art. In one aspect, the present disclosure provides a shift register unit suitable for use in display devices with reduced frame size and increased pixels per inch (PPI), and allows for random compensation during display operation. Avoid brightness non-uniformity.

For purposes of explanation, the definitions of "one frame," "every frame," or "a particular frame" include sequentially executed display periods and blank periods. For example, the gate drive circuit outputs a gate drive signal during the display period, and the gate drive signal is applied to the display panel so that one frame of display is completed by scanning from the first row to the last row. can be used to drive. During the blanking period, the gate driving circuit outputs a sensing driving signal, which drives the sensing transistor in the sub-pixel unit of one row in the display panel to compensate for the external compensation of the sub-pixel unit of the row. can be used to complete the

FIG. 1 is a block diagram of a shift register unit according to an embodiment of the present disclosure. Referring to FIG. 1, the shift register unit 10 includes a first subunit 100 and a second subunit 200. A plurality of such shift register units 10 may be cascaded to form a gate drive circuit according to some embodiments of the present disclosure. The gate drive circuit may be applied to a display device and provide a scanning signal to display one frame of image on the display device during display operation.

The first sub-unit 100 includes a first input circuit 110 and a first output circuit 120, which are connected to each other via a first node Q1. The first input circuit 110 is configured to control the voltage level at the first node Q1 in response to the received first input signal STU1. For example, the first input circuit 110 can charge the first node Q1. Optionally, the first input circuit 110 is configured to receive a first input signal STU1 and a first voltage VDD. Optionally, the first input circuit 110 becomes conductive in response to the first input signal STU1, so that the first voltage VDD can be used to charge the first node Q1. Optionally, the voltage level at the first node Q1 is charged to the level of the first voltage VDD within at least 10%. Optionally, the first voltage VDD is set to be a high voltage supplied from a power supply.

The first output circuit 120 is configured to output the shift register signal CR and the first output signal OUT1 in response to the voltage level at the first node Q1. For example, the first output circuit 120 may be configured to receive the second clock signal CLKB and the third clock signal CLKC. The first output circuit 120 becomes conductive in response to the voltage level at the first node Q1, so that it can output the second clock signal CLKB as the shift register signal CR and output the third clock signal CLKC to the first output. It can be output as signal OUT1.

Optionally, during a display period of one cycle for displaying one frame of image or just one frame, the shift register signal CR output from the first output circuit 120 is sent to another shift register unit ( in the gate drive circuit to complete a row-by-row shift scan during display operation. The first output signal OUT1 output from the first output circuit 120 can drive one row of sub-pixel units of the display panel to perform display scanning. Optionally, during the blank period of one frame, the first output signal OUT1 output from the first output circuit 120 drives the sensing transistors in the sub-pixel units of one row of the display panel to It can be used to complete external compensation for sub-pixel units.

Optionally, during the display period of the frame, the shift register signal output from the first output circuit 120 has the same or a different waveform compared to the first output signal OUT1 output from the same first output circuit 120. may have.

Referring to FIG. 1, the second subunit 200 includes a second input circuit 210 and a second output circuit 220, which are connected to each other via a second node Q2. The second input circuit 210 is configured to control the voltage level at the second node Q2 in response to the first input signal STU1. For example, the second input circuit 210 charges the second node Q2. Optionally, the second input circuit 210 receives the first input signal STUI1 and the first voltage VDD and is configured to be turned on by the first input signal STU1, so that it utilizes the first voltage VDD. can charge the second node Q2.

Optionally, the second output circuit 220 is configured to output a second output signal OUT2 in response to the voltage level at the second node Q2. For example, the second output circuit 220 is configured to receive the fourth clock signal CLKD. The second output circuit 220 is turned on by the voltage level at the second node Q2, and as a result, the fourth clock signal CLKD can be output as the second output signal OUT2.

During the display period of one frame, the second output circuit 220 outputs the second output signal OUT2 to drive one row of sub-pixel units of the display panel to perform display scanning. During the blank period of one frame, the second output circuit 220 outputs a second output signal OUT2 to drive the sensing transistors in the sub-pixel units in one row of the display panel, and Complete external compensation.

When a plurality of shift register units 10 are cascaded in series to form a gate drive circuit, some of the shift register units 10 are connected to a clock signal line and receive the first input provided by the clock signal line. A signal STU1 may be received. Optionally, some shift register units 10 may receive shift register signals CR output from shift register units 10 in other stages in the same gate drive circuit as the first input signal STU1.

Optionally, controlling the voltage level of a node (e.g., first node Q1, second node Q2, etc.) includes charging the node to increase the voltage level of the node or discharging the node. including lowering the voltage level of the node. Optionally, a capacitor may be electrically connected to the node, and charging the node means charging a capacitor electrically connected to the node. Similarly, discharging a node means discharging a capacitor electrically connected to the node. The capacitor can maintain a high or low level of the node.

The shift register unit 10 of the present disclosure can charge a plurality of subunits (first subunit 100, second subunit 200, etc.) simultaneously. FIG. 1 shows only two subunits in the shift register unit. Optionally, the shift register unit may include three, four or more subunits in a similar circuit structure depending on the actual setup under different applications. Only one of the plurality of subunits (for example, the first subunit 100) needs to output a shift register signal at a time, and the other subunits (for example, the second subunit 100) among the plurality of subunits 200) does not need to output a shift register signal. Therefore, the number of clock signal lines and transistors in the gate drive circuit can be saved, and the frame size of the display device employing the shift register unit 10 can be reduced, thereby improving the PPI of the display device.

FIG. 2 is a block diagram of a shift register unit according to another embodiment of the present disclosure. Referring to FIG. 2, the shift register unit 10A includes a blank input subunit 300, which is coupled to the first subunit 100 via a first node Q1 and coupled to the first subunit 100 via a second node Q2. is coupled to the second subunit 200 and configured to receive the selection control signal OE. The blank input subunit 300 is configured to control the voltage level Q1 of the first node and the second node Q2 in response to the selection control signal OE. For example, the blank input subunit 300 is configured to charge the first node Q1 and the second node Q2, respectively.

Optionally, during a display period of one frame, the blanking input subunit 300 can charge the first node Q1 and can also charge the second node Q2. The first output circuit 120 may output the first output signal OUT1 in response to the voltage level charged at the first node Q1, or the second output circuit 220 may output the first output signal OUT1 in response to the voltage level charged at the second node Q2. A second output signal OUT2 can be output in response to the level. The first output signal OUT1 or the second output signal OUT2 may be used to drive the sensing transistors in one row of sub-pixel units of the display panel to complete external compensation for the one row of sub-pixel units.

FIG. 3 is a block diagram of a blank input subunit of a shift register unit according to an embodiment of the present disclosure. In one embodiment, referring to FIG. 3, the blank input subunit 300 includes a common input circuit 310 coupled to a first transmission circuit 320 and a second transmission circuit 330 via a fourth node N. The common input circuit 310 further includes a selection control circuit 311 coupled to a third input circuit 312 via a third node H. The common input circuit 310 is configured to control the voltage level of the third node H and further control the voltage level of the fourth node N in response to the selection control signal OE. The selection control circuit 311 is configured to charge the third node H using the second input signal STU2 and maintain the voltage level at the third node H in response to the selection control signal OE. For example, during the frame display period, the selection control circuit 311 is turned on by the selection control signal OE, and as a result, the third node H can be charged using the second input signal STU2. The voltage level (eg, high voltage level) at the third node H can be maintained throughout the display period until the blank period after the display period of the same frame.

When a plurality of shift register units 10A are connected in series in multiple stages to form a gate drive circuit, the shift register unit 10A in one stage receives the shift register signal CR output from the shift register unit 10A in the other stage as a second input. It can be received as signal STU2. For example, when selecting one stage of shift register unit 10A and outputting a drive signal during the blank period of one frame, it is preferable to provide the same timing waveform to both the selection control signal OE and the second input signal STU2, The selection control circuit 311 in the shift register unit 10A of that stage is turned on, so that the corresponding charging operation described above can be performed.

Further, the third input circuit 312 is configured to control the voltage level at the fourth node N in response to the voltage level charged at the third node H. Optionally, the third input circuit 312 is configured to receive the first clock signal CLKA. When the third input circuit 312 is in a conductive state controlled by the voltage level at the third node H, the first clock signal CLKA can be passed to the fourth node N to control the voltage level at the fourth node N. For example, during the blank period of one frame, when the first clock signal CLKA is provided with a high voltage level, the third input circuit 312 passes the high voltage level to the fourth node N, causing the fourth node N to be at the high voltage level. do.

Referring to FIG. 3, the first transmission circuit 320 is connected to the first node Q1 and the fourth node N, and the voltage level of the fourth node N or the first transmission signal TS1 ( (not shown) to control the voltage level at the first node Q1. In some embodiments, the first transmission circuit 320 can receive the first voltage VDD at a high voltage level. When the first transmission circuit 320 becomes conductive due to the voltage level at the fourth node N, the first node Q1 can be charged using the high voltage level of the first voltage VDD. Optionally, the voltage level at the first node Q1 is charged to the level of the first voltage VDD within at least 10%. In some other embodiments, the first transmission circuit 320 can establish an electrical connection between the fourth node N and the first node Q1 by being brought into a conductive state by the first transmission signal TS1 (not shown). , as a result, the first node Q1 can be charged by the third input circuit 312.

Further, the second transmission circuit 330 is connected to the second node Q2 and the fourth node N, and the voltage level at the fourth node N or the second transmission signal TS2 (not shown) received by the second transmission circuit 330 is connected to the second node Q2 and the fourth node N. The second node Q2 is configured to control the voltage level at the second node Q2 in response to the second node Q2. In some embodiments, the second transmission circuit 330 can receive the first voltage VDD at a high voltage level. When the second transmission circuit 330 becomes conductive due to the voltage level at the fourth node N, the second node Q2 can be charged using the first voltage VDD at a high voltage level. The voltage level at the second node Q2 is charged to the level of the first voltage VDD with an error within at least 10%. In some other embodiments, the second transmission circuit 330 establishes an electrical connection between the fourth node N and the second node Q2 by being rendered conductive by the second transmission signal TS2 (not shown). As a result, the second node Q2 can be charged by the third input circuit 312.

Optionally, the first transmission signal TS1 and the second transmission TS2 can be the same signal, for example the first clock signal CLKA or the first voltage VDD. Therefore, the number of clock signal lines can be reduced. Optionally, different signals may be provided in the first transmission signal TS1 and the second transmission signal TS2 to control the first transmission circuit 320 and the second transmission circuit 330, respectively. For example, when there is no need to charge the second node Q2, the second transmission circuit 330 can be turned off to reduce power consumption.

Optionally, if shift register unit 10A includes three, four, or more subunits, three, four, or more transmissions to perform the function of blank input subunit 300. A circuit needs to be installed. The three, four or more subunits in the shift register unit 10A can share one blank input subunit 300 to reduce the area of the shift register unit 10A, thereby making the shift register unit 10A The size of the frame of the display device used is reduced and the PPI of the display device is improved. Optionally, the blank input subunit 300 is installed in the shift register unit 10A to enable the shift register unit to output a driving signal during a blank period of one frame. "Blank" simply refers to the blank period of the frame. Blank input subunit 300 is not limited to operating only during blank periods.

FIG. 4 is a circuit diagram of a blank input subunit according to an embodiment of the present disclosure. 5A-5F are circuit diagrams of blank input subunits according to embodiments of the present disclosure. In some embodiments, the selection control circuit 311 may be implemented by including a first transistor M1 and a first capacitor C1. The first transistor M1 has a gate terminal configured to receive said selection control signal OE. The first transistor M1 has a first terminal configured to receive a second input signal STU2. The first transistor M1 has a second terminal connected to the third node H. For example, if the selection control signal OE is provided as a high voltage turn-on signal, the first transistor M1 is turned on, so that the second input signal STU2 can be used to charge the third node H.

The first capacitor C1 has a first terminal coupled to the third node H and a second terminal configured to receive the fourth voltage VGL1 or the first voltage VDD. By installing the first capacitor C1, the voltage level at the third node H can be maintained. For example, during the frame display period, the selection control circuit 311 can charge the third node H to raise the voltage level of the third node H to a high voltage level. The first capacitor C1 can maintain the high voltage level at the third node H until the blank period of the frame. In some other embodiments, the first capacitor C1 has a second terminal coupled to the fourth node N. Optionally, the fourth voltage VGL1 is a low voltage level or a turn-off signal.

Referring to FIG. 4, the third input circuit 312 may be implemented by including a second transistor M2. The second transistor M2 has a gate terminal connected to the third node H, a first terminal CLKA configured to receive the first clock signal, and a second terminal connected to the fourth node N. . When the third node H is set to a high voltage level, the second transistor M2 is turned on, thereby passing the first clock signal CLKA to the fourth node N and raising the voltage level there to the high voltage level. be able to.

Referring to FIG. 4, the first transmission circuit 320 includes a third transistor M3, and the second transmission circuit 330 includes a fourth transistor M4. The third transistor M3 has a gate terminal coupled to the fourth node N, a first terminal configured to receive the first voltage VDD, and a second terminal coupled to the first node Q1. For example, when the fourth node N is set to a high voltage level, the third transistor M3 is turned on, so that the first voltage VDD can be used to charge the first node Q1. Optionally, the voltage level at the first node Q1 is charged to the level of the first voltage VDD within at least 10%. The fourth transistor M4 has a gate terminal coupled to the fourth node N, a first terminal configured to receive the first voltage VDD, and a second terminal coupled to the second node Q2. For example, when the fourth node N is set to a high voltage level, the fourth transistor M4 is turned on, so that the first voltage VDD can be used to charge the second node Q2.

Referring to FIG. 5A, in one specific embodiment, the blanking input subunit 300A includes a second transistor M2 having a first terminal configured to receive the first voltage VDD and a first transmission signal TS1. A third transistor M3 having a gate terminal configured to receive the second transmission signal TS2 and a fourth transistor M4 having a gate terminal configured to receive the second transmission signal TS2. The third transistor M3 further has a first terminal connected to the fourth node N, and the fourth transistor M4 further has a first terminal connected to the fourth node N. During the frame display period, when the first node Q1 needs to be charged, a high voltage may optionally be supplied to the first transmission signal TS1 to turn on the third transistor M3. Therefore, the first voltage VDD having a high voltage level can pass through the second transistor M2, the fourth node N, and the third transistor M3 to charge the first node Q1. During the blank period of the frame, when the second node Q2 needs to be charged, a high voltage may optionally be supplied to the second transmission signal TS2 to make the fourth transistor M4 conductive, so that the high The first voltage VDD having the voltage level may pass through the second transistor M2, the fourth node N, and the fourth transistor M4 to charge the second node Q2.

Referring to FIG. 5B, in another specific embodiment, blank input subunit 300B includes a third transistor M3 and a fourth transistor M4. The third transistor M3 and the fourth transistor M4 are each configured such that their gate terminals receive the first clock signal CLKA. In other words, TS1=TS2=CLKA. For example, in the blank period of a frame, when the first clock signal CLKA is provided with a high voltage level, the third transistor M3 and the fourth transistor M4 are turned on simultaneously, and the first voltage VDD at the high voltage level is Node Q1 and second node Q2 can be charged simultaneously.

Referring to FIG. 5C, in yet another specific embodiment, blank input subunit 300C includes a second transistor M2 having a first terminal configured to receive a first clock signal CLKA. The third transistor M3 and the fourth transistor M4 are each configured to have a gate terminal connected to a first terminal of the second transistor M2 to receive the first clock signal CLKA. Therefore, the first terminal of the second transistor M2 in FIG. 5C is connected to the high voltage in a shorter time than the second transistor M2 in FIG. 5B, where the first terminal is always connected to the first voltage VDD at the high voltage level. Can be set to level. Therefore, the second transistor M2 in FIG. 5C has a longer lifespan and can ensure the stability of the shift register unit.

Referring to FIG. 5D, in yet another specific embodiment, blank input subunit 300D further includes a first coupling capacitor CST1 in addition to the circuit shown in FIG. 5C. Coupling capacitor CST1 has a first terminal configured to receive the first clock signal CLKA and a second terminal coupled to the third node H. When the first clock signal CLKA is changed from a low voltage level to a high voltage level, the first clock signal CLKA raises the voltage level at the third node H due to the coupling effect of the first coupling capacitor CST1. The voltage level of the third node H can be pushed higher, ensuring that the second transistor M2 is fully turned on.

Referring to FIG. 5E, in yet another specific embodiment, blank input subunit 300E further includes a second coupling capacitor CST2 in addition to the circuit shown in FIG. 5D. The second coupling capacitor CST2 has a first terminal connected to the third node H and a second terminal connected to the fourth node N. When the first clock signal CLKA is changed from a low voltage level to a high voltage level, when the second transistor M2 is turned on, the first clock signal CLKA at the high voltage level is transferred to the fourth node N via the second transistor M2. can be passed. The voltage level at the second terminal of the second coupling capacitor CST2 is raised. The bootstrap effect of the coupling capacitor pushes the voltage level at the third node H even higher to ensure that the second transistor M2 is fully turned on.

Referring to FIG. 5F, in yet another specific embodiment, the blank input subunit 300F further includes a forty-second transistor M42 in addition to the circuit shown in FIG. 5E. The forty-second transistor M42 has a gate terminal connected to the third node H, a first terminal configured to receive the first clock signal CLKA, and a first terminal of the first coupling capacitor CST1. and a second terminal. When the third node H is set to a high voltage level, the forty-second transistor M42 is turned on. Then, the first clock signal CLKA can pull up the third node H due to the coupling effect of the first coupling capacitor CST1, and the third node H is pushed up to a higher voltage level, so that the second transistor M2 is fully activated. Guaranteed to turn on.

FIG. 6 is a circuit diagram of a blank input subunit including a leak-proof structure according to an embodiment of the present disclosure. Referring to FIG. 6, in an alternative embodiment, the blank input subunit 300' further includes a forty-third transistor M43, transistors M1_b, M3_b and M4_b in addition to the circuit shown in FIG. 5E. The forty-third transistor M43 has a gate terminal connected to the third node H, a first terminal configured to receive the sixth voltage VB, and a second terminal connected to the second terminal of the first transistor M1. and has. The transistor M1_b has a gate terminal configured to receive the selection control signal OE, a first terminal connected to the second terminal of the first transistor M1, and a second terminal connected to the third node H. has. Transistor M3_b and transistor M4_b are both configured such that their gate terminals receive the first clock signal CLKA. The first terminals of both the transistor M3_b and the transistor M4_b are connected to the seventh node OF. Transistor M3_b further has a second terminal connected to first node Q1, and transistor M4_b further has a second terminal connected to second node Q2.

The forty-third transistor M43 and the transistor M1_b are combined to provide a leakage prevention function that prevents leakage at the third node H. Transistor M3_b can also prevent leakage at the first node Q1. Transistor M4_b can also prevent leakage at the second node Q2. Optionally, the sixth voltage VB is set to a high voltage level. Optionally, more details about the anti-leakage function implemented in the blanking input subunit and its association with the seventh node OF will be explained in the following specification. Optionally, the transistors used in the blank input subunits shown in FIGS. 4, 5A to 5F, and 6 are all N-type transistors.

FIG. 7 is a block diagram of a shift register unit according to yet another embodiment of the present disclosure. Referring to FIG. 7, in addition to the circuit shown in FIG. 2, the shift register unit 10B includes a first control circuit 130, a first reset circuit 140, a second reset circuit 150, a shift register output terminal CRT, and a first output terminal OP1. A shift register output terminal CRT is provided to output a shift register signal CR. The first output terminal OP1 is provided to output the first output signal OUT1.

The first control circuit 1130 is configured to control the voltage level QB_A at the fifth node in response to the voltage level at the first node Q1 and the second voltage VDD_A. For example, the first control circuit 130 is connected to the first node Q1 and the fifth node QB_A, and is configured to receive the second voltage VDD_A and the fourth voltage VGL1. When the first node Q1 is set to a high voltage level (allowing a 10% error), the first control circuit 130 uses the fourth voltage VGL1 at a low voltage level to set the voltage level QB_A of the fifth node to a low voltage level. can be lowered to the level. Optionally, when the first node Q1 is set to a low voltage level (allowing a 10% error), the first control circuit 130 increases the voltage level QB_A of the fifth node to a high voltage level. The fifth node QB_A can be charged using the second voltage VDD_A at a high voltage level.

The first reset circuit 140 is configured to reset the voltage levels at the first node Q1, the shift register output terminal CRT, and the first output terminal OP1 in response to the voltage level at the fifth node QB_A. The first reset circuit 140 is connected to the first node Q1, the fifth node QB_A, the shift register output terminal CRT, and the first output terminal OP1, respectively, and is configured to receive the fourth voltage VGL1 and the fifth voltage VGL2. Ru. When the first reset circuit 140 is turned on by the voltage level QB_A at the fifth node, the fourth voltage VGL1 (at a low voltage level) is used to set the voltage level Q1 at the first node and the shift register output terminal CRT to a low voltage. level can be lowered or reset. At the same time, the voltage level of the first output terminal OP1 can be lowered or reset to a lower voltage level using the fifth voltage VGL2 (also at a lower voltage level). Optionally, the first reset circuit 140 may also use the fourth voltage VGL1 to lower or reset the voltage level of the first output terminal OP1 to a low voltage level.

The second reset circuit 150 is configured to reset the voltage levels of the first node Q1, the shift register output terminal CRT, and the first output terminal OP1 in response to the voltage level at the sixth node QB_B. Referring to FIG. 7, the second reset circuit 150 is connected to the first node Q1, the sixth node QB_B, the shift register output terminal CRT, and the first output terminal OP1, and receives the fourth voltage VGL1 and the fifth voltage VGL2. configured to receive. When turned on by the voltage level at the sixth node QB_B, the second reset circuit 150 optionally utilizes the fourth voltage VGL1 (at a low voltage level) to reset the voltage at the first node Q1 and the shift register output terminal CRT. The voltage level can be pulled down or reset to a lower voltage level. At the same time, the fifth voltage VGL2 (at a low voltage level) can optionally be used to reduce or reset the voltage level of the first output terminal OP1 to a low voltage level.

Referring to FIG. 7, the second subunit 200B further includes a second control circuit 230, a third reset circuit 240, a fourth reset circuit 250, and a second output terminal OP2. The second output terminal OP2 is configured to output a second output signal OUT2.

The second control circuit 230 is configured to control the voltage level of the sixth node QB-B in response to the voltage level of the second node Q2 and the third voltage VDD_B. Referring to FIG. 7, the second control circuit 230 is connected to the second node Q2 and the sixth node QB_B, and is configured to receive the third voltage VDD_B and the fourth voltage VGL1. When the second node Q2 is set to a high voltage level, the second control circuit 230 may lower the voltage level of the sixth node QB_B to a low voltage level using the fourth voltage VGL1 having a low voltage level. When the second node Q2 is set to a low voltage level, the second control circuit 230 also uses the third voltage VDD_B (at a high voltage level) to raise the voltage level of the sixth node QB_B. Can charge 6 nodes QB_B.

The third reset circuit 240 is configured to reset the second node Q2 and the second output terminal OP2 to a low voltage level in response to the voltage level at the sixth node QB_B. For example, the third reset circuit 240 is connected to the second node Q2, the sixth node QB_B, and the second output terminal OP2, and is configured to receive the fourth voltage VGL1 and the fifth voltage VGL2. When the third reset circuit 240 is turned on by the voltage level at the sixth node QB_B, the fourth voltage VGL1 may optionally be used to lower the voltage level at the second node Q2 to a low voltage level. At the same time, the fifth voltage VGL2 may optionally be used to lower the voltage level at the second output terminal OP2. Optionally, the fourth voltage VGL1 may be used to pull down or reset the second output terminal OP2 to a low voltage level.

The fourth reset circuit 250 is configured to reset the second node Q2 and the second output terminal OP2 in response to the voltage level at the fifth node QB_A. For example, the fourth reset circuit 250 is connected to the second node Q2, the fifth node QB_A, and the second output terminal OP2, and is configured to receive the fourth voltage VGL1 and the fifth voltage VGL2. When the fourth reset circuit 250 is turned on by the voltage level at the fifth node QB_A, it optionally utilizes the fourth voltage VGL1 (at a low voltage level) to pull down or reset the second node Q2 to a low voltage level. be able to. At the same time, the fifth voltage VGL2 (at a low voltage level) may optionally be used to pull down or reset the second output terminal OP2 to a low voltage level.

Optionally, the second voltage VDD_A and the third voltage VDD_B can be set as two opposite phase voltage signals, i.e. when the second voltage VDD_A is given a high voltage level, the third voltage VDD_B is given a low voltage level. is applied and the second voltage VDD_A is at a low voltage level, the third voltage VDD_B may be at a high voltage level. By setting in this way, only one of the first control circuit 130 and the second control circuit 230 can be in the operating mode at a time. This can avoid functional drift of the circuit due to long-term operation and improve the stability of the circuit.

Referring to FIG. 7, blank input subunit 300 of shift register unit 10B further includes a common reset circuit 340. The common reset circuit 340 is connected to the fourth node N, the fifth node QB_A, and the sixth node QB_B, respectively, and adjusts the voltage level of the fourth node N in response to the voltage level of the fifth node QB_A or the sixth node QB_B. configured to reset. For example, common reset circuit 340 may be configured to receive fourth voltage VGL1. When the common reset circuit 340 is turned on by the voltage level of the fifth node QB_A or the sixth node QB_B, the fourth node N may be pulled down or reset to a low voltage level using the fourth voltage VGL1. By installing a common reset circuit 340 in the blank input subunit, the voltage level at the fourth node N can be better controlled. When there is no need to charge the first node Q1 or the second node Q2, the fourth node N can be set to a low voltage level to turn off the first transmission circuit 320 and the second transmission circuit 330. Therefore, high voltage levels from the first voltage VDD are prevented from charging the first node Q1 and the second node Q2. In this way, abnormal signal output can be avoided and the stability of the circuit can be improved.

FIG. 8 is a block diagram of a shift register unit according to yet another embodiment of the present disclosure. Referring to FIG. 8, the shift register unit 10C includes a first subunit 100 that further includes a third control circuit 160 and a fourth control circuit 170 in addition to the circuit shown in FIG. The third control circuit 160 is configured to control the voltage level of the fifth node QB_A in response to the first clock signal CLKA. The fourth control circuit 170 is configured to control the voltage level of the fifth node QB_A in response to the first input signal STU1.

In one embodiment, the third control circuit 160 is connected to the fifth node QB_A and configured to receive the first clock signal CLKA and the fourth voltage VGL1. For example, during the display period of a frame, the third control circuit 160 is turned on in response to the first clock signal CLKA, and as a result, the fourth voltage VGL1 can be used to pull the fifth node QB_A to a low voltage level. can. In another embodiment, the third control circuit 160 is also connected to a third node H. During the blank period of the frame, if the third node H is set to a high voltage level and the first clock signal CLKA is provided with a high voltage level, the third control circuit 160 is turned on, resulting in a low voltage level. The fifth node QB_A can be pulled down to a low voltage level using the fourth voltage VGL1.

The fourth control circuit 170 is connected to the fifth node QB_A and configured to receive the first input signal STU1 and the fourth voltage VGL1. For example, during the display period of a frame, the fourth control circuit 170 is turned on in response to the first input signal STU1, and can pull down the fifth node QB_A to a low voltage level using the fourth voltage VGL1. When the fifth node QB_A is pulled down to a low voltage level, the influence of the fifth node QB_A on the first node Q1 can be avoided, resulting in more sufficient charging of the first node Q1 during the display period.

Referring to FIG. 8, the second subunit 200 further includes a fifth control circuit 260 and a sixth control circuit 270 in addition to the circuit shown in FIG. The fifth control circuit 260 is configured to control the voltage level of the sixth node QB_B in response to the first clock signal CLKA. The sixth control circuit 270 is configured to control the voltage level of the sixth node QB_B in response to the first input signal STU1.

In one embodiment, the fifth control circuit 260 is connected to the sixth node QB_B and configured to receive the first clock signal CLKA and the fifth voltage VGL1. For example, during a frame blank period, the fifth control circuit 260 may be turned on in response to the first clock signal CLKA. Therefore, the voltage level at the sixth node QB_B can be lowered by using the fourth voltage VLG1 at a low voltage level. In another embodiment, the fifth control circuit 260 is also connected to the third node H. For example, in the blank period of a frame, if the third node H is set to a high voltage level and the first clock signal CLKA is provided with a high voltage level, the fifth control circuit 260 is turned on, and as a result, the fourth Voltage VGL1 may be used to pull down the sixth node QB_B to a low voltage level.

The sixth control circuit 270 is connected to the sixth node QB_B and configured to receive the first input signal STU1 and the fourth voltage VGL1. For example, during a frame display period, the sixth control circuit 270 is turned on in response to the first input signal STU1. The sixth node QB_B can be pulled down using the fourth voltage VGL1 at a low voltage level. The sixth node QB_B is pulled down to a low voltage level to prevent the influence of the sixth node QB_B on the second node Q2, so that the second node Q2 is more fully charged during the display period.

Referring to FIG. 8, the first subunit 100C further includes a fifth reset circuit 180 and a sixth reset circuit 190. The fifth reset circuit 180 is configured to reset the first node Q1 in response to the display reset signal STD. The sixth reset circuit 190 is configured to reset the first node Q1 in response to the full-scale reset signal TRST.

In one embodiment, the fifth reset circuit 180 is connected to the first node Q1 and configured to receive the display reset signal STD and the fourth voltage VGL1. During the frame display period, the fifth reset circuit 180 is turned on in response to the display reset signal STD, and as a result, the first node Q1 can be pulled down or reset using the fourth voltage VGL1 at a low voltage level. can. For example, when a plurality of shift register units 10C are cascade-connected to form a multistage gate drive circuit, the shift register unit 10C at one stage uses the shift register signal CR output from the shift register unit at another stage as the display reset signal. Can be received as STD.

In one embodiment, the sixth reset circuit 190 is connected to the first node Q1 and configured to receive the full-scale reset signal TRST and the fourth voltage VGL1. When a plurality of shift register units 10C are cascade-connected to form a multistage gate drive circuit, the sixth reset circuit 190 in each stage of shift register units 10C responds to the full-scale reset signal TRST during the frame display period. Turns on. Therefore, the fourth voltage VGL1 at a low voltage level can be used to pull down or reset the first node Q1 of the shift register unit 10C of each stage, thereby realizing a full-scale reset for the gate drive circuit. .

Referring to FIG. 8, the second subunit 200C further includes a seventh reset circuit 280 and an eighth reset circuit 290. The seventh reset circuit 280 is configured to reset the second node Q2 in response to the display reset signal STD. The eighth reset circuit 290 is configured to reset the second node Q2 in response to the full-scale reset signal TRST.

In one embodiment, the seventh reset circuit 280 is connected to the second node Q2 and configured to receive the display reset signal STD and the fourth voltage VGL1. For example, during the display period of a frame, the seventh reset circuit 280 is turned on in response to the display reset signal STD, and as a result, uses the fourth voltage VGL1 at a low voltage level to pull down or reset the second node Q2. be able to.

In one embodiment, the eighth reset circuit 290 is connected to the second node Q2 and configured to receive the full-scale reset signal TRST and the fourth voltage VGL1. For example, when a plurality of shift register units 10C are cascade-connected to form a multistage gate drive circuit, the eighth reset circuit 290 in each stage of shift register units responds to the full-scale reset signal TRST during the frame display period. It can turn on. Therefore, the fourth voltage VGL1 at a low voltage level can be used to pull down or reset the second node Q2 in the shift register unit 10C of each stage, thereby realizing a full-scale reset for the gate drive circuit. .

9A and 9B are circuit diagrams of a first subunit and a second subunit, respectively, of a shift register unit according to an embodiment of the present disclosure. In particular, FIG. 9A shows a portion of a shift register unit including a first subunit 100 and a blank input subunit 300. FIG. 9B shows a part of the shift register unit including the second subunit 200 and the second transmission circuit 330. Referring to FIGS. 9A and 9B, the shift register unit includes a number of transistors M1 to M41, a first capacitor C1, a second capacitor C2, and a third capacitor C3. All transistors used here are exemplified as N-type transistors. 10A to 10C are circuit diagrams of three types of first input circuits of a shift register unit according to an embodiment of the present disclosure.

In one embodiment, referring to FIG. 9A, the first input circuit 110 may be implemented by including a fifth transistor M5. The fifth transistor M5 has a gate terminal configured to receive the first input signal STU1, a first terminal configured to receive the first voltage VDD, and a second transistor connected to the first node Q1. It has a terminal.

In another embodiment, referring to FIG. 10A, the fifth transistor M5 is configured such that its gate terminal and its first terminal both receive the first input signal STU1, such that the first input signal STU1 is high. If it is a voltage signal, the fifth transistor M5 can charge the first node Q1 using the high voltage first input signal STU1.

In yet another embodiment, referring to FIG. 10B, the first input circuit 110 further includes a transistor M5_b. The transistor M5_b has a gate terminal and a first terminal both connected to the second terminal of the fifth transistor M5. Transistor M5_b further has a second terminal connected to first node Q1. Since the transistor M5_b uses a diode connection method, current can only flow from the first terminal to the second terminal of the transistor M5_b, and not vice versa. Therefore, leakage of current from the first node Q1 via the fifth transistor M5 is prevented.

In yet another embodiment, referring to FIG. 10C, transistor M5_b has a gate terminal coupled to a gate terminal of a fifth transistor M5, both of which are configured to receive the first input signal STU1. Transistor M5_b has a first terminal connected to the seventh node OF. The first input circuit 110 shown in FIG. 10C employs a leakage prevention circuit structure that prevents leakage of the first node Q1.

Referring again to FIG. 9A, the first output circuit 120 may be implemented by including a sixth transistor M6, a seventh transistor M7, and a second capacitor C2. The sixth transistor M6 has a gate terminal connected to the first node Q1. The sixth transistor M6 has a first terminal configured to receive the second clock signal CLKB as a shift register signal CR. The sixth transistor M6 has a second terminal coupled to the shift register output terminal CRT and configured to output a shift register signal CR.

The seventh transistor M7 has a gate terminal connected to the first node Q1. The seventh transistor M7 has a first terminal configured to receive the third clock signal CLKC as a first output signal OUT1. The seventh transistor M7 has a second terminal coupled to the first output terminal OP1 and configured to output the first output signal OUT1. The second capacitor C2 has a first terminal connected to the first node Q1 and a second terminal connected to the second terminal of the seventh transistor M7, which is also the first output terminal OP1.

Referring again to FIG. 9B, the second input circuit 210 may be implemented by including an eighth transistor M8. The eighth transistor M8 has a gate terminal configured to receive the first input signal STU1. Eighth transistor M8 has a first terminal configured to receive a first voltage VDD. The eighth transistor M8 has a second terminal connected to the second node Q2. Alternatively, the second input circuit 210 may employ a similar circuit shown in FIGS. 10A to 10C.

Referring to FIG. 9B, the second output circuit 220 may be implemented by including a ninth transistor M9 and a third capacitor C3. The ninth transistor M9 has a gate terminal connected to the second node Q2. The ninth transistor M9 has a first terminal configured to receive the fourth clock signal CLKD as a second output signal OUT2. The ninth transistor M9 has a second terminal coupled to the second output terminal OP2 and configured to output a second output signal OUT2. The third capacitor C3 has a first terminal connected to the second node Q2 and a second terminal connected to the second terminal of the ninth transistor M9, which is also the second output terminal OP2.

Referring to FIG. 9A, the common reset circuit 340 may be implemented by including a tenth transistor M10 and an eleventh transistor M11. The tenth transistor M10 has a gate terminal connected to the fifth node QB_A. The tenth transistor M10 has a first terminal connected to the fourth node N. A tenth transistor M10 has a second terminal configured to receive a fourth voltage VGL1. The eleventh transistor M11 has a gate terminal connected to the sixth node QB_B. The eleventh transistor M11 has a first terminal connected to the fourth node N. The eleventh transistor M11 has a second terminal configured to receive the fourth voltage VGL1.

Referring to FIG. 9A, the first control circuit 130 may be implemented by including a twelfth transistor M12 and a thirteenth transistor M13. The twelfth transistor M12 has a gate terminal and a first terminal both configured to receive the second voltage VDD_A. The twelfth transistor M12 further has a second terminal connected to the fifth node QB_A. The thirteenth transistor M13 has a gate terminal connected to the first node Q1. The thirteenth transistor M13 has a first terminal connected to the fifth node QB_A. The thirteenth transistor M13 further has a second terminal configured to receive a fourth voltage VGL1.

Referring to FIG. 9A, the first reset circuit 140 may be implemented by including a fourteenth transistor M14, a fifteenth transistor M15, and a sixteenth transistor M16. The second reset circuit 150 can be realized by including a 17th transistor M17, an 18th transistor M18, and a 19th transistor M19.

The fourteenth transistor M14 has a gate terminal connected to the fifth node QB_A, a first terminal connected to the first node Q1, and a second terminal configured to receive the fourth voltage VGL1. The fifteenth transistor M15 has a gate terminal coupled to the fifth node QB_A, a first terminal coupled to the shift register output terminal CRT, and a second terminal configured to receive the fourth voltage VGL1. . The sixteenth transistor M16 has a gate terminal connected to the fifth node QB_A, a first terminal connected to the first output terminal OP1, and a second terminal configured to receive the fifth voltage VGL2. .

The seventeenth transistor M17 has a gate terminal connected to the sixth node QB_B, a first terminal connected to the first node Q1, and a second terminal configured to receive the fourth voltage VGL1. The eighteenth transistor M18 has a gate terminal coupled to the sixth node QB_B, a first terminal coupled to the shift register output terminal CRT, and a second terminal configured to receive the fourth voltage VGL1. . The nineteenth transistor M19 has a gate terminal connected to the sixth node QB_B, a first terminal connected to the first output terminal OP1, and a second terminal configured to receive the fifth voltage VGL2. .

Referring again to FIG. 9B, the second control circuit 230 may be implemented by including a 20th transistor M20 and a 21st transistor M21. The twentieth transistor M20 has a gate terminal and a first terminal, both of which are configured to receive the third voltage VDD_B. The twentieth transistor M20 has a second terminal connected to the sixth node QB_B. The twenty-first transistor M21 has a gate terminal connected to the second node Q2. The twenty-first transistor M21 has a first terminal connected to the sixth node QB_B. The twenty-first transistor M21 further has a second terminal configured to receive a fourth voltage VGL1.

Referring to FIG. 9B, the third reset circuit 240 includes a 22nd transistor M22 and a 23rd transistor M23. The fourth reset circuit 250 includes a 24th transistor M24 and a 25th transistor M25.

The twenty-second transistor M22 has a gate terminal connected to the sixth node QB_B, a first terminal connected to the second node Q2, and a second terminal configured to receive the fourth voltage VGL1. The twenty-third transistor M23 has a gate terminal connected to the sixth node QB_B, a first terminal connected to the second output terminal OP2, and a second terminal configured to receive the fifth voltage VGL2. .

The twenty-fourth transistor M24 has a gate terminal connected to the fifth node QB_A, a first terminal connected to the second node Q2, and a second terminal configured to receive the fourth voltage VGL1. The twenty-fifth transistor M25 has a gate terminal coupled to the fifth node QB_A, a first terminal coupled to the second output terminal OP2, and a second terminal configured to receive the fifth voltage VGL2. .

Optionally, the second voltage VDD_A and the third voltage VDD_B can be set as two opposite phase voltage signals, i.e. when the second voltage VDD_A is given a high voltage level, the third voltage VDD_B is given a low voltage level. is applied and the second voltage VDD_A is at a low voltage level, the third voltage VDD_B may be at a high voltage level. By setting in this way, only one of the first control circuit 130 and the second control circuit 230 can be brought into conduction at a time. Therefore, performance drift of the transistor due to being set in a conductive state for a long time can be avoided, and the stability of the circuit can be improved.

9A and 9B, the first control circuit 130 installed in the first subunit 100 is used to control the voltage level of the fifth node QB_A, and the second control circuit 130 installed in the second subunit 200 is used to control the voltage level of the fifth node QB_A. The control circuit 230 is used to control the voltage level of the sixth node QB_B. In this way, the number of transistors in the shift register unit can be reduced, making it possible to reduce the frame size and improve the PPI of a display device using the shift register unit.

Referring to FIG. 9A, the third control circuit 160 includes a 32nd transistor M32 and a 33rd transistor M33. The 32nd transistor M32 has a gate terminal configured to receive the first clock signal CLKA, a first terminal coupled to the fifth node QB_A, and a second terminal coupled to the first terminal of the 33rd transistor M13. It has a terminal. The thirty-third transistor M33 has a gate terminal coupled to the third node H and a second terminal configured to receive the fourth voltage VGL1. The fourth control circuit 170 includes a 34th transistor M34. The 34th transistor M34 has a gate terminal configured to receive the first input signal STU1, a first terminal coupled to the fifth node QB_A, and a second terminal configured to receive the fourth voltage VGL1. It has a terminal.

Referring to FIG. 9B, the fifth control circuit 260 includes a 35th transistor M35 and a 36th transistor M36. The 35th transistor M35 has a gate terminal configured to receive the first clock signal CLKA, a first terminal coupled to the sixth node QB_B, and a second terminal coupled to the first terminal of the 36th transistor M36. It has a terminal. The thirty-sixth transistor M36 further has a gate terminal coupled to the third node H and a second terminal configured to receive the fourth voltage VGL1. The sixth control circuit 270 includes a 37th transistor M37, the 37th transistor M37 has a gate terminal configured to receive the first input signal STU1, and a first terminal coupled to the sixth node QB_B. and a second terminal configured to receive a fourth voltage VGL1.

Referring to FIG. 9A, the fifth reset circuit 180 includes a 38th transistor M38, and the sixth reset circuit 190 includes a 40th transistor M40. The 38th transistor M38 has a gate terminal configured to receive the display reset signal STD, a first terminal connected to the first node Q1, and a second terminal configured to receive the fourth voltage VGL1. and has. The fortieth transistor M40 has a gate terminal configured to receive the full-scale reset signal TRST, a first terminal coupled to the first node Q1, and a second terminal configured to receive the fourth voltage VGL1. It has a terminal.

Referring to FIG. 9B, the seventh reset circuit 280 includes a 39th transistor M39, and the eighth reset circuit 290 includes a 41st transistor M41. The 39th transistor M39 has a gate terminal configured to receive the display reset signal STD, a first terminal connected to the second node Q2, and a second terminal configured to receive the fourth voltage VGL1. and has. The forty-first transistor M41 has a gate terminal configured to receive the full-scale reset signal TRST, a first terminal coupled to the second node Q2, and a second terminal configured to receive the fourth voltage VGL1. It has a terminal.

In an alternative embodiment, FIGS. 11A and 11B are circuit diagrams of respective first and second subunits of a shift register unit that are slightly different from the shift register units shown in FIGS. 9A and 9B. Referring to FIGS. 11A and 11B, the first subunit 100 further includes a third output terminal OP3 in addition to the circuits shown in FIGS. 9A and 9B. The third output terminal OP3 is configured to output a third output signal OUT3. In addition to the circuits shown in FIGS. 9A and 9B, the second subunit 200 further includes a fourth output terminal OP4 configured to output a fourth output signal OUT4. Accordingly, the first reset circuit 140 and the second reset circuit 150 are also configured to reset the third output terminal OP3. The third reset circuit 240 and the fourth reset circuit 250 are also configured to reset the fourth output terminal OP4.

Referring to FIG. 11A, the first output circuit 120 further includes a twenty-sixth transistor M26 and a fourth capacitor C4 in addition to the circuit shown in FIG. 9A. The twenty-sixth transistor M26 has a gate terminal connected to the first node Q1, a first terminal configured to receive the fifth clock signal CLKE, and a second terminal connected to the third output terminal OP3. have The fourth capacitor C4 has a first terminal connected to the first node Q1 and a second terminal connected to the third output terminal OP3.

In one example, the fifth clock signal CLKE is configured to be the same as the third clock signal CLKC. In another example, the fifth clock signal CLKE is configured differently than the third clock signal CLKC, such that the first output terminal OP1 and the third output terminal OP3 can output different signals, such that the first output terminal OP1 and the third output terminal OP3 can output different signals. The versatility of shift register units providing different drive signals is enhanced.

The first reset circuit 140 in FIG. 11A further includes a 27th transistor M27, and the 27th transistor M27 has a gate terminal connected to the fifth node QB_A, and a first terminal connected to the third output terminal OP3. and a second terminal configured to receive a fifth voltage VGL2. The second reset circuit 150 in FIG. 11A further includes a 28th transistor M28, and the 28th transistor M28 has a gate terminal connected to the sixth node QB_B, and a first terminal connected to the third output terminal OP3. and a second terminal configured to receive a fifth voltage VGL2.

Referring to FIG. 11B, the second output circuit 220 further includes a 29th transistor M29 and a fifth capacitor C5 in addition to the circuit of FIG. 9B. The 29th transistor M29 has a gate terminal connected to the second node Q2, a first terminal configured to receive the sixth clock signal CLKF, and a second terminal connected to the fourth output terminal OP4. . The fifth capacitor C5 has a first terminal connected to the second node Q2 and a second terminal connected to the fourth output terminal OP4.

In one embodiment, the sixth clock signal CLKF is configured to be the same as the fourth clock signal CLKD. In another embodiment, the sixth clock signal CLKF is configured to be different from the fourth clock signal CLKD, so that the second output terminal OP2 and the fourth output terminal OP4 can respectively output different signals. , the versatility of the shift register unit is enhanced by providing multiple different drive signals.

The third reset circuit 240 in FIG. 11B further includes a 30th transistor M30, and the 30th transistor M30 has a gate terminal connected to the sixth node QB_B, and a first terminal connected to the fourth output terminal OP4. and a second terminal configured to receive a fifth voltage VGL2. The fourth reset circuit 250 in FIG. 11B further includes a 31st transistor M31, and the 31st transistor M31 has a gate terminal connected to the fifth node QB_A, a first terminal connected to the fourth output terminal OP4, and a second terminal configured to receive a fifth voltage VGL2.

As described above, in the shift register unit 10 (or 10A, 10B, 10C) according to the embodiment of the present disclosure, the voltage level at the third node H can be maintained by the first capacitor C1. The voltage level at the first node Q1 can be maintained by the second capacitor C2 and the fourth capacitor C4 (error within at least 10%). The voltage level at the second node Q2 can be maintained by the third capacitor C3 and the fifth capacitor C5. The first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4, and the fifth capacitor C5 may be capacitor elements manufactured by a thin film process, for example, by manufacturing a specialized capacitor electrode to form a capacitor element. can be realized. The electrodes can be realized by metal layers, semiconductor layers (e.g. doped polysilicon), etc., or in some examples by designing circuit routing parameters, the first capacitor C1, the second capacitor C2, the second capacitor The third capacitor C3, the fourth capacitor C4, and the fifth capacitor C5 may be realized by parasitic capacitance between various elements. The method of connecting the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4, and the fifth capacitor C5 is not limited to the above method. Any other suitable connection scheme may be used as long as the accumulation of charge can be written to the voltage levels of the third node H, the first node Q1, and the second node Q2.

When the first node Q1, the second node Q2 or the third node H is maintained at a high voltage level, some transistors (the first transistor M1, the fourteenth transistor M14, the seventeenth transistor M17, the thirty-eighth transistor M38, the 40 transistors M40, 22nd transistors M22, 24th transistors M24, 39th transistors M39, 41st transistors M41, etc.) have their first terminals connected to the first node Q1, the second node Q2, or the third node H, respectively, The second terminal is coupled to a low voltage level. Although the gate terminals of these transistors receive the turn-off signal, current leakage may still occur between the first and second terminals due to the difference in voltage levels between the first and second terminals. This leakage problem reduces the stability of maintaining the voltage level at the first node Q1, the second node Q2, or the third node H, respectively.

12A-12C are circuit diagrams of shift register units with anti-leakage circuit structures according to some embodiments of the present disclosure. Referring to FIGS. 12A and 12B, the shift register unit further includes a common leakage prevention circuit, a first leakage prevention circuit, and a second leakage prevention circuit. Particularly, the common leakage prevention circuit is electrically connected to the first node Q1 and the seventh node OF, and configured to control the voltage level of the seventh node OF in response to the voltage level of the first node Q1. be done. The first leakage prevention circuit is connected to the seventh node OF, the first reset circuit 140, the second reset circuit 150, the fifth reset circuit 180, and the sixth reset circuit 190, and is responsive to the voltage level of the seventh node OF. The first node Q1 is configured to prevent electrical leakage at the first node Q1. The second leakage prevention circuit is connected to the seventh node OF, the third reset circuit 240, the fourth reset circuit 250, the seventh reset circuit 280, and the eighth reset circuit 290, and is connected to the voltage level at the seventh node OF. In response, the second node Q2 is configured to prevent electrical leakage.

For example, as shown in FIGS. 12A and 12B, the common leakage prevention circuit includes a 44th transistor M44, which has a gate terminal connected to the first node Q1 and a sixth voltage VB. a first terminal configured to receive, and a second terminal coupled to a seventh node OF. The first leakage prevention circuit includes transistors M14_b, M17_b, M38_b, and M40_b. The second leakage prevention circuit includes transistors M22_b, M24_b, M39_b, and M41_b.

Furthermore, referring to FIG. 12A, in order to prevent leakage from the third node H, a 43rd transistor M43 and a transistor M1_b are added to the circuit. The transistor M1_b has a gate terminal connected to the gate of the first transistor M1. The transistor M1_b has a first terminal connected to a second terminal of the forty-third transistor M43. Transistor M1_b has a second terminal connected to third node H. The forty-third transistor M43 has a gate terminal connected to the third node H. The forty-third transistor M43 has a first terminal configured to receive a sixth voltage VB (high voltage). When a high voltage level is applied to the third node H, the 43rd transistor M43 is turned on, and as a result, the 6th voltage VB at the high voltage level can be input to the first terminal of the transistor M1_b, and the 43rd transistor M43 is turned on. Both the terminal and the second terminal are at a high voltage level to prevent the charge on the third node H from leaking through the transistor M1_b. At this time, the gate terminal of the transistor M1_b is connected to the gate terminal of the first transistor M1. The combination of the first transistor M1 and the transistor M1_b can realize the same function as the first transistor M1 and at the same time prevent leakage.

Similarly, as shown in FIG. 12A, transistors M14_b, M17_b, M38_b, and M40_b are connected to the 44th transistor M44 via the seventh node OF, and have a leakage prevention function to prevent current leakage from the first node Q1. Each can be achieved. As shown in FIG. 12B, transistors M22_b, M24_b, M39_b, and M41_b are also connected to the 44th transistor M44 via the seventh node OF, and can each realize a leakage prevention function to prevent current leakage from the second node Q2. . Referring to FIGS. 12A and 12B, the first leakage prevention circuit and the second leakage prevention circuit share one 44th transistor M44, which saves the number of transistors, reduces the size of the frame, and improves the display device. Improve the PPI of

In an alternative embodiment shown in FIG. 12C, the second leakage prevention circuit (transistors M22_b, M24_b, M39_b and M41_b) associated with the second subunit of the shift register unit is connected to the first subunit of the shift register unit. It is not connected to the shared seventh node OF. Instead, the second anti-leakage circuit referred to herein is configured to be coupled to a single eighth node commonly connected to a separate forty-fifth transistor M45 to form a leakage-proof structure.

Similarly, as shown in FIG. 6, in the case of the third transistor M3 and the fourth transistor M4, two different transistors M3_b and M4_b can be installed to realize a leakage-proof structure. In particular, transistors M3_b and M4_b are configured such that their gate terminals receive the first clock signal CLKA, and their first terminals are coupled to the seventh node OF to connect with the forty-fourth transistor M44 of FIG. 12A. to establish a leak-proof structure. This leakage prevention structure can prevent electrical leakage from both the first node Q1 and the second node Q2.

Similarly, as shown in FIG. 10C, for the fifth transistor M5, a transistor M5_b may be added to provide a leakage prevention structure. In particular, the gate terminal of transistor M5_b is configured to receive the first input signal STU1, and the first terminal of transistor M5_b is coupled to the seventh node OF to establish a connection with the forty-fourth transistor M44 of FIG. 12A. Establish. The leakage prevention structure can prevent electrical leakage from the first node Q1.

In an alternative embodiment, the scanning transistor and sensing transistor in the sub-pixel unit of the display panel may be selected as P-type transistors. In this case, FIGS. 13A and 13B show circuit diagrams of respective first and second subunits of a shift register unit according to yet another embodiment of the present disclosure. The shift register unit shown in FIGS. 13A and 13B is used as one of multiple units that are cascaded to form a gate drive circuit and is implemented in the display panel to drive display scanning and external compensation. obtain.

Any transistor used in embodiments of the present disclosure may be a thin film transistor or a field effect transistor or other switching device with the same characteristics. In the embodiments of the present disclosure, a thin film transistor will be described as an example. The sources and drains of the transistors used herein may be structurally symmetrical, so that the sources and drains may be structurally indistinguishable. In embodiments of the present disclosure, to distinguish between the two terminals of the transistor except for the gate terminal, one of the two terminals is referred to as a first terminal and the other is referred to as a second terminal. Furthermore, transistors are classified into N-type transistors and P-type transistors depending on their characteristics. If the transistor is a P-type transistor, the turn-on voltage is a low voltage (e.g., 0V, -5V, -10V or other suitable voltage) and the turn-off voltage is a high voltage (e.g., 5V, 10V or other suitable voltage). appropriate voltage). If the transistor is an N-type transistor, the turn-on voltage is a high voltage (e.g., 5V, 10V or other suitable voltage) and the turn-off voltage is a low voltage (e.g., 0V, -5V, -10V or other suitable voltage). appropriate voltage).

In another aspect, the present disclosure provides a gate drive circuit manufactured by cascading a plurality of shift register units in multiple stages in series. FIG. 14 shows a schematic diagram of a gate drive circuit according to an embodiment of the present disclosure. Referring to FIG. 14, the gate drive circuit 20 includes a multi-stage shift register unit 10. Here, each of the plurality of shift register units is substantially the shift register unit 10 described herein throughout. The notations A1, A2, A3, A4, A5, and A6 in FIG. 14 represent subunits of the shift register unit 10, respectively. For example, A1, A3 and A5 each represent three first subunits of three shift register units, and A2, A4 and A6 each represent three second subunits of three shift register units.

Referring to FIG. 14, each shift register unit 10 includes a first subunit and a second subunit, and outputs a first output signal OUT1 and a second output signal OUT2, respectively. When the gate driving circuit 20 is applied to drive a display panel, the first output signal OUT1 and the second output signal OUT2 can individually drive one row of sub-pixel units of the display panel. For example, A1, A2, A3, A4, A5, and A6 can drive sub-pixel units in the first row, second row, third row, fourth row, fifth row, and sixth row, respectively, in the display panel.

The gate drive circuit 20 of the present disclosure shares a blanking input subunit to reduce the frame size of a display device using the gate drive circuit and improve the PPI of the display device. At the same time, the gate drive circuit provides external compensation to the drive transistors in the sub-pixel units of randomly selected rows to eliminate brightness non-uniformity caused by virtual scan line exposure and row-by-row sequential compensation on the display panel. Avoid.

Referring to FIG. 14, the gate drive circuit 20 cascade-connected by the multi-stage shift register unit 10 connects a first sub-clock signal line CLK_1, a second sub-clock signal line CLK_2, and a third sub-clock signal line CLK_3. include. The (3n-2)th stage shift register unit is connected to the first sub-clock signal line CLK_1, and the (3n-2)th stage shift register unit is the first sub-unit that receives the second clock signal CLKB. has. The (3n-1)th stage shift register unit has a first subunit that is connected to the second subclock signal line CLK_2 and receives the second clock signal CLKB of the (3n-1)th stage shift register unit. . The 3nth stage shift register unit has a first subunit connected to the third subclock signal line CLK_3 to receive the second clock signal CLKB of the 3nth stage shift register unit. Here, n is a positive integer. As shown, a second clock signal CLKB may optionally be provided to a respective first subunit of each stage of shift register units functioning as a cascaded member of the gate drive circuit. The second clock signal CLKB may be used as a shift register signal CR output to drive shift scanning through the display panel.

Referring to FIG. 14, the gate drive circuit 20 has a fourth sub-clock signal line CLK_4, a fifth sub-clock signal line CLK_5, a sixth sub-clock signal line CLK_6, a seventh sub-clock signal line CLK_7, and an eighth sub-clock signal line CLK_7. It further includes a sub-clock signal line CLK_8 and a ninth sub-clock signal line CLK_9.

The first subunit of the (3n-2)th stage shift register unit is connected to the fourth sub-clock signal line CLK_4 and receives the third clock signal CLKC of the (3n-2)th stage shift register unit. . The second subunit of the (3n-2)th stage shift register unit is connected to the fifth sub-clock signal line CLK_5 and receives the fourth clock signal CLKD of the (3n-2)th stage shift register unit. .

The first subunit of the (3n-1)th stage shift register unit is connected to the sixth sub-clock signal line CLK_6 and receives the third clock signal CLKC of the (3n-1)th stage shift register unit. . The second subunit of the (3n-1)th stage shift register unit is connected to the seventh sub-clock signal line CLK_7 and receives the fourth clock signal CLKD of the (3n-1)th stage shift register unit. .

The first sub-unit of the 3n-th stage shift register unit is connected to the eighth sub-clock signal line CLK_8 and receives the third clock signal CLKC of the 3n-th stage shift register unit. The second subunit of the 3nth stage shift register unit is connected to the 9th subclock signal line CLK_9 and receives the 3nth stage shift register unit fourth clock signal CLKD.

Six sub-clock signal lines CLK_4, 5th sub-clock signal line CLK_5, 6th sub-clock signal line CLK_6, 7th sub-clock signal line CLK_7, 8th sub-clock signal line CLK_8 and 9th sub-clock signal line CLK_9. The signals are sequentially provided to the shift register units in each stage through the clock signal line and output as respective drive signals. Therefore, the waveforms of the drive signals output from the gate drive circuits overlap. Optionally, the pre-charging time of each row of sub-pixel units can be effectively increased, so that the gate drive circuit can be suitable for high frequency scanning display. Alternatively, gate drive circuit 20 employs eight clock signals. Optionally, gate drive circuit 20 employs ten clock signals.

Referring to FIG. 14, the gate drive circuit 20 further includes a tenth sub-clock signal line CLK_10, an eleventh sub-clock signal line CLK_11, and a twelfth sub-clock signal line CLK_12. The first subunit and the second subunit of the shift register unit 10 in each stage are commonly connected to the tenth subclock signal line CLK_10 to receive the full-scale reset signal TRST. Each stage of the shift register unit 10 has a common input circuit 310 connected together to the eleventh sub-clock signal line CLK_11 to receive the selection control signal OE. The first subunit, second subunit, and common input circuit 310 of the shift register unit 10 in each stage are commonly connected to the twelfth subclock signal line CLK_12 to receive the first clock signal CLKA.

Referring to FIG. 14, the gate drive circuit 20 further includes a 13th sub-clock signal line CLK_13 and a 14th sub-clock signal line CLK_14. The first subunit of the shift register unit 10 in each stage is connected to the thirteenth subclock signal line CLK_13 and receives the second voltage VDD_A. The second sub-unit of the shift register unit 10 in each stage is connected to the fourteenth sub-clock signal line CLK_14 and receives the third voltage VDD_B.

Referring to FIG. 14, the gate drive circuit 20 further includes a fifteenth sub-clock signal line CLK_15. The first subunit and the second subunit of the first stage shift register unit 10 are both connected to the fifteenth subclock signal line CLK_15 to receive the first input signal STU1.

Referring to FIG. 14, except for the shift register unit 10 in the first stage, the first subunit and the second subunit of the shift register unit in each of the other stages are the first subunits in the shift register unit 10 in the previous stage. unit and configured to receive the shift register signal CR as its own first input signal STU1. Except for the last two stages of shift register units, the first subunit and second subunit of each of the other stages of shift register units 10 are connected to the first subunit of the next two stages of shift register units 10. , is configured to receive the shift register signal CR as its own display reset signal STD.

FIG. 14 is just one of many examples of stage-to-stage cascading. In one embodiment, the shift register unit 10 in the gate drive circuit 20 may employ the circuit structure shown in FIGS. 9A and 9B.

FIG. 15 is a timing diagram for operating the gate drive circuit of FIG. 14 according to an embodiment of the present disclosure. Referring to FIG. 15, H<5> represents the third node H in the third stage shift register unit 10. The third stage shift register unit 10 corresponds to the sub-pixel units in the fifth and sixth rows of the display panel. N<5> represents the fourth node N in the third stage shift register unit 10. Q1<1> and Q2<2> represent the first node Q1 and the second node Q2 of the first stage shift register unit 10, respectively. Q1<5> and Q2<6> represent the first node Q1 and the second node Q2 of the third stage shift register unit 10, respectively. <> The numbers in parentheses represent the number of rows of sub-pixel units in the display panel corresponding to the nodes Q1 and Q2.

OUT1<1> and OUT2<2> represent the first output signal OUT1 and the second output signal OUT2 output from the first stage shift register unit 10, respectively. Similarly, OUT1<3> and OUT2<4> represent the first output signal OUT1 and the second output signal OUT2 output from the second stage shift register unit 10, respectively. OUT1<5> and OUT2<6> represent the first output signal OUT1 and the second output signal OUT2 output from the third stage shift register unit 10, respectively. CR<1>, CR<3>, and CR<5> represent shift register signals CR output from the first, second, and third stage shift register units 10, respectively. Referring to FIG. 15, in one example, CR<1> is the same as OUT1<1>. CR<3> is the same as OUT1<3>. CR<5> is the same as OUT1<5>.

1F represents the first frame (cycle time for displaying one frame of an image). DS represents the display period in the first frame. BL represents a blank period in the first frame. In the example shown in FIG. 15, the second voltage VDD_A is provided as a low voltage, and the third voltage VDD_B is provided as a high voltage.

Before the first frame 1F (displaying one frame of an image) begins, the tenth sub-clock signal line CLK_10 and the eleventh sub-clock signal line CLK_11 both provide high voltage signals. Both the 40th transistor M40 and the 41st transistor M41 in the shift register unit 10 of each stage are turned on. The voltage levels at the first node Q1 and the second node Q2 of the shift register unit 10 in each stage are reset. The first transistor M1 in the shift register unit 10 of each stage is also turned on. The second input signal STU2 received at this time is a low voltage signal and is used to reset the voltage level of the third node H in the shift register unit 10 of each stage, thereby starting the first frame 1F. Achieve a full-scale reset before.

During the display period DS of the first frame 1F, the gate drive circuit 20 controls the operation of the third stage shift register unit 10 (corresponding to the sub-pixel units in the fifth and sixth rows in the display panel) for each frame. This is cited here as an example to explain how a display panel is driven to display an image.

In the first period 1 of DS, the second stage shift register unit 10 has a first subunit that outputs the shift register signal CR<3> as a high voltage signal. This is used as the next or third stage shift register unit 10. In other words, the third stage shift register unit receives the high voltage first input signal STU1. Therefore, both the fifth transistor M5 and the eighth transistor M8 in the third stage shift register unit 10 are turned on. The first voltage VDED, which is a high voltage supplied from the power supply, charges the first node Q1<5> through the fifth transistor M5, and charges the second node Q2<6> through the eighth transistor M8. Therefore, the first node Q1<5> and the second node Q2<6> are both pulled to a high voltage level.

The seventh transistor M7 of the third stage shift register unit 10 is turned on by the high voltage at the first node Q1<5>. However, at this time, the third clock signal CLKC provided through the eighth sub-clock signal line CLK_8 is a low voltage signal. Therefore, the first output signal OUT1<5> from the third stage shift register unit 10 is a low voltage signal. The ninth transistor M9 in the third stage shift register unit 10 is turned on by the high voltage at the second node Q2<6>. However, at this time, the fourth clock signal CLKD provided through the ninth sub-clock signal line CLK_9 is a low voltage signal. Therefore, the second output signal OUT2<6> from the third stage shift register unit 10 is a low voltage signal. In this period 1, the preliminary charging operation to both the first node and the second node in the third stage shift register unit has been completed.

In the second period 1 of DS, the third clock signal CLKC provided through the eighth sub-clock signal line CLK_8 is changed to a high voltage signal. The voltage level <5> at the first node Q1 is pulled higher due to the bootstrap effect, keeping the seventh transistor M7 conductive. The first output signal OUT1<5> from the third stage shift register unit 10 is also changed from CLKC to a high voltage signal. However, at this time, the fourth clock signal CLKD provided through the ninth sub-clock signal line CLK_9 is still a low voltage signal. Therefore, the second output signal OUT2<6> from the third stage shift register unit 10 continues to be a low voltage signal.

In the third period 3 of DS, the fourth clock signal CLKD provided through the ninth sub-clock signal line CLK_9 is changed to a high voltage signal. The voltage level <6> at the second node Q2 is pulled higher due to the bootstrap effect. The ninth transistor M9 is maintained in a conductive state. Therefore, the second output signal OUT2<6> output from the third stage shift register unit 10 becomes a high voltage signal.

During the fourth period 4 of DS, the first node Q1<5> is still maintained at a high voltage level due to the charge retention effect of the second capacitor C2. Therefore, the seventh transistor M7 is in a conductive state. However, the third clock signal CLKC provided through the eighth sub-clock signal line CLK_8 is changed to a low voltage signal. Therefore, the first output signal OUT1<5> from the third stage shift register unit 10 is also changed to a low voltage signal. At the same time, the voltage level at the first node Q1<5> is also relatively reduced due to the bootstrap effect of the second capacitor C2.

During the fifth period 5 of DS, the second node Q2<6> is still maintained at a high voltage level due to the charge retention effect of the third capacitor C3. Therefore, the ninth transistor M9 is in a conductive state. However, the fourth clock signal CLKD provided through the ninth sub-clock signal line CLK_9 is changed to a low voltage signal. Therefore, the second output signal OUT2<6> from the third stage shift register unit 10 is also changed to a low voltage signal. At the same time, the voltage level at the second node Q2<6> is also relatively reduced due to the bootstrap effect of the third capacitor C3.

In the sixth period 6 of the DS, based on the assumption that six clock signals are employed in the gate drive circuit 20, the signals output from the shift register units 10 of every three stages (i.e., the first output signal from each stage) OUT1 and the second output signal OUT2) are repeated in cycles. At the same time, the third stage shift register unit 10 is configured to receive the shift register signal CR from the fifth stage shift register unit as its own display reset signal STD. During the sixth period 6, the third clock signal CLKC provided through the sixth sub-clock signal line CLK_6 is changed to a high voltage signal. Here, the display reset signal STD received by the third stage shift register unit 10 is also a high voltage signal, and both the 38th transistor M38 and the 39th transistor M39 become conductive. Therefore, the lowering or resetting operation for the first node Q1<5> and the second node Q2<6> can be completed using the fourth voltage VGL1 provided as a low voltage.

After the third-stage shift register unit 10 drives the fifth-row sub-pixel unit and the sixth-row sub-pixel unit in the display panel to display on their respective rows, the gate drive circuit 20 drives the fourth-stage sub-pixel unit Enable the shift register unit, or subsequently the fifth stage shift register unit (the same applies hereinafter), and drive the sub-pixel units in all rows on the display panel until the display period DS of the first frame 1F ends. The display of one frame of image is completed.

Furthermore, during the display period DS of the first frame 1F, the gate drive circuit 20 is also configured to charge the third node H. For example, if compensation of the sub-pixel unit of the fifth row is required during the display operation in the first frame 1F, the compensation operation is performed as follows.

During the second period 2 and third period 3 of DS, the 11th sub-clock signal line CLK_11 is configured to provide the same signal as the shift register signal CR<5> output from the third stage shift register unit 10. configured to turn on the first transistor M1. At the same time, the second input signal STU2 received by the third stage shift register unit 10 may be configured to be the same as the shift register signal CR<5>. Therefore, by charging the third node H<5> using the high voltage from the second input signal STU2, the voltage level of the third node H<5> can be raised to a high voltage level.

In an alternative embodiment, the second input signal STU2 received by the third stage shift register unit 10 is selectively the same as the shift register signal CR output from the other stage shift register unit and at the same time The signal provided through the 11 sub-clock signal line CLK_11 has the same signal timing as the second input signal STU2.

The high voltage at the third node H<5> may be maintained at all times until the blank period BL of the first frame 1F begins. If the sub-pixel units of the fifth row require external compensation during the first frame 1F, the operation of the third stage shift register unit in the gate driving circuit is performed as follows.

In the seventh period 7 (BL) of the first frame 1F, the fourth node N<5> changes its voltage level from a low voltage to a high voltage due to the coupling effect of the first capacitor C1, and thereby the third node N<5> changes its voltage level from a low voltage to a high voltage. Raise the voltage level of H<5>. Therefore, the voltage level at the third node H<5> is maintained at a relatively high level, ensuring that the second transistor M2 is fully conductive. During this period, the first clock signal CLKA provided via the twelfth sub-clock signal line CLK_12 is changed from a high voltage signal to a low voltage signal. Therefore, the fourth node N<5> also becomes a low voltage. Due to the coupling effect of the first capacitor C1, the voltage level at the third node H<5> also decreases.

In the eighth period 8 (BL) of the first frame 1F, the third clock signal CLKC provided through the eighth sub-clock signal line CLK_8 is changed to a high voltage signal. The voltage level at the first node Q1<5> is pushed higher due to the bootstrap effect, keeping the seventh transistor M7 conductive. Therefore, the first output signal OUT1<5> output from the third stage shift register unit 10 is changed to a high voltage signal. However, since the fourth clock signal CLKD provided via the ninth sub-clock signal line CLK_9 is still a low voltage signal, the second output signal OUT2<6> output from the third stage shift register unit 10 is , is a low voltage signal. In one example, the first output signal OUT1<5> in the eighth period 8 is used to drive a sensing transistor in a sub-pixel unit of the display panel to drive the display panel to display an image frame with uniform brightness. It is possible to realize external compensation for

In the ninth period 9 (BL) of the first frame 1F, the first node Q1<5> is still maintained at a high voltage due to the charge maintenance effect of the second capacitor C2, and the seventh transistor M7 is maintained in a conductive state. . However, since the third clock signal CLKC provided via the eighth sub-clock signal line CLK_8 is changed to a low voltage signal, the first output signal OUT1<5> output from the third stage shift register unit 10 also Changes to low voltage signal. At the same time, the voltage level at the first node Q1<5> also decreases due to the bootstrap effect of the second capacitor C2.

During the tenth period 10 (BL) of the first frame 1F, both the tenth sub-clock signal line CLK_10 and the eleventh sub-clock signal line CLK_11 provide high voltage signals. The 40th transistor M40 and the 41st transistor M41 in each stage of the shift register unit 10 of the gate drive circuit 20 are turned on. Thereby, the first node Q1 and the second node Q2 of the shift register unit 10 in each stage can be reset at those voltage levels. Furthermore, the first transistor M1 in the shift register unit 10 of each stage is turned on. Since the second input signal STU2 received at this time is a low voltage signal, as an option, the voltage level of the third node H in the shift register unit of each stage is reset, thereby completing the full-scale reset for the gate drive circuit. It is possible. At this point, the first frame 1F ends. The driving operations of the gate driving circuit in the subsequent second and third frames (the same applies hereinafter) are substantially the same, and will not be described repeatedly.

In one embodiment, if the gate drive circuit needs to output a drive signal for driving the sensing transistor in the nth row sub-pixel unit of the display panel during the blank period of one frame, then during the display period of the same frame, It is necessary to raise the third node H to a high voltage level. At the same time, during the blank period of one frame, it is necessary to provide the high voltage first clock signal CLKA to raise the voltage levels of the first node Q1 and the second node Q2. If it is necessary to output a high voltage drive signal, a high voltage third clock signal CLKC or fourth clock signal CLKD is required. Here, n is any positive integer. Optionally, the timing of the two signals is the same, meaning that they are synchronized in time, but need not be of the same signal amplitude.

FIG. 16 is a timing diagram for operating the gate drive circuit of FIG. 14 according to another embodiment of the present disclosure. In one embodiment, a gate drive circuit 20 operating according to a timing diagram is formed by cascading multiple shift register units based on the circuits shown in FIGS. 13A and 13B. The timing sequence and operating principle are similar to the description shown in FIG.

FIG. 17 is a schematic diagram of a gate drive circuit according to another embodiment of the present disclosure. In this embodiment, the gate drive circuit 20A is provided by cascading a plurality of shift register units based on the circuits shown in FIG. 11A or 12A and FIG. 11B or 12B. The shift register units (for example, A1, A3, A5) in odd-numbered stages output a first output signal OUT1<N> in response to a clock signal from a clock signal line CLKE_N (N=1, 3, 5); It is configured to output a second output signal OUT2 in response to a clock signal from a clock signal line CLKF_N (N=1, 3, 5). Unlike the odd-numbered shift register units in the gate drive circuit 20, it simply outputs one output signal OUT1. Here, CLKE_1h is configured to provide a third clock signal CLKC (see FIG. 11A or FIG. 12A), and CLKF_1 is configured to provide a fifth clock signal CLKE (see FIG. 11A or FIG. 12A). ). Each shift register unit (for example, A2, A4, A6) in an even numbered stage outputs a first output signal OUT1<N> in response to a clock signal from a clock signal line CLKE_N (N=2, 4, 6). , and is configured to output a second output signal OUT2 in response to a clock signal from a clock signal line CLKF_N (N=2, 4, 6). Unlike the even-numbered shift register units in the gate drive circuit 20, it simply outputs one output signal OUT2. Here, CLKE_2 is configured to provide a fourth clock signal CLKD (see FIG. 11B or FIG. 12B), and CLKF_2 is configured to provide a sixth clock signal CLKF (see FIG. 11B or FIG. 12B). ). FIG. 18 shows a timing diagram for operating the gate drive circuit 20A according to the embodiment of the present disclosure. Referring to FIG. 18, the operation of the gate drive circuit 20A will be described with respect to the gate drive circuit 20 in FIG. 15, except that waveforms Q1<3> and Q2<4> are added to the DS period of 1F of one frame. However, Q1<3> and Q2<4> are similar to Q1<1> and Q2<4>, respectively, except for the time shift determined by the clock on clock signal lines CLKE_4 and CLKF_4, respectively. The waveform is substantially the same as that of 2>.

FIG. 19 is a schematic diagram of a gate drive circuit according to another embodiment of the present disclosure. Gate drive circuit 20B is provided as shown in FIG. FIG. 20 shows a timing diagram for operating the gate drive circuit of FIG. 19 according to an embodiment of the present disclosure. Some differences between gate drive circuit 20B of FIG. 19 and gate drive circuit 20 of FIG. 14 are shown below.

Referring to FIGS. 19 and 20, in this embodiment, the gate drive circuit 20B employs ten clock signal lines. The fourth sub-clock signal line CLK_4, the fifth sub-clock signal line CLK_5, the sixth sub-clock signal line CLK_6, the seventh sub-clock signal line CLK_7, the eighth sub-clock signal line CLK_8, and the ninth sub-clock signal line A total of 10 clock signal lines are used, including line CLK_9, 15th sub-clock signal line CLK_15, 16th sub-clock signal line CLK_16, 17th sub-clock signal line CLK_17, and 18th sub-clock signal line CLK_18. and provides a drive signal that is output row by row from the shift register unit of each stage in the cascaded gate drive circuit. In this embodiment, ten clock signal lines are used, which further increases the pre-charging time of the sub-pixel units in each row, so that the gate drive circuit 20B can drive the scanning display at a higher frequency. even more suitable for

In the embodiments shown in FIGS. 19 and 20, except for the first two stages of shift register units that are cascaded in series, the shift register units of each other stage are the first shift register units of the previous two stages. 1 subunit and configured to receive the shift register signal CR as its first input signal STU1. Except for the last four stages of shift register units that are cascaded in series, the shift register units of each other stage are also connected to the first subunit in each of the next four stages to output the shift register signal CR as its indicator. Received as reset signal STD.

Referring to FIG. 19, the tenth sub-clock signal line CLK_10 is connected to the first sub-unit and second sub-unit (i.e. A1, A2, A3 and A4) of each of the previous two stages of shift register units. , provides a first input signal STU1 (for the third stage shift register unit, ie A5 and A6). At the same time, the tenth sub-clock signal line CLK_10 may be connected to shift register units of other stages to provide a full-scale reset signal TRST. This signal line layout can save the number of clock signal lines, facilitate reduction in frame size of a display device using the gate drive circuit, and improve PPI of the display device. In one example, the 40th transistor M40 and the 41st transistor M41 may not be included as an option for the first two stages of shift register units.

Referring to FIG. 20, it is shown that the sub-pixel unit in the 11th row is selected to perform external compensation, and the sub-pixel unit in the 11th row corresponds to the shift register unit in the 6th stage. In the display period DS of the first frame 1F, the third node H<11> is charged. During the blank period BL (following the display period), a high voltage first clock signal CLKA is provided to complete charging of the first node Q1<11> and the second node Q2<12>. The high voltage signal provided via the fourth sub-clock signal line CLK_4 supplies the high voltage third clock signal CLKC, and the first output signal OUT1<11 output from the sixth stage shift register unit. > becomes a high voltage signal. Using this high voltage signal OUT1<11>, the sub-pixel unit in the 11th row can be driven to complete its external compensation. FIG. 21 shows simulation data of signals output from the gate drive circuit of FIG. 19.

In another aspect, the present disclosure provides a display device. FIG. 22 shows a schematic diagram of a display device according to an embodiment of the present disclosure. Display device 1 includes a gate drive circuit 20 (or 20B) described in this disclosure and a plurality of sub-pixel units 410 arranged in an array on display panel 40.

Gate drive circuit 20 has a plurality of shift register units described in this disclosure connected in series in cascade. Each shift register unit outputs a first output signal OUT1 and a second output signal OUT2, which are respectively provided to sub-pixel units 410 in different rows in the array. For example, gate drive circuit 20 is connected to each sub-pixel unit 410 via gate line GL. Gate drive circuit 20 is used to provide drive signals to the array of sub-pixel units 410. For example, the driving signals may be used to drive the scanning transistors and sensing transistors in one row of sub-pixel units 410, respectively.

In one embodiment, the display device 1 further includes a data driving circuit 30 configured to provide data signals to the array of sub-pixel units 410. Optionally, data driving circuit 30 is connected to each sub-pixel unit 410 via a data line DL.

Optionally, the display device 1 of the present disclosure includes a liquid crystal display panel, a liquid crystal television, a display, an OLED display panel, an OLED television, an e-paper display, a smartphone, a tablet computer, a notebook computer, a digital photo frame, a navigator, and a display device 1 of the present disclosure. It may be one selected from any product or component with a display function.

In yet another aspect, the present disclosure provides a method of driving a shift register unit described herein. The shift register unit 10 shown in some figures of this specification can be used as a unit member for cascading gate drive circuits including multi-stage shift register units, and the multi-stage shift register units are connected in at least one frame. The display panel is configured to drive the display panel to display the image.

The driving method operates a first input circuit of a shift register unit to increase a voltage level at a first node connected between the first input circuit and a first output circuit in response to a first input signal. Including controlling. The method includes causing the first output circuit to output a shift register signal and a first output signal in response to a voltage level at the first node. The driving method operates a second input circuit of the shift register unit to increase the voltage at a second node connected between the second input circuit and a second output circuit in response to the first input signal. Further including controlling the level. The method includes causing the second output circuit to output a second output signal in response to the voltage level at the second node.

Optionally, in one specific embodiment, the method comprises a first input circuit of a first subunit of a shift register unit described herein and a second input circuit of a second subunit of the same shift register unit. The method includes inputting a first input signal to the input circuit. The method further includes driving the first sub-unit to control a voltage level at a first node of the first sub-unit based on the first input signal. Additionally, the method includes coupling a first output circuit to a first node in the first subunit. The method further includes controlling the first output circuit to output a shift register signal and a first output signal in response to the voltage level of the first node by driving the first subunit. . Further, the method includes controlling a voltage level of a second node of the second sub-unit based on the first input signal by driving the second sub-unit; 2 to a second node in the subunit. Further, the method includes controlling the second output circuit to output a second output signal in response to a voltage level at the second node by driving the second subunit.

Optionally, controlling the voltage level of the first node by driving the first sub-unit uses a blank input circuit having a common input circuit to control the voltage level of the second input signal and the first clock. receiving a signal to determine voltage levels at a third node and a fourth node, and using a first transmission circuit to control the voltage level at the first node in response to the voltage level at the fourth node; including. At the same time, controlling the voltage level of the second node by driving the second sub-unit is responsive to the voltage level of the fourth node, further using a second transmission circuit in the blank input circuit. and controlling the voltage level of the second node.

Optionally, controlling the first output circuit by driving the first sub-unit includes controlling the shift register output terminal and the first output circuit using at least a first reset circuit and a second reset circuit. including resetting a voltage level at a first output terminal in the circuit. The step further includes controlling a second clock signal output as a shift register signal and a third clock signal output as the first output signal in response to the voltage at the first node. Alternatively, controlling the second output circuit by driving the second subunit may include resetting the voltage level at the second output terminal of the second output circuit using at least a third reset circuit. Including. The step further includes controlling a fourth clock signal output as the second output signal in response to the voltage level of the second node.

The foregoing description of embodiments of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form or exemplary embodiments disclosed. Accordingly, the foregoing description is to be regarded in an illustrative rather than a restrictive sense. It goes without saying that various modifications and changes will be apparent to those skilled in the art. The embodiments were chosen and described to illustrate the practical application of the principles of the invention and its best mode, and will allow those skilled in the art to understand the various variations suitable for a particular application or contemplated embodiment of the invention. You will be able to understand various embodiments and various modifications. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents, in which all terms, unless expressly stated otherwise, shall be defined in their broadest reasonable scope. It is the meaning. Therefore, the terms "invention,""the present invention," and the like do not necessarily limit the scope of the claims to specific embodiments, and references to exemplary embodiments of the invention do not necessarily limit the scope of the claims to specific embodiments. is not meant and no such limitation should be inferred. The invention is limited only by the spirit and scope of the appended claims. Note that these claims may use terms such as "first" and "second" before nouns or elements. Such terms should be understood as nomenclature and should not be construed as limitations on the quantity of the element modified by such nomenclature unless a specific quantity has already been given. The described effects and advantages may not apply to all embodiments of the invention. It should be understood that those skilled in the art may make modifications to the described embodiments without departing from the scope of the invention, which is limited by the following claims. It should be noted that no element or component in this disclosure is intended to be available to the public, whether or not such element or component is expressly recited in the claims below.

Claims (29)

A shift register unit,
including a first subunit and a second subunit,
The first sub-unit includes a first input circuit coupled to a first output circuit via a first node, and the first input circuit adjusts the voltage level of the first node in response to a first input signal. the first output circuit is configured to output a shift register signal and a first output signal in response to the voltage level of the first node;
The second sub-unit includes a second input circuit coupled to a second output circuit via a second node, and the second input circuit adjusts the voltage at the second node in response to the first input signal. A shift register unit configured to control a voltage level, and wherein the second output circuit is configured to output a second output signal in response to a voltage level at the second node. further comprising a blank input subunit coupled to the first node and the second node and configured to receive a selection control signal to control respective voltage levels of the first node and the second node. , The shift register unit according to claim 1. The blank input subunit includes a common input circuit, a first transmission circuit, and a second transmission circuit,
The common input circuit is configured to control the voltage level of a third node and control the voltage level of a fourth node in response to the selection control signal,
The first transmission circuit is connected to the first node and the fourth node and configured to control the voltage level of the first node in response to the voltage level of the fourth node or the first transmission signal. is,
The second transmission circuit is connected to the second node and the fourth node and configured to control the voltage level of the second node in response to the voltage level of the fourth node or a second transmission signal. 3. The shift register unit according to claim 2. The common input circuit further includes a selection control circuit and a third input circuit,
The selection control circuit is configured to control the voltage level of the third node using a second input signal in response to the selection control signal and maintain the voltage level of the third node;
4. The shift register unit of claim 3, wherein the third input circuit is configured to control the voltage level of the fourth node in response to the voltage level of the third node. The selection control circuit includes a first transistor and a first capacitor, the first transistor having a gate terminal configured to receive the selection control signal and a gate terminal configured to receive the second input signal. 5. The first capacitor has a first terminal connected to the third node, and the first terminal has a first terminal connected to the third node. shift register unit. The third input circuit is
5. The second transistor comprising a gate coupled to the third node, a first terminal configured to receive a first clock signal, and a second terminal coupled to the fourth node. 4. The shift register unit according to 4. The first transmission circuit includes a third transistor, the second transmission circuit includes a fourth transistor,
The third transistor has a gate terminal coupled to the fourth node, a first terminal configured to receive a first voltage, and a second terminal coupled to the first node;
The fourth transistor has a gate terminal coupled to the fourth node, a first terminal configured to receive the first voltage, and a second terminal coupled to the second node. A shift register unit according to any one of claims 3 to 6. The first input circuit includes a fifth transistor, the first output circuit includes a sixth transistor, a seventh transistor, and a second capacitor,
The fifth transistor has a gate terminal configured to receive the first input signal, a first terminal configured to receive a first voltage, and a second terminal coupled to the first node. and has
The sixth transistor has a gate terminal connected to the first node, a first terminal configured to receive the second clock signal as a shift register signal, and configured to output the shift register signal. and a second terminal,
The seventh transistor has a gate terminal connected to the first node, a first terminal configured to receive a third clock signal as the first output signal, and a first terminal configured to output the first output signal. and a second terminal configured to
7. The second capacitor has a first terminal connected to the first node and a second terminal connected to the second terminal of the seventh transistor. shift register unit. The second input circuit includes an eighth transistor, the second output circuit includes a ninth transistor, and a third capacitor,
The eighth transistor has a gate terminal configured to receive the first input signal, a first terminal configured to receive a first voltage, and a second terminal connected to the second node. and has
The ninth transistor has a gate terminal connected to the second node, a first terminal configured to receive a fourth clock signal as the second output signal, and a first terminal configured to output the second output signal. and a second terminal configured to
7. The third capacitor has a first terminal connected to the second node and a second terminal connected to the second terminal of the ninth transistor. shift register unit. The first subunit further includes a first control circuit, a first reset circuit, a second reset circuit, a shift register output terminal, and a first output terminal,
the first control circuit is configured to control a voltage level at a fifth node in response to a voltage level at the first node and a second voltage;
the first reset circuit is configured to reset the voltage level at the first node, the shift register output terminal, and the first output terminal in response to the voltage level at the fifth node;
6. The second reset circuit is configured to reset the voltage level at the first node, the shift register output terminal, and the first output terminal in response to a voltage level at a sixth node. Shift register unit described in . The second sub-unit further includes a second control circuit, a third reset circuit, a fourth reset circuit, and a second output terminal,
The second output terminal is configured to output the second output signal,
the second control circuit is configured to control a voltage level at the sixth node in response to a voltage level at the second node and a third voltage;
the third reset circuit is configured to reset the voltage level at the second node and the second output terminal in response to the voltage level at the sixth node;
11. The shift register unit of claim 10, wherein the fourth reset circuit is configured to reset the voltage level at the second node and the second output terminal in response to the voltage level at the fifth node. . The blank input subunit is
connected to the fourth node, the fifth node, and the sixth node, and configured to reset the voltage level of the fourth node in response to the voltage level at the fifth node or the sixth node. 12. The shift register unit of claim 11, further comprising a common reset circuit. The common reset circuit includes a tenth transistor and an eleventh transistor,
The tenth transistor has a gate terminal connected to the fifth node, a first terminal connected to the fourth node, and a second terminal configured to receive a fourth voltage.
The eleventh transistor has a gate terminal connected to the sixth node, a first terminal connected to the fourth node, and a second terminal configured to receive the fourth voltage. The shift register unit according to claim 12. The first control circuit includes a twelfth transistor and a thirteenth transistor,
The first reset circuit includes a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor,
The second reset circuit includes a 17th transistor, an 18th transistor, and a 19th transistor,
the twelfth transistor has a gate terminal and a first terminal both configured to receive the second voltage, and a second terminal coupled to the fifth node;
The thirteenth transistor has a gate terminal connected to the first node, a first terminal connected to the fifth node, and a second terminal configured to receive a fourth voltage.
The fourteenth transistor has a gate terminal connected to the fifth node, a first terminal connected to the first node, and a second terminal configured to receive the fourth voltage. , the fifteenth transistor has a gate terminal coupled to the fifth node, a first terminal coupled to the shift register output terminal, and a second terminal configured to receive the fourth voltage. have,
The sixteenth transistor has a gate terminal coupled to the fifth node, a first terminal coupled to the first output terminal, and a second terminal configured to receive a fifth voltage. , the seventeenth transistor has a gate terminal connected to the sixth node, a first terminal connected to the first node, and a second terminal configured to receive the fourth voltage. The eighteenth transistor has a gate terminal connected to the sixth node, a first terminal connected to the shift register output terminal, and a second terminal configured to receive the fourth voltage. has
The nineteenth transistor has a gate terminal connected to the sixth node, a first terminal connected to the first output terminal, and a second terminal configured to receive the fifth voltage. , The shift register unit according to claim 10. The second control circuit includes a 20th transistor and a 21st transistor,
The third reset circuit includes a 22nd transistor and a 23rd transistor,
The fourth reset circuit includes a 24th transistor and a 25th transistor,
the twentieth transistor has a gate terminal and a first terminal both configured to receive the third voltage, and a second terminal coupled to the sixth node;
The twenty-first transistor has a gate terminal connected to the second node, a first terminal connected to the sixth node, and a second terminal configured to receive a fourth voltage.
The 22nd transistor has a gate terminal connected to the sixth node, a first terminal connected to the second node, and a second terminal configured to receive the fourth voltage. , the twenty-third transistor has a gate terminal coupled to the sixth node, a first terminal coupled to the second output terminal, and a second terminal configured to receive a fifth voltage. The twenty-fourth transistor has a gate terminal connected to the fifth node, a first terminal connected to the second node, and a second terminal configured to receive the fourth voltage. the twenty-fifth transistor has a gate terminal connected to the fifth node, a first terminal connected to the second output terminal, and a second terminal configured to receive the fifth voltage. The shift register unit according to claim 11, comprising: The first subunit further includes a third output terminal configured to output a third output signal, and the second subunit further includes a fourth output terminal configured to output a fourth output signal. further including;
The first reset circuit and the second reset circuit are configured to reset the voltage level at the third output terminal, and the third reset circuit and the fourth reset circuit are configured to reset the voltage level at the fourth output terminal. 12. A shift register unit according to claim 11, configured to reset the voltage level. The first subunit further includes a third control circuit and a fourth control circuit,
The third control circuit is configured to control the voltage level of the fifth node in response to the first clock signal, and the fourth control circuit is configured to control the voltage level of the fifth node in response to the first input signal. configured to control the voltage level of the node;
The second subunit further includes a fifth control circuit and a sixth control circuit,
The fifth control circuit is configured to control the voltage level of the sixth node in response to the first clock signal, and the sixth control circuit is configured to control the voltage level of the sixth node in response to the first input signal. 12. A shift register unit according to claim 11, configured to control the voltage level of the node. The first subunit further includes a fifth reset circuit and a sixth reset circuit,
The fifth reset circuit is configured to reset a voltage level at the first node in response to a display reset signal, and the sixth reset circuit is configured to reset a voltage level at the first node in response to a full-scale reset signal. configured to reset the voltage level of
The second subunit further includes a seventh reset circuit and an eighth reset circuit,
The seventh reset circuit is configured to reset the voltage level at the second node in response to the display reset signal, and the eighth reset circuit is configured to reset the voltage level at the second node in response to the full-scale reset signal. 18. A shift register unit according to claim 17, configured to reset the voltage level at the node. further comprising a common leak prevention circuit, a first leak prevention circuit, and a second leak prevention circuit;
The common leakage prevention circuit is connected to the first node and the seventh node and is configured to control a voltage level at the seventh node in response to a voltage level at the first node, and the common leakage prevention circuit is configured to control a voltage level at the seventh node in response to a voltage level at the first node. The first leakage prevention circuit is connected to the seventh node, the first reset circuit, the second reset circuit, the fifth reset circuit, and the sixth reset circuit, and is configured to configured to prevent leakage from occurring in the first node;
The second leakage prevention circuit is connected to the seventh node, the third reset circuit, the fourth reset circuit, the seventh reset circuit, and the eighth reset circuit, and is connected to the voltage level at the seventh node. 19. The shift register unit of claim 18, configured to responsively prevent leakage from occurring at the second node. The first sub-unit includes a first input circuit connected to the first node, a first control circuit connected to the first node and the fifth node, and a first control circuit connected to the third node and the fifth node. a third control circuit connected to the fifth node; a fourth control circuit connected to the fifth node; a first output circuit controlled by the voltage level of the first node; a first reset circuit connected to a seventh node; a second reset circuit connected to the first node, the sixth node, and the seventh node; and a second reset circuit connected to the first node and the seventh node. 5 reset circuit, and a sixth reset circuit connected to the first node and the seventh node,
The first input circuit includes a gate terminal configured to receive the first input signal, a first terminal configured to receive a first voltage, and a second terminal coupled to the first node. a fifth transistor having a terminal;
The first control circuit includes:
a twelfth transistor having a gate terminal and a first terminal both configured to receive a second voltage, and a second terminal coupled to the fifth node;
a thirteenth transistor having a gate terminal coupled to the first node, a first terminal coupled to the fifth node, and a second terminal configured to receive a fourth voltage; The third control circuit is
a 32nd transistor having a gate terminal configured to receive a first clock signal, a first terminal connected to the fifth node, and a second terminal;
a 33rd transistor having a gate terminal coupled to the third node, a first terminal coupled to the second terminal of the 32nd transistor, and a second terminal configured to receive the fourth voltage. including
The fourth control circuit includes a gate terminal configured to receive the first input signal, a first terminal coupled to the fifth node, and a fourth control circuit configured to receive the fourth voltage. a 34th transistor having two terminals;
The first output circuit is
a gate terminal coupled to the first node; a first terminal configured to receive a second clock signal; a sixth transistor having a second terminal for outputting a second clock signal as the shift register signal;
a gate terminal coupled to the first node; a first terminal configured to receive a third clock signal; a seventh transistor having a second terminal for outputting a third clock signal as the first output signal;
a second capacitor having a first terminal connected to the first node and a second terminal connected to the first output terminal;
a gate terminal coupled to the first node; a first terminal configured to receive a fifth clock signal; a 26th transistor having a second terminal for outputting a fifth clock signal;
a fourth capacitor having a first terminal connected to the first node and a second terminal connected to the third output terminal;
The first reset circuit includes:
a fourteenth leakage prevention transistor having a gate terminal connected to the fifth node, a first terminal connected to the first node, and a second terminal connected to the seventh node;
a fourteenth transistor having a gate terminal coupled to the fifth node, a first terminal coupled to the seventh node, and a second terminal configured to receive the fourth voltage;
a fifteenth transistor having a gate terminal coupled to the fifth node, a first terminal coupled to the shift register output terminal, and a second terminal configured to receive the fourth voltage;
a sixteenth transistor having a gate terminal coupled to the fifth node, a first terminal coupled to the first output terminal, and a second terminal configured to receive a fifth voltage;
a twenty-seventh transistor having a gate terminal coupled to the fifth node, a first terminal coupled to the third output terminal, and a second terminal configured to receive the fifth voltage. ,
The second reset circuit includes:
a seventeenth leakage prevention transistor having a gate terminal connected to the sixth node, a first terminal connected to the first node, and a second terminal;
a gate terminal coupled to the sixth node; a first terminal coupled to the second terminal of the seventeenth leakage prevention transistor; and a second terminal configured to receive the fourth voltage. 17 transistors and
an eighteenth transistor having a gate terminal coupled to the sixth node, a first terminal coupled to the shift register output terminal, and a second terminal configured to receive the fourth voltage;
a nineteenth transistor having a gate terminal coupled to the sixth node, a first terminal coupled to the first output terminal, and a second terminal configured to receive the fifth voltage; a 28th transistor having a gate terminal coupled to a sixth node, a first terminal coupled to the third output terminal, and a second terminal configured to receive the fifth voltage;
The fifth reset circuit is
a thirty-eighth leakage prevention transistor having a gate terminal configured to receive a display reset signal, a first terminal coupled to the first node, and a second terminal coupled to the seventh node;
a 38th transistor having a gate terminal configured to receive the display reset signal, a first terminal coupled to the seventh node, and a second terminal configured to receive the fourth voltage. including
The sixth reset circuit is
a fortieth leakage prevention transistor having a gate terminal configured to receive a full scale reset signal, a first terminal coupled to the first node, and a second terminal coupled to the seventh node;
a fortieth terminal having a gate terminal configured to receive the full scale reset signal, a first terminal coupled to the seventh node, and a second terminal configured to receive the fourth voltage. including a transistor;
The blank input subunit includes a selection control circuit connected to the third node and the fourth node, a third input circuit connected to the third node and the fourth node, and a selection control circuit connected to the third node and the fourth node. a first transmission circuit connected to a fourth node, and a common reset circuit connected to the fifth node, the sixth node, and the fourth node,
The selection control circuit includes:
a first transistor having a gate terminal configured to receive the selection control signal, a first terminal configured to receive a second input signal, and a second terminal;
a first leak having a gate terminal configured to receive the selection control signal, a first terminal coupled to a second terminal of the first transistor, and a second terminal coupled to the third node. a prevention transistor;
a first capacitor having a first terminal connected to the third node and a second terminal connected to the fourth node;
a forty-third transistor having a gate terminal coupled to the third node, a first terminal configured to receive a sixth voltage, and a second terminal coupled to the second terminal of the first transistor; including;
The third input circuit includes a gate terminal coupled to the third node , a first terminal configured to receive the first clock signal , and a third input circuit coupled to the fourth node . a second transistor having two terminals;
The first transmission circuit has a gate terminal connected to the fourth node, a first terminal configured to receive the first voltage, and a second terminal connected to the first node. including a third transistor;
The common reset circuit is
a tenth transistor having a gate terminal coupled to the fifth node, a first terminal coupled to the fourth node, and a second terminal configured to receive the fourth voltage;
an eleventh transistor having a gate terminal coupled to the sixth node, a first terminal coupled to the fourth node, and a second terminal configured to receive the fourth voltage;
4. The shift register unit according to claim 3, wherein the first voltage, the second voltage, and the sixth voltage are supplied with high level voltages, and the fourth voltage and the fifth voltage are supplied with low level voltages. further comprising a common leakage prevention circuit connected to the first node and the seventh node;
The common leakage prevention circuit has a gate terminal connected to the first node, a first terminal configured to receive the sixth voltage, and a second terminal connected to the seventh node. including a forty-fourth transistor;
The seventh node is shared with a first leakage prevention circuit including the fourteenth leakage prevention transistor, the seventeenth leakage prevention transistor, the thirty-eighth leakage prevention transistor, and the fortieth leakage prevention transistor. 21. Shift register unit according to item 20. The second subunit is
the second input circuit connected to the second node; a second control circuit connected to the second node and the sixth node; and a fifth control circuit connected to the sixth node and the third node. a sixth control circuit connected to the sixth node; a second output circuit controlled by the voltage level of the second node; and a sixth control circuit connected to the second node, the sixth node, and the eighth node. a fourth reset circuit connected to the second node, the eighth node, and the fifth node; a seventh reset circuit connected to the second node and the eighth node; a second node and an eighth reset circuit connected to the eighth node;
The second input circuit is
an eighth transistor having a gate terminal configured to receive the first input signal, a first terminal configured to receive a first voltage, and a second terminal coupled to the second node. including;
The second control circuit includes:
a twentieth transistor having a gate terminal and a first terminal both configured to receive a third voltage, and a second terminal coupled to the sixth node;
a twenty-first transistor having a gate terminal coupled to the second node, a first terminal coupled to the sixth node, and a second terminal configured to receive a fourth voltage; The fifth control circuit is
a 35th transistor having a gate terminal configured to receive a first clock signal, a first terminal coupled to the sixth node, and a second terminal;
a 36th transistor having a gate terminal coupled to the third node, a first terminal coupled to the second terminal of the 35th transistor, and a second terminal configured to receive the fourth voltage. including
The sixth control circuit includes a gate terminal configured to receive the first input signal, a first terminal coupled to the sixth node, and a third control circuit configured to receive the fourth voltage. a 37th transistor having two terminals;
The second output circuit is
a gate terminal coupled to the second node; a first terminal configured to receive a fourth clock signal; a ninth transistor having a second terminal for outputting a fourth clock signal as the second output signal;
a third capacitor having a first terminal connected to the second node and a second terminal connected to the second output terminal;
a gate terminal coupled to the second node; a first terminal configured to receive a sixth clock signal; and a fourth output terminal coupled to the voltage level of the second node. a 29th transistor having a second terminal for outputting the sixth clock signal as a fourth output signal;
a fifth capacitor having a first terminal connected to the second node and a second terminal connected to the fourth output terminal;
The third reset circuit is
a twenty-second leakage prevention transistor having a gate terminal connected to the sixth node, a first terminal connected to the second node, and a second terminal connected to the eighth node;
a twenty-second transistor having a gate terminal coupled to the sixth node, a first terminal coupled to the eighth node, and a second terminal configured to receive the fourth voltage;
a twenty-third transistor having a gate terminal coupled to the sixth node, a first terminal coupled to the second output terminal, and a second terminal configured to receive a fifth voltage;
a 30th transistor having a gate terminal coupled to the sixth node, a first terminal coupled to the fourth output terminal, and a second terminal configured to receive the fifth voltage. ,
The fourth reset circuit is
a twenty-fourth leakage prevention transistor having a gate terminal connected to the fifth node, a first terminal connected to the second node, and a second terminal connected to the eighth node;
a twenty-fourth transistor having a gate terminal coupled to the fifth node, a first terminal coupled to the eighth node, and a second terminal configured to receive the fourth voltage;
a twenty-fifth transistor having a gate terminal coupled to the fifth node, a first terminal coupled to a second output terminal, and a second terminal configured to receive a fifth voltage;
a 31st transistor having a gate terminal coupled to the fifth node, a first terminal coupled to the fourth output terminal, and a second terminal configured to receive the fifth voltage. ,
The seventh reset circuit is
a 39th leakage prevention transistor having a gate terminal configured to receive a display reset signal, a first terminal coupled to the second node, and a second terminal coupled to the eighth node;
a 39th transistor having a gate terminal configured to receive the display reset signal, a first terminal coupled to the eighth node, and a second terminal configured to receive the fourth voltage. including
The eighth reset circuit is
a forty-first leakage prevention transistor having a gate terminal configured to receive a full scale reset signal, a first terminal coupled to the second node, and a second terminal coupled to the eighth node;
a forty-first terminal having a gate terminal configured to receive the full scale reset signal, a first terminal coupled to the eighth node, and a second terminal configured to receive the fourth voltage; including a transistor;
The blank input subunit further includes a second transmission circuit connected to the second node and the fourth node,
The second transmission circuit is
a fourth transistor having a gate terminal coupled to the fourth node, a first terminal configured to receive the first voltage, and a second terminal coupled to the second node; The shift register unit of claim 20 , wherein the first voltage, the third voltage, and the sixth voltage are supplied with a high voltage level voltage, and the fourth voltage and the fifth voltage are supplied with a low voltage level voltage. . the eighth node is connected to the seventh node,
The shift register unit further includes a common leakage prevention circuit connected to the first node and the seventh node,
The common leakage prevention circuit has a gate terminal connected to the first node, a first terminal configured to receive the sixth voltage, and a second terminal connected to the seventh node. including a forty-fourth transistor;
The seventh node is shared with a second leakage prevention circuit including the 22nd leakage prevention transistor, the 24th leakage prevention transistor, the 39th leakage prevention transistor, and the 41st leakage prevention transistor. 23. Shift register unit according to item 22. further comprising a separate leakage prevention circuit connected to the second node and the eighth node;
The separate leakage prevention circuit includes a gate terminal coupled to the second node, a first terminal configured to receive the sixth voltage, and a second terminal coupled to the eighth node. a 45th transistor having
The eighth node is shared with a second leakage prevention circuit including the 22nd leakage prevention transistor, the 24th leakage prevention transistor, the 39th leakage prevention transistor, and the 41st leakage prevention transistor. 23. Shift register unit according to item 22. A gate drive circuit including a plurality of shift register units connected in series in cascade,
The plurality of shift register units are each a shift register unit according to any one of claims 1 to 24, and each of the plurality of shift register units is a first sub in an odd numbered stage controlled by the voltage level of a first node and a second node. unit and a second subunit in the next even stage;
The voltage levels of the first node and the second node are controlled by a first transmission circuit and a second transmission circuit, respectively, which are both connected from a common input circuit,
The first subunit of each shift register unit outputs the shift register signal as a first input signal to drive both the first subunit and the second subunit in the next shift register unit, or outputs a display reset signal. A gate drive circuit that outputs as follows, and drives both the first subunit and the second subunit in the previous shift register unit. A display device comprising the gate drive circuit according to claim 25 and a plurality of sub-pixel units arranged in an array,
A first output signal and a second output signal respectively output from a first output circuit and a second output circuit of each one shift register unit in the gate driving circuit are respectively provided to sub-pixel units in different rows of the array. display device. 25. The method of driving a shift register unit according to claim 1, wherein a first input circuit of a first subunit of the shift register unit and a second input circuit of a second subunit of the same shift register unit are provided. Inputting a first input signal to the input circuit;
controlling a voltage level of a first node of the first sub-unit based on the first input signal by driving the first sub-unit;
coupling a first output circuit to the first node;
controlling the first output circuit to output a shift register signal and a first output signal in response to the voltage level of the first node by driving the first subunit;
controlling the voltage level of a second node of the second sub-unit based on the first input signal by driving the second sub-unit;
coupling a second output circuit to the second node;
controlling the second output circuit to output a second output signal in response to a voltage level at the second node by driving the second subunit. Controlling the voltage level of the first node by driving the first sub-unit includes receiving a second input signal and a first clock signal using a blank input circuit having a common input circuit. determining voltage levels at a third node and a fourth node, and using a first transmission circuit to control the voltage level at the first node in response to the voltage level at the fourth node;
Controlling the voltage level of the second node by driving the second subunit is responsive to the voltage level of the fourth node using the blanking input circuit further comprising a second transmission circuit. 28. The method of claim 27, comprising controlling a voltage level at the second node. Controlling the first output circuit by driving the first subunit includes resetting voltage levels at the shift register output terminal and the first output terminal using at least a first reset circuit and a second reset circuit. , controlling a second clock signal output as a shift register signal and a third clock signal output as the first output signal in response to the voltage of the first node;
Controlling the second output circuit by driving the second subunit includes:
resetting the voltage level at the second output terminal using at least a third reset circuit, and controlling a fourth clock signal output as the second output signal in response to the voltage level at the second node. 28. The method of claim 27.

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