JP7428166B2 - Head system, liquid ejection device and delay time calculation method - Google Patents

Description

The present technology relates to a head system, a liquid ejection device, and a delay time calculation method that calculate a delay time from receiving image data to ejecting liquid.

A droplet ejection device has been proposed in which a main controller and a plurality of head control boards (hereinafter referred to as HC boards) are connected in a daisy chain. A plurality of HC substrates each control a plurality of inkjet heads. In this droplet ejection apparatus, a different amount of delay is determined for each HC substrate, synchronization is achieved based on the amount of delay, and ejection from the nozzles is synchronized to print at a desired position (see Patent Document 1).

Japanese Patent Application Publication No. 2010-76142

The inkjet head includes a drive element and a pressure chamber, and the ink in the pressure chamber is ejected from the nozzle by driving the drive element. Heat is generated on the HC substrate by the discharge. The responsiveness of the HC board after heat generation is lower than before heat generation. The HC board sends data to the downstream HC board. Since the responsiveness is different before and after heat generation, the data transmission timing of the HC board is also different. The amount of delay described above is a predetermined amount and does not take into account changes in the transmission timing of the HC board. Therefore, there is a possibility that the discharge from the nozzles cannot be synchronized.

Furthermore, the amount of delay described above is determined in advance by assuming the format, for example, the capacity, of the received print data, but if the format of the received print data is different from the expected format, the ejection from the nozzles cannot be synchronized. There is a risk.

The present disclosure has been made in view of such circumstances, and aims to provide a head system, a liquid ejection device, and a delay time calculation method that can reflect temperature, print data volume, etc. in delay time. .

A head system according to an embodiment of the present disclosure includes a main control circuit, a plurality of head units each having a nozzle, and a sub-control circuit having a counter and connected to each of the plurality of head units. A control circuit and each of the sub-control circuits are connected in series via a communication cable, and the plurality of sub-control circuits include a first sub-control circuit to an N-th sub-control circuit (N is a natural number of 2 or more). the first sub-control circuit is connected to the main control circuit, the N-th sub-control circuit is located at the end of the plurality of sub-control circuits connected in series, and the main control circuit is connected to the communication A process of transmitting first test data and a first timing signal to the first sub-control circuit via a cable is executed, and each of the first sub-control circuit to the N-1 sub-control circuit transmits the received transmitting first test data and the first timing signal to the sub-control circuit connected to the terminal side of the sub-control circuit; 1 transmission time point is measured by the counter, and based on the first reception time point or the first transmission time point measured by the counter, a delay time for ejecting liquid from the head unit connected to the head unit. Execute the delayed calculation process to be calculated.

A liquid ejecting apparatus according to an embodiment of the present disclosure includes the above-described head system and a transport device that transports a recording medium, and the main control circuit sends an image to the first sub-control circuit via the communication cable. The first sub-control circuit to the N-th sub-control circuit each transmit the received image data to the sub-control circuit connected to the terminal side thereof, and transmit the image data to the sub-control circuit connected to the terminal side thereof. When the delay time has elapsed from the time of reception, the liquid is ejected from the head unit onto the recording medium.

A delay time calculation method according to an embodiment of the present disclosure includes a main control circuit, a plurality of head units having nozzles, and a sub-control circuit having a counter and connected to each of the plurality of head units, The main control circuit and each of the sub-control circuits are connected in series via a communication cable, and the plurality of sub-control circuits include a first sub-control circuit to an N-th sub-control circuit (N is a natural number of 2 or more). ), the first sub-control circuit is connected to the main control circuit, and the N-th sub-control circuit is executed in a head system located at the end of the plurality of sub-control circuits connected in series. In the delay time calculation method, the main control circuit executes a process of transmitting first test data and a first timing signal to the first sub-control circuit via the communication cable, and ~ The N-1th sub-control circuit transmits the received first test data and the first timing signal to the sub-control circuit connected to its terminal side, and transmits the first timing signal. The first reception time point received or the first transmission time point at which the first timing signal was transmitted is measured by the counter, and based on the first reception time point or the first transmission time point measured by the counter, A delay time for ejecting liquid from the connected head unit is calculated.

In the head system, liquid ejecting device, and delay time calculation method according to an embodiment of the present disclosure, the first sub-control circuit to the N-th sub-control circuit transmit and receive the first test data, and receive the first test data. The delay time between the time when the liquid is ejected from the head unit to which it is connected is calculated. By transmitting and receiving the first test data and calculating the delay time when printing is not being performed, it is possible to calculate the delay time that reflects the temperature of the head unit immediately before printing or the capacity of print data.

1 is a schematic plan view of a printer according to Embodiment 1. FIG. FIG. 2 is a block diagram of a control device, an encoder, and an inkjet head. FIG. 3 is a timing diagram illustrating a method of calculating delay time. 3 is a flowchart illustrating delay time calculation processing by SoC(k) (k=1 to n-1). 7 is a timing diagram illustrating a method of calculating delay time according to the second embodiment. FIG. 3 is a flowchart illustrating delay time calculation processing by SoC(k) (k=1 to n-1). FIG. 7 is an explanatory diagram illustrating delay time caused by data transfer between a main control circuit and a plurality of SoCs according to Embodiment 3; FIG. 3 is a timing diagram illustrating a method of calculating delay time.

(Embodiment 1)
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below based on drawings showing a printer according to a first embodiment. FIG. 1 is a schematic plan view of the printer 1. As shown in FIG. In FIG. 1 , the conveyance direction of the recording paper 100 corresponds to the front-rear direction of the printer 1 . Further, the width direction of the recording paper 100 corresponds to the left-right direction of the printer 1. Further, a direction perpendicular to the front-rear direction and the left-right direction, that is, a direction perpendicular to the paper surface of FIG. 1 corresponds to the vertical direction of the printer 1. The left-right direction corresponds to the first direction, and the front-back direction corresponds to the second direction. The printer 1 corresponds to a liquid ejection device.

As shown in FIG. 1, the printer 1 includes a platen 3 housed in a case 2, four inkjet heads 4, two transport rollers 5 and 6, a control device 7, and the like. The printer 1 corresponds to a liquid ejection device, and the conveyance rollers 5 and 6 correspond to a conveyance device.

A recording paper 100 passes over the upper surface of the platen 3. The four inkjet heads 4 are arranged above the platen 3 in the transport direction. Each inkjet head 4 is a so-called line type head. Ink is supplied to the inkjet head 4 from an ink tank (not shown). Inks of different colors are supplied to the four inkjet heads 4.

As shown in FIG. 1, two conveyance rollers 5 and 6 are arranged on the rear side and the front side of the platen 3, respectively. The two transport rollers 5 and 6 are each driven by a motor (not shown), and transport the recording paper 100 on the platen 3 forward. Conveyance rollers 5 and 6 correspond to a conveyance device.

The control device 7 includes FPGA, EEPROM, RAM, etc. Note that the control device 7 may include a CPU, an ASIC, or the like. The control device 7 is connected to an external device 9 such as a PC for data communication, and controls each part of the printer 1 based on print data sent from the external device 9. The print data includes image data.

FIG. 2 is a block diagram of the control device 7, encoder 8, and inkjet head 4. The control device 7 includes a main control circuit 7a. The main control circuit 7a includes a counter 7b, a communication section 7c, and a storage section 7d. The inkjet head 4 includes a plurality of head units 40. The plurality of head units 40 are arranged in a row in the left-right direction. The head unit 40 has a nozzle.

The plurality of head units 40 includes, for example, a first head unit 40(1), a second head unit 40(2), . . . , an n-th head unit 40(n) (n is a natural number). The first head unit 40(1) is located at the far left, and the nth head unit 40(n) is located at the far right.

Each of the first head unit 40(1) to the nth head unit 40(n) includes an SoC 41 and a plurality of heads 42. Head 42 has multiple nozzles. SoC41 corresponds to a sub control circuit. The SoC 41 includes a control section 41a, a storage section 41b, a counter 41c, and a communication section 41d. The control unit 41a controls the operation of the SoC 41. If necessary, the SoC 41 causes the head unit 40 to eject ink when a delay time described below has elapsed after receiving the image data. The storage unit 41b is, for example, a rewritable nonvolatile memory such as an EPROM or an EEPROM. Hereinafter, the SoCs 41 of the head unit 40(1) to the n-th head unit 40(n) will be referred to as SoC(1) to SoC(n).

The communication section 7c and each communication section 41d are connected in series by a communication cable 50. The communication unit 7c transmits image data included in the print data to the communication unit 41d of the SoC (1). The communication unit 41d of SoC(1) transfers the image data to the communication unit 41d of SoC(2), and the communication unit 41d of SoC(2) transfers it to the communication unit 41d of SoC(3). In this way, the image data is sequentially transferred to the communication unit 41d of SoC(n).

The image data includes identifiers for each of SoC(1) to SoC(n) and print information associated with each identifier. The control units 41a of SoC(1) to SoC(n) acquire image information linked to their own identifiers from the received image data.

The conveyance rollers 5 and 6 are equipped with a motor (not shown), and the motor is provided with an encoder 8. An encoder 8 detects the rotational position of the motor. The rotational position of the motor corresponds to the front and rear positions of the recording paper 100, and the encoder 8 is synchronized with the main control circuit 7a every time it detects the rotational position corresponding to the printing position (the position at which one line of printing should be performed on the recording paper 100). Send a signal.

The main control circuit 7a transmits a synchronization signal to the communication unit 41d of the SoC (1) as necessary. The communication unit 41d of SoC(1) transfers the synchronization signal to the communication unit 41d of SoC(2), and the communication unit 41d of SoC(2) transfers it to the communication unit 41d of SoC(3). In this way, the synchronization signal is sequentially transferred to the communication unit 41d of SoC(n).

At the time when the SoC(n) which receives image data the latest causes the head unit 40(n) to eject ink, SoC(1) to SoC(n-1) also receive the head units 40(1) to 40(n-1). ) to eject ink. SoC(1) to SoC(n-1) eject liquid from each head unit 40 with a delay of a predetermined delay time from the time of reception of the synchronization signal. For each of SoC(1) to SoC(n-1), the predetermined delay time is calculated by a calculation method described later.

FIG. 3 is a timing diagram illustrating a method of calculating delay time. In FIG. 3, the upper side shows the past and the lower side shows the future. Further, the left side indicates the upstream side, and the right side indicates the downstream side. Solid squares indicate time slots in which the main control circuit 7a and each of SoC(1) to SoC(n) receive first test data from the upstream side. The squares indicated by two-dot chain lines indicate the time slots in which the main control circuit 7a and SoC(1) to SoC(n-1) each receive the second test data from the downstream side, and the time slots in which SoC(n) receives the second test data from the downstream side. ) indicates the time slot for transmitting the second test data. The first and second test data are data of the same capacity, and are data of the same capacity as the image data, and are data for which no ejection is performed. Right-pointing arrows indicate first timing signals that are transmitted and received, and left-pointing arrows indicate second timing signals that are transmitted and received. The broken line indicates the time point at which the SoC(n) can cause the head unit 40(n) to eject ink, that is, the time point at which ink can be ejected. In the present embodiment, each of SoC(1) to SoC(n-1) has its own ejection enabled time and SoC( The time between n) and the ejectable time point, that is, the delay time, is calculated.

Ta(k) (k=1, 2, . . . , n-1) indicates the first transmission time point at which the SoC(k) transmits the first timing signal to the SoC 41 downstream from itself. Tb(k) indicates a second reception time point at which SoC(k) receives the second timing signal from SoC 41 downstream of itself.

The main control circuit 7a and the SoC 41 calculate the delay time when printing is not performed, for example, at the time of initialization, maintenance, or flushing operation.
Main control circuit 7a transmits the first test data to SoC (1). Main control circuit 7a receives first test data from external device 9. Note that the first test data may be stored in the storage section 7d in advance, and the main control circuit 7a may acquire the first test data from the storage section 7d. The main control circuit 7a is transmitting the first test data and transmits the first timing signal to the SoC (1) at a predetermined time point.

SoC (1) receives the first test data from main control circuit 7a, and transmits the received first test data to SoC (2). Also, while the SoC (1) is transmitting the first test data, it transmits the first timing signal to the SoC (2) at a predetermined time point Ta (1).

SoC (2) receives the first test data from SoC (1) and transmits the received first test data to SoC (3). Also, SoC (2) is transmitting the first test data and transmits the first timing signal to SoC (3) at a predetermined time point Ta (2). In this way, the first test data and the first timing signal are sequentially transmitted to the terminal SoC(n).

SoC(n) receives a first timing signal from SoC(n-1) at time Ta(n-1). A hold time PT is stored in advance in the storage unit 41b of SoC(n). As shown in FIG. 3, after the SoC(n) receives the first timing signal from the SoC(n-1), the time when the holding time PT has elapsed is the time when the SoC(n) can discharge, and each This is the time point when the SoC 41 causes each head unit 40 to eject ink simultaneously, that is, the ejection time point. SoC(n) transmits the second timing signal to SoC(n-1) at a time twice the hold time PT from time Ta(n-1), that is, at time Tb(n-1). . Time Tb(n-1) is a time after the ejection time, and is a time when the second test data is being transmitted by SoC(n).

SoC(n-1) receives the second test data from SoC(n) and transmits the received second test data to SoC(n-2). Also, SoC(n-1) is transmitting the second test data and transmits a second timing signal to SoC(n-2) at a predetermined time Tb(n-2). In this way, the second test data and the second timing signal are sequentially transmitted to the main control circuit 7a. Note that the time between time points Ta(k) and Ta(k+1) (k=1, 2, . . . , n-2) and time points Tb(k) and Tb(k+1) (k=1, 2, . . . , n-2) are all Ts and have the same length.

In SoC(k) (k=1, 2, ..., n-1), the time point Ta(k) when the first timing signal is transmitted downstream, that is, the first transmission time point, and the time point when the second timing signal is transmitted downstream The time Tb(k) received from the side, ie, the time between the second reception time, is twice the time from the first transmission time to the ejection time (ie, delay time).

FIG. 4 is a flowchart illustrating delay time calculation processing by SoC(k) (k=1 to n-1). In the initial state, the main control circuit 7a transmits the first test data to the SoC (1).

SoC(k) determines whether or not the first test data has been received (S1). If the first test data has not been received (S1: NO), the SoC(k) returns the process to step S1. If the first test data is received (S1: YES), SoC(k) transmits the first test data to SoC(k+1) (S2).

The SoC(k) determines whether the first timing signal has been received from the upstream SoC 41 or the main control circuit 7a (S3). If the first timing signal is not received from the upstream SoC 41 or the main control circuit 7a (S3: NO), the SoC(k) returns the process to step S3. When the first timing signal is received from the upstream SoC 41 or the main control circuit 7a (S3: YES), the SoC(k) refers to the counter 41c and determines whether it is time Ta(k) (S4). .

If it is not the time Ta(k) (S4: NO), the SoC(k) returns the process to step S4. If it is time Ta(k) (S4: YES), the first timing signal is transmitted to the downstream SoC(k+1) (S5).

SoC(k) determines whether or not the second test data has been received (S6). If the second test data has not been received (S6: NO), the SoC(k) returns the process to step S6. If the second test data is received (S6: YES), the SoC(k) transmits the second test data to the upstream SoC 41 or the main control circuit 7a (S7).

SoC(k) determines whether the second timing signal has been received from SoC(k+1) on the downstream side (S8). If the second timing signal has not been received from the downstream SoC (k+1) (S8: NO), the SoC (k) returns the process to step S8. When the second timing signal is received from the downstream SoC (k+1) (S8: YES), the SoC (k) refers to the counter 41c and determines whether it is time Tb (k-1) (S9). .

If it is not time Tb(k-1) (S9: NO), SoC(k) returns the process to step S9. If it is the time Tb(k-1) (S9: YES), the SoC(k) transmits the second timing signal to the upstream SoC 41 or the main control circuit 7a (S10).

SoC(k) executes delay calculation processing (S11). As described above, SoC(k) calculates the time between time Ta(k) and time Tb(k), and ejects ink at half the calculated time, that is, after transmitting the first timing signal. The delay time until the process is performed is stored in the storage unit 41b, and the process is ended. Note that steps S3 to S5 may be executed while transmitting the first test data, and steps S6 to S11 may be executed while transmitting the second test data.

In the printer 1 according to the first embodiment, SoC(1) to SoC(n) transmit and receive the first test data and the first timing signal, and determine when the first timing signal is transmitted and when the SoC(n) is connected. The delay time between the time when ink is ejected from the head unit 40 is calculated. When printing is not being performed, for example, at the time of initialization, maintenance, or flushing operation, the temperature of the SoC 41 immediately before printing or printing is determined by transmitting and receiving the first test data and the first timing signal and calculating the delay time. It is possible to calculate a delay time that reflects the data capacity.

(Embodiment 2)
The present invention will be described below based on drawings showing a printer 1 according to a second embodiment. Among the configurations according to the second embodiment, configurations similar to those in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

FIG. 5 is a timing diagram illustrating a method of calculating delay time. In FIG. 5, the upper side shows the past and the lower side shows the future. Further, the left side indicates the upstream side, and the right side indicates the downstream side. The solid line squares indicate the time slots in which the main control circuit 7a and SoC(1) to SoC(n) each receive the first test data, and the time slots in which the main control circuit 7a and each of SoC(1) to SoC(n-1) receive the first test data. 2 shows a time slot in which the second test data is received, as well as a time slot in which the SoC(n) transmits the second test data.

Ta(k) (k=1, 2,..., n) is the time point after the SoC(k) receives the first timing signal from the main control circuit 7a or the SoC 41 on the upstream side thereof. Indicates the ejection possible time point at which ink can be ejected from the head unit 40(k) provided therein without delay time.

The SoC(k) has a logic circuit, and the logic circuit calculates a time point Ta(k) using reception of a synchronization signal from the upstream main control circuit 7a or the SoC 41 as a trigger. In FIG. 5, the dashed squares indicate time slots from time point Ta(k) after completion of reception of the first test data.

Tb(k) (k=1, 2,..., n-1) is the time when SoC(k) receives the second timing signal from the SoC 41 downstream from itself, that is, at the second reception time. be. Tc(k) (k=1, 2, . . . , n) is the time point at which the second timing signal is transmitted to the SoC 41 on the upstream side of itself, that is, the second transmission time point.

The main control circuit 7a and the SoC 41 calculate the delay time when printing is not performed, for example, at the time of initialization, maintenance, or flushing operation.
Main control circuit 7a transmits the first test data to SoC (1). The main control circuit 7a is transmitting the first test data and transmits the first timing signal to the SoC (1) at a predetermined time point. SoC (1) receives the first test data from main control circuit 7a, and transmits the received first test data to SoC (2). SoC(1) uses reception of the first timing signal from main control circuit 7a as a trigger to calculate time point Ta(1) and stores it in storage unit 41b.

SoC (1) transmits a first timing signal to SoC (2) during transmission of the first test data. In this way, the first test data and the first timing signal are sequentially transmitted to the terminal SoC(n). Also, SoC(k) (k=1 to n) calculates time point Ta(k) and stores it in the storage unit 41b.

Time Ta(n) is the time when SoC(n), which receives image data latest, causes head unit 40(n) to eject ink. That is, this is the ejection point in time when all SoCs 41 eject ink from all head units 40 at the same time.

After the ejection time, SoC(n) transmits second test data having the same capacity as the first test data received to SoC(n-1). SoC(n) sends a second timing signal to SoC(n-1) at time Tc(n). Time Tc(n) is the time when the second test data is being transmitted by SoC(n).

SoC(n-1) receives a second timing signal from SoC(n) at time Tb(n-1) and also receives second test data. Time Tb(n-1) is the same as time Tc(n). SoC(n-1) transmits the received second test data to SoC(n-2), and transmits a second timing signal to SoC(n-2) at time Tc(n-1). Time Tc(n-1) is a time when the second test data is being transmitted by SoC(n-1). In this way, the second test data and the second timing signal are sequentially transmitted to the main control circuit 7a. SoC(k) (k=1 to n-1) stores Tb(k) and Tc(k) in storage unit 41b, and SoC(n) stores Tc(n) in storage unit 41b. Time Tb(k-1) is the same as time Tc(k) (k=2 to n). SoC(n) transmits ejection possible time Ta(n) to SoC(1) to SoC(n-1), and SoC(1) to SoC(n-1) store Ta(n). Note that Ta(n) is also the ejection time point at which ink is ejected from all head units 40 simultaneously.

In SoC(k) (k=1, 2,..., n-1), the time between time Ta(k) and discharge time Ta(n), that is, the delay time, is (Tb(k)- It is calculated by Ta(k))-(Tc(k)-Ta(n)). Tb(k)-Ta(k) corresponds to the first time, and Tc(k)-Ta(n) corresponds to the second time.

FIG. 6 is a flowchart illustrating delay time calculation processing by SoC(k) (k=1 to n-1). In the initial state, the main control circuit 7a transmits the first test data to the SoC (1).

SoC(k) determines whether or not the first test data has been received (S21). If the first test data has not been received (S21: NO), the SoC(k) returns the process to step S21. If the first test data is received (S21: YES), the SoC (k) transmits the first test data to the SoC (k+1) (S22), and receives the first timing signal from the upstream main control circuit 7a or SoC 41. It is determined whether or not it has been received (S23). If the first timing signal is not received from the upstream main control circuit 7a or the SoC 41 (S23: NO), the SoC(k) returns the process to step S23.

When the first timing signal is received from the upstream main control circuit 7a or the SoC 41 (S23: YES), the SoC(k) calculates and stores the time Ta(k) (S24), and the downstream SoC(k+1 ) (S25). SoC(k) determines whether or not the second test data has been received (S26). If the second test data has not been received (S26: NO), the SoC(k) returns the process to step S26.

When the second test data is received (S26: YES), the SoC (k) transmits the second test data to the downstream main control circuit 7a or SoC 41 (S27), and the second test data is transmitted from the downstream SoC (k+1) to the second test data. It is determined whether a timing signal has been received (S28). If the second timing signal has not been received from the downstream SoC (k+1) (S28: NO), the SoC (k) returns the process to step S28.

If the second timing signal is received from the downstream SoC (k+1) (S28: YES), the SoC (k) refers to the counter 41c and stores time Tb(k) (S29). SoC(k) refers to counter 41c and determines whether it is time Tc(k) (S30). If it is not time Tc(k) (S30: NO), SoC(k) returns the process to step S30.

If it is the time Tc(k) (S30: YES), the SoC(k) transmits the second timing signal to the upstream main control circuit 7a or the SoC 41 (S31), and calculates the delay time (S32). The delay time is calculated based on the above formula.

In the printer 1 according to the second embodiment, SoC(1) to SoC(n-1) measure the ejectable time Ta and the second reception time Tb, and measure the ejectable time Ta and the second reception time Tb. A first time between time Tb and time Tb is calculated. In addition, SoC(1) to SoC(n-1) calculate the second transmission time Tc, and calculate the ejection possible time Ta(k) (k=1 to n-1) measured by themselves and SoC(n) A second time between the ejection possible time Ta(n) is calculated, and a difference between the first time and the second time, that is, a delay time is calculated. When printing is not being performed, for example, during initialization, maintenance, or flushing operation, the delay time is calculated to reflect the temperature of the head unit immediately before printing or the capacity of print data. Can be done.

(Embodiment 3)
The present invention will be described below based on drawings showing a printer 1 according to a third embodiment. Among the configurations according to Embodiment 3, configurations similar to those of Embodiment 2 are given the same reference numerals, and detailed description thereof will be omitted.

FIG. 7 is an explanatory diagram illustrating the delay time caused by data transfer between the main control circuit 7a and the plurality of SoCs 41. The consecutive numbers shown in FIG. 7 indicate the count values by the counter 7b of the main control circuit 7a and the counter 41c of each SoC 41. Each counter 7b, 41c is synchronized, for example, by inputting an external reset signal to each counter 7b in parallel. Alternatively, the main control circuit 7a may continue to transmit a reset signal to each counter 7b, 41c via the communication cable 50 for a predetermined period of time to simultaneously reset and synchronize each counter 7b, 41c.

Note that the counters 7b and 41c of the main control circuit 7a may be used as a master clock and the counter 41c of the SoC 41 as a slave clock, and the counters 7b and 41c may be simultaneously reset and synchronized based on PTP (Precision Time Protocol). Alternatively, each counter 7b, 41c may be reset and synchronized simultaneously based on NTP (Network Time Protocol), that is, each counter 7b, 41c may receive time information from an NTP server.

In order to measure the delay time caused by data transfer, the main control circuit 7a transfers a test timing signal to the SoC 41(1). At this time, the main control circuit 7a associates the count value at the time of transfer (for example, "5") with its own identifier, and transfers it to the SoC (1) together with the timing signal. Hereinafter, the count value and the identifier will be referred to as count value information, the count value information having the identifier of the main control circuit 7a will be referred to as count value information (0), and the count value information having the identifier of SoC(n) will be referred to as count value information (n). It is written as.

SoC (1) forwards the received timing signal to SoC (2). At this time, the SoC (1) transmits the count value information (0), the count value of its own counter at the time of transfer (for example, "6"), and the count value information (1) that is linked to its own identifier using a timing signal. It is also transferred to SoC (2).

SoC (2) forwards the received timing signal to SoC (3). At this time, the SoC (2) links the count value information (0), the count value information (1), the count value of its own counter at the time of transfer (for example, "7"), and its own identifier. The information (2) is transferred together with the timing signal to the SoC (3). In this way, the timing signal and each count value information are transferred to the most downstream SoC(n).

In addition, SoC (n) transfers its own count value information (n) when receiving the timing signal to SoC (n-1), and SoC (n-1) transfers the count value information (n) and the count value information (n) to SoC (n-1). Transfer information (n-1) to SoC (n-2). In this way, each count value information is transferred to the most upstream SoC (1).

As a result, each SoC 41 can obtain the count value at which it and all other SoCs 41 receive timing signals. Each SoC 41 can calculate the delay time caused by the transfer between itself and the SoC 41 to which it transfers data. Therefore, each SoC 41 can recognize the SoC 41 that receives data the latest, and can simultaneously eject liquid from each head unit 40 at the time when the SoC 41 that receives data latest ejects ink.

For example, in FIG. 7, the SoC 41 that receives data the latest is SoC(n). If the count value at the time when SoC(n) receives the timing signal is "10", for SoC(1), the time when it receives the timing signal is "6", so it cannot receive the timing signal. The count value, ie, the delay time, from when the SoC(n) receives the timing signal is 4. For SoC(2), the time when it receives the timing signal is "7", so the delay time from receiving the timing signal until SoC(n) receives the timing signal is 3. In this way, SoC(1) to SoC(n-1) obtain their respective delay times.

FIG. 8 is a timing diagram illustrating a method of calculating delay time. The main control circuit 7a and the SoC 41 calculate the delay time when printing is not performed, for example, at the time of initialization, maintenance, or flushing operation.

The SoC 41 that receives data the latest is SoC(n). As in the second embodiment, the ejection enabled time Ta(n) is the ejection time when ink is ejected from all head units 40 simultaneously. Each SoC(k) transmits the ejection possible time Ta(k) to each SoC 41 other than itself, and each SoC 41 stores each Ta(k) (k=1 to n). SoC(k) (k=1 to n-1) calculates the difference between the ejectable time Ta(k) calculated by itself and the ejectable time Ta(n) of SoC(n), that is, the delay time. . By delaying SoC(k) from time point Ta(k) by its own delay time, liquid can be ejected from each head unit 40 at the same time.

In printer 1 according to the third embodiment, by synchronizing the counters 41c of SoC(1) to SoC(n), SoC(k) (k=1 to n-1) can The time (third time), ie, the delay time, between the calculated ejectable time Ta(k) and the ejectable time Ta(n) calculated by the terminal SoC(n) is calculated. When printing is not being performed, for example, during initialization, maintenance, or flushing operation, the delay time is calculated to reflect the temperature of the head unit immediately before printing or the capacity of print data. Can be done.

The embodiments disclosed herein are illustrative in all respects and should be considered not to be restrictive. The technical features described in each embodiment can be combined with each other, and the scope of the present invention is intended to include all changes within the scope of the claims and the range of equivalents to the scope of the claims. be done.

1 Printer (liquid ejection device)
5 Conveyance roller (conveyance device)
7a Main control circuit 7b Counter 40 Head unit 41 SoC (sub control circuit)
41c counter 50 communication cable

Claims (9)

a main control circuit;
a plurality of head units having nozzles;
a sub-control circuit having a counter and connected to each of the plurality of head units;
The main control circuit and each of the sub control circuits are connected in series via a communication cable,
The plurality of sub-control circuits include a first sub-control circuit to an N-th sub-control circuit (N is a natural number of 2 or more),
the first sub-control circuit is connected to the main control circuit,
The Nth sub-control circuit is located at the end of the plurality of sub-control circuits connected in series,
The main control circuit executes a process of transmitting first test data and a first timing signal to the first sub-control circuit via the communication cable,
The first sub-control circuit to the N-1 sub-control circuit each include:
transmitting the received first test data and the first timing signal to the sub-control circuit connected to the terminal side thereof;
measuring with the counter a first reception time point at which the first timing signal is received or a first transmission time point at which the first timing signal is transmitted;
A head system that executes a delay calculation process for calculating a delay time for ejecting liquid from the head unit connected to the head unit based on the first reception time point or the first transmission time point measured by the counter. After receiving the first test data and the first timing signal, the N-th sub-control circuit transmits second test data and a second timing signal to the N-1 sub-control circuit via the communication cable. ,
The N-1st sub-control circuit to the first sub-control circuit each include:
transmitting the received second test data and the second timing signal to the next sub-control circuit connected to the main control circuit side;
measuring a second reception time point at which the second timing signal is received by the counter;
The head system according to claim 1, wherein in the delay calculation process, the delay time is calculated based on the first reception time point or the first transmission time point and the second reception time point measured by the counter. The first sub-control circuit to the N-th sub-control circuit include a k-th sub-control circuit and a k+1-th sub-control circuit connected to each other (k=1, 2, . . . , N-1),
A capacity of the first test data transmitted from the kth sub-control circuit to the k+1st sub-control circuit, and a capacity of the second test data transmitted from the k+1st sub-control circuit to the k-th sub-control circuit. The head system according to claim 2. The k-th sub-control circuit and the k+1-th sub-control circuit each calculate half of the time between the first transmission time point and the second reception time point measured by the counter in the delay calculation process. 3. The head system described in 3. The first sub-control circuit to the N-th sub-control circuit each perform the following steps in the delay calculation process:
Calculating an ejectable time point after the first reception time point at which liquid can be ejected from the head unit provided therein without delay;
Measuring a second transmission time point at which the second timing signal is transmitted to the sub-control circuit connected to the main control circuit side of the device using the counter of the device;
The first sub-control circuit to the N-th sub-control circuit include a k-th sub-control circuit and a k+1-th sub-control circuit that are connected to each other (k=1, 2, . . . , N-2),
The k-th sub-control circuit, in the delay calculation process,
calculating a first time between the second reception time point measured by the k-th sub-control circuit and the ejection possible time point calculated by the k-th sub-control circuit;
Calculating a second time between the second transmission time point when the k+1st sub-control circuit transmits the second timing signal to the k-th sub-control circuit and the ejection possible time point calculated by the N-th sub-control circuit. death,
The head system according to claim 2, wherein a difference between the first time and the second time is calculated. The counters of each of the first sub-control circuit to the N-th sub-control circuit are synchronized,
The first sub-control circuit to the N-th sub-control circuit each perform the following steps in the delay calculation process:
Calculating an ejectable time point after the first reception time point at which liquid can be ejected from the head unit provided therein without delay;
The first sub-control circuit to the N-th sub-control circuit include a k-th sub-control circuit and a k+1-th sub-control circuit connected to each other (k=1, 2, . . . , N-1),
In the delay calculation process, the k-th sub-control circuit calculates a third time between the ejection-enabled time point calculated by the N-th sub-control circuit and the ejection-enabled time point calculated by the k-th sub-control circuit. The head system according to claim 1. A head system according to any one of claims 1 to 6,
A transport device that transports the recording medium;
The main control circuit transmits image data to the first sub-control circuit via the communication cable,
The first sub-control circuit to the N-th sub-control circuit each include:
transmitting the received image data to the sub-control circuit connected to the terminal side thereof;
A liquid ejecting device that causes the head unit to eject liquid onto the recording medium when the delay time has elapsed after receiving the image data. The liquid ejecting device according to claim 7, wherein the size of the image data and the capacity of the first test data are the same. A main control circuit, a plurality of head units having nozzles, and a sub-control circuit having a counter and connected to each of the plurality of head units, wherein the main control circuit and each of the sub-control circuits communicate. The plurality of sub-control circuits are connected in series via a cable, and the plurality of sub-control circuits include a first sub-control circuit to an N-th sub-control circuit (N is a natural number of 2 or more), and the first sub-control circuit is connected to the main control circuit. A delay time calculation method executed in a head system connected to a circuit, the N-th sub-control circuit being located at the end of the plurality of sub-control circuits connected in series,
The main control circuit executes a process of transmitting first test data and a first timing signal to the first sub-control circuit via the communication cable,
The first sub-control circuit to the N-1 sub-control circuit each include:
transmitting the received first test data and the first timing signal to the sub-control circuit connected to the terminal side thereof;
measuring with the counter a first reception time point at which the first timing signal is received or a first transmission time point at which the first timing signal is transmitted;
A delay time calculation method, comprising calculating a delay time for ejecting liquid from the head unit to which the head unit is connected, based on the first reception time point or the first transmission time point measured by the counter.

Images