JP2010076147A - Liquid droplet ejection control apparatus and liquid droplet ejecting apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid droplet ejection control apparatus and a liquid droplet ejecting apparatus which enable communication of control information by a compact device configuration by reducing the number of cables. <P>SOLUTION: A plurality of head control (HC) substrates 24 are arranged correspondingly to a plurality of arrayed ejection parts of a liquid droplet ejecting head in which the ejection parts for ejecting liquid droplets are arranged in the plurality of arrays. At the same time, the substrates 24 are daisy chain connected with each other by a synchronizing signal line 16. A main control substrate 12 is connected via the synchronizing signal line 16 to a head control part of the front end and a head control part of the tail end of a plurality of the daisy chain connected head control parts. The main control substrate 12 transmits superposing transmission destination information and a control signal corresponding to the transmission destination information on a synchronizing signal to the head control part of the front end. Each of the HC substrates 24 controls on the basis of control information shown by the control signal if the transmission destination information indicative of itself and the control signal showing the control information are superposed on the synchronizing signal received from the preceding stage. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a droplet discharge control device and a droplet discharge device, and more particularly to a droplet discharge control device and a droplet discharge device provided with a head control unit that controls the discharge of droplets according to a synchronization signal.

  There is known a liquid droplet ejection apparatus that is provided with a head in which a plurality of nozzles that eject liquid droplets are arranged and that ejects liquid droplets onto a recording medium. Along with the increase in the density and size of the head, a droplet discharge device has been developed in which a plurality of control substrates are provided corresponding to a plurality of nozzles arranged in the head and the head is driven by the plurality of control substrates. . Control information is transmitted to each control board, and each control board controls driving of the head based on the transmitted control information.

  For example, Patent Document 1 described below describes a recording apparatus in which a substrate is mounted for identifying an ink tank, the substrates are connected in a daisy chain, and device information of the ink tank is acquired based on sequentially read information. . Further, Patent Document 2 below describes a recording apparatus in which drive substrates are connected in a daisy chain and serially converted drive data is transferred.

The droplet discharge device includes a communication unit for transferring image data to be printed, a communication unit for controlling the operation of the substrate, and a synchronization signal for transmitting a synchronization signal for determining discharge timing. Communication means are required. As a communication means for control, in order to communicate with a large number of substrates, conventionally, each communication means is provided individually for communication. For example, a network such as Ethernet (registered trademark) or CAN (Contoroller Area Network), or a bus connection sharing the same data address signal line is used. As the communication means for the synchronization signal, for example, a communication technique such as LVDS (Low Voltage Differential Signaling) or optical communication is applied. A cable, a driver for transmission / reception (receiver) or the like is required according to each communication means.
JP 2007-1208 A JP 2008-12909 A

  However, the conventional technique has a problem that the number of cables increases and the apparatus becomes large.

  The present invention has been made in consideration of the above facts, and an object of the present invention is to provide a droplet discharge control device and a droplet discharge device capable of reducing the number of cables and communicating control information with a compact device configuration. And

  In order to achieve the above object, a droplet discharge control device according to a first aspect of the present invention is arranged corresponding to the plurality of arranged discharge portions of a droplet discharge head in which a plurality of discharge portions for discharging droplets are arranged. And a synchronization signal line having a pulse for determining the ejection timing of the liquid droplets and a synchronization signal on which a control signal indicating control information corresponding to the transmission destination information and the transmission destination information is superimposed as necessary is daisy-chained. Transmission / reception means that are connected in a chain and each transmit a synchronization signal received from the previous stage to the subsequent stage, and droplets are ejected from the ejection unit according to image data at ejection timings corresponding to the received synchronization signal. When the control signal is superimposed on the received synchronization signal and the destination information indicated by the control signal indicates self, control is performed based on the control information indicated by the control signal. A plurality of head control units having a discharge control means for performing control, and a head control unit at the head and a head control unit at the end of the plurality of head control units connected in a daisy chain via the synchronization signal line. When the control information is transmitted with at least one of the plurality of head control units as a transmission destination, the control signal is superimposed on the synchronization signal and transmitted to the head control unit via the synchronization signal line. And a portion.

This droplet discharge control apparatus includes head control units connected in a daisy chain via synchronization signal lines. When the destination information indicated by the control signal superimposed on the synchronization signal received from the previous stage indicates itself, each head control unit performs control based on the control information indicated by the control signal. The received synchronization signal is transmitted to the subsequent stage.
According to such a configuration, the number of cables can be reduced, and control information can be communicated between the plurality of head control units and the main control unit with a compact device configuration.

  According to a second aspect of the present invention, a state signal indicating a result controlled by the discharge control unit based on the control signal is superimposed on each of the plurality of head control units of the droplet discharge control device according to the first aspect. Further, a state transmission control means for transmitting the synchronized signal from the transmission / reception means is further provided.

  According to such a configuration, a state signal indicating a result of control based on the control information can be transmitted from the head control unit to the main control unit via the synchronization signal line.

  According to a third aspect of the present invention, in the droplet discharge control apparatus according to the first or second aspect, the discharge control means determines a discharge timing by replacing the control signal superimposed on the synchronization signal with the pulse. It is used as a signal.

  According to such a configuration, the synchronization signal on which the control signal is superimposed can also be used as the synchronization signal that determines the discharge timing.

  According to a fourth aspect of the present invention, in the liquid droplet ejection control apparatus according to the second or third aspect, the main control unit is configured to perform a period in which droplets are ejected by the ejection unit according to image data with respect to the synchronization signal. The superimposition of the control signal is stopped, and the state transmission control means stops the superposition of the state signal with respect to the synchronization signal during a period in which droplets are ejected by the ejection unit in accordance with image data.

  According to such a configuration, the control signal and the state signal are not superimposed on the synchronization signal during the period during which the liquid droplet is ejected according to the image data, that is, the image drawing period. Discharging can be performed.

  According to a fifth aspect of the present invention, in the liquid droplet ejection control apparatus according to the second or third aspect, the main control unit is configured to transport a recording medium on which an image is recorded by the liquid droplet ejection head. The synchronization signal is transmitted in response to the carrier signal generated in response to the carrier signal, and the synchronization signal can be transmitted in a state in which the carrier signal is not generated. The synchronization signal is transmitted in response to the carrier signal. After the elapse of a predetermined time until the next synchronization signal is transmitted in response to the next carrier signal, superposition of the control signal on the synchronization signal is stopped, and the state transmission control means In the transmission stop period of the synchronization signal on which the signal is superimposed, the state signal is not superimposed on the synchronization signal.

  According to such a configuration, it is possible to perform communication of control information and state information by generating a synchronization signal even if no carrier signal is generated, and at the same time, discharge the synchronization signal transmitted in accordance with the carrier signal. It can be used as a defining signal.

  According to a sixth aspect of the present invention, in the liquid droplet ejection control apparatus according to the second or third aspect, the main control unit is a synchronization signal on which a control signal indicating control information designating one of the head control units is superimposed. During the period from when the predetermined time elapses until the predetermined time elapses, transmission of the synchronization signal superimposed with a control signal whose destination is a head control unit other than the head control unit specified by the control information is stopped, The state transmission control means receives the synchronization signal on which a control signal indicating control information designating itself is superimposed, and after a predetermined time has elapsed after receiving the synchronization signal, The superposition of the state signal to the signal is stopped.

  According to such a configuration, it is possible to superimpose a control signal for designating a head control unit to be communicated on the synchronization signal, and it is possible to ensure a communication period for each head control unit. As a result, traffic loss and communication retry can be prevented.

  According to a seventh aspect of the present invention, there is provided a liquid droplet ejection apparatus according to any one of the first to sixth aspects, and a liquid droplet ejection control device according to any one of the first to sixth aspects. , And is configured.

  According to such a configuration, the number of cables can be reduced, and control information can be communicated with a compact device configuration.

  As described above, the present invention has an excellent effect that the number of cables can be reduced and control information can be communicated with a compact device configuration.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a diagram illustrating a configuration example of a droplet discharge device 10 according to an embodiment of the present invention.

  The droplet discharge device 10 includes a main control board 12, a head module 14, and a mechanical control main unit 30.

  The main control board 12 is a board provided with a CPU and various circuits for controlling the entire droplet discharge device 10.

  The head module 14 includes a bar unit 20 in which a droplet discharge head 28 (hereinafter simply referred to as the head 28) and a control board group of the head 28 are modularized, and a mechanism control subunit 40 that controls the mechanism around the head 28. It has.

  The mechanism control main unit 30 is a unit having a substrate for controlling the mechanism of the main body other than the periphery of the head 28, such as a recording medium transport mechanism for ejecting droplets by the head 28.

  Hereinafter, each configuration of the head module 14 will be described in more detail.

The bar unit 20 of the head module 14 includes an image driver substrate 22, a plurality of head control (HC) substrates 24 1- _n , a plurality of head driver (HD) substrates 26 1- _n , and a head 28.

  The head 28 is a long head in which a plurality of nozzles for discharging droplets are arranged. In this embodiment, a discharge chamber is provided that includes a pressure chamber that is supplied and accommodated with a liquid to be discharged, a nozzle that communicates with the pressure chamber, and a drive element that changes the pressure in the pressure chamber. By applying a drive signal, the pressure in the pressure chamber is changed, and droplets are ejected from each nozzle to the recording medium. The head 28 according to the present embodiment has a length corresponding to the width of the recording medium, and ejects droplets while transporting the recording medium in a direction intersecting the nozzle arrangement direction with the head 28 fixed. Thus, recording on the recording medium is performed.

  Here, the recording medium transport mechanism will be described. The conveyance belt that conveys the recording medium is provided with a driving roller. When the driving force of the motor is applied to the driving roller, the conveying roller is driven to rotate, and the conveying belt moves. Thereby, the recording medium on the conveying belt is conveyed from the upstream side in the conveying direction toward the image recording position of the head 28. These operations are controlled by the mechanical control main unit 30.

An encoder is attached to the drive roller. The encoder generates and outputs a rectangular wave (encoder signal) according to the rotation of the driving roller. This encoder signal is input to the main control board 12. Based on this encoder signal, the main control board 12 generates a synchronization signal that serves as a reference signal when an image is recorded on the recording medium, and outputs it to the HC boards ₂₄₁ to _n via the synchronization signal line 16. . This synchronization signal defines the droplet discharge timing of the head 28.

The HC substrates _{241 to n} are control substrates for controlling the head 28, and each nozzle when a plurality of nozzles are divided into n (n is an integer of 2 or more) nozzle groups along the nozzle arrangement direction. It is provided for each group. Note that the head 28 may be configured by connecting a plurality of head units in which a plurality of nozzles are arranged side by side in the nozzle arrangement direction. A plurality of nozzles arranged in each nozzle unit may be used as a group of nozzle groups, and the HC substrate 24 may be provided for each head unit.

Further, the HC boards _{241 to n} are daisy chain connected to each other by a synchronization signal line 16 for inputting a synchronization signal (see also FIG. 3). There are two types of synchronization signals, Psync and Lsync. Psync is a synchronization signal (vertical synchronization signal) for one page of image data, and Lsync is a synchronization signal (horizontal synchronization signal) for one line of image data (see also FIG. 4). Lsync is treated as a valid signal for image recording while Psync is enabled (Low level), and is invalid during other periods. Note that LVDS (Low Voltage Differential Signaling) or optical communication may be applied to the transmission and reception of the synchronization signal.

Since the configurations of the HC substrates 24 1 to _n are common, in the following, when the HC substrates 24 1 to _n are described without being distinguished from each other, the last symbol is omitted and referred to as the HC substrate 24. . Also, since the HD boards _{261 to n} have the same configuration, the HD boards ₂₆₁ to _n will be referred to as the HD board 26 by omitting the reference numerals when they are described without distinction.

  FIG. 2 is a diagram illustrating a configuration example of the HC substrate 24. The HC board 24 includes a CPU (Central Processing Unit) 50, a flash memory 52, an ASIC (Application Specific Integrated Circuit) 54, a DA (Digital / Analog) converter 56, a head IF (Interface) 58, a synchronization signal transmission unit 62, a synchronization signal. A receiving unit 64 and an image data receiving unit 66 are provided.

  The CPU 50 is connected to the flash memory 52 and the ASIC 54. The CPU 50 controls the entire HC board 24 by executing a program stored in the flash memory 52.

  Further, the CPU 50 generates a digital signal indicating a voltage serving as a reference of a driving signal applied to the driving element corresponding to each nozzle of the head 28 based on the image data acquired by the ASIC 54, and the digital signal is transmitted via the ASIC 54. Output to the DA converter 56. Further, when control information addressed to itself is input from the ASIC 54, the CPU 50 performs control according to the control information. In addition, status information indicating the result of control based on the control information is output to the ASIC 54.

  Here, specific examples of control information and state information will be described.

  The control information is information that defines the control content of the HC substrate 24. For example, the control information is control information for setting a parameter (correction value or the like) for correcting the displacement position of the droplet on the recording medium. May be.

  For example, in a droplet discharge device, the discharge characteristics of each nozzle (droplet speed or discharge direction when discharging a droplet) may vary due to manufacturing variations, resulting in a deviation in the attachment position of the droplet. In addition, the temperature of the pressure chamber may fluctuate due to discharge, the viscosity of the liquid in the pressure chamber may change, the droplet speed may vary, and the droplet attachment position may shift. Therefore, when correcting the timing at which the droplet is ejected and the waveform of the drive signal so as not to cause the deviation of the droplet attachment position, control information indicating the correction value is transmitted to the HC substrate 24.

  Such a correction value differs depending on the arrangement position of the nozzle (or nozzle group, head unit). Therefore, control information related to the correction value is generated for each identification information and transmitted to each HC board 24.

  The control information is not limited to the above, and includes, for example, an initialization command for initializing the substrate and a forced stop command for forcibly stopping droplet discharge.

  On the other hand, the status information includes various statuses such as status information indicating that the initialization is normally completed based on the control information of the initialization command and status information indicating that the initialization is forcibly stopped based on the forced stop command. There is information.

  The flash memory 52 stores a program executed by the CPU 50 in advance. Further, identification information for identifying each of the HC substrates 24 is also recorded.

  The ASIC 54 outputs the digital signal input from the CPU 50 to the DA converter 56 and outputs the image data received by the image data receiving unit 66 to the CPU 50 and the head IF 58.

  Further, when a control signal is superimposed on the synchronization signal received by the synchronization signal receiving unit 64, the ASIC 54 inputs information indicated by the superimposed control signal to the CPU 50. When the state information is input from the CPU 50, a state signal indicating the state information is superimposed on the synchronization signal and transmitted from the synchronization signal transmission unit 62.

  The DA converter 56 converts the digital signal input from the ASIC 54 into an analog signal and outputs the analog signal to the HD board 26. The head IF 58 converts the level of the image data input from the ASIC 54 and outputs it to the HD board 26.

  The synchronization signal transmission unit 62 and the synchronization signal reception unit 64 are connected to the synchronization signal line 16.

  The synchronization signal receiving unit 64 receives the synchronization signal transmitted from the preceding HC board 24 connected in a daisy chain. When the HC board 24 is the first HC board 24 connected in a daisy chain, the synchronization signal transmitted from the main control board 12 is received. The synchronization signal received by the synchronization signal receiving unit 64 is input to the ASIC 54.

  The synchronization signal transmission unit 62 transmits the synchronization signal input from the ASIC 54 to the HC board 24 at the subsequent stage. If the HC board 24 is the last HC board 24 connected in a daisy chain, a synchronization signal is transmitted to the main control board 12.

  The image data receiving unit 66 receives image data from the image driver board 22.

  Each of the HC substrates 24 and each of the HD substrates 26 are provided corresponding to each other. The HD board 26 is an analog driver board that applies drive signals to the drive elements provided corresponding to the nozzles. When a digital signal and image data serving as a reference of a drive signal are input from the corresponding HC substrate 24, the HD board 26 amplifies the digital signal to generate a drive signal, and each of the HD boards 26 corresponds to the input image data. The drive signal is applied to the nozzle drive element.

  The image driver board 22 is connected to the main control board 12 via the image data signal line 15. The image driver board 22 distributes and supplies image data received from the main control board 12 via the image data signal line 15 to each of the HC boards 24. As described above, the HC board 24 is provided in correspondence with the nozzle arrangement position, and image data corresponding to the nozzle arrangement position is transferred to the HC board 24. Note that identification information for identifying each of the HC boards 24 is set in advance in each HC board 24 (stored in the flash memory 52), and the image driver board 22 follows the identification information set for the HC boards 24. Image data is distributed and supplied.

  The mechanism control subunit 40 of the head module 14 is a unit that controls the mechanism around the head 28.

  The main control board 12, the mechanical control main unit 30, and the mechanical control subunit 40 are connected to a network 18 such as Ethernet (registered trademark) or CAN (Contoroller Area Network). These send and receive control information and status information to and from each other via the network 18. These may be connected by a bus.

  On the other hand, in the present embodiment, transmission / reception of control information and status information between the HC board 24 and the main control board 12 is performed via the synchronization signal line 16. Hereinafter, the transmission / reception of control information and state information will be specifically described with reference to FIGS. 3 and 4.

FIG. 3 shows four HC boards 24 (24 ₁ , 24 ₂ , 24 ₃ , 24 ₄ ) connected in a daisy chain via the synchronization signal line 16 and HD boards 26 corresponding to the four HC boards 24. _{(26 1,} 26 _2, 26 3, 26 ₄₎ If a is provided, it is a diagram showing a connection state of each substrate.

The HC substrates 24 _{1 to} 24 ₄ are provided for each group when the plurality of nozzles are divided into four groups along the nozzle arrangement direction. The four HC substrates 24 _{1 to} 24 ₄ are daisy chain connected in the order of the HC substrates 24 ₁ , 24 ₂ , 24 ₃ , 24 ₄ , and are arranged corresponding to the respective nozzle groups along the nozzle arrangement direction. Has been.

As shown in FIG. 3, the top of the HC synchronization signal transmission part 62 of the substrate 24 ₁ it is connected via a synchronization signal line 16 to the HC synchronization signal receiver 64 of the substrate 24 ₂ of the rear stage, the HC board 24 ₂ synchronization signal transmission unit 62 is connected via a synchronization signal line 16 to the HC synchronization signal receiver 64 of the substrate 24 ₃ of a subsequent stage, HC board 24 ₃ of the synchronization signal transmitter 62 is the end of the HC board 24 ₄ synchronization The signal receiver 64 is connected via the synchronization signal line 16.

Further, the synchronization signal receiving unit 64 of the head of the HC board 24 ₁ is connected via a synchronization signal line 16 to the main control board 12, the synchronization signal transmitter 62 of the last HC board 24 _4, the main control board 12 Are connected to each other via a synchronization signal line 16.

  With this configuration, the synchronization signal input from the main control board 12 to the first HC board 24 is sequentially input to the subsequent HC board 24, and finally the synchronization signal is input to all the HC boards 24. The

  First, transmission / reception of control information will be described.

The main control board 12, as shown in FIG. 4 (A), and transmits the synchronization signal Lsync, the HC board 24 ₁ of the top by superimposing control signals. In the example shown in FIG. 4A, the synchronization signal Lsync superimposed with the control signal is transmitted during the high level period of the synchronization signal Psync. The synchronization signal Lsync before the control signal is superimposed is composed of pulses that determine the ejection timing. In the present embodiment, when the control signal and the status signal are not superimposed, the ejection timing is defined by using the falling edge of the pulse of the synchronization signal Lsync as a trigger. A control signal is superimposed on the empty part after this pulse. Further, the main control board 12 generates and superimposes the control signal so as to have a cycle different from the cycle of the pulse constituting the synchronization signal Lsync before the control signal is superimposed (here, shorter than the cycle of the pulse). To do.

  FIG. 4B is a diagram illustrating an example of the synchronization signal Lsync on which the control signal is superimposed. As shown in the figure, the control signal starts with the pulse having a relatively long period (start bit), and is followed by a control signal having a period shorter than that of the pulse. The control signal includes a signal indicating control information and an end bit indicating the end of the signal.

  The main control board 12 generates transmission source information indicating a transmission source, transmission destination information indicating a transmission destination, and a control signal indicating control information. In FIG. 4B, the “Address 1” portion contains transmission source information, the “Address 2” portion contains transmission destination information, and the “Data” portion contains control information. For example, identification information preset in the HC board 24 can be applied to the transmission source information and the transmission destination information.

FIG. 4C is a diagram illustrating an example of transmission source information and transmission destination information. As shown in the figure, 00 is identification information indicating the master (in the present embodiment, the main control board 12), and 01 is identification information indicating the slave 1 (in the present embodiment, the HC board 24 ₁ ). 02 is identification information indicating the slave 2 (HC board 24 _{2 in the} present embodiment), and 03 is identification information indicating the slave 3 (HC board 24 _{3 in the} present embodiment). Yes, 04 is identification information indicating the slave 4 (in this embodiment, the HC board 24 ₄ ).

  FIG. 4D is a diagram illustrating an example of a combination of transmission source information and transmission destination information. As shown in the figure, for example, 0000 indicates that the transmission source is the master (00) and the transmission destination is all the slaves (00). 0001 indicates that the transmission source is the master (00) and the transmission destination is the slave 1 (01). 0002 indicates that the transmission source is the master (00) and the transmission destination is the slave 2 (02). Note that 0100, 0200, and 0201 will be described when the transmission / reception of the status signal is described.

  FIG. 4E is a diagram illustrating an example of control information. In this example, if Data is aa55, the synchronization signal on which the control signal is superimposed is handled as a synchronization signal Lsync that defines the discharge timing on the HC substrate 24, and if Data is 5a5a, the control signal is superimposed. The synchronized signal thus processed is handled as a reset signal Reset by the HC board 24. Reset means an initialization command.

  As described above, in the case of the synchronization signal in which the control signal and the state signal are not superimposed, the falling edge of the pulse defines the ejection timing. However, in the present embodiment, whether or not to handle the synchronization signal on which the control signal and the status signal are superimposed is specified as the synchronization signal for determining the discharge timing is determined by the content of the data indicated by the superimposed signal. The In this embodiment, if Data is aa55, the control signal superimposed on the synchronization signal is treated as a control signal that defines the discharge timing, and the discharge timing is defined by the rising timing of the end bit of the control signal. .

When the head of the HC board 24 ₁ is superimposed control signal in the synchronization signal receiving unit 64 synchronization signal Lsync is received, the synchronization signal Lsync is input to ASIC54 of HC substrate 24 _1. ASIC54 of HC substrate 24 ₁ performs a process of extracting a short signal periodicity from the synchronizing signal Lsync which is the received as a control signal. ASIC54 of HC board 24 _1, when the control signal from the synchronizing signal Lsync is extracted, and inputs the destination information indicated by the extracted control signals, the transmission destination information, and control information to the CPU 50. Further, ASIC 54 of the HC board 24 ₁ transmits a synchronization signal Lsync received via the synchronization signal transmitter 62 to the HC board 24 ₂ in the subsequent stage.

The CPU 50 confirms transmission destination information among information input from the ASIC 54. When the transmission destination information corresponds to the identification information stored in its own HC board 24, it is determined that the input control information is control information transmitted to itself, and processing is performed according to the control information. To do. For example, if the reset signal, it performs the initialization processing of the HC substrate 24 _1. Further, the control information, parameters for the HC board 24 ₁ (e.g., the correction value or the like for correcting the attachment positional deviation of liquid droplets) in the case of shows the configuration of, CPU 50 may store the parameters in the flash memory 52 To do. The CPU 50 can read and use the parameters stored in the flash memory 52 at a necessary timing.

Further, CPU 50, when the destination information does not correspond to the identification information stored in the HC board 24 ₁ self does not perform processing based on the input control information.

  In the present embodiment, the ASIC 54 is configured to perform a process of extracting the control signal from the synchronization signal Lsync regardless of whether the control signal is superimposed. However, when the control signal is not superimposed on the synchronization signal, the control signal is not extracted, so that the destination information, destination information, and control information are not input to the CPU 50.

When the second HC board 24 ₂ of the control information in the synchronization signal receiving unit 64 is superimposed synchronization signal Lsync is received, the synchronization signal Lsync is input to ASIC54 of HC board 24 _2. ASIC54 of HC board 24 ₂ is also as described above for processing the synchronization signal. Further, ASIC 54 of the HC board 24 ₂ transmits a synchronization signal Lsync received via the synchronization signal transmission unit 62 downstream of the HC board 24 _3.

Third HC board 24 ₃ similarly, the synchronization signal Lsync received and treated in the same manner as described above, also transmits the synchronization signal Lsync received via the synchronization signal transmission unit 62 downstream of the HC board 24 ₄ .

End of the HC board 24 ₄ are similarly a synchronization signal Lsync received and treated in the same manner as described above, also transmits to the subsequent main control board 12 via a synchronization signal transmitting unit 62 a synchronization signal Lsync received .

The main control board 12 checks the transmitted synchronization signal Lsync from the end of the HC board 24 _4. For example, if there is a disturbance in the cycle of the synchronization signal Lsync, it is possible to determine an error and transmit the synchronization signal on which the control signal is superimposed again in the same manner.

  Next, transmission / reception of status information will be described.

  In some cases, status information indicating the result of control based on the control information is transmitted from each HC board 24 to the main control board 12 (or to another HC board 24). In this case, the CPU 50 of each HC board 24 generates transmission source information, transmission destination information, and status information and inputs them to the ASIC 54. The ASIC 54 superimposes the state signal indicating the information input from the CPU 50 on the synchronization signal received by the synchronization signal receiving unit 64 and transmits it from the synchronization signal transmitting unit 62.

  As shown in FIG. 4B, the status signal is also generated with the same configuration as the control signal, and is superimposed on the original pulse of the synchronization signal Lsync. However, in the case of a status signal, status information is entered in the “Data” portion of FIG.

  As combinations of transmission source information and transmission destination information, there are 0100, 0200, 0201, and the like as shown in FIG.

  For example, 0100 indicates that the transmission source is slave 1 (01) and the transmission destination is master (00). 0200 indicates that the transmission source is slave 2 (02) and the transmission destination is master (00).

  0201 indicates that the transmission source is slave 2 (02) and the transmission destination is slave 1 (01). The state information is normally transmitted from the HC board 24 to the main control board 12, but when the control result of the other HC board 24 defines the control timing and control content of the other HC board 24, The status information may be transmitted from the slave to another slave (from the HC board 24 to another HC board 24).

  In addition, when transmitting the status information, the ASIC 54 of each HC board 24 transmits the status signal superimposed on the synchronization signal received from the previous stage. In this case, the control signal and the status signal are superimposed. A status signal may be further superimposed on the synchronization signal. If a control signal or other HC board 24 status signal is superimposed on the received synchronization signal, the received synchronization signal is transmitted to the subsequent stage without superimposing the status signal on the synchronization signal. When the control signal and the state signal of the other HC board 24 are not superimposed on the synchronization signal received from the previous stage, the state signal may be superimposed on the synchronization signal and transmitted.

  In addition, when the ASIC 54 of each HC board 24 receives the synchronization signal on which the state signal is superimposed from the previous stage, the ASIC 54 processes the synchronization signal in the same manner as when the synchronization signal on which the control signal is superimposed is received from the previous stage. To do.

That is, when the synchronization signal Lsync on which the state signal is superimposed is received by the synchronization signal receiving unit 64 of the HC board 24, the synchronization signal Lsync is input to the ASIC 54 of the HC board 24. The ASIC 54 of the HC board 24 extracts a signal with a short cycle from the received synchronization signal Lsync as a status signal. ASIC54 of HC substrate 24 _1, the extracted status destination information signal indicates to input destination information, and status information to the CPU 50. Further, ASIC 54 of the HC board 24 ₁ is transmitted to the subsequent stage of the HC substrate 24 a synchronizing signal Lsync received via the synchronization signal transmitter 62.

  The CPU 50 confirms transmission destination information among information input from the ASIC 54. When the transmission destination information corresponds to the identification information stored in its own HC board 24, it is determined that the input state information is the state information transmitted to itself, and processing is performed according to the state information. To do. Further, when the destination information does not correspond to the identification information stored in its own HC board 24, the CPU 50 does not perform processing based on the input state information.

  Even when the main control board 12 receives a synchronization signal on which the state signal is superimposed, the same processing as the ASIC 54 is performed.

  As described above, since the control signal and the status signal are superimposed and transmitted on the synchronization signal, the required number of cables can be reduced and the apparatus can be made compact.

  The present invention is not limited to the above-described embodiments, and various design changes can be made within the scope of the invention described in the claims.

  For example, in the above-described embodiment, the example in which the control signal and the status signal are superimposed on the synchronization signal Lsync has been described. However, the control signal and the status signal may be superimposed on the synchronization signal Psync. Even when the control signal and the status signal are superimposed on the synchronization signal Psync, the same effect as described above can be obtained by performing the same processing as in the above embodiment.

  Note that there may be noise in the synchronization signal. In this case, there is a possibility that control information and status information are not correctly recognized. Therefore, an error correction bit may be included in the control signal and the status signal. Further, the error may be determined by measuring the period of the synchronization signal.

  Each HC board 24 is configured to receive a synchronization signal by the ASIC 54, process the synchronization signal by the ASIC 54, and then pass it to a subsequent board. This process causes a delay. Therefore, when performing the discharge control based on the image data in accordance with the synchronization signal, the ASIC 54 is controlled so that the discharge is controlled at a discharge timing delayed by a delay correction value with respect to the discharge timing determined by the synchronization signal. The timing adjustment may be performed between all the HC substrates 24.

  For example, if a delay of 20 clocks occurs in one HC substrate 24, the leading HC substrate 24 is adjusted to delay the discharge timing by a delay time (correction value) corresponding to the total number of substrates, and then Each time the synchronization signal passes through the HC boards 24, the ASIC 54 of each HC board 24 reduces the correction value by 20 clocks and finally adjusts the timing of all the HC boards 24.

  The correction value is determined according to the identification information set on the HC board 24. In each HC board 24, it is possible to determine the number of the HC board 24 from the beginning from the stored identification information. Therefore, for example, if information on the delay time for the total number of substrates and the delay time for each HC substrate 24 is stored in the flash memory 52 in advance, the CPU 50 calculates a correction value according to the identification information. And can be adjusted with the calculated correction value. Further, as will be described later, a control signal indicating the correction value may be transmitted from the main control board 12 via the network 18 in advance to the synchronization signal and transmitted to each HC board 24 for storage. With such a configuration, timing deviation can be prevented.

  In the above-described embodiment, an example has been described in which the control signal superimposed on the synchronization signal Lsync is used as a synchronization signal that determines the discharge timing instead of the pulse (when Data = aa55), but the present invention is not limited to this. Not. For example, in the image drawing period (Psync low level period, that is, a period in which droplets are ejected from the nozzles according to image data), the ejection timing is defined without superimposing a control signal or a status signal on the synchronization signal Lsync. A synchronization signal having only a pulse may be generated and transmitted, and each HC substrate 24 may eject droplets at an ejection timing corresponding to the falling edge of the pulse.

  FIG. 5 is a diagram illustrating an example of a timing chart when the superimposition of the control signal and the state signal with respect to the synchronization signal is stopped during the image drawing period. In FIG. 5, the Low level and the High level are inverted. During an image drawing period in which the synchronization signal Psync is at a low level, communication of control information and state information is not performed as a drawing mode. In communication modes other than the image drawing period, control information and status information are communicated.

  In FIG. 5, black signals (S1, S2) and signals indicated by halftone dots are synchronization signals used for communication of control information and status information, and white signals are control information and status information. This is a synchronization signal that is not used for communication. Of the signals painted black, S1 is a synchronization signal on which a control signal indicating a print start command is superimposed. After S1, the drawing mode is set, and each HC board 24 waits for a synchronization signal. S2 is a synchronization signal on which a control signal indicating a print end command is superimposed. After S2, the mode is switched to the communication mode.

  Here, an example in which the control is switched between the drawing mode and the communication mode as described above will be described with reference to the flowcharts of FIGS. 6 and 7.

  FIG. 6 is a flowchart showing a flow of an initialization process routine performed on the main control board 12.

  In step 100, the main control board 12 sets itself to the communication mode.

  Step 102, the main control board 12 superimposes a control signal indicating an initialization command of each HC board 24 on the synchronization signal Lsync and transmits it via the synchronization signal line 16. For example, in the example illustrated in FIG. 4, the control signal is generated by setting the address combination to “0000 (Master-> All slave)” and Data to “5a5a”. The synchronization signal on which the control signal is superimposed passes through each HC board 24 and returns to the main control board 12 as described above. In addition, after each HC board 24 normally initializes itself, the HC board 24 superimposes a state signal indicating state information indicating that the initialization process has been normally completed, and transmits it to the main control board 12.

  In step 104, when the main control board 12 receives the synchronization signal on which the status signal received from the HC board 24 is superimposed, the main control board 12 checks the status information included in the status signal. Then, the source information included in the status signal is collated with the identification information of each HC board 24. Since the identification information of each HC board 24 is grasped in advance by the main control board 12, in the main control board 12, which HC board 24 has been normally initialized, which HC board 24 has not yet been initialized. You can see if it has been completed.

  After the initialization is normally completed in each HC board 24, in step 106, the main control board 12 superimposes a control signal indicating the parameter setting of each HC board 24 on the synchronization signal Lsync via the synchronization signal line 16. To send.

  FIG. 7 is a flowchart showing the flow of a print processing routine performed on the main control board 12.

  In step 120, the main control board 12 superimposes a control signal for instructing print preparation on each HC board 24 on the synchronization signal Lsync and transmits it via the synchronization signal line 16. When each HC board 24 receives this synchronization signal, each HC board 24 performs processing necessary for print preparation, and when the print preparation is completed, the synchronization signal on which the state signal indicating the state information indicating the completion of print preparation is superimposed is displayed. Transmit to the control board 12.

  In step 122, the main control board 12 checks the status of each HC board 24 from the status information received from each HC board 24.

  In step 124, the main control board 12 determines whether all the HC boards 24 are ready for printing. If the main control board 12 makes a negative determination, the process returns to step 122 and waits until all the HC boards 24 receive a synchronization signal superimposed with a status signal indicating status information indicating completion of print preparation. If the main control board 12 makes an affirmative determination in step 124, the process proceeds to step 126.

  In step 126, a control signal indicating a print start command is superimposed on the synchronization signal Lsync and transmitted to each HC board 24 (corresponding to the synchronization signal S1 in FIG. 5). As a result, each HC board 24 waits for a synchronization signal. Thereafter, the status signal is not transmitted from the HC board 24 until a print end command is received.

  In step 128, the main control board 12 sets itself to the drawing mode.

  In step 130, the main control board 12 transmits the synchronization signal Psync and the synchronization signal Lsync via the synchronization signal line 16, and discharges at each HC board 24 at a timing corresponding to the synchronization signal Psync and the synchronization signal Lsync. To be controlled. Each HC substrate 24 controls ejection at a timing corresponding to the received synchronization signal Psync and synchronization signal Lsync.

  When printing for one page is completed, in step 132, the main control board 12 superimposes a control signal instructing the end of printing of each HC board 24 on the synchronization signal Lsync and transmits it via the synchronization signal line 16 (FIG. 5 equivalent to the synchronizing signal S2). Thereby, in each HC board | substrate 24, the synchronous signal waiting for drawing is cancelled | released.

  In step 134, the main control board 12 sets itself to the communication mode.

  In step 136, when the main control board 12 receives the synchronization signal on which the status signal indicating the print control status or the like is superimposed, the main control board 12 checks the print control status indicated by the status signal and sets the status of each HC board 24. To check.

  In the above embodiment, it has been described that the main control board 12 generates the synchronization signal by the encoder signal. However, the main control board 12 is configured to generate a synchronization signal by generating an encoder signal and to generate a synchronization signal even when no encoder signal is generated. Regardless, communication of control information and status information may be performed by generating a synchronization signal.

  When configured in this way, control information and state information can be communicated not only during the communication mode but also during the drawing mode (during the image drawing period).

  FIG. 8 is a diagram illustrating an example of a timing chart when communication of control information and state information is performed even during an image drawing period. As shown in FIG. 8A, control information and status information are communicated during the communication mode, as described above. During the drawing mode, control information and status information are displayed as shown in FIG. 8B. Communication is performed.

  In FIG. 8B, the outline synchronization signal is the synchronization signal generated in response to the generation of the encoder signal. On the other hand, the halftone dot synchronization signal is a synchronization signal generated in a state where no encoder signal is generated. Hereinafter, in order to distinguish between the two, the synchronization signal generated in response to the generation of the encoder signal is referred to as synchronization signal A, and the synchronization signal generated in the state where the encoder signal is not generated is referred to as synchronization signal B.

  The main control board 12 generates the synchronization signal A in response to the generation of the encoder signal. The cycle of the encoder signal changes according to the drawing condition (operating state of the transport mechanism). Accordingly, the interval between successive synchronization signals A, that is, the cycle of the synchronization signal A also changes. However, the period variation often falls within a predetermined range. Therefore, a period from the generation of the synchronization signal A until a predetermined time elapses (however, the period of the synchronization signal A is not exceeded) is defined as a communicable period for permitting communication of control information and state information. After the period, a period until the next synchronization signal A is generated is controlled as a communication stop period for stopping communication of control information and state information.

  For example, when the average period of the synchronization signal A is 100 μs, 50 μs from the generation of the synchronization signal A may be a communicable period, and thereafter, a period until the next synchronization signal A is generated may be a communication stop period. .

  Thus, during the communicable period, the main control board 12 generates the synchronization signal B, superimposes the control signal as necessary, and transmits it to the HC board 24 via the synchronization signal line 16.

  The HC board 24 also transmits a synchronization signal with state information superimposed as necessary during the communicable period, and stops transmission of a synchronization signal with the state information superimposed during the communication stop period. Each CPU 50 of the HC board 24 can grasp the communicable period and the communication stop period by receiving the synchronization signal A.

  Note that communication of control information and status information during the image drawing period is difficult to perform software processing, and therefore communication processing may be performed by hardware.

  In addition, regardless of whether in the drawing mode or the communication mode, the main control board 12 transmits a synchronization signal on which a control signal for designating any one of the HC boards 24 is superimposed, until a predetermined time elapses. This period may be a communication period in which communication is performed between the designated HC board 24 and the main control board 12, and communication with the HC boards 24 other than the designated HC board 24 may be stopped.

  FIG. 9 is a diagram illustrating an example of a timing chart of the synchronization signal Lsync when the HC board 24 is specified for communication. In FIG. 9, a white synchronizing signal Lsync is a synchronizing signal on which a control signal designating the HC board 24 is superimposed. The halftone dot synchronization signal Lsync is a synchronization signal Lsync on which a control signal for the designated HC board 24 and a status signal of the designated HC board 24 are superimposed.

  For example, when the main control board 12 designates the No. 1 HC board 24 by the synchronization signal, a period until a predetermined time elapses from the transmission of the synchronization signal (hereinafter referred to as a designated period). Performs communication of control information and status information with the No. 1 HC board 24 and stops communication with the HC boards 24 other than the No. 1 HC board 24.

  On the other hand, when the No. 1 HC board 24 receives a synchronization signal designating itself, it can communicate state information during the designated period. In addition, communication of the status information is stopped outside the specified period (until the reception of the synchronization signal designating the self and after the predetermined time has elapsed since the reception of the synchronization signal). In addition, the other HC boards 24 other than the No. 1 HC board 24 continue to be in the state information communication stop state until receiving the synchronization signal designating itself.

  In this way, a communication period is secured for each HC board 24 by superimposing the control signal designating the HC board 24 to be communicated on the synchronization signal Lsync. As a result, traffic loss and communication retry can be prevented. Of course, in this case as well, communication may be performed by generating a synchronization signal (the synchronization signal B) in a state where no encoder signal is generated, as described above.

  In the above embodiment, the processing for the synchronization signal is performed by the ASIC 54. However, the present invention is not limited to this. For example, the ASIC 54 may be configured by an FPGA (Field Programmable Gate Array).

It is a figure which shows the structural example of the droplet discharge apparatus which concerns on one Embodiment of this invention. It is a figure which shows the structural example of HC board | substrate. It is a figure which shows the connection state of each board | substrate when the four HC board | substrates connected by the daisy chain via the synchronizing signal line and the HD board | substrate corresponding to these four HC board | substrates are provided. It is a figure which shows an example of the synchronizing signal with which the identification information was superimposed. It is a figure which shows an example of the timing chart in the case of stopping superimposition of the control signal and state signal with respect to a synchronizing signal during an image drawing period. It is a flowchart which shows the flow of the initialization process routine performed with a main control board | substrate. It is a flowchart which shows the flow of the print processing routine performed with a main control board. It is a figure which shows an example of a timing chart in the case of communicating control information and status information also during an image drawing period. It is a figure which shows an example of the timing chart of the synchronizing signal Lsync in the case of specifying and communicating HC board | substrate.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Droplet discharge device 12 Main control board 14 Head module 15 Image data signal line 16 Synchronization signal line 18 Network 20 Bar unit 22 Image driver board 24 Head control board 26 Head driver board 28 Droplet discharge head 30 Mechanical control main unit 40 Mechanism Control subunit 50 CPU
52 Flash memory 54 ASIC
62 synchronization signal transmission unit 64 synchronization signal reception unit 66 image data reception unit

Claims (7)

A plurality of ejection units for ejecting droplets are arranged corresponding to the plurality of arranged ejection units of the droplet ejection head, and have pulses for determining the ejection timing of the droplets, and transmission destination information and transmission destinations Transmission / reception means for daisy-chaining each other by a synchronization signal line to which a control signal indicating control information corresponding to information is superimposed as necessary is input, and each transmitting a synchronization signal received from the previous stage to the subsequent stage And a control so that a droplet is ejected from the ejection unit according to image data at ejection timing according to the received synchronization signal, and a control signal is superimposed on the received synchronization signal, and the control signal A plurality of head control units having ejection control means for performing control based on the control information indicated by the control signal;
Connected to the head control unit and the last head control unit of the plurality of head control units connected in the daisy chain via the synchronization signal line, and controlled using at least one of the plurality of head control units as a transmission destination When transmitting information, a main control unit that superimposes a control signal on a synchronization signal and transmits the signal to the head control unit via the synchronization signal line;
A droplet discharge control device comprising: Each of the plurality of head controllers is further provided with a state transmission control unit that transmits from the transmission / reception unit a synchronization signal on which a state signal indicating a result of the control by the ejection control unit based on the control signal is superimposed. Item 2. A droplet discharge control device according to Item 1. The droplet discharge control apparatus according to claim 1, wherein the discharge control unit uses the control signal superimposed on the synchronization signal as a signal for determining discharge timing instead of the pulse. The main control unit stops superimposing the control signal on the synchronization signal during a period in which droplets are ejected by the ejection unit according to image data,
4. The droplet discharge control device according to claim 2, wherein the state transmission control unit stops superposition of the state signal with respect to the synchronization signal during a period in which droplets are discharged by the discharge unit according to image data. . The main control unit transmits a synchronization signal in response to a transport signal generated in response to a transport operation of a transport unit that transports a recording medium on which an image is recorded by the droplet discharge head, and the transport signal is generated. The synchronization signal can be transmitted in a state in which the synchronization signal is not transmitted, and the next synchronization signal is transmitted according to the next carrier signal after a predetermined time has elapsed since the synchronization signal was transmitted according to the carrier signal. During the period until, the superposition of the control signal to the synchronization signal is stopped,
4. The droplet discharge control device according to claim 2, wherein the state transmission control unit stops superimposing the state signal on the synchronization signal during a transmission stop period of the synchronization signal on which the control signal is superimposed. The main control unit is designated by the control information for a period until a predetermined time elapses after transmitting a synchronization signal on which a control signal indicating control information designating one of the head control units is superimposed. Stop transmission of a synchronization signal superimposed with a control signal whose destination is a head control unit other than the head control unit,
The state transmission control means receives the synchronization signal on which a control signal indicating control information designating itself is superimposed, and after a predetermined time has elapsed after receiving the synchronization signal, The droplet discharge control device according to claim 2, wherein the superposition of the state signal with respect to the signal is stopped. A droplet discharge head in which a plurality of discharge units for discharging droplets are arranged; and
A droplet discharge control device according to any one of claims 1 to 6,
A droplet discharge device comprising:

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