JP7427225B2 - Manufacturing method of semiconductor parts and composite wafer - Google Patents

Description

The present invention relates to a method for manufacturing semiconductor components and a composite wafer.

In the field of technology for manufacturing semiconductor components, manufacturing technologies for semiconductor components that achieve even higher functionality and miniaturization are being considered. For example, Patent Document 1 discloses a technique for manufacturing a semiconductor component in which a plurality of semiconductor chips are stacked. The semiconductor chips are bonded to each other using a thermosetting bonding member. However, as the number of stacked semiconductor chips increases, a temperature difference occurs between a bonding member located close to the heating location and a bonding member located far from the heating location. Patent Document 1 focuses on such a problem and discloses a technique that can appropriately mount a plurality of semiconductor chips even if the number of stacked layers is large.

Japanese Patent Application Publication No. 2018-060952

In the production of semiconductor components, it is desired to produce a plurality of highly functional and miniaturized semiconductor components from a single semiconductor wafer. Therefore, when semiconductor chips are arranged on a semiconductor wafer, the intervals between the semiconductor chips are made as narrow as possible.

When mounting a semiconductor chip on a semiconductor substrate, for example, a load may be applied to the semiconductor chip. It may also provide heat to the semiconductor chip. In such processing, if the distance between the semiconductor chips is narrow, the processing may affect semiconductor chips placed around the semiconductor chip to be processed. Such influence on semiconductor chips that are not the target of processing may cause defects in semiconductor components. Therefore, semiconductor components that may malfunction may be manufactured, resulting in a decrease in yield.

An object of the present invention is to provide a method for manufacturing semiconductor components and a composite wafer that can reduce the number of semiconductor components and suppress a decrease in yield.

A method for manufacturing a semiconductor component, which is an embodiment of the present invention, includes a composite wafer including a base wafer including a plurality of placement areas to which semiconductor chips are bonded, and a support wafer that is detachably bonded to the base wafer. , the thickness of the support wafer is larger than the thickness of the base wafer, and the support wafer includes a thermal barrier portion formed to surround the placement area in a plan view. and a step of mounting the semiconductor chip in the placement area using a chip bonding member.

In this manufacturing method, a base wafer is bonded to a support wafer. The support wafer includes a thermal barrier portion formed to surround the placement area of the base wafer. Then, when a semiconductor chip is mounted by applying heat to the thermosetting chip bonding member in a certain placement area, the thermal barrier section prevents the influence of the heat on another placement area adjacent to the certain placement area. suppress. As a result, the occurrence of unintended thermal hardening of the chip bonding member is suppressed, making it possible to mount each semiconductor chip in a desired manner. Therefore, a decrease in yield can be suppressed.

In one form, the support wafer has a support wafer bonding surface to which the base wafer is removably bonded, and a support wafer back surface opposite to the support wafer bonding surface, and the thermal barrier section has a support wafer back surface on the opposite side to the support wafer bonding surface. The support wafer may extend from the support wafer to the bonding surface. According to this configuration, the flatness of the support wafer bonding surface can be maintained.

In one form, the thermal barrier section may include a groove having an opening on the back surface of the support wafer and a molding material filled in the groove. According to this configuration, it is possible to enhance the heat shielding effect exerted by the thermal barrier portion and to suppress a decrease in rigidity of the support wafer.

In one form, the thermal barrier portion may be a gap formed by a groove having an opening in the back surface of the support wafer. According to this configuration, a heat shielding effect can be obtained with a simple structure.

In one form, the step of mounting the semiconductor chip may include the step of arranging a chip bonding member on a base wafer bonding surface of a base wafer on which a plurality of placement regions are set. According to this step, it is possible to suppress the occurrence of unintended heat curing of another chip bonding member adjacent to the chip bonding member undergoing the heat curing treatment.

In one form, the step of mounting the semiconductor chip includes a step of arranging a chip bonding member, and, after mounting the semiconductor chip on the chip bonding member, pressing the semiconductor chip toward the composite wafer while mounting the semiconductor chip through the semiconductor chip. The method may also include a step of applying heat to the joining member. According to these steps, the chip bonding members can be placed all at once on the base mounting surface.

In one form, the step of mounting the semiconductor chip includes the step of providing a chip bonding member on the chip bonding surface of the semiconductor chip facing the base wafer bonding surface, and the step of arranging the chip bonding member in an arrangement area of the base wafer bonding surface. a step of placing a semiconductor chip provided with a chip bonding member on a semiconductor chip; a step of applying heat to the chip bonding member via the semiconductor chip while pressing the semiconductor chip provided with the chip bonding member toward the composite wafer; May include. According to these steps, a chip bonding member can be arranged for each semiconductor chip.

In one form, in the step of mounting a semiconductor chip, one semiconductor chip provided with a chip bonding member may be placed in one placement area. According to this process, a semiconductor component with a simple configuration can be manufactured.

In one form, in the process of mounting semiconductor chips, a plurality of semiconductor chips each provided with a chip bonding member may be stacked in one placement area. According to this process, a stacked semiconductor component can be manufactured.

A composite wafer according to another embodiment of the present invention includes a base wafer including a plurality of placement areas to which semiconductor chips are bonded, and a support wafer that is detachably bonded to the base wafer, and the support wafer has a thickness of: The support wafer has a thickness greater than that of the base wafer, and includes a thermal barrier portion formed to surround the arrangement region when viewed from above.

The support wafer includes a thermal barrier portion formed to surround the placement area of the base wafer. Then, when a semiconductor chip is mounted by applying heat to the thermosetting chip bonding member in a certain placement area, the thermal barrier section prevents the influence of the heat on another placement area adjacent to the certain placement area. suppress. As a result, the occurrence of unintended thermal hardening of the chip bonding member is suppressed, making it possible to mount each semiconductor chip in a desired manner. Therefore, the number of semiconductor components that may malfunction can be reduced. As a result, a decrease in yield can be suppressed.

According to the present invention, a method for manufacturing semiconductor components and a composite wafer that can suppress a decrease in yield are provided.

FIG. 1 is a schematic diagram showing a bonding apparatus used in a method of manufacturing a semiconductor device. FIG. 2 is a perspective view of the composite wafer viewed from the base wafer side. FIG. 3 is a perspective view of the composite wafer viewed from the support wafer side. FIG. 4 is an enlarged plan view of a part of the support wafer of the composite wafer. FIG. 5 is a sectional view taken along line V-V in FIG. 2. 6(a), FIG. 6(b), and FIG. 6(c) are diagrams showing a process of preparing a composite wafer in the method for manufacturing a semiconductor component according to the first embodiment. FIG. 7(a) is a diagram showing a step of preparing a composite wafer following FIG. 6(c). FIGS. 7(b) and 7(c) are diagrams showing a process of mounting a semiconductor chip following FIG. 7(a). 8(a), FIG. 8(b), and FIG. 8(c) are diagrams showing a process of mounting a semiconductor chip following FIG. 7(c). FIGS. 9(a) and 9(b) are diagrams showing a process of cutting into each semiconductor component. 10(a), FIG. 10(b), and FIG. 10(c) are diagrams showing the step of cutting into individual semiconductor components following FIG. 9(b). FIG. 11A is an enlarged perspective view for explaining the effects of a composite wafer of a comparative example. FIG. 11(b) is an enlarged perspective view for explaining the effects of the composite wafer of the embodiment. FIGS. 12(a) and 12(b) are diagrams showing a step of mounting a semiconductor chip in the method for manufacturing a semiconductor component according to the second embodiment. FIG. 13 is a diagram showing a process of mounting a semiconductor chip following FIG. 12(b). FIGS. 14(a) and 14(b) are diagrams illustrating a step of mounting a semiconductor chip in the method for manufacturing a semiconductor component according to the third embodiment. 15(a) and 15(b) are diagrams showing a process of mounting a semiconductor chip following FIG. 14(b).

<First embodiment>
Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the accompanying drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant description will be omitted.

<Bonding equipment>
As shown in FIG. 1, the bonding apparatus 100 mounts a semiconductor chip 30, which is an example of an electronic component, on the composite wafer 1. Through this mounting, a semiconductor component 90 (see FIG. 10(c)) including a part of the composite wafer 1 and the semiconductor chip 30 is obtained. In the following description, the X-axis and Y-axis, which are orthogonal to each other, are assumed to be parallel to the main surface of the semiconductor chip 30 (or the main surface of any stage). The Z-axis is a direction perpendicular to both the X-axis and the Y-axis.

First, the bonding apparatus 100 will be explained. As shown in FIG. 1, the bonding apparatus 100 includes a chip stage 101, an intermediate stage 102, a bonding stage 103, a bonding unit 104, an XY stage 105, and a bonding control section (hereinafter simply referred to as "control section 106"). ).

A wafer 110 including a plurality of semiconductor chips 30 is temporarily placed on the chip stage 101 . A wafer 110 is fixed to the chip stage 101 with an adhesive film (not shown).

The semiconductor chip 30 is temporarily placed on the intermediate stage 102 . The intermediate stage 102 removably holds the semiconductor chip 30 with an adhesive film (not shown). Intermediate stage 102 is arranged between chip stage 101 and bonding stage 103. The intermediate stage 102 is configured to be movable in the X-axis direction and the Y-axis direction by a drive mechanism such as a linear motor (not shown).

The composite wafer 1 is placed on the bonding stage 103. The composite wafer 1 will be explained in detail later. The bonding stage 103 removably holds the composite wafer 1 with an adhesive film (not shown). The bonding stage 103 can move the composite wafer 1 in the X-axis direction and/or the Y-axis direction by a drive mechanism (not shown) including a guide rail. Further, the bonding stage 103 may include a heater for heating the composite wafer 1. Furthermore, the bonding stage 103 may include a light source 103a that irradiates the composite wafer 1 with ultraviolet rays.

The bonding unit 104 includes a bonding head 104a, a bonding tool 104b, a Z-axis drive mechanism 104c, and an imaging section 104d. The bonding head 104a is attached to an XY stage 105 and is movable in the X-axis direction and the Y-axis direction. Bonding tool 104b is attached to bonding head 104a via Z-axis drive mechanism 104c. The bonding tool 104b has an air vacuum function and/or an air blow function. With this function, the bonding tool 104b can attract or detach the semiconductor chip 30.

The imaging section 104d is also attached to the bonding head 104a. That is, when the bonding head 104a is moved by the XY stage 105, the bonding tool 104b and the imaging unit 104d attached to the bonding head 104a also move in the same way. The imaging unit 104d is spaced apart from the bonding tool 104b by a predetermined distance in the Y-axis direction. The imaging unit 104d images the semiconductor chip 30 placed on the intermediate stage 102. Further, the imaging unit 104d images the semiconductor chip 30 placed on the bonding stage 103. Note that the imaging unit 104d does not need to be fixed to the bonding head 104a. The imaging unit 104d may be movable separately from the bonding tool 104b.

<Composite wafer>
Next, the composite wafer 1 will be explained in detail. Composite wafer 1 is a composite semiconductor wafer including two semiconductor wafers. Specifically, composite wafer 1 includes a base wafer 10 and a support wafer 20. Note that the composite wafer 1 may include a wafer made of a material different from the semiconductor wafer. For example, composite wafer 1 may include a glass wafer.

FIG. 2 is a perspective view of the composite wafer 1 viewed from the base wafer 10 side. The base wafer 10 is, for example, a silicon thin film wafer. The base wafer 10 is diced into pieces in a later step, and together with the semiconductor chip 30 constitutes a semiconductor component 90 . The base wafer 10 includes a circuit forming surface 10a to which the semiconductor chip 30 is bonded, and a base wafer bonding surface 10b (see FIG. 5) to be bonded to the support wafer 20. On the circuit forming surface 10a, a plurality of arrangement areas P are set in parallel two-dimensionally. One or more semiconductor chips 30 are mounted in one placement area P. The thickness of the base wafer 10 is, for example, about 100 μm. Therefore, a support wafer 20 is bonded to the base wafer 10 in order to facilitate handling during transportation.

FIG. 3 is a perspective view of the composite wafer 1 viewed from the support wafer 20 side. Support wafer 20 defines the rigidity of composite wafer 1 . That is, the rigidity of the support wafer 20 is greater than the rigidity of the base wafer 10. This stiffness is provided by the thickness of the support wafer 20. That is, the thickness of the support wafer 20 is greater than the thickness of the base wafer 10. For example, the thickness of the support wafer 20 is about 500 μm. Support wafer 20 may be made of the same material as base wafer 10. According to this configuration, the coefficient of thermal expansion of the base wafer 10 and the coefficient of thermal expansion of the support wafer 20 are the same. Therefore, the difference between the amount of thermal deformation of the base wafer 10 and the amount of thermal deformation of the support wafer 20 during heat treatment is eliminated, and damage caused to each wafer due to thermal stress can be suppressed. In this embodiment, the support wafer 20 is made of silicon. Note that the material of the support wafer 20 may be different from that of the base wafer 10. For example, glass may be used as the material for the support wafer 20. Further, the shape of the support wafer 20 is the same as the base wafer 10 except for the thickness. That is, when the support wafer 20 and the base wafer 10 are viewed from above in a plan view, their external shapes match.

The support wafer 20 has a support wafer bonding surface 20a (see FIG. 5) and a support wafer back surface 20b. The base wafer 10 is bonded to the support wafer bonding surface 20a. Support wafer 20 differs from base wafer 10 in that it does not constitute semiconductor component 90 . That is, the support wafer 20 is removed at a certain point in the process of manufacturing the semiconductor component 90 (step S10: see FIG. 9(b), etc.). Therefore, a bonding member whose bonding strength can be controlled is used to bond the support wafer 20 and the base wafer 10. For example, a resin material whose bonding strength can be weakened by irradiation with ultraviolet rays is used. In order to perform such optical processing, the support wafer 20 transmits light having a predetermined wavelength.

The support wafer 20 has a thermal barrier section 21 therein. The thermal barrier section 21 includes a plurality of barriers 22 arranged in a grid pattern. Barrier 22 inhibits heat transfer in the diametrical direction of support wafer 20 . The lattice formed by the plurality of barriers 22 corresponds to the arrangement region P described above. That is, one grid corresponds to one arrangement area P. In other words, when the composite wafer 1 is viewed from above, the thermal barrier section 21 is formed so as to surround the semiconductor chip 30.

FIG. 4 is an enlarged plan view showing the peripheral portion of the support wafer back surface 20b. As shown in FIG. 4, the ends of each barrier 22 do not reach the outer peripheral edge 20e of the support wafer 20. Therefore, a wallless region 25 in which the barrier 22 is not formed is formed around the outer periphery of the support wafer 20. That is, the support wafer 20 includes a walled region 26 in which a plurality of barriers 22 are formed and a wallless region 25 in which no barriers 22 are formed. The wallless region 25 is formed in a ring shape so as to surround the walled region 26. According to such a wallless region 25, the degree of influence that the formation of the barrier 22 has on the rigidity of the support wafer 20 can be reduced. In other words, a decrease in the rigidity of the support wafer 20 can be suppressed.

The barrier 22 is formed in a region corresponding to the gap between the semiconductor chips 30 adjacent to each other. That is, the semiconductor chip 30 is not placed on the barrier 22. The width of the barrier 22 may be larger or smaller than the distance between the semiconductor chips 30. Further, the width of the barrier 22 may be approximately the same as the interval between the semiconductor chips 30.

The barrier 22 includes a portion that does not completely surround the outermost placement region P. For example, the arrangement region P1 is surrounded by barriers 22 on all sides. In other words, the barriers 22 surrounding the placement area P1 are connected to each other. On the other hand, a barrier 22 is also formed around the arrangement region P2. However, in the arrangement region P2, barriers 22 are formed near some of the sides. In other words, "surrounding the placement area" in this embodiment refers not only to the case where the barriers 22 are formed near all four sides as in the placement area P1, but also to the case where the barriers 22 are formed near all four sides as in the placement area P2. This also includes a case where a barrier 22 is formed near some of the sides. The barrier 22 surrounding the arrangement region P2 includes unconnected portions 27 that are not connected to each other. Such an unconnected portion 27 is formed by a protrusion 28 of the barrier 22 .

According to the protrusion 28, it is possible to lengthen the heat path from one arrangement region P2 to the other arrangement region P2. Therefore, it is possible to suppress the heat applied to one semiconductor chip 30 from being transmitted to the other semiconductor chip 30.

Furthermore, the non-connected portion 27 is formed on the side where the semiconductor chip 30 is not located next to it. According to such a non-connecting portion 27, formation of the groove 23, which would cause a decrease in rigidity, in a region near the outer peripheral edge 20e of the support wafer 20 can be avoided. Therefore, a decrease in rigidity of the support wafer 20 can be suppressed.

As shown in FIG. 5, the barrier 22 is composed of a groove 23 and a molding material 24. As shown in FIG. The groove 23 includes an opening 23a provided on the support wafer back surface 20b and a bottom surface 23b formed on the support wafer bonding surface 20a side. In other words, the groove 23 does not reach the support wafer bonding surface 20a. The depth of the groove 23 is defined by the distance from the support wafer back surface 20b to the bottom surface 23b. In this embodiment, the depth of the groove 23 is deeper than about half the thickness of the support wafer 20. Note that the depth of the groove 23 may be approximately half the thickness of the support wafer 20, or may be shallow.

The groove 23 is filled with a molding material 24 such as resin. The molding material 24 compensates for the rigidity of the support wafer 20 that decreases as the grooves 23 are formed. Furthermore, the mold material 24 constitutes a thermal resistance section in the diametrical direction of the support wafer 20. Therefore, the thermal conductivity of the mold material 24 is significantly lower than that of the support wafer 20. Further, the thermal expansion coefficient of the molding material 24 is preferably close to that of the support wafer 20. By using such a molding material 24, it is possible to suppress thermal stress caused by a difference in the amount of thermal deformation between the molding material 24 and the support wafer 20.

<Method for manufacturing semiconductor components>
Next, a method for manufacturing the semiconductor component 90 using the composite wafer 1 will be described with reference to FIGS. 6 to 10.

<Process of preparing composite wafer>
A composite wafer 1 is prepared (steps S1 to S4). First, a wafer 20S is prepared (step S1: FIG. 6(a)). Then, using a dicing cutter 301 or the like, a cut (groove 23) is formed in the back surface 20b of the support wafer (step S2: FIG. 6(b)). Next, a molding material 24 is poured into the groove 23 (step S3: FIG. 6(c)). Through the above steps S1 to S3, a support wafer 20 including a thermal barrier section 21 is obtained. Next, a wafer bonding member 42 is applied to the support wafer bonding surface 20a. Then, the base wafer 10 is bonded to the support wafer 20 (step S4: FIG. 7(a)). A composite wafer 1 is obtained through the above steps S1 to S4.

<Process of mounting semiconductor chips>
Next, a semiconductor chip is mounted (steps S5 to S8). First, the composite wafer 1 is placed on the bonding stage 103 (step S5: FIG. 7(b)). Subsequently, a film-like chip bonding member 41 is placed on the circuit forming surface 10a of the base wafer 10 (step S6: FIG. 7(c)). This chip bonding member 41 is, for example, a non-conductive film material called NCF (Non Conductive Film). After this chip bonding member 41 is sandwiched between the semiconductor chip 30 and the base wafer 10, it is cured by heat.

The chip bonding member 41 has a softening start temperature and a hardening start temperature. The hardening start temperature is higher than the softening start temperature. When the temperature of the chip bonding member 41 is lower than the softening start temperature, the chip bonding member 41 maintains, for example, a film-like shape without exhibiting fluidity. When the temperature of the chip bonding member 41 is higher than the softening start temperature and lower than the hardening start temperature, the chip bonding member 41 exhibits fluidity. In this state, the chip joining member 41 is easily deformed by external force. Therefore, it is possible to completely fill the gap between the semiconductor chip 30 and the base wafer 10. When the temperature of the chip bonding member 41 is higher than the hardening start temperature, the chip bonding member 41 gradually hardens.

Subsequently, the semiconductor chip 30 is bonded (steps S7 and S8). The bonding apparatus 100 picks up the semiconductor chip 30 from the intermediate stage 102 using the bonding tool 104b. Then, the bonding apparatus 100 places the semiconductor chip 30 on the predetermined placement area P (step S7: FIG. 8(a)). The bonding apparatus 100 continuously performs the next process (step S8) without separating the semiconductor chip 30 from the bonding tool 104b.

As shown in FIG. 8(b), the bonding apparatus 100 increases the temperature of the bonding tool 104b. When the temperature of the chip bonding member 41 becomes higher than the softening starting point as the temperature of the bonding tool 104b increases, the chip bonding member 41 exhibits fluidity. Then, the bonding apparatus 100 presses the bonding tool 104b against the composite wafer 1 side. As a result, the chip bonding member 41 exhibiting fluidity completely fills the gap between the semiconductor chip 30 and the base wafer 10. For example, the load applied by the bonding tool 104b to the semiconductor chip 30 is set to such an extent that the softened chip bonding member 41 is pushed away, the bumps 33 come into contact with the electrode terminals 11, and the bumps 33 are not significantly deformed.

When the temperature of the bonding tool 104b further increases and the temperature of the chip bonding member 41 becomes higher than the hardening start temperature, the chip bonding member 41 exhibiting fluidity begins to harden. When the temperature of the bonding tool 104b further increases and the temperature of the bump 33 becomes higher than the melting temperature, the bump 33 melts and comes into close contact with the electrode terminal 11. As a result, the bump 33 is electrically connected to the electrode terminal 11. After that, the bonding tool 104b is separated from the semiconductor chip 30.

Here, the heat provided from the bonding head 104a is transmitted inside the composite wafer 1 and tries to diffuse to the surroundings. In this case, heat diffusion is suppressed by the thermal barrier portion 21 in the diametrical direction of the composite wafer 1 . That is, heat is difficult to move to the placement area P adjacent to the placement area P where the semiconductor chip 30 is bonded. As a result, the temperature rise of the chip bonding member 41 in the adjacent arrangement region P is suppressed, so that unintended thermal hardening of the chip bonding member 41 is suppressed. This suppressing effect is particularly effective when the temperature of the bonding tool 104b is higher than the hardening start temperature of the chip bonding member 41, or when the temperature of the bonding tool 104b is higher than the melting temperature of the bump 33. Note that the function of the thermal barrier section 21 will be explained in detail later.

Then, the semiconductor chips 30 are sequentially bonded to each other in the arrangement region P. As a result, a plurality of semiconductor chips 30 are mechanically and electrically bonded to the base wafer 10 (see FIG. 8(c)).

Subsequently, each semiconductor component 90 is cut into pieces (steps S9 to S11). First, a buried region 302 is formed (step S9: FIG. 9(a)). In this step S9, a buried region 302 is formed so as to cover the circuit forming surface 10a of the base wafer 10 and the semiconductor chip 30. The embedded region 302 may be made of, for example, a resin material. Subsequently, the base wafer 10 is removed from the support wafer 20. In this step S10, ultraviolet rays L are irradiated from the support wafer back surface 20b of the support wafer 20 (step S10: FIG. 9(b)). As a result, the bonding strength of the wafer bonding member 42 decreases, so the base wafer 10 can be removed from the support wafer 20 (see FIG. 10(a)). Subsequently, the semiconductor component 90 is cut into pieces using a dicing cutter 301 or the like (step S11: FIG. 10(b)). As a result, a plurality of singulated semiconductor components 90 are obtained (see FIG. 10(c)).

<Effect>
The method for manufacturing a semiconductor component uses a composite wafer 1 that includes a base wafer 10 including a plurality of placement areas P to which semiconductor chips 30 are bonded, and a support wafer 20 that is detachably bonded to the base wafer 10. The thickness of the support wafer 20 is greater than the thickness of the base wafer 10. The support wafer 20 includes a thermal barrier section 21 formed to surround the arrangement region P in plan view. The method for manufacturing the semiconductor component 90 includes the steps of preparing the composite wafer 1 (steps S1 to S4) and the step of mounting the semiconductor chip 30 in the placement area P using the thermosetting chip bonding member 41 (step S5). ~S8).

In this manufacturing method, a base wafer 10 is bonded to a support wafer 20. The support wafer 20 includes a thermal barrier section 21 formed to surround the placement region P of the base wafer 10. Then, when mounting the semiconductor chip 30 by applying heat to the thermosetting chip bonding member 41 in a certain placement area P, the thermal barrier section 21 is placed in another placement area P adjacent to the certain placement area P. suppress the effects of the heat.

The function of the thermal barrier section 21 will be explained in more detail. FIG. 11A is an enlarged perspective view of a portion of a composite wafer 1E of a comparative example. The composite wafer 1E of the comparative example does not have the thermal barrier section 21. It is assumed that a certain region R1 is a heat input surface that receives heat from the bonding tool 104b. In this case, the heat tends to diffuse inside the base wafer 10 and the support wafer 20E. For example, attention is paid to the direction from a certain region R1 to an adjacent region R2. The movement of heat H is expressed by equation (1) when the amount of heat flowing per unit area (q: heat flux) is defined.
q=Q/A...(1)
q: Heat flux Q: Heat amount A: Area

Further, Fourier's law regarding heat transfer is expressed by equation (2).
q=-λ×dT/dx…(2)
λ: Thermal conductivity dT/dx: Thermal gradient

According to equations (1) and (2), equation (3) is obtained.
Q=-λ×dT/dx×A…(3)
In other words, the amount of heat (Q) transferred is proportional to the area and temperature gradient.

Then, when heat H moves from a certain region R1 to an adjacent region R2, if the area that contributes to heat transfer is limited, the amount of heat (Q) that moves is also limited. In the structure shown in FIG. 11A, for example, a plane N1 located between a certain region R1 and an adjacent region R2 is defined. This surface N1 includes a base wafer 10 and a support wafer 20. If the base wafer 10 and the support wafer 20 are made of the same material (silicon), the entire surface N1 can be defined as contributing to heat transfer. In such a configuration, the amount of heat (Q) transferred from one region R1 to the adjacent region R2 becomes large. In this case, unintended thermal hardening of the chip bonding member 41 may occur in a portion of the adjacent region R2. If the original bonding process is performed on the chip bonding member 41 that has partially thermally hardened, the intended bonded state may not be formed in some cases. For example, the semiconductor chip 30 may be tilted, resulting in poor contact between the bumps 33 and the electrode terminals 11.

On the other hand, FIG. 11(b) is an enlarged perspective view of a part of the composite wafer 1 of the embodiment. In the structure shown in FIG. 11(b), a plane N2 located between a certain region R1 and an adjacent region R2 is defined. This plane N2 includes a barrier 22 in addition to the base wafer 10 and the support wafer 20. As described above, if the base wafer 10 and the support wafer 20 are made of the same material (silicon), a partial region N2a of the surface N2 can be defined as contributing to heat transfer. On the other hand, since the barrier 22 has a higher thermal resistance than the base wafer 10 and the support wafer 20, it can be considered that it does not substantially contribute to heat transfer. Then, the area contributing to heat transfer in the composite wafer 1 of the embodiment becomes smaller than that of the composite wafer 1 of the comparative example due to the barrier 22. Therefore, as the area decreases, the amount of heat (Q) transferred also decreases.

As a result, it is possible to suppress the degree to which the temperature of the adjacent region R2 increases due to heating in a certain region R1. Since unintended thermal hardening of the chip bonding member 41 is suppressed, each semiconductor chip 30 can be mounted in a desired manner. Therefore, the number of semiconductor components 90 that may malfunction can be reduced. As a result, a decrease in yield can be suppressed.

In other words, the thermal barrier portion 21 makes it difficult for heat to move from the placement region P to which heat is provided. The heat then tends to stay in the area surrounded by the barrier 22. As a result, the semiconductor chip 30 and the chip bonding member 41 can be suitably heated. Specifically, the temperature difference that may occur between the semiconductor chip 30 and the chip bonding member 41 can be reduced. This effect is particularly effective when stacking a plurality of semiconductor chips 30 manufactured in the third embodiment described later.

The support wafer 20 has a support wafer bonding surface 20a to which the base wafer 10 is removably bonded, and a support wafer back surface 20b on the opposite side to the support wafer bonding surface 20a. The thermal barrier section 21 extends from the support wafer back surface 20b toward the support wafer bonding surface 20a. According to this configuration, the flatness of the support wafer bonding surface 20a can be maintained.

The thermal barrier section 21 includes a groove 23 having an opening 23a on the back surface 20b of the support wafer, and a molding material 24 filled in the groove 23. According to this configuration, it is possible to enhance the heat shielding effect of the thermal barrier section 21 and to suppress a decrease in the rigidity of the support wafer 20.

<Second embodiment>
The method for manufacturing a semiconductor component according to the second embodiment differs from the method for manufacturing a semiconductor component according to the first embodiment in the details of the process of mounting the semiconductor chip 30. Hereinafter, different steps will be described in detail, and descriptions of steps similar to those in the first embodiment will be omitted as appropriate.

First, a composite wafer 1 is prepared (steps S1 to S4). These steps S1 to S4 are similar to those in the first embodiment.

Next, the semiconductor chip 30 is mounted (steps S21 to S23). In the first embodiment, after the chip bonding member 41 was provided on the base wafer 10, the semiconductor chip 30 was placed on the base wafer 10. In the second embodiment, first, the chip bonding member 41 is provided on the semiconductor chip 30. Then, the semiconductor chip 30 provided with the chip bonding member 41 is placed on the base wafer 10.

More specifically, first, the chip bonding member 41 is provided on the chip bonding surface 31b (step S21: FIG. 12(a)). Through this step S21, the semiconductor chip 30 provided with the chip bonding member 41 is obtained. Next, the semiconductor chips 30 provided with the chip bonding members 41 are sequentially arranged on the base wafer 10 (step S22: FIG. 12(b)). At this time, the semiconductor chip 30 is temporarily bonded to the base wafer 10. Temporary bonding refers to a process of heating the chip bonding member 41 to a temperature higher than the softening start temperature and lower than the hardening start temperature. Step S22 is repeatedly executed until all the scheduled placement of semiconductor chips 30 is completed.

Subsequently, the semiconductor chips 30 are sequentially bonded (step S23: FIG. 13). In this step S23, the temperature of the bonding tool 104b is set higher than the curing start temperature and higher than the melting temperature. For example, when bonding semiconductor chips 30, there is another semiconductor chip 30 adjacent to the semiconductor chip 30 being bonded. That is, when bonding the semiconductor chips 30, the uncured chip bonding member 41 is present in the adjacent placement area P. However, since the composite wafer 1 includes the thermal barrier section 21, the influence of heat on the chip bonding member 41 existing in the adjacent arrangement region P is suppressed. That is, when the semiconductor chips 30 are being bonded, unintended thermal hardening of the chip bonding member 41 in the adjacent semiconductor chip 30 is suppressed.

When the bonding work of all the semiconductor chips 30 is completed, a step of cutting out the semiconductor component 90 is performed (steps S9 to S11). These steps S9 to S11 are similar to those in the first embodiment.

The method for manufacturing the semiconductor component 90 of the second embodiment can also provide the same effects as the first embodiment. In other words, the composite wafer 1 can be effectively applied when another chip bonding member 41 is present in the arrangement region P adjacent to the processing target when performing a heat curing process on the chip bonding member 41.

<Third embodiment>
In the semiconductor component manufacturing method according to the third embodiment, the configuration of the semiconductor component 90 manufactured is different from the configuration of the semiconductor component 90 manufactured by the method of the first embodiment. Therefore, a part of the process of mounting the semiconductor chip 30 in the third embodiment is different from the process of mounting the semiconductor chip 30 of the first embodiment. Hereinafter, different steps will be described in detail, and descriptions of steps similar to those in the first embodiment will be omitted as appropriate.

First, a composite wafer 1 is prepared (steps S1 to S4). These steps S1 to S4 are similar to those in the first embodiment.

Next, the semiconductor chip 30 is mounted (steps S31 and S32). The semiconductor component 90 manufactured by the method of the third embodiment is a chip stack in which a plurality of semiconductor chips 30 are stacked. That is, in the third embodiment, a so-called collective bonding method is adopted.

First, a plurality of semiconductor chips 30 are stacked in a certain placement area P (step S31: see FIG. 14(a)). As shown in FIG. 14A, first, the first semiconductor chip 30 is temporarily bonded to the placement area P. Next, the second semiconductor chip 30 is temporarily bonded onto the first semiconductor chip 30. Then, as shown in FIG. 14(b), the third semiconductor chip 30 is temporarily bonded onto the second semiconductor chip 30. As a result, as shown in FIG. 15(a), a temporarily laminated chip 50 in which a plurality of semiconductor chips 30 are temporarily bonded is obtained. This step S31 is performed for each placement area P.

Next, main bonding is performed (step S32: FIG. 15(b)). In this step S32, the temperature of the bonding tool 104b is set higher than the curing start temperature and higher than the melting temperature.

When the bonding work of all the semiconductor chips 30 is completed, a step of cutting out the semiconductor component 90 is performed (steps S9 to S11). These steps S9 to S11 are similar to those in the first embodiment.

Although the method for manufacturing semiconductor components has been described above, the method for manufacturing semiconductor components is not limited to the above embodiments and may be implemented in various forms. For example, the thermal barrier portion 21 may be a gap formed only by the groove 23.

DESCRIPTION OF SYMBOLS 1... Composite wafer, 10... Base wafer, 10b... Base wafer bonding surface, 20... Support wafer, 20a... Support wafer bonding surface, 20b... Support wafer back surface, 21... Thermal barrier part, 23... Groove, 23a... Opening, 24 ...Mold material, 30...Semiconductor chip, 31b...Chip bonding surface, 41...Chip bonding member, 90...Semiconductor component.

Claims (10)

A composite wafer comprising a base wafer including a plurality of arrangement areas each corresponding to a bonding surface of a semiconductor chip, and a support wafer removably bonded to the base wafer, and the thickness of the support wafer is equal to or smaller than the base wafer. preparing the composite wafer, the support wafer including a thermal barrier portion that is larger than the thickness of the wafer and is formed to surround each of the placement regions when viewed in plan;
A method for manufacturing a semiconductor component, comprising the step of mounting the semiconductor chip in the placement area using a thermosetting chip bonding member. The support wafer has a support wafer bonding surface to which the base wafer is removably bonded, and a support wafer back surface opposite to the support wafer bonding surface,
The method for manufacturing a semiconductor component according to claim 1, wherein the thermal barrier portion extends from the back surface of the support wafer toward the bonding surface of the support wafer. 3. The method of manufacturing a semiconductor component according to claim 2, wherein the thermal barrier section is configured by a groove having an opening on the back surface of the support wafer, and a molding material filled in the groove. 3. The method of manufacturing a semiconductor component according to claim 2, wherein the thermal barrier portion is a gap formed by a groove having an opening on the back surface of the support wafer. 5. The step of mounting the semiconductor chip includes the step of arranging the chip bonding member on a base wafer bonding surface of the base wafer on which the plurality of placement regions are set. A method for manufacturing semiconductor components. The step of mounting the semiconductor chip includes:
arranging the chip bonding member;
5. After placing the semiconductor chip on the chip bonding member, applying heat to the chip bonding member via the semiconductor chip while pressing the semiconductor chip toward the composite wafer. A method for manufacturing a semiconductor component as described in . The step of mounting the semiconductor chip includes:
providing the chip bonding member on the chip bonding surface of the semiconductor chip facing the base wafer bonding surface;
The step of arranging the chip bonding member is a step of placing the semiconductor chip provided with the chip bonding member in the placement area of the base wafer bonding surface;
The semiconductor component according to claim 5, comprising the step of applying heat to the chip bonding member via the semiconductor chip while pressing the semiconductor chip provided with the chip bonding member toward the composite wafer. Production method. 8. The method for manufacturing a semiconductor component according to claim 7, wherein in the step of placing the semiconductor chip, one semiconductor chip provided with the chip bonding member is placed in one placement area. 8. The method for manufacturing a semiconductor component according to claim 7, wherein in the step of mounting the semiconductor chip, a plurality of the semiconductor chips each provided with the chip bonding member are stacked in one arrangement region. a base wafer including a plurality of placement areas each corresponding to a bonding surface of a semiconductor chip;
a support wafer detachably bonded to the base wafer,
The thickness of the support wafer is greater than the thickness of the base wafer,
The support wafer is a composite wafer including a thermal barrier section formed so as to surround each of the arrangement regions in plan view.

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