JP2021114523A - Manufacturing method for semiconductor component and composite wafer - Google Patents

Abstract

To suppress the decrease in yield.SOLUTION: A manufacturing method for a semiconductor component uses a composite wafer 1 including a base wafer 10 including a plurality of arrangement regions P to which semiconductor chips 30 are bonded, and a support wafer 20 detachably bonded to the base wafer 10. The support wafer 20 is thicker than the base wafer 10. The support wafer 20 includes a thermal barrier wall part 21 formed to surround the arrangement regions P in a plan view. The manufacturing method for a semiconductor component includes steps S1 to S4 of preparing the composite wafer 1, and steps S5 to S8 of mounting the semiconductor chips 30 in the arrangement regions P using a thermosetting chip bonding member 41.SELECTED DRAWING: Figure 5

Description

The present invention relates to a method for manufacturing a semiconductor component and a composite wafer.

In the technical field of manufacturing semiconductor parts, manufacturing technology of semiconductor parts that realizes further high functionality and miniaturization is being studied. For example, Patent Document 1 discloses a technique for manufacturing a semiconductor component in which a plurality of semiconductor chips are laminated. The semiconductor chips are joined to each other by a thermosetting joining member. However, when the number of laminated semiconductor chips increases, a temperature difference occurs between the joining member located near the heating portion and the joining member located far from the heating portion. Patent Document 1 pays attention to such a problem and discloses a technique capable of appropriately mounting a plurality of semiconductor chips even if the number of layers is large.

JP-A-2018-060952

In the manufacture of semiconductor parts, it is desired to manufacture a plurality of highly functional and miniaturized semiconductor parts from a single semiconductor wafer. Therefore, when arranging the semiconductor chips on the semiconductor wafer, the distance between the semiconductor chips is made as narrow as possible.

When mounting a semiconductor chip on a semiconductor substrate, for example, a load may be provided to the semiconductor chip. It may also provide heat to the semiconductor chip. In such a process, if the distance between the semiconductor chips is narrow, the semiconductor chips arranged around the semiconductor chip to be processed may be affected by the process. Such an influence on a semiconductor chip that is not a processing target may cause a defect of a semiconductor component. Therefore, semiconductor parts that may cause malfunction may be manufactured, and the yield may decrease.

An object of the present invention is to provide a method for manufacturing a semiconductor component and a composite wafer capable of reducing the number of semiconductor components capable of suppressing a decrease in yield.

A method for manufacturing a semiconductor component, which is one embodiment of the present invention, is a composite wafer including a base wafer including a plurality of arrangement regions to which semiconductor chips are bonded and a support wafer detachably bonded to the base wafer. The thickness of the support wafer is larger than the thickness of the base wafer, and the support wafer has a step of preparing a composite wafer including a thermal barrier portion formed so as to surround the arrangement region in a plan view and a thermocurable property. It includes a step of mounting a semiconductor chip in an arrangement region using a chip bonding member.

In this manufacturing method, the base wafer is bonded to the support wafer. The support wafer includes a thermal barrier portion formed so as to surround the arrangement area of the base wafer. Then, when the semiconductor chip is mounted by applying heat to the thermosetting chip bonding member in a certain arrangement region, the thermal barrier portion exerts the influence of the heat on another arrangement region adjacent to the one arrangement region. Suppress. As a result, the occurrence of unintended thermosetting of the chip bonding member is suppressed, so that each semiconductor chip can be mounted in a desired manner. Therefore, the decrease in yield can be suppressed.

In one form, the support wafer has a support wafer bonding surface to which the base wafer is detachably bonded and a support wafer back surface opposite to the support wafer bonding surface, and the thermal barrier portion is the support wafer back surface. It may extend from to the support wafer joint surface. According to this configuration, the flatness of the support wafer joint surface can be maintained.

In one form, the thermal barrier portion may be composed of a groove having an opening on the back surface of the support wafer and a molding material filled in the groove. According to this configuration, it is possible to enhance the heat shielding effect exerted by the heat barrier portion and suppress a decrease in the rigidity of the support wafer.

In one form, the thermal barrier may be a void formed by a groove having an opening on the back surface of the support wafer. According to this configuration, a heat shielding effect can be obtained by a simple structure.

In one embodiment, the step of mounting the semiconductor chip may include a step of arranging the chip bonding member on the base wafer bonding surface of the base wafer in which a plurality of arrangement regions are set. According to this step, it is possible to suppress the occurrence of unintended thermosetting of another chip joining member adjacent to the chip joining member on which the thermosetting treatment is performed.

In one form, the steps of mounting the semiconductor chip are the step of arranging the chip bonding member and the process of placing the semiconductor chip on the chip bonding member, and then pressing the semiconductor chip toward the composite wafer while pressing the chip through the semiconductor chip. It may include a step of applying heat to the joining member. According to these steps, the chip joining members can be collectively arranged with respect to the base mounting surface.

In one embodiment, the step of mounting the semiconductor chip is a step of providing a chip bonding member on the chip bonding surface of the semiconductor chip facing the base wafer bonding surface, and a step of arranging the chip bonding member, which is an arrangement area of the base wafer bonding surface. A step of placing a semiconductor chip provided with a chip bonding member on the wafer, and a step of applying heat to the chip bonding member via the semiconductor chip while pressing the semiconductor chip provided with the chip bonding member toward the composite wafer. May include. According to these steps, a chip bonding member can be arranged for each semiconductor chip.

In one form, in the step of mounting the semiconductor chip, one semiconductor chip provided with the chip bonding member may be arranged in one arrangement region. According to this step, a semiconductor component having a simple structure can be manufactured.

In one form, in the step of mounting the semiconductor chips, a plurality of semiconductor chips provided with chip bonding members may be stacked in one arrangement region. According to this step, a laminated semiconductor component can be manufactured.

The composite wafer, which is another embodiment of the present invention, includes a base wafer including a plurality of arrangement regions to which semiconductor chips are bonded and a support wafer that is detachably bonded to the base wafer. Being larger than the thickness of the base wafer, the support wafer includes a thermal barrier formed to surround the placement region in plan view.

The support wafer includes a thermal barrier portion formed so as to surround the arrangement area of the base wafer. Then, when the semiconductor chip is mounted by applying heat to the thermosetting chip bonding member in a certain arrangement region, the thermal barrier portion exerts the influence of the heat on another arrangement region adjacent to the one arrangement region. Suppress. As a result, the occurrence of unintended thermosetting of the chip bonding member is suppressed, so that each semiconductor chip can be mounted in a desired manner. Therefore, it is possible to reduce the number of semiconductor components that may cause malfunction. As a result, a decrease in yield can be suppressed.

According to the present invention, there is provided a method for manufacturing a semiconductor component and a composite wafer capable of suppressing a decrease in yield.

FIG. 1 is a schematic view showing a bonding apparatus used in a method for manufacturing a semiconductor device. FIG. 2 is a perspective view of the composite wafer as viewed from the base wafer side. FIG. 3 is a perspective view of the composite wafer as viewed from the support wafer side. FIG. 4 is an enlarged plan view showing a part of the support wafer of the composite wafer. FIG. 5 is a cross-sectional view taken along the line VV of FIG. 6 (a), 6 (b) and 6 (c) are diagrams showing a step of preparing a composite wafer in the method for manufacturing a semiconductor component of the first embodiment. FIG. 7A is a diagram showing a step of preparing a composite wafer following FIG. 6C. 7 (b) and 7 (c) are diagrams showing a process of mounting a semiconductor chip following FIG. 7 (a). 8 (a), 8 (b) and 8 (c) are diagrams showing a process of mounting a semiconductor chip following FIG. 7 (c). 9 (a) and 9 (b) are diagrams showing a process of separating each semiconductor component. 10 (a), 10 (b), and 10 (c) are diagrams showing a step of separating each semiconductor component following FIG. 9 (b). FIG. 11A is an enlarged perspective view for explaining the action and effect of the composite wafer of the comparative example. FIG. 11B is an enlarged perspective view for explaining the action and effect of the composite wafer of the embodiment. 12 (a) and 12 (b) are diagrams showing a step of mounting a semiconductor chip in the method of manufacturing a semiconductor component of the second embodiment. FIG. 13 is a diagram showing a process of mounting a semiconductor chip following FIG. 12 (b). 14 (a) and 14 (b) are diagrams showing a process of mounting a semiconductor chip in the method for manufacturing a semiconductor component according to the third embodiment. 15 (a) and 15 (b) are diagrams showing a process of mounting a semiconductor chip following FIG. 14 (b).

<First Embodiment>
Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the accompanying drawings. In the description of the drawings, the same elements are designated by the same reference numerals, and duplicate description will be omitted.

<Bonding device>
As shown in FIG. 1, the bonding apparatus 100 mounts a semiconductor chip 30, which is an example of an electronic component, on a composite wafer 1. By this mounting, a semiconductor component 90 (see FIG. 10C) including a part of the composite wafer 1 and the semiconductor chip 30 is obtained. In the following description, the X-axis and the Y-axis orthogonal to each other are oriented parallel to the main surface of the semiconductor chip 30 (or the main surface of any stage). The Z-axis is a direction perpendicular to both the X-axis and the Y-axis.

First, the bonding apparatus 100 will be described. As shown in FIG. 1, the bonding apparatus 100 includes a chip stage 101, an intermediate stage 102, a bonding stage 103, a bonding unit 104, an XY stage 105, and a bonding control unit (hereinafter, simply “control unit 106””. ), And.

A wafer 110 including a plurality of semiconductor chips 30 is temporarily placed on the chip stage 101. The wafer 110 is fixed to the chip stage 101 by a sticking film (not shown).

The semiconductor chip 30 is temporarily placed on the intermediate stage 102. The intermediate stage 102 holds the semiconductor chip 30 detachably by a sticking film (not shown). The intermediate stage 102 is arranged between the chip stage 101 and the bonding stage 103. The intermediate stage 102 is configured to be movable in the X-axis direction and the Y-axis direction by a drive mechanism such as a linear motor (not shown).

The composite wafer 1 is placed on the bonding stage 103. The composite wafer 1 will be described in detail later. The bonding stage 103 holds the composite wafer 1 detachably by a sticking film (not shown). The bonding stage 103 can move the composite wafer 1 in the X-axis direction and / or the Y-axis direction by a drive mechanism (not shown) including a guide rail. Further, the bonding stage 103 may have a heater for heating the composite wafer 1. Further, the bonding stage 103 may have a light source 103a that irradiates the composite wafer 1 with ultraviolet rays.

The bonding unit 104 includes a bonding head 104a, a bonding tool 104b, a Z-axis drive mechanism 104c, and an imaging unit 104d. The bonding head 104a is attached to the XY stage 105 and is movable in the X-axis direction and the Y-axis direction. The bonding tool 104b is attached to the bonding head 104a via the Z-axis drive mechanism 104c. The bonding tool 104b has an air vacuum function and / or an air blow function. With this function, the bonding tool 104b can suck or detach the semiconductor chip 30.

The imaging unit 104d is also attached to the bonding head 104a. That is, when the bonding head 104a is moved by the XY stage 105, the bonding tool 104b and the imaging unit 104d attached to the bonding head 104a also move in the same manner. The imaging unit 104d is separated from the bonding tool 104b by a predetermined distance in the Y-axis direction. The imaging unit 104d images the semiconductor chip 30 mounted on the intermediate stage 102. Further, the imaging unit 104d images the semiconductor chip 30 mounted on the bonding stage 103. The imaging unit 104d does not have to be fixed to the bonding head 104a. The imaging unit 104d may be movable separately from the bonding tool 104b.

<Composite wafer>
Next, the composite wafer 1 will be described in detail. The composite wafer 1 is a composite semiconductor wafer including two semiconductor wafers. Specifically, the composite wafer 1 includes a base wafer 10 and a support wafer 20. The composite wafer 1 may include a wafer formed of a material different from that of the semiconductor wafer. For example, the composite wafer 1 may include a glass wafer.

FIG. 2 is a perspective view of the composite wafer 1 as viewed from the base wafer 10 side. The base wafer 10 is, for example, a thin film wafer made of silicon. The base wafer 10 is fragmented in a later process to form a semiconductor component 90 together with the semiconductor chip 30. The base wafer 10 includes a circuit forming surface 10a to which the semiconductor chip 30 is bonded and a base wafer bonding surface 10b (see FIG. 5) to be bonded to the support wafer 20. A plurality of arrangement regions P arranged two-dimensionally are set on the circuit forming surface 10a. One or a plurality of semiconductor chips 30 are mounted in one arrangement region P. The thickness of the base wafer 10 is, for example, about 100 μm. Therefore, a support wafer 20 is bonded to the base wafer 10 in order to facilitate handling during transportation and the like.

FIG. 3 is a perspective view of the composite wafer 1 as viewed from the support wafer 20 side. The support wafer 20 defines the rigidity of the composite wafer 1. That is, the rigidity of the support wafer 20 is larger than the rigidity of the base wafer 10. This rigidity is provided by the thickness of the support wafer 20. That is, the thickness of the support wafer 20 is larger than the thickness of the base wafer 10. For example, the thickness of the support wafer 20 is about 500 μm. The support wafer 20 may be made of the same material as the base wafer 10. According to this configuration, the coefficient of thermal expansion of the base wafer 10 and the coefficient of thermal expansion of the support wafer 20 are the same. Therefore, the difference between the amount of thermal deformation of the base wafer 10 and the amount of thermal deformation of the support wafer 20 during heat treatment can be eliminated, and damage due to thermal stress can be suppressed from occurring in each wafer. In this embodiment, the support wafer 20 is made of silicon. The material of the support wafer 20 may be different from the material of the base wafer 10. For example, glass may be used as the material of the support wafer 20. The shape of the support wafer 20 is the same as that of the base wafer 10 except that the thickness is different from that of the base wafer 10. That is, when the support wafer 20 and the base wafer 10 are overlapped and viewed in a plan view, their outer shapes match.

The support wafer 20 has a support wafer bonding surface 20a (see FIG. 5) and a support wafer back surface 20b. The base wafer 10 is bonded to the support wafer bonding surface 20a. Unlike the base wafer 10, the support wafer 20 does not form the semiconductor component 90. That is, the support wafer 20 is removed at a certain point in the process of manufacturing the semiconductor component 90 (step S10: see FIG. 9B and the like). Therefore, a joining member whose joining strength can be controlled is used for joining the support wafer 20 and the base wafer 10. For example, a resin material capable of weakening the bonding strength by irradiating with ultraviolet rays is used. In order to perform such light processing, the support wafer 20 transmits light having a predetermined wavelength.

The support wafer 20 has a heat barrier portion 21 inside. The thermal barrier portion 21 includes a plurality of barriers 22 provided in a grid pattern. The barrier 22 inhibits heat transfer in the radial direction of the support wafer 20. The grid formed by the plurality of barriers 22 corresponds to the above-mentioned arrangement region P. That is, one grid corresponds to one arrangement area P. In other words, the heat barrier portion 21 is formed so as to surround the semiconductor chip 30 in a plan view of the composite wafer 1.

FIG. 4 is an enlarged plan view showing a peripheral portion of the back surface 20b of the support wafer. As shown in FIG. 4, the end of each barrier 22 does not reach the outer peripheral edge 20e of the support wafer 20. Therefore, a wallless region 25 in which the barrier 22 is not formed is formed on the outer periphery of the support wafer 20. That is, the support wafer 20 includes a walled region 26 in which a plurality of barriers 22 are formed, and a wallless region 25 in which the barriers 22 are not formed. The wallless region 25 is formed in a ring shape so as to surround the walled region 26. According to such a wallless region 25, the degree of influence of the formation of the barrier 22 on the rigidity of the support wafer 20 can be reduced. In other words, it is possible to suppress a decrease in the rigidity of the support wafer 20.

The barrier 22 is formed in a region corresponding to a gap between semiconductor chips 30 adjacent to each other. That is, the semiconductor chip 30 is not arranged on the barrier 22. The width of the barrier 22 may be larger or smaller than the distance between the semiconductor chips 30. Further, the width of the barrier 22 may be substantially the same as the distance between the semiconductor chips 30.

The barrier 22 includes a portion that does not completely surround the outermost arrangement area P. For example, the arrangement area P1 is surrounded on all four sides by a barrier 22. In other words, the barriers 22 surrounding the arrangement area P1 are connected to each other. On the other hand, the arrangement region P2 also has a barrier 22 formed around it. However, in the arrangement region P2, a barrier 22 is formed in the vicinity of a part of the sides. That is, "to surround the arrangement area" in the present embodiment means not only when the barriers 22 are formed in the vicinity of all four sides as in the arrangement area P1, but also when the barriers 22 are formed in the vicinity of all four sides as in the arrangement area P2. This includes the case where the barrier 22 is formed in the vicinity of some of the sides. The barrier 22 surrounding the placement area P2 includes a non-connected portion 27 that is not connected to each other. Such a non-connecting portion 27 is formed by a protrusion 28 of the barrier 22.

According to the protrusion 28, the heat path from one arrangement region P2 to the other arrangement region P2 can be lengthened. Therefore, it is possible to suppress the heat applied to one semiconductor chip 30 from being transferred to the other semiconductor chip 30.

Further, the non-connecting portion 27 is formed on the side where the semiconductor chip 30 does not exist next to the non-connecting portion 27. According to such a non-connecting portion 27, the formation of the groove 23 which causes a decrease in rigidity is avoided in the region near the outer peripheral edge 20e of the support wafer 20. Therefore, it is possible to suppress a decrease in the rigidity of the support wafer 20.

As shown in FIG. 5, the barrier 22 is composed of a groove 23 and a molding material 24. The groove 23 includes an opening 23a provided on the back surface 20b of the support wafer and a bottom surface 23b formed on the joint surface 20a side of the support wafer. That is, the groove 23 does not reach the support wafer bonding surface 20a. The depth of the groove 23 is defined by the distance from the back surface 20b of the support wafer to the bottom surface 23b. In the present embodiment, the depth of the groove 23 is deeper than about half the thickness of the support wafer 20. The depth of the groove 23 may be about half the thickness of the support wafer 20 or may be shallow.

The groove 23 is filled with a molding material 24 such as resin. The molding material 24 compensates for the rigidity of the support wafer 20 that decreases with the formation of the groove 23. Further, the molding material 24 constitutes a thermal resistance portion in the diameter direction of the support wafer 20. Therefore, the thermal conductivity of the molding material 24 is significantly lower than the thermal conductivity of the support wafer 20. Further, the coefficient of thermal expansion of the molding material 24 is preferably close to the coefficient of thermal expansion of the support wafer 20. By using such a molding material 24, it is possible to suppress the thermal stress caused by the difference in the amount of thermal deformation between the molding material 24 and the support wafer 20.

<Manufacturing method of semiconductor parts>
Next, a method of manufacturing the semiconductor component 90 using the composite wafer 1 will be described with reference to FIGS. 6 to 10.

<Process of preparing composite wafer>
The composite wafer 1 is prepared (steps S1 to S4). First, the wafer 20S is prepared (step S1: FIG. 6A). Then, a notch (groove 23) is formed in the back surface 20b of the support wafer by using a dicing cutter 301 or the like (step S2: FIG. 6B). Next, the molding material 24 is poured into the groove 23 (step S3: FIG. 6C). The support wafer 20 including the heat barrier portion 21 is obtained by the above steps S1 to S3. Next, the wafer bonding member 42 is applied to the support wafer bonding surface 20a. Then, the base wafer 10 is joined to the support wafer 20 (step S4: FIG. 7A). The composite wafer 1 is obtained by the above steps S1 to S4.

<Process for mounting semiconductor chips>
Next, the semiconductor chip is mounted (steps S5 to S8). First, the composite wafer 1 is arranged on the bonding stage 103 (step S5: FIG. 7B). Subsequently, the film-shaped chip bonding member 41 is arranged on the circuit forming surface 10a of the base wafer 10 (step S6: FIG. 7C). The chip bonding member 41 is, for example, a non-conductive film material called NCF (Non Conductive Film). The chip bonding member 41 is sandwiched between the semiconductor chip 30 and the base wafer 10 and then cured by heat.

The chip joining member 41 has a softening start temperature and a curing start temperature. The curing start temperature is higher than the softening start temperature. When the temperature of the chip bonding member 41 is lower than the softening start temperature, the chip bonding member 41 does not exhibit fluidity and maintains, for example, a film-like shape. When the temperature of the chip joining member 41 is higher than the softening start temperature and lower than the curing start temperature, the chip joining member 41 exhibits fluidity. In this state, the chip joining member 41 is easily deformed by an external force. Therefore, it is possible to fill the gap between the semiconductor chip 30 and the base wafer 10 without any gap. When the temperature of the chip joining member 41 is higher than the curing start temperature, the chip joining member 41 is gradually cured.

Subsequently, the semiconductor chips 30 are joined (steps S7 and S8). The bonding apparatus 100 picks up the semiconductor chip 30 from the intermediate stage 102 by the bonding tool 104b. Then, the bonding device 100 places the semiconductor chip 30 on the predetermined arrangement region P (step S7: FIG. 8A). The bonding apparatus 100 continuously performs the next process (step S8) without separating the semiconductor chip 30 from the bonding tool 104b.

As shown in FIG. 8B, the bonding apparatus 100 raises the temperature of the bonding tool 104b. When the temperature of the chip bonding member 41 becomes higher than the softening start point as the temperature of the bonding tool 104b rises, the chip bonding member 41 exhibits fluidity. Then, the bonding device 100 presses the bonding tool 104b against the composite wafer 1 side. As a result, the chip bonding member 41 exhibiting fluidity fills the gap between the semiconductor chip 30 and the base wafer 10 without gaps. For example, the load applied to the semiconductor chip 30 by the bonding tool 104b is set so that the bump 33 pushes away the softened chip bonding member 41 so that the bump 33 comes into contact with the electrode terminal 11 and the bump 33 is not significantly deformed.

Further, when the temperature of the bonding tool 104b rises and the temperature of the chip bonding member 41 becomes higher than the curing start temperature, the chip bonding member 41 exhibiting fluidity starts curing. Further, when the temperature of the bonding tool 104b rises and the temperature of the bump 33 becomes higher than the melting temperature, the bump 33 melts and comes into close contact with the electrode terminal 11. As a result, the bump 33 is electrically joined to the electrode terminal 11. After that, the bonding tool 104b is separated from the semiconductor chip 30.

Here, the heat provided by the bonding head 104a is transmitted inside the composite wafer 1 and tends to diffuse to the surroundings. In this case, in the radial direction of the composite wafer 1, heat diffusion is suppressed by the heat barrier portion 21. That is, the heat does not easily move to the arrangement region P adjacent to the arrangement region P where the semiconductor chip 30 is bonded. As a result, the temperature rise of the chip joining member 41 in the adjacent arrangement region P is suppressed, so that the occurrence of unintended thermosetting of the chip joining member 41 is suppressed. This suppressing effect is particularly effective when the temperature of the bonding tool 104b is higher than the curing start temperature of the chip bonding member 41, or when the temperature of the bonding tool 104b is higher than the melting temperature of the bump 33. The action of the heat barrier portion 21 will be described in detail later.

Then, the semiconductor chips 30 are sequentially joined to the arrangement region P. As a result, a plurality of semiconductor chips 30 are mechanically and electrically bonded to the base wafer 10 (see FIG. 8C).

Subsequently, each semiconductor component 90 is separated (steps S9 to S11). First, the embedded region 302 is formed (step S9: FIG. 9A). In this step S9, the embedded region 302 is formed so as to cover the circuit forming surface 10a of the base wafer 10 and the semiconductor chip 30. The embedded region 302 may be made of, for example, a resin material. Subsequently, the base wafer 10 is removed from the support wafer 20. In this step S10, ultraviolet rays L are irradiated from the back surface 20b of the support wafer 20 of the support wafer 20 (step S10: FIG. 9B). As a result, the bonding strength of the wafer bonding member 42 is reduced, so that the base wafer 10 can be removed from the support wafer 20 (see FIG. 10A). Subsequently, the semiconductor component 90 is separated by using a dicing cutter 301 or the like (step S11: FIG. 10B). As a result, a plurality of semiconductor parts 90 that have been separated from each other can be obtained (see FIG. 10C).

<Effect>
As a method for manufacturing a semiconductor component, a composite wafer 1 including a base wafer 10 including a plurality of arrangement regions P to which a semiconductor chip 30 is bonded and a support wafer 20 detachably bonded to the base wafer 10 are used. The thickness of the support wafer 20 is larger than the thickness of the base wafer 10. The support wafer 20 includes a thermal barrier portion 21 formed so as to surround the arrangement region P in a plan view. The method for manufacturing the semiconductor component 90 includes a step of preparing the composite wafer 1 (steps S1 to S4) and a step of mounting the semiconductor chip 30 in the arrangement region P using the thermosetting chip bonding member 41 (step S5). ~ S8) and.

In this manufacturing method, the base wafer 10 is bonded to the support wafer 20. The support wafer 20 includes a thermal barrier portion 21 formed so as to surround the arrangement region P of the base wafer 10. Then, when the semiconductor chip 30 is mounted by applying heat to the thermosetting chip bonding member 41 in a certain arrangement region P, the heat barrier portion 21 is placed in another arrangement region P adjacent to the one arrangement region P. Suppress the effect of the heat.

The action of the heat barrier portion 21 will be described in more detail. FIG. 11A is an enlarged perspective view showing a part of the composite wafer 1E of the comparative example. The composite wafer 1E of the comparative example does not have the thermal barrier portion 21. It is assumed that a certain region R1 is a heat input surface that receives heat from the bonding tool 104b. In this case, the heat tends to diffuse inside the base wafer 10 and the support wafer 20E. For example, pay attention to the direction from a certain region R1 toward an adjacent region R2. The transfer of heat H is represented by the equation (1) when the amount of heat flowing per unit area (q: heat flux) is defined.
q = Q / A ... (1)
q: Heat flux Q: Heat quantity A: Area

Further, Fourier's law regarding heat transfer is expressed by Eq. (2).
q = −λ × dT / dx… (2)
λ: Thermal conductivity dT / dx: Thermal gradient

According to the equations (1) and (2), the equation (3) is obtained.
Q = −λ × dT / dx × A ... (3)
That is, the amount of heat transferred (Q) is proportional to the area and the temperature gradient.

Then, when the heat H is transferred from the certain region R1 to the adjacent region R2, if the area contributing to the heat transfer is limited, the amount of heat (Q) to be transferred is also limited. In the structure shown in FIG. 11A, for example, a surface N1 located between a certain region R1 and an adjacent region R2 is defined. This surface N1 includes a base wafer 10 and a support wafer 20. Assuming that the base wafer 10 and the support wafer 20 are made of the same material (silicon), it can be defined that the entire surface N1 contributes to heat transfer. In such a configuration, the amount of heat (Q) transferred from a certain region R1 to an adjacent region R2 becomes large. Then, unintended thermosetting of the chip joining member 41 may occur in a part of the adjacent region R2. When the original bonding treatment is performed on the chip bonding member 41 that has been partially thermoset, the intended bonding state may not be formed. For example, the semiconductor chip 30 may be tilted, resulting in poor contact between the bump 33 and the electrode terminal 11.

On the other hand, FIG. 11B is an enlarged perspective view showing a part of the composite wafer 1 of the embodiment. In the structure shown in FIG. 11B, a surface N2 located between a certain region R1 and an adjacent region R2 is defined. This surface N2 includes a barrier 22 in addition to the base wafer 10 and the support wafer 20. As described above, assuming that the base wafer 10 and the support wafer 20 are made of the same material (silicon), it can be defined that a partial region N2a of the surface N2 contributes to heat transfer. On the other hand, since the barrier 22 has a higher thermal resistance than the base wafer 10 and the support wafer 20, it can be considered that the barrier 22 does not substantially contribute to heat transfer. Then, the area contributing to the heat transfer in the composite wafer 1 of the embodiment becomes smaller than that of the composite wafer 1 of the comparative example due to the barrier 22. Therefore, as the area decreases, the amount of heat (Q) transferred also decreases.

As a result, it is possible to suppress the degree to which the temperature of the adjacent region R2 rises due to the heating in the certain region R1. Then, since the occurrence of unintended thermosetting of the chip joining member 41 is suppressed, each semiconductor chip 30 can be mounted in a desired manner. Therefore, the number of semiconductor components 90 that may cause malfunction can be reduced. As a result, a decrease in yield can be suppressed.

That is, the heat barrier portion 21 makes it difficult for heat to move from the arrangement region P where heat is provided. Then, the heat tends to stay in the area surrounded by the barrier 22. As a result, the semiconductor chip 30 and the chip bonding member 41 can be suitably heated. Specifically, the temperature difference that can occur in the semiconductor chip 30 and the chip bonding member 41 can be reduced. This effect is particularly effective when a plurality of semiconductor chips 30 manufactured in the third embodiment described later are laminated.

The support wafer 20 has a support wafer bonding surface 20a to which the base wafer 10 is detachably bonded, and a support wafer back surface 20b opposite to the support wafer bonding surface 20a. The thermal barrier portion 21 extends from the back surface 20b of the support wafer toward the bonding surface 20a of the support wafer. According to this configuration, the flatness of the support wafer bonding surface 20a can be maintained.

The heat barrier portion 21 is composed of a groove 23 having an opening 23a in the back surface 20b of the support wafer and a molding material 24 filled in the groove 23. According to this configuration, it is possible to enhance the heat shielding effect exerted by the heat barrier portion 21 and suppress a decrease in the rigidity of the support wafer 20.

<Second Embodiment>
The details of the process of mounting the semiconductor chip 30 are different from the semiconductor component manufacturing method according to the first embodiment in the semiconductor component manufacturing method according to the second embodiment. Hereinafter, the different steps will be described in detail, and the same steps as in the first embodiment will be omitted as appropriate.

First, the composite wafer 1 is prepared (steps S1 to S4). The steps S1 to S4 are the same as those in the first embodiment.

Next, the semiconductor chip 30 is mounted (steps S21 to S23). In the first embodiment, after the chip bonding member 41 is provided on the base wafer 10, the semiconductor chip 30 is arranged on the base wafer 10. In the second embodiment, first, the chip joining member 41 is provided on the semiconductor chip 30. Then, the semiconductor chip 30 provided with the chip bonding member 41 is placed on the base wafer 10.

More specifically, first, the chip bonding member 41 is provided on the chip bonding surface 31b (step S21: FIG. 12A). By this step S21, the semiconductor chip 30 provided with the chip bonding member 41 is obtained. Next, the semiconductor chip 30 provided with the chip bonding member 41 is sequentially arranged on the base wafer 10 (step S22: FIG. 12B). At this time, the semiconductor chip 30 is temporarily bonded to the base wafer 10. Temporary bonding refers to a process of heating the temperature of the chip bonding member 41 to a temperature higher than the softening start temperature and lower than the curing start temperature. Step S22 is repeatedly executed until all the planned arrangements of the semiconductor chips 30 are completed.

Subsequently, the semiconductor chips 30 are sequentially joined (step S23: FIG. 13). In this step S23, the temperature of the bonding tool 104b is set higher than the curing start temperature and higher than the melting temperature. For example, when joining a semiconductor chip 30, there is another semiconductor chip 30 adjacent to the semiconductor chip 30 being joined. That is, when the semiconductor chips 30 are joined, the uncured chip joining member 41 exists in the adjacent arrangement region P. However, since the composite wafer 1 includes the thermal barrier portion 21, the influence of heat on the chip bonding member 41 existing in the adjacent arrangement region P is suppressed. That is, when the semiconductor chip 30 is bonded, the occurrence of unintended thermosetting of the chip bonding member 41 in the adjacent semiconductor chip 30 is suppressed.

Then, when the joining work of all the semiconductor chips 30 is completed, a step of cutting out the semiconductor component 90 is performed (steps S9 to S11). These steps S9 to S11 are the same as those in the first embodiment.

The same effect as that of the first embodiment can be obtained by the method of manufacturing the semiconductor component 90 of the second embodiment. That is, the composite wafer 1 can be effectively applied when another chip bonding member 41 is present in the arrangement region P adjacent to the processing target when the chip bonding member 41 is thermosetting.

<Third Embodiment>
In the method for manufacturing a semiconductor component according to the third embodiment, the configuration of the semiconductor component 90 to be manufactured is different from the configuration of the semiconductor component 90 manufactured by the method of the first embodiment. Therefore, a part of the step of mounting the semiconductor chip 30 in the third embodiment is different from the step of mounting the semiconductor chip 30 of the first embodiment. Hereinafter, the different steps will be described in detail, and the same steps as in the first embodiment will be omitted as appropriate.

First, the composite wafer 1 is prepared (steps S1 to S4). The steps S1 to S4 are the same as those in the first embodiment.

Next, the semiconductor chip 30 is mounted (steps S31 and S32). The semiconductor component 90 manufactured by the method of the third embodiment is a chip laminate in which a plurality of semiconductor chips 30 are laminated. That is, in the third embodiment, the so-called collective bonding method is adopted.

First, a plurality of semiconductor chips 30 are laminated on a certain arrangement region P (step S31: see FIG. 14A). As shown in FIG. 14A, first, the first semiconductor chip 30 is temporarily joined to the arrangement region P. Next, the second semiconductor chip 30 is temporarily bonded onto the first semiconductor chip 30. Then, as shown in FIG. 14B, the third semiconductor chip 30 is temporarily bonded onto the second semiconductor chip 30. As a result, as shown in FIG. 15A, a temporary laminated chip 50 in which a plurality of semiconductor chips 30 are temporarily bonded is obtained. This step S31 is carried out for each placement region P.

Next, the main joining is performed (step S32: FIG. 15 (b)). In this step S32, the temperature of the bonding tool 104b is set higher than the curing start temperature and higher than the melting temperature.

Then, when the joining work of all the semiconductor chips 30 is completed, a step of cutting out the semiconductor component 90 is performed (steps S9 to S11). These steps S9 to S11 are the same as those in the first embodiment.

Although the method for manufacturing the semiconductor component has been described above, the method for manufacturing the semiconductor component is not limited to the above embodiment and may be implemented in various forms. For example, the heat barrier portion 21 may be a void formed only by the groove 23.

1 ... Composite wafer, 10 ... Base wafer, 10b ... Base wafer bonding surface, 20 ... Support wafer, 20a ... Support wafer bonding surface, 20b ... Support wafer back surface, 21 ... Thermal barrier, 23 ... Groove, 23a ... Opening, 24 ... Mold material, 30 ... Semiconductor chip, 31b ... Chip bonding surface, 41 ... Chip bonding member, 90 ... Semiconductor component.

Claims (10)

It is a composite wafer including a base wafer including a plurality of arrangement regions to which semiconductor chips are bonded and a support wafer detachably bonded to the base wafer, and the thickness of the support wafer is the thickness of the base wafer. The step of preparing the composite wafer, wherein the support wafer is larger than, and includes a thermal barrier portion formed so as to surround the arrangement region in a plan view.
A method for manufacturing a semiconductor component, comprising a step of mounting the semiconductor chip in the arrangement region using a thermosetting chip joining member. The support wafer has a support wafer bonding surface to which the base wafer is detachably bonded, and a support wafer back surface opposite to the support wafer bonding surface.
The method for manufacturing a semiconductor component according to claim 1, wherein the thermal barrier portion extends from the back surface of the support wafer toward the bonding surface of the support wafer. The method for manufacturing a semiconductor component according to claim 2, wherein the heat barrier portion is composed of a groove having an opening on the back surface of the support wafer and a molding material filled in the groove. The method for manufacturing a semiconductor component according to claim 2, wherein the heat barrier portion is a gap formed by a groove having an opening on the back surface of the support wafer. The step of mounting the semiconductor chip according to any one of claims 1 to 4, wherein the step of mounting the chip bonding member includes a step of arranging the chip bonding member on the base wafer bonding surface of the base wafer in which the plurality of arrangement regions are set. Manufacturing method of semiconductor parts. The process of mounting the semiconductor chip is
The process of arranging the chip joining member and
5. A step of mounting the semiconductor chip on the chip bonding member and then applying heat to the chip bonding member via the semiconductor chip while pressing the semiconductor chip toward the composite wafer, claim 5 The method for manufacturing a semiconductor component according to. The process of mounting the semiconductor chip is
A step of providing the chip bonding member on the chip bonding surface of the semiconductor chip facing the base wafer bonding surface, and
As a step of arranging the chip bonding member, a step of placing the semiconductor chip provided with the chip bonding member in the arrangement region of the base wafer bonding surface and a step of placing the semiconductor chip.
The semiconductor component according to claim 5, further comprising a step of applying heat to the chip bonding member via the semiconductor chip while pressing the semiconductor chip provided with the chip bonding member toward the composite wafer. Production method. The method for manufacturing a semiconductor component according to claim 7, wherein in the step of mounting the semiconductor chip, one semiconductor chip provided with the chip bonding member is arranged in one arrangement region. The method for manufacturing a semiconductor component according to claim 7, wherein in the step of mounting the semiconductor chip, a plurality of the semiconductor chips provided with the chip bonding member are stacked on one of the arrangement regions. A base wafer containing multiple placement regions to which semiconductor chips are bonded, and
A support wafer that is detachably joined to the base wafer is provided.
The thickness of the support wafer is larger than the thickness of the base wafer.
The support wafer is a composite wafer including a heat barrier portion formed so as to surround the arrangement region in a plan view.

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