JP7419453B2 - semiconductor equipment - Google Patents

Description

One embodiment of the present invention relates to a semiconductor device.

Further, one embodiment of the present invention relates to a product, a method, or a manufacturing method. Alternatively, one aspect of the present invention relates to a process, machine, manufacture, or composition of matter. One embodiment of the present invention relates to a method for driving the same or a method for manufacturing the same.

Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Storage devices, display devices, electro-optical devices, power storage devices, semiconductor circuits, and electronic equipment may include semiconductor devices.

Although silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors (OS) are attracting attention as other materials. As oxide semiconductors, not only oxides of single-component metals such as indium oxide and zinc oxide, but also oxides of multi-component metals are known. Among multi-element metal oxides, research on In--Ga--Zn oxide (hereinafter also referred to as IGZO) has been actively conducted.

Through research on IGZO, a CAAC (c-axis aligned crystalline) structure and an nc (nanocrystalline) structure, which are neither single crystal nor amorphous, have been found in oxide semiconductors (see Non-Patent Documents 1 to 3). ). Non-Patent Document 1 and Non-Patent Document 2 also disclose a technique for manufacturing a transistor using an oxide semiconductor having a CAAC structure. Furthermore, Non-Patent Document 4 and Non-Patent Document 5 show that even oxide semiconductors with lower crystallinity than the CAAC structure and the nc structure have minute crystals.

Furthermore, transistors using IGZO as an active layer have an extremely low off-state current (see Non-Patent Document 6), and LSIs and displays that utilize this property have been reported (see Non-Patent Documents 7 and 8). ).

Further, various semiconductor devices have been proposed that use a transistor (hereinafter also referred to as an "OS transistor") having an oxide semiconductor in a channel formation region.

Patent Document 1 discloses an example in which an OS transistor is used in a DRAM (Dynamic Random Access Memory). Since the OS transistor has a very small leakage current (off current) in the off state, a DRAM with a long refresh period and low power consumption can be manufactured.

Further, Patent Document 2 discloses a nonvolatile memory using an OS transistor. Unlike flash memories, these nonvolatile memories have no limit to the number of times they can be rewritten, can easily operate at high speed, and consume less power.

In a memory using these OS transistors, by increasing the threshold voltage of the OS transistor, the off-state current can be reduced, and the data retention characteristics of the memory can be improved. Patent Document 2 discloses an example in which an OS transistor is provided with a second gate to control the threshold voltage of the OS transistor and reduce the off-state current.

In order for the memory to retain data for a long period of time, it is necessary to continue applying a certain negative potential to the second gate of the OS transistor. Patent Document 2 and Patent Document 3 disclose configuration examples of a circuit for driving the second gate of an OS transistor.

Japanese Patent Application Publication No. 2013-168631 JP2012-069932A Japanese Patent Application Publication No. 2012-146965

S. Yamazaki et al. , “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, p. 183-186 S. Yamazaki et al. , “Japanese Journal of Applied Physics”, 2014, volume 53, Number 4S, p. 04ED18-1-04ED18-10 S. Ito et al. , “The Proceedings of AM-FPD’13 Digest of Technical Papers”, 2013, p. 151-154 S. Yamazaki et al. , “ECS Journal of Solid State Science and Technology”, 2014, volume 3, issue 9, p. Q3012-Q3022 S. Yamazaki, “ECS Transactions”, 2014, volume 64, issue 10, p. 155-164 K. Kato et al. , “Japanese Journal of Applied Physics”, 2012, volume 51, p. 021201-1-021201-7 S. Matsuda et al. , “2015 Symposium on VLSI Technology Digest of Technical Papers”, 2015, p. T216-T217 S. Amano et al. , “SID Symposium Digest of Technical Papers”, 2010, volume 41, issue 1, p. 626-629

An object of one embodiment of the present invention is to provide a semiconductor device with high on-current. Another object of one embodiment of the present invention is to provide a semiconductor device that operates at high speed. Another object of one embodiment of the present invention is to provide a semiconductor device that can retain data for a long period of time. Another object of one embodiment of the present invention is to provide a semiconductor device with reduced power consumption. An object of one embodiment of the present invention is to provide a novel semiconductor device.

Note that the description of multiple assignments does not preclude the existence of each assignment. Note that one embodiment of the present invention does not need to solve all of these problems. In addition, problems other than those listed above will naturally become apparent from the description of the specification, drawings, claims, etc., and these problems can also be problems of one embodiment of the present invention.

One aspect of the present invention is a semiconductor device including a first circuit, a second circuit, a third circuit, a fourth circuit, and an output terminal, wherein the first circuit applies a voltage to the second circuit. The second circuit has a function of supplying the first voltage to the output terminal and a function of holding the voltage of the output terminal, and the third circuit has a function of acquiring temperature information. , a function of supplying a digital signal according to temperature information to a fourth circuit, the fourth circuit has a function of outputting a second voltage according to the digital signal, and the voltage of the output terminal is This semiconductor device is characterized in that the voltage is the sum of a first voltage and a second voltage.

Preferably, the fourth circuit includes a plurality of capacitive elements. Each of the plurality of capacitive elements is electrically connected to an output terminal. Further, it is preferable that the plurality of capacitive elements have different capacitance values.

According to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. Further, according to one embodiment of the present invention, a semiconductor device that operates at high speed can be provided. Further, according to one embodiment of the present invention, a semiconductor device that can retain data for a long period of time can be provided. Further, according to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. Further, according to one embodiment of the present invention, a novel semiconductor device can be provided.

Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not need to have all of these effects. Note that effects other than these will become obvious from the description, drawings, claims, etc., and effects other than these can be extracted from the description, drawings, claims, etc. It is.

FIG. 2 is a diagram illustrating a configuration example of a semiconductor device. FIG. 3 is a diagram illustrating electrical characteristics of a transistor. FIG. 2 is a diagram illustrating a configuration example of a voltage generation circuit. FIG. 2 is a diagram illustrating a configuration example of a voltage holding circuit. FIG. 2 is a diagram illustrating a configuration example of a temperature detection circuit. FIG. 4 is a diagram illustrating an example of a change in voltage VBias with respect to temperature change. 5 is a timing chart illustrating an example of the operation of a semiconductor device. FIG. 2 is a diagram illustrating a configuration example of a storage device. FIG. 3 is a diagram illustrating a configuration example of a cell array. FIG. 3 is a circuit diagram illustrating a configuration example of a memory cell. FIG. 2 is a diagram illustrating a configuration example of a storage device. FIG. 2 is a diagram illustrating a configuration example of a storage device. FIG. 3 is a diagram illustrating a configuration example of a transistor. FIG. 3 is a diagram illustrating a configuration example of a transistor. FIG. 3 is a diagram illustrating a configuration example of a transistor. FIG. 2 is a diagram illustrating an example of an electronic component. FIG. 1 is a diagram illustrating an example of an electronic device. FIG. 3 is a diagram illustrating an application example of a storage device.

Embodiments of the present invention will be described in detail using the drawings. However, those skilled in the art will easily understand that the present invention is not limited to the following description, and that the form and details thereof can be changed in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the contents of the embodiments and examples shown below.

In the configuration of the invention described below, the same parts or parts having similar functions are designated by the same reference numerals in different drawings, and repeated explanation thereof will be omitted. Furthermore, when referring to similar functions, the same hatch pattern may be used and no particular reference numeral may be attached.

Note that in the drawings described in this specification, the size of each component, the thickness of a layer, or a region may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

Note that in this specification, high power supply voltage is referred to as H level (also referred to as "VDD" or "H potential"), and low power supply voltage is referred to as L level (also referred to as "GND" or "L potential"). There is.

Further, in this specification, the following embodiments and examples can be combined as appropriate. Further, when a plurality of configuration examples are shown in one embodiment, it is possible to combine the configuration examples as appropriate.

In this specification and the like, metal oxide refers to a metal oxide in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors, and the like. For example, when a metal oxide is used for a semiconductor layer of a transistor, the metal oxide is sometimes called an oxide semiconductor. In addition, when describing an OS transistor, it can also be referred to as a transistor including a metal oxide or an oxide semiconductor. Further, in this specification and the like, metal oxides containing nitrogen may also be collectively referred to as metal oxides.

Further, transistors shown in this specification and the like are enhancement type (normally-off type) n-channel field effect transistors, unless otherwise specified. Therefore, its threshold voltage (also referred to as "Vth") is assumed to be greater than 0V.

(Embodiment 1)
<Semiconductor device 100>
FIG. 1 is a circuit diagram illustrating a configuration example of a semiconductor device 100 according to one embodiment of the present invention. The semiconductor device 100 includes a voltage generation circuit 110, a voltage holding circuit 120, a temperature detection circuit 130, and a voltage control circuit 140. The node between the voltage holding circuit 120 and the voltage control circuit 140 is called a node ND. Voltage holding circuit 120 and voltage control circuit 140 are electrically connected to output terminal VOUT via node ND.

Furthermore, the semiconductor device 100 is electrically connected to the second gates of the plurality of transistors M11 via the output terminal VOUT. The transistor M11 is a transistor having a first gate (also referred to as a "front gate" or simply "gate") and a second gate (also referred to as a "back gate"). The first gate and the second gate have regions that overlap each other with the semiconductor layer interposed therebetween. The second gate has a function of controlling, for example, the threshold voltage of the transistor M11.

The transistor M11 represents a transistor used in various circuits included in a memory device, a pixel device, an arithmetic device, and the like. For example, it represents a transistor included in a NOR type or NAND type storage device. It also represents a transistor included in a display device such as a liquid crystal display device or an EL display device. It also represents a transistor included in, for example, a CPU (Central Processing Unit), a GPU (Graphic Processing Unit), or an FPGA (Field Programmable Gate Array).

Although three transistors M11 are illustrated in FIG. 1, one embodiment of the present invention is not limited thereto, and the semiconductor device 100 may be connected to even more transistors M11.

Here, the temperature dependence of the Id-Vg characteristic, which is one of the electrical characteristics of a transistor, will be explained. FIGS. 2A and 2B show an example of Id-Vg characteristics, which is one of the electrical characteristics of a transistor. The Id-Vg characteristic indicates a change in drain current (Id) with respect to a change in gate voltage (Vg). The horizontal axes in FIGS. 2(A) and 2(B) indicate Vg on a linear scale. Moreover, the vertical axis of FIG. 2(A) and FIG. 2(B) shows Id on a log scale.

FIG. 2(A) shows the Id-Vg characteristics of the OS transistor. FIG. 2B shows the Id-Vg characteristics of a transistor (also referred to as a "Si transistor") in which silicon is used as a semiconductor layer in which a channel is formed. Note that both FIGS. 2A and 2B show Id-Vg characteristics of an n-channel transistor.

As shown in FIG. 2A, the off-state current of the OS transistor does not easily increase even when operating at high temperatures. Further, as the operating temperature of the OS transistor increases, Vth shifts in the negative direction, and the on-current increases. On the other hand, as shown in FIG. 2B, the off-state current of the Si transistor increases as the temperature rises. Further, in the Si transistor, Vth shifts in the positive direction as the temperature rises, and the on-current decreases.

Therefore, by using an OS transistor as the transistor M11, the power consumption of the entire semiconductor device including the transistor M11 can be reduced even when operating at high temperatures.

Further, the semiconductor device 100 has a function of writing the voltage VBG to the second gate of the transistor M11 and further holding it. For example, when a negative potential is applied as the voltage VBG, the transistor M11 can shift Vth in the positive direction while the negative potential of the second gate is maintained. Vth can be kept high even when operating at high temperatures. For example, when the transistor M11 is used as a selection transistor of a memory cell, the charge of a capacitive element functioning as a storage can be held for a long period of time.

[Voltage generation circuit 110]
Examples of the circuit configuration of the voltage generation circuit 110 are shown in FIGS. 3A and 3B. These circuit diagrams show a step-down charge pump, in which GND is input to the input terminal IN, and VBG0 is output from the output terminal OUT. Here, as an example, the number of stages of the basic circuit of the charge pump circuit is four stages, but the charge pump circuit is not limited to this and may be configured with any number of stages.

The voltage generation circuit 110a shown in FIG. 3A includes transistors M21 to M24 and capacitors C21 to C24.

The transistors M21 to M24 are connected in series between the input terminal IN and the output terminal OUT, and their respective gates and first electrodes are connected to function as diodes. The gates of the transistors M21 to M24 are connected to capacitive elements C21 to C24, respectively.

CLK is input to the first electrodes of the capacitive elements C21 and C23 in the odd-numbered stages, and CLKB is inputted to the first electrodes of the capacitive elements C22 and C24 in the even-numbered stages. CLKB is an inverted clock signal obtained by inverting the phase of CLK.

The voltage generation circuit 110a has a function of lowering the voltage of GND input to the input terminal IN to generate VBG0. The voltage generation circuit 110a can generate a negative potential only by supplying CLK and CLKB.

The transistors M21 to M24 described above may be formed of OS transistors. The use of OS transistors is preferable because the reverse current of the diode-connected transistors M21 to M24 can be reduced.

The voltage generation circuit 110b shown in FIG. 3B includes transistors M31 to M34, which are p-channel transistors. Regarding other components, the description of the voltage generation circuit 110a is referred to.

The voltage generation circuit 110 may be not only a step-down charge pump but also a step-up charge pump. Further, the voltage generation circuit 110 may include both a step-down type and a step-up type charge pump.

[Voltage holding circuit 120]
The voltage holding circuit 120 includes a transistor M12 (see FIG. 1(A)). A first terminal (one of the source or drain) of the transistor M12 is electrically connected to the voltage generation circuit 110, and a second terminal (the other of the source or drain) of the transistor M12 is electrically connected to the node ND.

The voltage holding circuit 120 has a function of turning on the transistor M12 and supplying the voltage VBG0 generated by the voltage generating circuit 110 to the node ND. Assuming that the threshold voltage of the transistor M12 is Vth1, when turning on the transistor M12, it is preferable to apply a voltage equal to or higher than VBG0+Vth1 to the gate of the transistor M12. Further, the voltage holding circuit 120 has a function of turning off the transistor M12 and holding the voltage of the node ND.

When a negative potential is supplied as the voltage VBG0, a transistor having a first gate and a second gate may be used as the transistor M12, and the first gate and the second gate may be electrically connected to the second terminal (Fig. 4 (See (A)). In this case, transistor M12 can function as a diode. Furthermore, if the voltage output from the transistor M12 is the voltage VBG1, then the relationship VBG1=VBG0+Vth1 holds true. By setting the first terminal of the transistor M12 to GND, the negative potential written to the node ND can be held.

In the transistor M12 shown in FIG. 4A, when a negative potential is supplied to the node ND and then the first terminal is set to GND, Vg becomes 0V. Therefore, it is preferable that Id (also referred to as "cutoff current") be small when Vg is 0V. By making the cutoff current sufficiently small, the negative potential written to the node ND can be maintained for a long period of time.

The channel length of transistor M12 is preferably longer than the channel length of transistor M11. For example, when the channel length of the transistor M11 is less than 1 μm, the channel length of the transistor M12 is 1 μm or more, more preferably 3 μm or more, still more preferably 5 μm or more, and still more preferably 10 μm or more. By increasing the channel length of the transistor M12, the transistor M12 is not affected by the short channel effect, and the cutoff current can be kept low. Further, the transistor M12 can have a high breakdown voltage between the source and the drain. It is preferable that the breakdown voltage between the source and drain of the transistor M12 is high because it facilitates the connection between the voltage generation circuit 110 that generates a high voltage and the transistor M11.

As the transistor M12, it is preferable to use an OS transistor or a transistor whose channel formation region uses a wide bandgap semiconductor. An OS transistor or a transistor using a wide bandgap semiconductor has a small cutoff current and a high breakdown voltage between a source and a drain. Note that in this specification, a wide bandgap semiconductor is a semiconductor with a bandgap of 2.2 eV or more. Examples include silicon carbide, gallium nitride, and diamond.

Transistor M12 is required to have a smaller cutoff current than transistor M11. On the other hand, the transistor M11 is required to have a larger on-current than the transistor M12. In this way, when transistors with different required properties are formed on the same substrate, each transistor may be formed using different semiconductors. It is preferable that the transistor M12 uses a semiconductor having a larger band gap than the transistor M11 in its channel formation region. Further, it is preferable that a semiconductor having higher electron mobility be used in the channel formation region of the transistor M11 than that of the transistor M12.

Further, the voltage holding circuit 120 may include a plurality of transistors M12 connected in series (see FIGS. 4B and 4C).

[Temperature detection circuit 130]
The temperature detection circuit 130 includes a temperature sensor 131 and an analog-to-digital conversion circuit (also referred to as "ADC") 132 (see FIG. 5).

The temperature sensor 131 has a function of sensing the temperature of the semiconductor device 100 and outputting an analog signal VA according to the temperature. As the temperature sensor 131, for example, a resistance temperature detector made of platinum, nickel, or copper, a thermistor, a thermocouple, an IC temperature sensor, or the like can be used.

The analog-digital conversion circuit 132 has a function of converting the analog signal VA into an n-bit (n is an integer of 1 or more) digital signal VD. Digital signal VD is output from temperature detection circuit 130 and supplied to voltage control circuit 140.

By converting the temperature information of the analog signal detected by the temperature detection circuit 130 into a digital signal and outputting it, signal attenuation due to wiring resistance and parasitic capacitance and the influence of noise can be reduced. Therefore, even if the temperature detection circuit 130 is provided at a location away from the voltage control circuit 140, temperature information can be accurately transmitted to the voltage control circuit 140.

[Voltage control circuit 140]
As described using FIG. 2A, as the temperature of the OS transistor decreases, Vth shifts to the positive side and the on-current decreases. As a result, the operating speed of the circuit decreases. Further, as the temperature increases, Vth shifts to the negative side and the cutoff current increases. This becomes a factor that narrows the temperature range in which the circuit can operate. A circuit electrically connected to the output terminal VOUT corrects the voltage output from the output terminal VOUT of the semiconductor device 100 by applying a correction voltage according to the operating temperature to the node ND using the voltage control circuit 140. The operating temperature range can be expanded.

The voltage control circuit 140 includes a logic circuit 145 and a voltage generation circuit 146 (see FIG. 1(B)). The logic circuit 145 has a function of supplying the digital signal (temperature information) supplied from the temperature detection circuit 130 to the voltage generation circuit 146. For example, a serial signal supplied from the temperature detection circuit 130 is converted into a parallel signal and supplied to the voltage generation circuit 146. It also has a function of converting an n-bit digital signal supplied from the temperature detection circuit 130 into an m-bit digital signal (m is an integer of 1 or more) and supplying the converted signal to the voltage generation circuit 146.

The voltage generation circuit 146 has a function of converting the m-bit digital signal supplied from the logic circuit 145 into a voltage of 2 ^m levels and outputting the voltage. In FIG. 1(B), a case where m is 4 is illustrated. In FIG. 1B, the voltage generation circuit 146 includes a buffer BF1, a buffer BF2, a buffer BF3, a buffer BF4, a capacitor C1, a capacitor C2, a capacitor C4, and a capacitor C8.

The 4-bit digital signal output from the logic circuit 145 is supplied to the inputs of buffers BF1 to BF4. Specifically, the first digit information of a 4-bit digital signal is input to buffer BF1, the second digit information is input to buffer BF2, the third digit information is input to buffer BF3, and the fourth digit information is input to buffer BF2. information is input to buffer BF4.

One electrode of the capacitive element C1 is electrically connected to the output of the buffer BF1, and the other electrode is electrically connected to the output terminal OUT. One electrode of the capacitive element C2 is electrically connected to the output of the buffer BF2, and the other electrode is electrically connected to the output terminal OUT. One electrode of the capacitive element C4 is electrically connected to the output of the buffer BF3, and the other electrode is electrically connected to the output terminal OUT. One electrode of the capacitive element C8 is electrically connected to the output of the buffer BF4, and the other electrode is electrically connected to the output terminal OUT.

The voltage output from the output terminal OUT of the voltage control circuit 140 is called "voltage VBias." An output terminal OUT of the voltage control circuit 140 is electrically connected to a node ND of the semiconductor device 100.

The voltage applied to node ND from voltage control circuit 140 is determined by the ratio of the combined capacitance of capacitive element C1, capacitive element C2, capacitive element C4, and capacitive element C8 to the parasitic capacitance occurring at node ND. It is preferable that the capacitance value of the capacitive element C1 is sufficiently larger than the capacitance value of the parasitic capacitance. Specifically, the capacitance value of the capacitive element C1 is preferably 5 times or more, more preferably 10 times or more, the capacitance value of the parasitic capacitance.

Further, the capacitance values of the capacitive element C1, the capacitive element C2, the capacitive element C4, and the capacitive element C8 may all be the same, but it is preferable that at least some or all of them have different capacitance values. In this embodiment, the capacitance value of capacitive element C2 is twice that of capacitive element C1, the capacitive value of capacitive element C4 is four times that of capacitive element C1, and the capacitive value of capacitive element C8 is set to It is assumed to be eight times the capacitance value of element C1. By doing so, 16 levels of voltage can be supplied from the voltage control circuit 140 to the node ND.

FIGS. 6A to 6C show examples of voltage changes in the voltage VBias with respect to temperature changes. The horizontal axes in FIGS. 6(A) to 6(C) indicate temperature on a linear scale. Further, the vertical axis in FIGS. 6A to 6C indicates the voltage VBias on a linear scale. When the transistor M11 is an OS transistor, it is preferable that the magnitude of the voltage VBias decreases as the operating temperature of the transistor M11 increases (see FIG. 6A). Further, depending on the purpose and application, the temperature may be changed to become larger as the operating temperature becomes higher (see FIG. 6(B)). Furthermore, the magnitude of the voltage VBias may change nonlinearly with respect to temperature changes (see FIG. 6(C)). The voltage change in voltage VBias with respect to temperature change can be set by the logic circuit 145.

<Example of operation of semiconductor device 100>
FIG. 7 is a timing chart illustrating an example of the operation of the semiconductor device 100. In this embodiment, an operation example in which the transistor M11 is an OS transistor and the voltage VBias changes linearly in the range of 0V to 7.5V when the operating temperature changes in the range of 100°C to -50°C will be described. explain. Further, it is assumed that the voltage VBG becomes -3V when the operating temperature is 20°C.

Further, it is assumed that the temperature detection circuit 130 outputs a 4-bit digital signal VD. In this embodiment, it is assumed that "0000" is output as the digital signal VD when the operating temperature is 100.degree. C., and "1111" is output when the operating temperature is -50.degree.

Further, it is assumed that when the output of the buffer BF1 connected to one electrode of the capacitive element C1 changes from an L potential to an H potential, the potential of the other electrode of the capacitive element C1 increases by 0.5V. Further, it is assumed that when the output of the buffer BF2 connected to one electrode of the capacitive element C2 changes from the L potential to the H potential, the potential of the other electrode of the capacitive element C2 increases by 1.0V. Further, it is assumed that when the output of the buffer BF3 connected to one electrode of the capacitive element C4 changes from an L potential to an H potential, the potential of the other electrode of the capacitive element C4 increases by 2.0V. Further, it is assumed that when the output of the buffer BF4 connected to one electrode of the capacitive element C8 changes from the L potential to the H potential, the potential of the other electrode of the capacitive element C8 increases by 4.0V.

[Period T0]
Period T0 is a reset period. During the period T0, the L potential (0V) is output from each output of the buffers BF1 to BF4. Further, the voltage VBG0 is set to -7V, and the transistor M12 is turned on. Therefore, voltage VBG becomes -7V. During the period T0, the temperature detection circuit 130 may stop outputting the digital signal VD. Further, the operation of the temperature detection circuit 130 may be stopped.

[Period T1]
During period T1, transistor M12 is turned off. The voltage at node ND is held at -7V. Therefore, the voltage VBG also remains at -7V.

[Period T2]
In period T2, a digital signal VD (temperature information) is supplied from the temperature detection circuit 130 to the voltage control circuit 140. For example, "1000" is supplied to the voltage control circuit 140 as the digital signal VD indicating 20°C.

The logic circuit 145 inputs potentials corresponding to the digital signal VD to the buffers BF1 to BF4. Specifically, when the digital signal VD is "1000", the buffers BF1 to BF4 are controlled so that the outputs of the buffers BF1 to BF3 are at L potential and the output of buffer BF4 is at H potential.

Then, the potential of the voltage control circuit 140 increases by 4V. Then, the voltage at node ND changes from -7V to -3V, and voltage VBG becomes -3V.

[Period T3]
In period T3, a digital signal VD (temperature information) is supplied from the temperature detection circuit 130 to the voltage control circuit 140. For example, "0101" is supplied to the voltage control circuit 140 as the digital signal VD indicating 50°C.

Similarly to the period T2, the logic circuit 145 inputs potentials corresponding to the digital signal VD to the buffers BF1 to BF4. When the digital signal VD is "0101", the output of buffer BF1 is at H potential, the output of buffer BF2 is at L potential, the output of buffer BF3 is at H potential, and the output of buffer BF4 is at L potential. Then, the voltage VBG becomes -4.5V.

[Period T4]
During period T4, the digital signal VD (temperature information) is supplied from the temperature detection circuit 130 to the voltage control circuit 140. For example, "1100" is supplied to the voltage control circuit 140 as the digital signal VD indicating -20°C.

Similarly to the period T2 and the period T3, the logic circuit 145 inputs a potential according to the digital signal VD to the buffers BF1 to BF4. When the digital signal VD is "1100", the output of the buffer BF1 is at L potential, the output of buffer BF2 is at L potential, the output of buffer BF3 is at H potential, and the output of buffer BF4 is at H potential. Then, the voltage VBG becomes -1.0V.

In this way, voltage VBG can be changed in accordance with temperature changes. Further, if temperature changes in the electrical characteristics of the transistor M11 are not taken into consideration, a voltage larger than necessary will be applied to the second gate of the transistor M11. If an unnecessarily large voltage is applied to the second gate of the transistor M11 for a long time, the electrical characteristics of the transistor M11 may deteriorate and reliability may be impaired. According to one embodiment of the present invention, the voltage applied to the second gate of the transistor M11 can be changed in accordance with temperature changes. Therefore, the minimum necessary voltage can be applied to the second gate of the transistor M11. According to one embodiment of the present invention, reliability of a semiconductor device including the transistor M11 can be improved.

Further, a reset period (period T0) may be provided at regular intervals to refresh the voltage of the node ND.

This embodiment mode can be implemented in appropriate combination with the structures described in other embodiment modes.

(Embodiment 2)
In this embodiment, a memory device using the semiconductor device 100 described in Embodiment 1 will be described.

<Storage device>
FIG. 8 is a block diagram showing an example of the configuration of a storage device. Memory device 300 includes peripheral circuit 311, cell array 401, and semiconductor device 100. The peripheral circuit 311 includes a row decoder 321, a word line driver circuit 322, a bit line driver circuit 330, an output circuit 340, and a control logic circuit 360.

The word line driver circuit 322 has a function of supplying a potential to the wiring WL. The bit line driver circuit 330 includes a column decoder 331, a precharge circuit 332, an amplifier circuit 333, and a write circuit 334. The precharge circuit 332 has a function of precharging the wiring SL (not shown) and the like. The amplifier circuit 333 has a function of amplifying the data signal read from the wiring BIL or the wiring RBL. Note that the wiring WL, the wiring SL, the wiring BIL, and the wiring RBL are wirings connected to the memory cells 411 included in the cell array 401, and will be described in detail later. The amplified data signal is outputted to the outside of the storage device 300 via the output circuit 340 as a digital data signal RDATA.

The storage device 300 is externally supplied with a low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 311, and a high power supply voltage (VIL) for the cell array 401 as power supply voltages.

Furthermore, control signals (CE, WE, RE), address signal ADDR, and data signal WDATA are input to the storage device 300 from the outside. Address signal ADDR is input to row decoder 321 and column decoder 331, and WDATA is input to write circuit 334.

The control logic circuit 360 processes external input signals (CE, WE, RE) to generate control signals for the row decoder 321 and column decoder 331. CE is a chip enable signal, WE is a write enable signal, and RE is a read enable signal. The signals processed by the control logic circuit 360 are not limited to these, and other control signals may be input as necessary.

Note that each of the circuits or signals described above can be removed or removed as necessary.

OS transistors can be used as transistors forming the cell array 401. Further, an OS transistor can be used as a transistor included in the peripheral circuit 311. By forming the cell array 401 and the peripheral circuit 311 using OS transistors, the cell array 401 and the peripheral circuit 311 can be manufactured in the same manufacturing process, and manufacturing costs can be kept low.

[Example of cell array configuration]
FIG. 9 shows an example of the configuration of the cell array 401. The cell array 401 has a total of m×n memory cells 411, m (m is an integer of 1 or more) in one column and n (n is an integer of 1 or more) in one row. Cells 411 are arranged in rows and columns. In FIG. 9, the addresses of the memory cells 411 are also shown, and are [1,1], [m,1], [i,j], [1,n], [m,n] (i is (j is an integer between 1 and m, and j is an integer between 1 and n). Note that the number of wires connecting the cell array 401 and the word line driver circuit 322 is determined by the configuration of the memory cells 411, the number of memory cells 411 included in one column, and the like. Further, the number of wires connecting the cell array 401 and the bit line driver circuit 330 is determined by the configuration of the memory cells 411, the number of memory cells 411 included in one row, and the like.

[Example of memory cell configuration]
FIG. 10 shows a configuration example of memory cells 411A to 411E that can be applied to the above-described memory cell 411.

[DOSRAM]
FIG. 10A shows an example of a circuit configuration of a DRAM type memory cell 411A. In this specification and the like, a DRAM using an OS transistor is referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 411A includes a transistor M11 and a capacitor CA.

The first terminal of the transistor M11 is connected to the first terminal of the capacitive element CA, the second terminal of the transistor M11 is connected to the wiring BIL, the gate of the transistor M11 is connected to the wiring WL, and the back gate of the transistor M11 is connected to the wiring BIL. is connected to the wiring BGL. A second terminal of the capacitive element CA is connected to the wiring GNDL. The wiring GNDL is a wiring that provides a low-level potential (sometimes referred to as a reference potential).

The wiring BIL functions as a bit line, and the wiring WL functions as a word line. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M11. Further, the wiring BGL is electrically connected to the output terminal VOUT of the semiconductor device 100. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M11 can be increased or decreased.

Data writing and reading are performed by applying a high-level potential to the wiring WL, turning on the transistor M11, and electrically connecting the wiring BIL and the first terminal of the capacitive element CA.

Furthermore, the memory cells included in the above-described memory device 300 are not limited to the memory cell 411A, and the circuit configuration can be changed.

When the transistor M11 is used in a memory cell, it is preferable to use an OS transistor as the transistor M11. Further, it is preferable to use an oxide semiconductor containing any one of indium, element M (element M is aluminum, gallium, yttrium, or tin), and zinc for the semiconductor layer of the OS transistor. In particular, it is preferable to use an oxide semiconductor made of indium, gallium, or zinc.

An OS transistor using an oxide semiconductor containing indium, gallium, and zinc has a characteristic of extremely low off-state current. By using an OS transistor as the transistor M11, the leakage current of the transistor M11 can be made very low. In other words, the written data can be held for a long time by the transistor M11, so the frequency of refreshing the memory cells can be reduced. Furthermore, refresh operations for memory cells can be made unnecessary. Furthermore, since the leakage current is very low, multi-level data or analog data can be held in the memory cell 411A, memory cell 420, and memory cell 430.

By using an OS transistor as the transistor M11, a DOSRAM can be configured.

[NOSRAM]
FIG. 10B shows an example of a circuit configuration of a gain cell type (also referred to as "2Tr1C type") memory cell 411B having two transistors and one capacitor. The memory cell 411B includes a transistor M11, a transistor M3, and a capacitor CB.

The first terminal of the transistor M11 is connected to the first terminal of the capacitive element CB, the second terminal of the transistor M11 is connected to the wiring WBL, the gate of the transistor M11 is connected to the wiring WL, and the back gate of the transistor M11 is connected to the wiring WBL. is connected to the wiring BGL. A second terminal of the capacitive element CB is connected to the wiring BL. A first terminal of the transistor M3 is connected to the wiring RBL, a second terminal of the transistor M3 is connected to the wiring SL, and a gate of the transistor M3 is connected to the first terminal of the capacitive element CB.

The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WL functions as a word line. The wiring BL functions as a wiring for applying a predetermined potential to the second terminal of the capacitive element CB. It is preferable to apply a reference potential to the wiring BL during data writing and data retention.

The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M11. Further, the wiring BGL is electrically connected to the output terminal VOUT of the semiconductor device 100. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M11 can be increased or decreased.

Data writing is performed by applying a high-level potential to the wiring WL, turning on the transistor M11, and electrically connecting the wiring WBL and the first terminal of the capacitive element CB. Specifically, when the transistor M11 is in a conductive state, a potential corresponding to information to be recorded is applied to the wiring WBL, and the potential is written to the first terminal of the capacitive element CB and the gate of the transistor M3. Thereafter, by applying a low-level potential to the wiring WL and making the transistor M11 non-conductive, the potential of the first terminal of the capacitive element CB and the potential of the gate of the transistor M3 are held.

Data reading is performed by applying a predetermined potential to the wiring BL and the wiring SL. The current flowing between the source and drain of the transistor M3 and the potential of the first terminal of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3. By reading the potential of the wiring RBL, it is possible to read the potential held at the first terminal of the capacitive element CB (or the gate of the transistor M3). In other words, the information written in this memory cell can be read from the potential held at the first terminal of the capacitive element CB (or the gate of the transistor M3). Alternatively, it is possible to know the presence or absence of information written in this memory cell.

Further, the memory cell included in the above-described memory device 300 is not limited to the memory cell 411B, and the circuit configuration can be changed as appropriate.

For example, the wiring WBL and the wiring RBL may be combined into one wiring BIL. An example of the circuit configuration of the memory cell is shown in FIG. 10(C). The memory cell 411C has a configuration in which the wiring WBL and the wiring RBL of the memory cell 411B are used as one wiring BIL, and the second terminal of the transistor M11 and the first terminal of the transistor M3 are connected to the wiring BIL. . In other words, the memory cell 411C is configured to operate using a write bit line and a read bit line as one wiring BIL.

Note that in the memory cell 411B as well, it is preferable to use an OS transistor as the transistor M11. A memory device using an OS transistor as the transistor M11 and using 2Tr1C type memory cells such as the memory cell 411B and the memory cell 411C is called NOSRAM (Non-volatile Oxide Semiconductor Random Access Memory).

Note that the channel formation region of the transistor M3 preferably contains silicon. In particular, the silicon can be amorphous silicon, polycrystalline silicon, or low temperature polysilicon (LTPS) (hereinafter referred to as a Si transistor). Since a Si transistor may have higher field effect mobility than an OS transistor, it is preferable to use a Si transistor as a read transistor.

Further, when an OS transistor is used as the transistor M3, the memory cell can be configured with a unipolar circuit.

Further, FIG. 10D shows an example of the circuit configuration of a gain cell type (also referred to as "3Tr1C type") memory cell 411D having three transistors and one capacitive element. The memory cell 411D includes a transistor M11, a transistor M5, a transistor M6, and a capacitor CC.

The first terminal of the transistor M11 is connected to the first terminal of the capacitive element CC, the second terminal of the transistor M11 is connected to the wiring BIL, the gate of the transistor M11 is connected to the wiring WL, and the back gate of the transistor M11 is connected to the wiring BIL. is electrically connected to the wiring BGL. The second terminal of the capacitive element CC is electrically connected to the first terminal of the transistor M5 and the wiring GNDL. The second terminal of the transistor M5 is connected to the first terminal of the transistor M6, and the gate of the transistor M5 is connected to the first terminal of the capacitive element CC. The second terminal of the transistor M6 is connected to the wiring BIL, and the gate of the transistor M6 is connected to the wiring RL.

The wiring BIL functions as a bit line, the wiring WL functions as a write word line, and the wiring RL functions as a read word line.

The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M11. Further, the wiring BGL is electrically connected to the output terminal VOUT of the semiconductor device 100. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M11 can be increased or decreased.

Data writing is performed by applying a high-level potential to the wiring WL, turning on the transistor M11, and connecting the wiring BIL to the first terminal of the capacitive element CC. Specifically, when the transistor M11 is in a conductive state, a potential corresponding to information to be recorded is applied to the wiring BIL, and the potential is written to the first terminal of the capacitive element CC and the gate of the transistor M5. Thereafter, by applying a low-level potential to the wiring WL and making the transistor M11 non-conductive, the potential of the first terminal of the capacitive element CC and the potential of the gate of the transistor M5 are held.

Data reading is performed by precharging the wiring BIL with a predetermined potential, then placing the wiring BIL in an electrically floating state, and applying a high-level potential to the wiring RL. Since the wiring RL has a high level potential, the transistor M6 becomes conductive, and the wiring BIL and the second terminal of the transistor M5 are electrically connected. At this time, the potential of the wiring BIL is applied to the second terminal of the transistor M5, but the potential of the wiring BIL is applied to the second terminal of the transistor M5. The potential of the second terminal of M5 and the potential of the wiring BIL change. Here, by reading the potential of the wiring BIL, it is possible to read the potential held at the first terminal of the capacitive element CC (or the gate of the transistor M5). In other words, the information written in this memory cell can be read from the potential held at the first terminal of the capacitive element CC (or the gate of the transistor M5). Alternatively, it is possible to know the presence or absence of information written in this memory cell.

Furthermore, the circuit configuration of the memory cells included in the above-described memory device 300 can be changed as appropriate.

Note that in the memory cell 411D as well, it is preferable to use an OS transistor as the transistor M11. The 3Tr1C type memory cell 411D to which an OS transistor is applied as the transistor M11 is one embodiment of the NOSRAM described above.

Note that the channel formation regions of transistors M5 and M6 described in this embodiment mode preferably include silicon. In particular, the silicon can be amorphous silicon, polycrystalline silicon, low temperature polysilicon. Since a Si transistor may have higher field effect mobility than an OS transistor, it is preferable to use a Si transistor as a read transistor.

Furthermore, when OS transistors are used as the transistors M5 and M6, the memory cell can be configured with a unipolar circuit.

[oxSRAM]
FIG. 10E shows an example of a circuit configuration of an SRAM (Static Random Access Memory) type memory cell 411E using an OS transistor. In this specification and the like, an SRAM using an OS transistor is referred to as an oxSRAM. Note that the memory cell 411E shown in FIG. 10E is an SRAM type memory cell that can be backed up.

The memory cell 411E includes transistors M7 to M10, transistors MS1 to MS4, a capacitor CD1, and a capacitor CD2. Further, the transistor M7 and the transistor M8 correspond to the transistor M11. Note that the transistors M7 to M10 are transistors having a back gate. Note that the transistor MS1 and the transistor MS2 are p-channel transistors, and the transistor MS3 and transistor MS4 are n-channel transistors.

The first terminal of the transistor M7 is connected to the wiring BIL, and the second terminal of the transistor M7 is connected to the first terminal of the transistor MS1, the first terminal of the transistor MS3, the gate of the transistor MS2, and the gate of the transistor MS4. The first terminal of the transistor M10 is connected to the first terminal of the transistor M10. The gate of the transistor M7 is connected to the wiring WL, and the back gate of the transistor M7 is connected to the wiring BGL1.

The first terminal of the transistor M8 is connected to the wiring BILB, and the second terminal of the transistor M8 is connected to the first terminal of the transistor MS2, the first terminal of the transistor MS4, the gate of the transistor MS1, and the gate of the transistor MS3. The first terminal of the transistor M9 is connected to the first terminal of the transistor M9. The gate of the transistor M8 is connected to the wiring WL, and the back gate of the transistor M8 is connected to the wiring BGL2.

A second terminal of the transistor MS1 is electrically connected to the wiring VDL. A second terminal of the transistor MS2 is electrically connected to the wiring VDL. A second terminal of the transistor MS3 is electrically connected to the wiring GNDL. A second terminal of the transistor MS4 is connected to the wiring GNDL.

The second terminal of the transistor M9 is connected to the first terminal of the capacitive element CD1, the gate of the transistor M9 is connected to the wiring BRL, and the back gate of the transistor M9 is connected to the wiring BGL3. The second terminal of the transistor M10 is connected to the first terminal of the capacitive element CD2, the gate of the transistor M10 is connected to the wiring BRL, and the back gate of the transistor M10 is connected to the wiring BGL4.

The second terminal of the capacitive element CD1 is connected to the wiring GNDL, and the second terminal of the capacitive element CD2 is connected to the wiring GNDL.

The wiring BIL and the wiring BILB function as a bit line, the wiring WL functions as a word line, and the wiring BRL is a wiring that controls the conduction state and non-conduction state of the transistor M9 and the transistor M10.

The wirings BGL1 to BGL4 function as wirings for applying potentials to the back gates of the transistors M7 to M10, respectively.

The wiring BGL1 to the wiring BGL4 are electrically connected to the output terminal VOUT of the semiconductor device 100. Note that a plurality of semiconductor devices 100 may be provided in the storage device 300, and the wirings BGL1 to BGL4 may be electrically connected to different semiconductor devices 100, respectively. By applying arbitrary potentials to the wirings BGL1 to BGL4, the threshold voltages of the transistors M7 to M10 can be increased or decreased, respectively.

The wiring VDL is a wiring that provides a high level potential, and the wiring GNDL is a wiring that provides a low level potential.

Data writing is performed by applying a high-level potential to the wiring WL and applying a high-level potential to the wiring BRL. Specifically, when the transistor M10 is in a conductive state, a potential corresponding to information to be recorded on the wiring BIL is applied, and the potential is written to the second terminal side of the transistor M10.

By the way, since the memory cell 411E has an inverter loop formed by the transistors MS1 and MS2, an inverted signal of the data signal corresponding to the potential is input to the second terminal side of the transistor M8. Since the transistor M8 is conductive, the potential applied to the wiring BIL, that is, the inverted signal of the signal input to the wiring BIL, is output to the wiring BILB. Further, since the transistor M9 and the transistor M10 are in a conductive state, the potential of the second terminal of the transistor M7 and the potential of the second terminal of the transistor M8 are the first terminal of the capacitive element CD2 and the potential of the second terminal of the capacitive element CD1, respectively. It is held at one terminal. Thereafter, by applying a low-level potential to the wiring WL and applying a low-level potential to the wiring BRL to make the transistors M7 to M10 non-conductive, the potential of the first terminal of the capacitor CD1 and the capacitor The potential of the first terminal of CD2 is held.

To read data, after precharging the wiring BIL and the wiring BILB to a predetermined potential, applying a high level potential to the wiring WL and applying a high level potential to the wiring BRL, the first terminal of the capacitive element CD1 is read. The potential of the memory cell 411E is refreshed by the inverter loop of the memory cell 411E and output to the wiring BILB. Furthermore, the potential of the first terminal of the capacitive element CD2 is refreshed by the inverter loop of the memory cell 411E and output to the wiring BIL. In the wiring BIL and wiring BILB, the potential of the first terminal of the capacitive element CD2 and the potential of the first terminal of the capacitive element CD1 change from the precharged potential, respectively, so that the potential of the wiring BIL or the wiring BILB changes from the potential of the wiring BIL or the wiring BILB to the potential of the memory cell. The potential held at this point can be read out.

Note that it is preferable to use OS transistors as the transistors M7 to M10. By using OS transistors for the transistors M7 to M10, the data written to the memory cell 411E can be held for a long time, so that the frequency of refreshing the memory cell 411E can be reduced. Further, the refresh operation of the memory cell 411E can be made unnecessary. Furthermore, since the leakage current is very low, multi-value data or analog data can be held in the memory cell 411E.

Note that the channel formation regions of the transistors MS1 to MS4 preferably contain silicon. In particular, the silicon may be amorphous silicon, polycrystalline silicon, low temperature polysilicon. Since Si transistors may have higher field effect mobility than OS transistors, it is preferable to use Si transistors as transistors included in the inverter.

Furthermore, by using an OS transistor in the memory cell, information written in the memory cell can be retained for a long period of time even if power supply to the memory cell is stopped. Therefore, power supply to part or all of the peripheral circuit 311 can be stopped during a period when reading and writing information is not necessary.

One semiconductor device 100 may be electrically connected to all memory cells. Alternatively, a plurality of semiconductor devices 100 may be provided in the memory device 300, and a plurality of memory cells and one semiconductor device 100 may be electrically connected for each column or for each plurality of columns. Further, a plurality of memory cells and one semiconductor device 100 may be electrically connected row by row or row by row. Alternatively, a plurality of memory cells included in a cell array may be divided into a plurality of blocks, and one semiconductor device 100 may be provided for each block or for each of a plurality of blocks.

The memory cells described in this embodiment can be used for storage elements such as registers and caches included in CPUs, GPUs, and the like.

This embodiment mode can be implemented in appropriate combination with the structures described in other embodiment modes.

(Embodiment 3)
In this embodiment, an example of a cross-sectional configuration of a storage device 300 will be described with reference to the drawings.

<Structure example of storage device>
FIG. 11 shows a cross section of a portion of the storage device 300. A storage device 300 shown in FIG. 11 has a layer 310 and a layer 320 stacked on a substrate 231. FIG. 11 shows a case where a single crystal semiconductor substrate (for example, a single crystal silicon substrate) is used as the substrate 231.

[Layer 310]
In FIG. 11, layer 310 has transistor 233a, transistor 233b, and transistor 233c on substrate 231. In FIG. FIG. 11 shows cross sections of a transistor 233a, a transistor 233b, and a transistor 233c in the channel length direction.

Channels of the transistors 233a, 233b, and 233c are formed in part of the substrate 231. If high-speed operation is required for the integrated circuit, it is preferable to use a single crystal semiconductor substrate as the substrate 231.

Transistor 233a, transistor 233b, and transistor 233c are electrically isolated from each other by element isolation layer 232. The element isolation layer can be formed using a LOCOS (Local Oxidation of Silicon) method, an STI (Shallow Trench Isolation) method, or the like.

Further, an insulating layer 234 is provided over the substrate 231, an insulating layer 235 and an insulating layer 237 are provided over the transistor 233a, the transistor 233b, and the transistor 233c, and an electrode 238 is embedded in the insulating layer 237. Electrode 238 is electrically connected to one of the source and drain of transistor 233a via contact plug 236.

Further, an insulating layer 239, an insulating layer 240, and an insulating layer 241 are provided on the electrode 238 and the insulating layer 237, and an electrode 242 is embedded in the insulating layer 239, the insulating layer 240, and the insulating layer 241. . Electrode 242 is electrically connected to electrode 238.

Further, an insulating layer 243 and an insulating layer 244 are provided on the electrode 242 and the insulating layer 241, and an electrode 245 is embedded in the insulating layer 243 and the insulating layer 244. Electrode 245 is electrically connected to electrode 242.

Further, an insulating layer 246 and an insulating layer 247 are provided on the electrode 245 and the insulating layer 244, and an electrode 249 is embedded in the insulating layer 246 and the insulating layer 247. Electrode 249 is electrically connected to electrode 245.

Further, an insulating layer 248 and an insulating layer 250 are provided on the electrode 249 and the insulating layer 247, and an electrode 251 is embedded in the insulating layer 248 and the insulating layer 250. Electrode 251 is electrically connected to electrode 249.

[Layer 320]
Layer 320 is provided on layer 310. The layer 320 includes a transistor 368a, a transistor 368b, a capacitor 369a, and a capacitor 369b. FIG. 11 shows cross sections of the transistor 368a and the transistor 368b in the channel length direction. Note that the transistor 368a and the transistor 368b are transistors with a back gate.

The transistor 368a and the transistor 368b correspond to the transistor M11 described in the above embodiment mode. Therefore, it is preferable to use an oxide semiconductor, which is a type of metal oxide, for the semiconductor layers of the transistors 368a and 368b. That is, it is preferable to use OS transistors for the transistor 368a and the transistor 368b.

The transistor 368a and the transistor 368b are provided over the insulating layer 361 and the insulating layer 362. Further, an insulating layer 363 and an insulating layer 364 are provided on the insulating layer 362. The back gates of transistor 368a and transistor 368b are buried in insulating layer 363 and insulating layer 364. An insulating layer 365 and an insulating layer 366 are provided on the insulating layer 364. Further, an electrode 367 is embedded in the insulating layers 361 to 366. Electrode 367 is electrically connected to electrode 251.

Further, an insulating layer 371, an insulating layer 372, and an insulating layer 373 are formed over the transistor 368a, the transistor 368b, the capacitor 369a, and the capacitor 369b, and an electrode 375 is formed over the insulating layer 373. Electrode 375 is electrically connected to electrode 367 via contact plug 374.

Further, on the electrode 375, an insulating layer 376, an insulating layer 377, an insulating layer 378, and an insulating layer 379 are provided. Further, an electrode 380 is embedded in the insulating layers 376 to 379. Electrode 380 is electrically connected to electrode 375.

Further, an insulating layer 381 and an insulating layer 382 are provided on the electrode 380 and the insulating layer 379.

<Modified example>
FIG. 12 shows a cross section of a portion of the storage device 300A. The storage device 300A is a modification of the storage device 300. Storage device 300A has layer 310A and layer 320. In the storage device 300A, an insulating substrate (for example, a glass substrate) is used as the substrate 231.

Layer 310A includes a transistor 268a, a transistor 268b, and a capacitor 269a. A thin film transistor (for example, an OS transistor) is used as a transistor included in the layer 310A. By making all the transistors included in the layer 310A OS transistors, the layer 310A can be made into a unipolar integrated circuit. By using all the transistors included in the storage device 300A as OS transistors, the storage device 300A can be made into a unipolar storage device.

<About constituent materials>
〔substrate〕
Although there are no major restrictions on the material used for the substrate, it is required that the material has at least enough heat resistance to withstand subsequent heat treatment. For example, a single crystal semiconductor substrate made of silicon, silicon carbide, or the like, a polycrystalline semiconductor substrate, a compound semiconductor substrate made of silicon germanium, or the like can be used as the substrate. Further, an SOI substrate or a semiconductor substrate in which a semiconductor element such as a strain transistor or a FIN type transistor is provided can also be used. Alternatively, gallium arsenide, aluminum gallium arsenide, indium gallium arsenide, gallium nitride, indium phosphide, silicon germanium, or the like which can be used in a high electron mobility transistor (HEMT) may be used. That is, the substrate is not limited to a simple support substrate, but may be a substrate on which other devices such as transistors are formed.

Further, as the substrate, a glass substrate such as barium borosilicate glass or aluminoborosilicate glass, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. can also be used. Note that a flexible substrate may be used as the substrate. When using a flexible substrate, transistors, capacitive elements, etc. may be fabricated directly on the flexible substrate, or transistors, capacitive elements, etc. may be fabricated on another fabrication substrate, and then transferred to the flexible substrate. It may be peeled off or relocated. Note that in order to peel off and transfer from the fabrication substrate to a flexible substrate, it is preferable to provide a peeling layer between the fabrication substrate and the transistor, capacitor, or the like.

As the flexible substrate, for example, metal, alloy, resin, glass, or fibers thereof can be used. It is preferable that the flexible substrate used for the substrate has a lower coefficient of linear expansion, since deformation caused by the environment is suppressed. The flexible substrate used for the substrate may be made of a material having a coefficient of linear expansion of 1×10 ⁻³ /K or less, 5×10 ⁻⁵ /K or less, or 1×10 ⁻⁵ /K or less, for example. Examples of the resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic, and the like. In particular, aramid is suitable as a flexible substrate because it has a low coefficient of linear expansion.

[Insulating layer]
The insulating layer includes aluminum nitride, aluminum oxide, aluminum nitride oxide, aluminum oxynitride, magnesium oxide, silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, A material selected from neodymium oxide, hafnium oxide, tantalum oxide, aluminum silicate, etc. is used in a single layer or in a stacked manner. Alternatively, a mixture of a plurality of materials among oxide materials, nitride materials, oxynitride materials, and nitrided oxide materials may be used.

Note that in this specification and the like, a nitrided oxide refers to a compound containing more nitrogen than oxygen. Further, oxynitride refers to a compound containing more oxygen than nitrogen. Note that the content of each element can be measured using, for example, Rutherford Backscattering Spectrometry (RBS).

Further, when an oxide semiconductor, which is a type of metal oxide, is used as the semiconductor layer, it is preferable to reduce the hydrogen concentration in the insulating layer in order to prevent an increase in the hydrogen concentration in the semiconductor layer. Specifically, the hydrogen concentration in the insulating layer is determined to be 2×10 ²⁰ atoms/cm ³ or less, preferably 5×10 ¹⁹ atoms/cm ³ or less in secondary ion mass spectrometry (SIMS), More preferably it is 1×10 ¹⁹ atoms/cm ³ or less, and even more preferably 5×10 ¹⁸ atoms/cm ³ or less. In particular, it is preferable to reduce the hydrogen concentration in the insulating layer in contact with the semiconductor layer.

Further, in order to prevent an increase in the nitrogen concentration in the semiconductor layer, it is preferable to reduce the nitrogen concentration in the insulating layer. Specifically, the nitrogen concentration in the insulating layer is determined by SIMS to be 5×10 ¹⁹ atoms/cm ³ or less, preferably 5×10 ¹⁸ atoms/cm ³ or less, more preferably 1×10 ¹⁸ atoms/cm ³ or less, More preferably, it is 5×10 ¹⁷ atoms/cm ³ or less.

Further, it is preferable that at least a region of the insulating layer in contact with the semiconductor layer has few defects, and typically, it is preferable that there are few signals observed by electron spin resonance (ESR). For example, the above-mentioned signal includes the E' center observed at a g value of 2.001. Note that the E' center is caused by a dangling bond of silicon. For example, when a silicon oxide layer or a silicon oxynitride layer is used as the insulating layer, the spin density due to the E' center is 3×10 ¹⁷ spins/cm ³ or less, preferably 5×10 ¹⁶ spins/cm ³ or less. A silicon oxide layer or a silicon oxynitride layer may be used.

Further, in addition to the above-mentioned signals, signals caused by nitrogen dioxide (NO ₂ ) may be observed. The signal is split into three signals by the nuclear spin of N, each with a g value of 2.037 or more and 2.039 or less (the first signal), and a g value of 2.001 or more and 2.003. (referred to as a second signal), and a g value of 1.964 to 1.966 (referred to as a third signal).

For example, it is preferable to use an insulating layer in which the spin density of signals caused by nitrogen dioxide (NO ₂ ) is 1×10 ¹⁷ spins/cm ³ or more and less than 1×10 ¹⁸ spins/cm ³ as the insulating layer.

Note that nitrogen oxides (NO _x ) including nitrogen dioxide (NO ₂ ) form a level in the insulating layer. The level is located within the energy gap of the oxide semiconductor layer. Therefore, when nitrogen oxide (NO _x ) diffuses into the interface between the insulating layer and the oxide semiconductor layer, the level may trap electrons on the insulating layer side. As a result, the trapped electrons remain near the interface between the insulating layer and the oxide semiconductor layer, thereby shifting the threshold voltage of the transistor in the positive direction. Therefore, when a film containing a small amount of nitrogen oxide is used as the insulating layer, the shift in the threshold voltage of the transistor can be reduced.

As the insulating layer that releases a small amount of nitrogen oxides (NO _x ), for example, a silicon oxynitride layer can be used. The silicon oxynitride layer is a film that releases more ammonia than nitrogen oxides (NO _x ) in thermal desorption spectroscopy (TDS); The amount of emission is 1×10 ¹⁸ molecules/cm ³ or more and 5×10 ¹⁹ molecules/cm ³ or less. Note that the amount of ammonia released above is the total amount when the temperature of the heat treatment in TDS is in the range of 50° C. or more and 650° C. or less, or 50° C. or more and 550° C. or less.

Since nitrogen oxides (NO _x ) react with ammonia and oxygen during heat treatment, nitrogen oxides (NO _x ) are reduced by using an insulating layer that releases a large amount of ammonia.

Further, at least one of the insulating layers in contact with the oxide semiconductor layer is preferably formed using an insulating layer that releases oxygen when heated. Specifically, in TDS performed by heat treatment at a surface temperature of the insulating layer of 100° C. or higher and 700° C. or lower, preferably 100° C. or higher and 500° C. or lower, the amount of oxygen desorbed in terms of oxygen atoms is 1.0. It is preferable to use an insulating layer having a density of at least × ^{10 18} atoms/cm ³ , at least 1.0 × 10 ¹⁹ atoms/cm ³ , or at least 1.0 × 10 ²⁰ atoms/cm ³ . Note that in this specification and the like, oxygen released by heating is also referred to as "excess oxygen."

Further, the insulating layer containing excess oxygen can also be formed by adding oxygen to the insulating layer. The process of adding oxygen can be performed by heat treatment, plasma treatment, etc. in an oxidizing atmosphere. Alternatively, oxygen may be added using an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like. Examples of the gas used in the process of adding oxygen include gases containing oxygen such as oxygen gas such as ¹⁶ O ₂ or ¹⁸ O ₂ , nitrous oxide gas, or ozone gas. Note that in this specification, the process of adding oxygen is also referred to as "oxygen doping process." The oxygen doping treatment may be performed by heating the substrate.

Further, as the insulating layer, a heat-resistant organic material such as polyimide, acrylic resin, benzocyclobutene resin, polyamide, epoxy resin, etc. can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials), siloxane resins, PSG (phosphorus glass), BPSG (phosphorus boron glass), etc. can be used. Note that the insulating layer may be formed by laminating a plurality of insulating layers made of these materials.

Note that the siloxane-based resin corresponds to a resin containing Si--O--Si bonds formed using a siloxane-based material as a starting material. In the siloxane resin, an organic group (for example, an alkyl group or an aryl group) or a fluoro group may be used as a substituent. Further, the organic group may have a fluoro group.

The method of forming the insulating layer is not particularly limited. Note that a firing process may be necessary depending on the material used for the insulating layer. In this case, by combining the step of baking the insulating layer with another heat treatment step, it becomes possible to efficiently manufacture a transistor.

〔electrode〕
Conductive materials for forming electrodes include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, etc. A material containing one or more metal elements selected from can be used. Further, a semiconductor having high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

Further, a conductive material containing the above metal elements and oxygen may be used. Further, a conductive material containing the above metal element and nitrogen may be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used. In addition, indium tin oxide (ITO), indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc An oxide, indium gallium zinc oxide, or indium tin oxide added with silicon may also be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used.

Further, a plurality of conductive layers formed of the above materials may be laminated and used. For example, a layered structure may be used in which a material containing the metal element described above and a conductive material containing oxygen are combined. Alternatively, a laminated structure may be used in which a material containing the aforementioned metal element and a conductive material containing nitrogen are combined. Alternatively, a laminated structure may be used in which a material containing the aforementioned metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined. Alternatively, a layered structure may be used in which a conductive material containing nitrogen and a conductive material containing oxygen are combined.

Note that when using an oxide semiconductor for the semiconductor layer and a stacked structure in which a material containing the metal element described above and a conductive material containing oxygen are used as the gate electrode, the conductive material containing oxygen is used as the semiconductor layer. It is best to provide it on the layer side. By providing a conductive material containing oxygen on the semiconductor layer side, oxygen released from the conductive material is easily supplied to the semiconductor layer.

Note that as the electrode, for example, a conductive material with high embeddability such as tungsten or polysilicon may be used. Further, a highly embeddable conductive material and a barrier layer (diffusion prevention layer) such as a titanium layer, a titanium nitride layer, or a tantalum nitride layer may be used in combination. Note that the electrode is sometimes referred to as a "contact plug."

In particular, it is preferable to use a conductive material through which impurities hardly pass, for the electrode in contact with the gate insulating layer. An example of a conductive material that is difficult for impurities to pass through is tantalum nitride.

Diffusion of impurities into the transistor can be further suppressed by using an insulating material that is difficult for impurities to pass through for the insulating layer and a conductive material that is difficult for impurities to pass through for the electrodes. Therefore, reliability of the transistor can be further improved. In other words, the reliability of the storage device can be further improved.

[Semiconductor layer]
As the semiconductor layer, a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used alone or in combination. As the semiconductor material, silicon, germanium, etc. can be used, for example. Further, compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, oxide semiconductors, and nitride semiconductors, organic semiconductors, and the like can be used.

Furthermore, when an organic semiconductor is used as the semiconductor layer, a low-molecular organic material having an aromatic ring, a π-electron conjugated conductive polymer, or the like can be used. For example, rubrene, tetracene, pentacene, perylene diimide, tetracyanoquinodimethane, polythiophene, polyacetylene, polyparaphenylene vinylene, etc. can be used.

Note that semiconductor layers may be stacked. When stacking semiconductor layers, semiconductors having different crystal states or different semiconductor materials may be used.

Further, since the band gap of an oxide semiconductor, which is a type of metal oxide, is 2 eV or more, when an oxide semiconductor is used for the semiconductor layer, a transistor with extremely low off-state current can be realized. Specifically, the off-state current per 1 μm of channel width is less than 1×10 ^{−20 A} and 1×10 ⁻²² A at a voltage of 3.5 V between the source and drain and at room temperature (typically 25° C.). or less than 1×10 ⁻²⁴ A. That is, the on-off ratio can be set to 20 digits or more. Further, a transistor in which an oxide semiconductor is used for a semiconductor layer (OS transistor) has a high dielectric strength voltage between a source and a drain. Therefore, a highly reliable transistor can be provided. Furthermore, a transistor with a large output voltage and high breakdown voltage can be provided. Furthermore, a highly reliable storage device can be provided. Furthermore, a memory device with a large output voltage and high breakdown voltage can be provided.

Further, in this specification and the like, a transistor in which silicon having crystallinity is used for a semiconductor layer in which a channel is formed is also referred to as a "crystalline Si transistor."

Crystalline Si transistors tend to have relatively higher mobility than OS transistors. On the other hand, it is difficult for crystalline Si transistors to realize an extremely small off-state current like OS transistors. Therefore, it is important to appropriately select the semiconductor material used for the semiconductor layer depending on the purpose and application. For example, depending on the purpose and application, an OS transistor and a crystalline Si transistor may be used in combination.

When using an oxide semiconductor layer as the semiconductor layer, the oxide semiconductor layer is preferably formed by a sputtering method. The oxide semiconductor layer is preferably formed by sputtering because the density of the oxide semiconductor layer can be increased. When forming an oxide semiconductor layer by a sputtering method, a rare gas (typically argon), oxygen, or a mixed gas of a rare gas and oxygen may be used as the sputtering gas. It is also necessary to highly purify the sputtering gas. For example, the oxygen gas or rare gas used as the sputtering gas is a highly purified gas with a dew point of -60°C or lower, preferably -100°C or lower. By forming a film using a highly purified sputtering gas, it is possible to prevent moisture and the like from being taken into the oxide semiconductor layer as much as possible.

Further, when forming an oxide semiconductor layer by a sputtering method, it is preferable to remove as much moisture as possible in a film formation chamber of a sputtering apparatus. For example, it is preferable to evacuate the film forming chamber to a high vacuum (approximately 5×10 ⁻⁷ Pa to 1×10 ⁻⁴ Pa) using an adsorption type vacuum evacuation pump such as a cryopump. In particular, when the sputtering apparatus is on standby, the partial pressure of gas molecules equivalent to H ₂ O (gas molecules corresponding to m/z=18) in the film forming chamber is set to 1×10 ⁻⁴ Pa or less, preferably 5×10 ⁻ It is preferable to set it to ⁵ Pa or less.

[Metal oxide]
The oxide semiconductor, which is a type of metal oxide, preferably contains at least indium or zinc. In particular, it is preferable to include indium and zinc. Moreover, in addition to these, it is preferable that aluminum, gallium, yttrium, tin, or the like is contained. Further, one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium may be included.

Here, a case will be considered in which the oxide semiconductor contains indium, element M, and zinc. Note that the element M is aluminum, gallium, yttrium, tin, or the like. Other elements that can be used as the element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. However, as the element M, there are cases where a plurality of the above-mentioned elements may be combined.

Note that in this specification and the like, metal oxides containing nitrogen may also be collectively referred to as metal oxides. Furthermore, a metal oxide containing nitrogen may be referred to as a metal oxynitride.

[Composition of metal oxide]
The structure of a CAC (Cloud-Aligned Composite)-OS that can be used for the transistor disclosed in one embodiment of the present invention will be described below.

Note that in this specification and the like, it may be described as CAAC (c-axis aligned crystal) and CAC (Cloud-Aligned Composite). Note that CAAC represents an example of a crystal structure, and CAC represents an example of a function or a material configuration.

CAC-OS or CAC-metal oxide has a part of the material having a conductive function, a part of the material having an insulating function, and the entire material having a semiconductor function. Note that when CAC-OS or CAC-metal oxide is used in the active layer of a transistor, the conductive function is to flow electrons (or holes) that serve as carriers, and the insulating function is to flow electrons (or holes) that serve as carriers. This function does not allow electrons to flow. A switching function (on/off function) can be imparted to CAC-OS or CAC-metal oxide by making the conductive function and the insulating function act complementary to each other. By separating the functions of CAC-OS or CAC-metal oxide, the functions of both can be maximized.

Further, CAC-OS or CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. Further, in a material, a conductive region and an insulating region may be separated at the nanoparticle level. Further, the conductive region and the insulating region may be unevenly distributed in the material. Further, the conductive regions may be observed to be connected in a cloud-like manner with the periphery blurred.

Further, in CAC-OS or CAC-metal oxide, when the conductive region and the insulating region are each dispersed in the material with a size of 0.5 nm or more and 10 nm or less, preferably 0.5 nm or more and 3 nm or less. There is.

Further, CAC-OS or CAC-metal oxide is composed of components having different band gaps. For example, CAC-OS or CAC-metal oxide is composed of a component having a wide gap caused by an insulating region and a component having a narrow gap caused by a conductive region. In the case of this configuration, carriers mainly flow in the component having a narrow gap. Furthermore, the component having a narrow gap acts complementary to the component having a wide gap, and carriers also flow into the component having a wide gap in conjunction with the component having a narrow gap. Therefore, when the above-mentioned CAC-OS or CAC-metal oxide is used in the channel formation region of a transistor, a high current driving force, that is, a large on-state current, and high field effect mobility can be obtained in the on state of the transistor.

That is, CAC-OS or CAC-metal oxide can also be referred to as a matrix composite or a metal matrix composite.

[Structure of metal oxide]
Oxide semiconductors, which are a type of metal oxide, are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single crystal oxide semiconductors include CAAC-OS (c-axis aligned crystalline oxide semiconductor), polycrystalline oxide semiconductor, nc-OS (nanocrystalline oxide semiconductor), and pseudo-amorphous oxide. Semiconductor (a-like OS: amorphous-like oxide semiconductor) and amorphous oxide semiconductor.

CAAC-OS has c-axis orientation and a plurality of nanocrystals connected in the a-b plane direction, resulting in a distorted crystal structure. Note that distortion refers to a location where the orientation of the lattice arrangement changes between a region where the lattice arrangement is uniform and another region where the lattice arrangement is uniform in a region where a plurality of nanocrystals are connected.

Although nanocrystals are basically hexagonal, they are not limited to regular hexagonal shapes and may have irregular hexagonal shapes. In addition, the distortion may have a pentagonal or heptagonal lattice arrangement. Note that in CAAC-OS, it is difficult to confirm clear grain boundaries (also referred to as grain boundaries) even in the vicinity of strain. That is, it can be seen that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction, and the bond distance between atoms changes due to substitution of metal elements. It's for a reason.

In addition, CAAC-OS is a layered crystal in which a layer containing indium and oxygen (hereinafter referred to as an "In layer") and a layer containing element M, zinc, and oxygen (hereinafter referred to as a (M, Zn) layer) are laminated. They tend to have a structure (also called a layered structure). Note that indium and element M can be substituted with each other, and when element M in a (M, Zn) layer is substituted with indium, it can also be expressed as an (In, M, Zn) layer. Furthermore, when indium in the In layer is replaced with element M, it can also be expressed as an (In, M) layer.

CAAC-OS is a highly crystalline metal oxide. On the other hand, in CAAC-OS, it is difficult to confirm clear grain boundaries, so it can be said that reduction in electron mobility due to grain boundaries is less likely to occur. Further, since the crystallinity of a metal oxide may be reduced due to the incorporation of impurities or the formation of defects, CAAC-OS can also be said to be a metal oxide with few impurities or defects (oxygen vacancies, etc.). Therefore, the metal oxide with CAAC-OS has stable physical properties. Therefore, metal oxides with CAAC-OS are resistant to heat and have high reliability.

The nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Further, in nc-OS, no regularity is observed in crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be indistinguishable from a-like OS or amorphous oxide semiconductor.

The a-like OS is a metal oxide with a structure between that of an nc-OS and an amorphous oxide semiconductor. A-like OS has holes or low density areas. That is, a-like OS has lower crystallinity than nc-OS and CAAC-OS.

Oxide semiconductors (metal oxides) have a variety of structures, each with different properties. The oxide semiconductor may include two or more types of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.

[Transistor with metal oxide]
Next, a case where the above metal oxide is used in a channel formation region of a transistor will be described.

Note that by using the above metal oxide in a channel formation region of a transistor, a transistor with high field-effect mobility can be realized. Further, a highly reliable transistor can be realized.

Further, it is preferable to use a metal oxide with low carrier density for the transistor. In order to lower the carrier density of the metal oxide film, the impurity concentration in the metal oxide film may be lowered to lower the defect level density. In this specification and the like, the term "high purity intrinsic" or "substantially high purity intrinsic" means that the impurity concentration is low and the defect level density is low. For example, the metal oxide has a carrier density of less than 8×10 ¹¹ /cm ³ , preferably less than 1×10 ¹¹ /cm ³ , more preferably less than 1×10 ¹⁰ /cm ³ , and 1×10 ⁻⁹ /cm 3 . cm ³ or more.

Further, since a metal oxide film that is highly pure or substantially pure has a low defect level density, the trap level density may also be low.

Furthermore, charges captured in the trap levels of metal oxides take a long time to disappear, and may behave as if they were fixed charges. Therefore, a transistor including a metal oxide with a high trap level density in a channel formation region may have unstable electrical characteristics.

Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the metal oxide. Furthermore, in order to reduce the impurity concentration in the metal oxide, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[impurities]
Here, the influence of each impurity in the metal oxide will be explained.

When a metal oxide contains silicon or carbon, which is one of the Group 14 elements, a defect level is formed in the metal oxide. Therefore, the concentration of silicon and carbon in the metal oxide and the concentration of silicon and carbon near the interface with the metal oxide (concentration obtained by secondary ion mass spectrometry (SIMS)) are set to 2×10 ¹⁸ atoms/ cm ³ or less, preferably 2×10 ¹⁷ atoms/cm ³ or less.

Further, when the metal oxide contains an alkali metal or an alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using a metal oxide containing an alkali metal or an alkaline earth metal in a channel formation region tends to have normally-on characteristics. For this reason, it is preferable to reduce the concentration of the alkali metal or alkaline earth metal in the metal oxide. Specifically, the concentration of the alkali metal or alkaline earth metal in the metal oxide obtained by SIMS is set to 1×10 ¹⁸ atoms/cm ³ or less, preferably 2×10 ¹⁶ atoms/cm ³ or less.

Further, when nitrogen is contained in a metal oxide, electrons as carriers are generated, the carrier density increases, and the metal oxide tends to become n-type. As a result, a transistor in which a metal oxide containing nitrogen is used in a channel formation region tends to have normally-on characteristics. Therefore, in the metal oxide, it is preferable that nitrogen in the channel forming region be reduced as much as possible. For example, the nitrogen concentration in the metal oxide is determined by SIMS to be less than 5×10 ¹⁹ atoms/cm ³ , preferably 5×10 ¹⁸ atoms/cm ³ or less, more preferably 1×10 ¹⁸ atoms/cm ³ or less, and further Preferably it is 5×10 ¹⁷ atoms/cm ³ or less.

Furthermore, hydrogen contained in metal oxides reacts with oxygen bonded to metal atoms to become water, which may result in the formation of oxygen vacancies. When hydrogen enters the oxygen vacancy, electrons, which are carriers, may be generated. Further, a portion of hydrogen may combine with oxygen that is bonded to a metal atom to generate electrons, which are carriers. Therefore, a transistor in which a metal oxide containing hydrogen is used in a channel formation region tends to have normally-on characteristics. For this reason, it is preferable that hydrogen in the metal oxide be reduced as much as possible. Specifically, in metal oxides, the hydrogen concentration obtained by SIMS is less than 1×10 ²⁰ atoms/cm ³ , preferably less than 1×10 ¹⁹ atoms/cm ³ , more preferably 5×10 ¹⁸ atoms/cm It is less than ³ , more preferably less than 1×10 ¹⁸ atoms/cm ³ .

By using a metal oxide with sufficiently reduced impurities in a channel formation region of a transistor, stable electrical characteristics can be provided.

<About the film formation method>
An insulating material for forming an insulating layer, a conductive material for forming an electrode, or a semiconductor material for forming a semiconductor layer can be prepared using a sputtering method, a spin coating method, or a CVD (Chemical Vapor Deposition) method (thermal CVD). method, MOCVD (Metal Organic Chemical Vapor Deposition) method, PECVD (Plasma Enhanced CVD) method, high density plasma CVD (High density plasma CVD) method, LPCVD (low pr essure CVD) method, APCVD (atmosphere pressure CVD) method, etc. ), ALD (Atomic Layer Deposition) method, MBE (Molecular Beam Epitaxy) method, PLD (Pulsed Laser Deposition) method, dip method, spray coating method, droplet discharge method (inkjet method, etc.), printing method ( (screen printing, offset printing, etc.).

The plasma CVD method can obtain a high quality film at a relatively low temperature. When a film formation method that does not use plasma during film formation, such as MOCVD, ALD, or thermal CVD, the surface on which the film is formed is less likely to be damaged. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a memory device may be charged up by receiving charges from plasma. At this time, the accumulated charges may destroy wiring, electrodes, elements, etc. included in the memory device. On the other hand, in the case of a film formation method that does not use plasma, such plasma damage does not occur, so that the yield of memory devices can be increased. Furthermore, since no plasma damage occurs during film formation, a film with fewer defects can be obtained.

The CVD method and the ALD method are film-forming methods in which a film is formed by a reaction on the surface of an object, unlike film-forming methods in which particles emitted from a target or the like are deposited. Therefore, this is a film forming method that is not easily affected by the shape of the object to be processed and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, and is therefore suitable for coating the surface of an opening with a high aspect ratio. However, since the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods such as the CVD method, which has a fast film formation rate.

In the CVD method and the ALD method, the composition of the obtained film can be controlled by the flow rate ratio of source gases. For example, in the CVD method and the ALD method, a film having an arbitrary composition can be formed by changing the flow rate ratio of source gases. Further, for example, in the CVD method and the ALD method, by changing the flow rate ratio of the raw material gas while forming the film, it is possible to form a film in which the composition changes continuously. When forming a film while changing the flow rate ratio of source gases, compared to forming a film using multiple film forming chambers, the time required for film forming can be reduced by the amount of time required for transportation and pressure adjustment. can. Therefore, it may be possible to increase the productivity of the storage device.

Note that when forming a film by the ALD method, it is preferable to use a gas that does not contain chlorine as the material gas.

This embodiment mode can be implemented in appropriate combination with the structures described in other embodiment modes.

(Embodiment 4)
In this embodiment mode, a structural example of a transistor that can be used in the semiconductor device described in the above embodiment mode or the like will be described.

<Transistor structure example 1>
A structural example of the transistor 510 will be described with reference to FIGS. 13A, 13B, and 13C. FIG. 13A is a top view of the transistor 510. FIG. 13(B) is a cross-sectional view of a portion indicated by a dashed line L1-L2 in FIG. 13(A). FIG. 13(C) is a cross-sectional view of a portion indicated by a dashed line W1-W2 in FIG. 13(A). Note that in the top view of FIG. 13(A), some elements are omitted for clarity.

13A, 13B, and 13C, a transistor 510, an insulating layer 511, an insulating layer 512, an insulating layer 514, an insulating layer 516, an insulating layer 580, an insulating layer 582, and an insulating layer functioning as interlayer films are illustrated in FIGS. Layer 584 is shown. Further, a conductive layer 546 (a conductive layer 546a and a conductive layer 546b) that is electrically connected to the transistor 510 and functions as a contact plug, and a conductive layer 503 that functions as a wiring are illustrated.

The transistor 510 includes a conductive layer 560 (a conductive layer 560a and a conductive layer 560b) functioning as a first gate electrode, a conductive layer 505 (a conductive layer 505a and a conductive layer 505b) functioning as a second gate electrode, An insulating layer 550 that functions as a first gate insulating film, an insulating layer 521, an insulating layer 522, and an insulating layer 524 that function as a second gate insulating layer, and an oxide 530 (oxidized a conductive layer 540a that functions as one of a source or a drain, a conductive layer 540b that functions as the other of a source or a drain, and an insulating layer 574.

Further, in the transistor 510 illustrated in FIG. 13, an oxide 530c, an insulating layer 550, and a conductive layer 560 are arranged in an opening provided in an insulating layer 580 with an insulating layer 574 interposed therebetween. Further, the oxide 530c, the insulating layer 550, and the conductive layer 560 are arranged between the conductive layer 540a and the conductive layer 540b.

Insulating layer 511 and insulating layer 512 function as interlayer films.

Interlayer films include silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ) or (Ba, Sr). An insulator such as TiO ₃ (BST) can be used in a single layer or in a stack. Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulator.

For example, the insulating layer 511 preferably functions as a barrier film that suppresses impurities such as water or hydrogen from entering the transistor 510 from the substrate side. Therefore, for the insulating layer 511, it is preferable to use an insulating material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the impurities are difficult to pass through). Alternatively, it is preferable to use an insulating material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (the above-mentioned oxygen is difficult to permeate). Further, for example, aluminum oxide, silicon nitride, or the like may be used as the insulating layer 511. With this structure, impurities such as hydrogen and water can be suppressed from diffusing from the substrate side of the insulating layer 511 to the transistor 510 side.

For example, the insulating layer 512 preferably has a lower dielectric constant than the insulating layer 511. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.

The conductive layer 503 is formed to be embedded in the insulating layer 512. Here, the height of the top surface of the conductive layer 503 and the height of the top surface of the insulating layer 512 can be made to be approximately the same. Note that although the conductive layer 503 is shown as a single layer, the present invention is not limited to this. For example, the conductive layer 503 may have a multilayer structure of two or more layers. Note that the conductive layer 503 is preferably made of a highly conductive material containing tungsten, copper, or aluminum as a main component.

In the transistor 510, the conductive layer 560 may function as a first gate (also referred to as a top gate) electrode. Further, the conductive layer 505 sometimes functions as a second gate (also referred to as a bottom gate) electrode. In that case, the threshold voltage of the transistor 510 can be controlled by changing the potential applied to the conductive layer 505 independently of the potential applied to the conductive layer 560 without interlocking with the potential applied to the conductive layer 560. In particular, by applying a negative potential to the conductive layer 505, the threshold voltage of the transistor 510 can be made larger than 0 V, and the off-state current can be reduced. Therefore, when a negative potential is applied to the conductive layer 505, the drain current when the potential applied to the conductive layer 560 is 0 V can be made smaller than when no negative potential is applied.

Further, for example, by providing the conductive layer 505 and the conductive layer 560 in an overlapping manner, when a potential is applied to the conductive layer 560 and the conductive layer 505, the electric field generated from the conductive layer 560 and the electric field generated from the conductive layer 505 are are connected to each other, and can cover a channel formation region formed in the oxide 530.

In other words, the channel formation region can be electrically surrounded by the electric field of the conductive layer 560 that functions as the first gate electrode and the electric field of the conductive layer 505 that functions as the second gate electrode. In this specification, a structure of a transistor in which a channel formation region is electrically surrounded by electric fields of a first gate electrode and a second gate electrode is referred to as a surrounded channel (S-channel) structure.

The insulating layer 514 and the insulating layer 516 function as interlayer films similarly to the insulating layer 511 or the insulating layer 512. For example, the insulating layer 514 preferably functions as a barrier film that suppresses impurities such as water or hydrogen from entering the transistor 510 from the substrate side. With this structure, impurities such as hydrogen and water can be suppressed from diffusing from the substrate side of the insulating layer 514 to the transistor 510 side. Further, for example, the insulating layer 516 preferably has a lower dielectric constant than the insulating layer 514. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.

In the conductive layer 505 functioning as a second gate, a conductive layer 505a is formed in contact with the inner walls of the openings of the insulating layers 514 and 516, and a conductive layer 505b is further formed inside. Here, the heights of the top surfaces of the conductive layers 505a and 505b and the top surface of the insulating layer 516 can be made to be approximately the same. Note that although the transistor 510 has a structure in which the conductive layer 505a and the conductive layer 505b are stacked, the present invention is not limited to this. For example, the conductive layer 505 may be provided as a single layer or a stacked structure of three or more layers.

Here, for the conductive layer 505a, it is preferable to use a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the impurities are difficult to pass through). Alternatively, it is preferable to use a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (the above-mentioned oxygen is difficult to permeate). Note that in this specification, the function of suppressing the diffusion of impurities or oxygen refers to the function of suppressing the diffusion of any one or all of the impurities or the oxygen.

For example, since the conductive layer 505a has a function of suppressing oxygen diffusion, the conductive layer 505b can be prevented from being oxidized and its conductivity is reduced.

Further, in the case where the conductive layer 505 also serves as a wiring, it is preferable to use a highly conductive material containing tungsten, copper, or aluminum as a main component for the conductive layer 505b. In that case, the conductive layer 503 does not necessarily need to be provided. Note that although the conductive layer 505b is illustrated as a single layer, it may have a laminated structure, for example, it may be a laminated layer of titanium, titanium nitride, and the above conductive material.

The insulating layer 521, the insulating layer 522, and the insulating layer 524 function as a second gate insulator.

Further, the insulating layer 522 preferably has barrier properties. Since the insulating layer 522 has barrier properties, it functions as a layer that suppresses entry of impurities such as hydrogen into the transistor 510 from the periphery of the transistor 510.

The insulating layer 522 is made of, for example, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ), or ( It is preferable to use an insulator containing a so-called high-k material such as Ba, Sr) TiO ₃ (BST) in a single layer or in a stacked layer. As transistors become smaller and more highly integrated, problems such as leakage current may occur due to thinning of gate insulators. By using a high-k material for the insulator that functions as a gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

For example, the insulating layer 521 is preferably thermally stable. For example, silicon oxide and silicon oxynitride are suitable because they are thermally stable. Further, by combining an insulator made of a high-k material with silicon oxide or silicon oxynitride, an insulating layer having a stacked structure that is thermally stable and has a high dielectric constant can be obtained.

Note that although FIG. 13 shows a three-layer stacked structure as the second gate insulator, it may be a single layer or a stacked structure of two or more layers. In that case, the structure is not limited to a laminated structure made of the same material, but may be a laminated structure made of different materials.

The oxide 530 having a region functioning as a channel formation region includes an oxide 530a, an oxide 530b over the oxide 530a, and an oxide 530c over the oxide 530b. By having the oxide 530a below the oxide 530b, diffusion of impurities from a structure formed below the oxide 530a to the oxide 530b can be suppressed. Further, by providing the oxide 530c over the oxide 530b, diffusion of impurities from a structure formed above the oxide 530c to the oxide 530b can be suppressed. As the oxide 530, an oxide semiconductor that is a type of metal oxide described in the above embodiments can be used.

Note that the oxide 530c is preferably provided in an opening provided in the insulating layer 580 with the insulating layer 574 interposed therebetween. When the insulating layer 574 has barrier properties, diffusion of impurities from the insulating layer 580 into the oxide 530 can be suppressed.

One of the conductive layers 540a and 540b functions as a source electrode, and the other functions as a drain electrode.

For the conductive layer 540a and the conductive layer 540b, a metal such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or an alloy containing this as a main component can be used. . In particular, a metal nitride film such as tantalum nitride is preferable because it has barrier properties against hydrogen or oxygen and has high oxidation resistance.

Further, although a single layer structure is shown in FIG. 13, a laminated structure of two or more layers may be used. For example, a tantalum nitride film and a tungsten film may be laminated. Alternatively, a titanium film and an aluminum film may be laminated. In addition, a two-layer structure in which an aluminum film is laminated on a tungsten film, a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is laminated on a titanium film, and a two-layer structure in which a copper film is laminated on a titanium film. A two-layer structure in which copper films are laminated may be used.

In addition, a three-layer structure in which a titanium film or titanium nitride film is laminated, an aluminum film or a copper film is stacked on top of the titanium film or titanium nitride film, and a titanium film or titanium nitride film is further formed on top of the titanium film or titanium nitride film, a molybdenum film or There is a three-layer structure in which a molybdenum nitride film, an aluminum film or a copper film is laminated on the molybdenum film or the molybdenum nitride film, and a molybdenum film or molybdenum nitride film is further formed thereon. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

Further, a barrier layer may be provided over the conductive layer 540. The barrier layer preferably uses a substance that has barrier properties against oxygen or hydrogen. With this structure, oxidation of the conductive layer 540 can be suppressed when the insulating layer 574 is formed.

For example, a metal oxide can be used for the barrier layer. In particular, it is preferable to use an insulating film that has barrier properties against oxygen and hydrogen, such as aluminum oxide, hafnium oxide, and gallium oxide. Alternatively, silicon nitride formed by CVD may be used.

By including the barrier layer, the range of material selection for the conductive layer 540 can be expanded. For example, for the conductive layer 540, a material having low oxidation resistance but high conductivity, such as tungsten or aluminum, can be used. Further, for example, a conductor that can be easily formed into a film or processed can be used.

Insulating layer 550 functions as a first gate insulator. The insulating layer 550 is preferably provided in the opening provided in the insulating layer 580 with the oxide 530c and the insulating layer 574 interposed therebetween.

As transistors become smaller and more highly integrated, problems such as leakage current may occur due to thinning of gate insulators. In that case, the insulating layer 550 may have a stacked structure like the second gate insulator. By making the insulator that functions as a gate insulator a laminated structure of a high-k material and a thermally stable material, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. becomes. Further, a laminated structure that is thermally stable and has a high dielectric constant can be obtained.

A conductive layer 560 functioning as a first gate electrode includes a conductive layer 560a and a conductive layer 560b over the conductive layer 560a. Similarly to the conductive layer 505a, the conductive layer 560a is preferably formed using a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. Alternatively, it is preferable to use a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules).

Since the conductive layer 560a has a function of suppressing oxygen diffusion, the material selectivity of the conductive layer 560b can be improved. In other words, by including the conductive layer 560a, oxidation of the conductive layer 560b can be suppressed, and a decrease in conductivity can be prevented.

As the conductive material having the function of suppressing oxygen diffusion, it is preferable to use, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide. Further, as the conductive layer 560a, an oxide semiconductor that can be used as the oxide 530 can be used. In that case, by forming the conductive layer 560b by a sputtering method, the electrical resistance value of the conductive layer 560a can be reduced and the conductive layer 560a can be made into a conductor. This can be called an OC (Oxide Conductor) electrode.

The conductive layer 560b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Further, since the conductive layer 560 functions as a wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. Further, the conductive layer 560b may have a laminated structure, for example, a laminated layer of titanium, titanium nitride, and the above conductive material.

An insulating layer 574 is disposed between the insulating layer 580 and the transistor 510. For the insulating layer 574, it is preferable to use an insulating material that has a function of suppressing diffusion of impurities such as water or hydrogen and oxygen. For example, it is preferable to use aluminum oxide or hafnium oxide. In addition, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide, silicon nitride oxide, or silicon nitride can also be used.

By including the insulating layer 574, impurities such as water and hydrogen included in the insulating layer 580 can be suppressed from diffusing into the oxide 530b via the oxide 530c and the insulating layer 550. Further, oxidation of the conductive layer 560 due to excess oxygen in the insulating layer 580 can be suppressed.

Insulating layer 580, insulating layer 582, and insulating layer 584 function as interlayer films.

Like the insulating layer 514, the insulating layer 582 preferably functions as a barrier insulating film that suppresses impurities such as water or hydrogen from entering the transistor 510 from the outside.

Further, the insulating layer 580 and the insulating layer 584 preferably have a lower dielectric constant than the insulating layer 582, similarly to the insulating layer 516. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.

Further, the transistor 510 may be electrically connected to other structures through plugs or wiring such as the conductive layer 546 embedded in the insulating layer 580, the insulating layer 582, and the insulating layer 584.

Further, as the material for the conductive layer 546, similarly to the conductive layer 505, a single layer or a stack of conductive materials such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used. . For example, it is preferable to use a high melting point material such as tungsten or molybdenum, which has both heat resistance and conductivity. Alternatively, it is preferable to use a low resistance conductive material such as aluminum or copper. Wiring resistance can be lowered by using a low resistance conductive material.

For example, as the conductive layer 546, a laminated structure of tantalum nitride, which is a conductor having barrier properties against hydrogen and oxygen, and tungsten, which has high conductivity, can be used to improve conductivity as a wiring. Diffusion of impurities from the outside can be suppressed while maintaining the content.

With the above structure, a semiconductor device including a transistor including an oxide semiconductor with a large on-state current can be provided. Alternatively, a semiconductor device including a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, it is possible to provide a semiconductor device that suppresses fluctuations in electrical characteristics, has stable electrical characteristics, and has improved reliability.

<Transistor structure example 2>
A structural example of the transistor 510 will be described with reference to FIGS. 14A, 14B, and 14C. FIG. 14A is a top view of the transistor 520. FIG. 14(B) is a cross-sectional view of a portion indicated by a dashed line L1-L2 in FIG. 14(A). FIG. 14(C) is a cross-sectional view of a portion indicated by a dashed line W1-W2 in FIG. 14(A). Note that in the top view of FIG. 14(A), some elements are omitted for clarity.

Transistor 520 is a modification of transistor 510. Therefore, in order to avoid repeating the description, mainly the points different from the transistor 510 will be described.

The transistor 520 has a region where a conductive layer 540 (a conductive layer 540a and a conductive layer 540b), an oxide 530c, an insulating layer 550, and a conductive layer 560 overlap. With this structure, a transistor with high on-state current can be provided. Further, a transistor with high controllability can be provided.

A conductive layer 560 functioning as a first gate electrode includes a conductive layer 560a and a conductive layer 560b over the conductive layer 560a. Similarly to the conductive layer 505a, the conductive layer 560a is preferably formed using a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. Alternatively, it is preferable to use a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules).

Since the conductive layer 560a has a function of suppressing oxygen diffusion, the material selectivity of the conductive layer 560b can be improved. In other words, by including the conductive layer 560a, oxidation of the conductive layer 560b can be suppressed, and a decrease in conductivity can be prevented.

Further, it is preferable that the insulating layer 574 be provided so as to cover the upper surface and side surfaces of the conductive layer 560, the side surfaces of the insulating layer 550, and the side surfaces of the oxide 530c. Note that the insulating layer 574 is preferably formed using an insulating material that has a function of suppressing diffusion of impurities such as water or hydrogen, and oxygen. For example, it is preferable to use aluminum oxide or hafnium oxide. In addition, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide, silicon nitride oxide, or silicon nitride can also be used.

By providing the insulating layer 574, oxidation of the conductive layer 560 can be suppressed. Further, by providing the insulating layer 574, impurities such as water and hydrogen included in the insulating layer 580 can be suppressed from diffusing into the transistor 520.

Further, an insulating layer 576 (an insulating layer 576a and an insulating layer 576b) having barrier properties may be provided between the conductive layer 546 and the insulating layer 580. By providing the insulating layer 576, oxygen in the insulating layer 580 can be prevented from reacting with the conductive layer 546, and oxidation of the conductive layer 546 can be suppressed.

Further, by providing the insulating layer 576 having barrier properties, the range of material selection for the conductor used for the plug and wiring can be expanded. For example, by using a metal material that has a property of absorbing oxygen and has high conductivity for the conductive layer 546, a semiconductor device with low power consumption can be provided. Specifically, a material having low oxidation resistance but high conductivity, such as tungsten or aluminum, can be used. Further, for example, a conductor that can be easily formed into a film or processed can be used.

<Transistor structure example 3>
A structural example of the transistor 535 will be described with reference to FIGS. 15A, 15B, and 15C. FIG. 15A is a top view of the transistor 535. FIG. 15(B) is a cross-sectional view of the L1-L2 portion indicated by the dashed line in FIG. 15(A). FIG. 15(C) is a cross-sectional view of the W1-W2 portion indicated by the dashed line in FIG. 15(A). Note that in the top view of FIG. 15(A), some elements are omitted for clarity of illustration.

Transistor 535 is a modification of transistor 510. Therefore, in order to avoid repeating the description, mainly the points different from the transistor 510 will be described.

In the transistor 510, part of the insulating layer 574 is provided within an opening provided in the insulating layer 580, and is provided to cover the side surface of the conductive layer 560. On the other hand, in the transistor 535, an opening is formed by removing part of the insulating layer 580 and the insulating layer 574.

Further, an insulating layer 576 (an insulating layer 576a and an insulating layer 576b) having barrier properties may be provided between the conductive layer 546 and the insulating layer 580. By providing the insulating layer 576, oxygen in the insulating layer 580 can be prevented from reacting with the conductive layer 546, and oxidation of the conductive layer 546 can be suppressed.

Note that when an oxide semiconductor is used as the oxide 530, it is preferable that the oxide has a stacked structure using oxides having different atomic ratios of metal atoms. Specifically, in the metal oxide used for the oxide 530a, the atomic ratio of the element M among the constituent elements is larger than the atomic ratio of the element M among the constituent elements in the metal oxide used for the oxide 530b. is preferred. Further, in the metal oxide used for the oxide 530a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 530b. Further, in the metal oxide used for the oxide 530b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 530a. Further, as the oxide 530c, a metal oxide that can be used for the oxide 530a or the oxide 530b can be used.

The oxide 530a, the oxide 530b, and the oxide 530c preferably have crystallinity, and it is particularly preferable to use CAAC-OS. Crystalline oxides such as CAAC-OS have few impurities and defects (oxygen vacancies, etc.) and have a highly crystalline and dense structure. Therefore, extraction of oxygen from the oxide 530b by the source electrode or the drain electrode can be suppressed. As a result, even if heat treatment is performed, extraction of oxygen from the oxide 530b can be reduced, so the transistor 535 is stable against high temperatures (so-called thermal budget) during the manufacturing process.

Note that one or both of the oxide 530a and the oxide 530c may be omitted. The oxide 530 may be a single layer of the oxide 530b. When the oxide 530 is a stack of oxide 530a, oxide 530b, and oxide 530c, the energy at the bottom of the conduction band of oxide 530a and oxide 530c is higher than the energy at the bottom of the conduction band of oxide 530b. It is preferable. In other words, it is preferable that the electron affinity of the oxide 530a and the oxide 530c is smaller than that of the oxide 530b. In this case, the oxide 530c is preferably a metal oxide that can be used for the oxide 530a. Specifically, in the metal oxide used for the oxide 530c, the atomic ratio of the element M among the constituent elements is larger than the atomic ratio of the element M among the constituent elements in the metal oxide used for the oxide 530b. It is preferable. Further, in the metal oxide used for the oxide 530c, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 530b. Further, in the metal oxide used for the oxide 530b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 530c.

Here, at the junction of oxide 530a, oxide 530b, and oxide 530c, the energy level at the lower end of the conduction band changes gently. In other words, the energy level at the lower end of the conduction band at the junction of the oxide 530a, the oxide 530b, and the oxide 530c can be said to change continuously or form a continuous junction. In order to do this, it is preferable to lower the defect level density of the mixed layer formed at the interface between the oxide 530a and the oxide 530b and the interface between the oxide 530b and the oxide 530c.

Specifically, the oxide 530a and the oxide 530b, and the oxide 530b and the oxide 530c have a common element other than oxygen (as a main component), thereby forming a mixed layer with a low defect level density. can do. For example, when the oxide 530b is an In--Ga--Zn oxide, an In--Ga--Zn oxide, a Ga--Zn oxide, a gallium oxide, or the like may be used as the oxide 530a and the oxide 530c. Further, the oxide 530c may have a layered structure. For example, a stacked structure of an In-Ga-Zn oxide and a Ga-Zn oxide on the In-Ga-Zn oxide, or a stacked structure of an In-Ga-Zn oxide and a Ga-Zn oxide on the In-Ga-Zn oxide. A laminated structure with gallium oxide can be used. In other words, a stacked structure of an In-Ga-Zn oxide and an oxide not containing In may be used as the oxide 530c.

Specifically, a metal oxide with In:Ga:Zn=1:3:4 [atomic ratio] or 1:1:0.5 [atomic ratio] may be used as the oxide 530a. Further, as the oxide 530b, a metal oxide with In:Ga:Zn=4:2:3 [atomic ratio] or 3:1:2 [atomic ratio] may be used. In addition, as the oxide 530c, In:Ga:Zn=1:3:4 [atomic ratio], In:Ga:Zn=4:2:3 [atomic ratio], Ga:Zn=2:1 [atomic ratio]. A metal oxide having an atomic ratio of Ga:Zn of 2:5 may be used. Further, as a specific example of the case where the oxide 530c has a layered structure, a layered structure of In:Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn=2:1 [atomic ratio] Structure, layered structure of In:Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn=2:5 [atomic ratio], In:Ga:Zn=4:2:3 [atomic ratio] number ratio] and a laminated structure of gallium oxide.

At this time, the main path of carriers is through the oxide 530b. By providing the oxide 530a and the oxide 530c with the above structure, the density of defect levels at the interface between the oxide 530a and the oxide 530b and at the interface between the oxide 530b and the oxide 530c can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 535 can obtain high on-current and high frequency characteristics. Note that when the oxide 530c has a layered structure, in addition to the effect of lowering the defect level density at the interface between the oxide 530b and the oxide 530c, the constituent elements of the oxide 530c are It is expected that the spread of the virus will be suppressed. More specifically, since the oxide 530c has a layered structure and the oxide not containing In is located above the layered structure, In that may diffuse toward the insulating layer 550 can be suppressed. Since the insulating layer 550 functions as a gate insulator, if In is diffused, the characteristics of the transistor will be deteriorated. Therefore, by forming the oxide 530c into a layered structure, a highly reliable display device can be provided.

As the oxide 530, a metal oxide that functions as an oxide semiconductor is preferably used. For example, as the metal oxide that becomes the channel formation region of the oxide 530, it is preferable to use one with a band gap of 2 eV or more, preferably 2.5 eV or more. In this way, by using a metal oxide with a large band gap, the off-state current of the transistor can be reduced. By using such a transistor, a semiconductor device with low power consumption can be provided.

This embodiment mode can be implemented in appropriate combination with the structures described in other embodiment modes.

(Embodiment 5)
This embodiment mode shows an example of an electronic component and an electronic device in which the storage device shown in the above embodiment mode is incorporated.

<Electronic parts>
First, an example of an electronic component incorporating the storage device 300 will be described using FIGS. 16(A) and 16(B).

FIG. 16A shows a perspective view of an electronic component 700 and a board (mounted board 704) on which the electronic component 700 is mounted. The electronic component 700 shown in FIG. 16(A) is an IC chip and has leads and a circuit section. The electronic component 700 is mounted on a printed circuit board 702, for example. A mounting board 704 is completed by combining a plurality of such IC chips and electrically connecting them on the printed circuit board 702.

As a circuit section of electronic component 700, memory device 300 shown in the above embodiment is provided. In FIG. 16A, a QFP (Quad Flat Package) is applied to the package of the electronic component 700, but the form of the package is not limited to this.

FIG. 16(B) shows a perspective view of the electronic component 730. The electronic component 730 is an example of a SiP (System in package) or an MCM (Multi Chip Module). In the electronic component 730, an interposer 731 is provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of storage devices 300 are provided on the interposer 731.

In the electronic component 730, an example is shown in which the storage device 300 is used as a high bandwidth memory (HBM). Further, as the semiconductor device 735, an integrated circuit (semiconductor device) such as a CPU, GPU, or FPGA can be used.

The package substrate 732 can be a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like. As the interposer 731, a silicon interposer, a resin interposer, or the like can be used.

The interposer 731 has a plurality of wiring lines and has a function of electrically connecting a plurality of integrated circuits having different terminal pitches. The plurality of wirings are provided in a single layer or in multiple layers. Further, the interposer 731 has a function of electrically connecting the integrated circuit provided on the interposer 731 to the electrodes provided on the package substrate 732. For these reasons, interposers are sometimes called "rewiring boards" or "intermediate boards." Further, in some cases, a through electrode is provided in the interposer 731, and the integrated circuit and the package substrate 732 are electrically connected using the through electrode. Further, in the silicon interposer, TSV (Through Silicon Via) can also be used as the through electrode.

It is preferable to use a silicon interposer as the interposer 731. Since silicon interposers do not require active elements, they can be manufactured at lower cost than integrated circuits. On the other hand, since wiring formation in a silicon interposer can be performed by a semiconductor process, it is easy to form fine wiring, which is difficult to do with a resin interposer.

In HBM, it is necessary to connect many wires to realize a wide memory bandwidth. For this reason, an interposer mounting an HBM is required to form fine and high-density wiring. Therefore, it is preferable to use a silicon interposer as the interposer for mounting the HBM.

Further, in SiP, MCM, etc. using a silicon interposer, reliability is less likely to deteriorate due to a difference in expansion coefficient between the integrated circuit and the interposer. Furthermore, since the silicon interposer has a highly flat surface, poor connection between the integrated circuit provided on the silicon interposer and the silicon interposer is less likely to occur. In particular, it is preferable to use a silicon interposer in a 2.5D package (2.5-dimensional packaging) in which a plurality of integrated circuits are arranged side by side on an interposer.

Further, a heat sink (heat sink) may be provided to overlap the electronic component 730. When a heat sink is provided, it is preferable that the heights of the integrated circuits provided on the interposer 731 are the same. For example, in the electronic component 730 shown in this embodiment, it is preferable that the storage device 300 and the semiconductor device 735 have the same height.

In order to mount the electronic component 730 on another substrate, an electrode 733 may be provided at the bottom of the package substrate 732. FIG. 16B shows an example in which the electrode 733 is formed of a solder ball. By providing solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be realized. Further, the electrode 733 may be formed of a conductive pin. By providing conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be realized.

The electronic component 730 can be mounted on other boards using various mounting methods, not limited to BGA and PGA. For example, SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-lead package), or QFN (Quad Flat Use implementation methods such as Non-leaded package) be able to.

<Electronic equipment>
Next, an example of an electronic device including the above electronic component will be described using FIG. 17.

The robot 7100 includes an illuminance sensor, a microphone, a camera, a speaker, a display, various sensors (infrared sensor, ultrasonic sensor, acceleration sensor, piezo sensor, optical sensor, gyro sensor, etc.), a movement mechanism, and the like. The electronic component 730 includes a processor and the like, and has a function of controlling these peripheral devices. For example, the electronic component 700 has a function of storing data acquired by a sensor.

Microphones have the ability to detect audio signals such as the user's voice and environmental sounds. The speaker also has the function of emitting audio signals such as voice and warning sounds. The robot 7100 can analyze an audio signal input through a microphone and emit a necessary audio signal from a speaker. In the robot 7100, it is possible to communicate with the user using a microphone and a speaker.

The camera has a function of capturing an image of the surroundings of the robot 7100. Furthermore, the robot 7100 has a function of moving using a movement mechanism. The robot 7100 can capture images of its surroundings using a camera, analyze the images, and detect the presence or absence of obstacles during movement.

The flying object 7120 includes a propeller, a camera, a battery, and the like, and has the ability to fly autonomously. The electronic component 730 has a function of controlling these peripheral devices.

For example, image data taken with a camera is stored in the electronic component 700. The electronic component 730 can analyze image data and detect the presence or absence of obstacles during movement. Further, the electronic component 730 allows the remaining battery power to be estimated from changes in the battery's storage capacity.

The cleaning robot 7140 has a display placed on the top surface, a plurality of cameras placed on the side, a brush, operation buttons, various sensors, and the like. Although not shown, the cleaning robot 7140 is equipped with tires, a suction port, and the like. The cleaning robot 7140 is self-propelled, can detect dirt, and can suck up dirt from a suction port provided on the bottom surface.

For example, the electronic component 730 can analyze an image taken by a camera and determine the presence or absence of an obstacle such as a wall, furniture, or step. In addition, if image analysis detects an object that is likely to become entangled with the brush, such as wiring, the brush can stop rotating.

The automobile 7160 has an engine, tires, brakes, a steering device, a camera, and the like. For example, the electronic component 730 performs control to optimize the driving condition of the automobile 7160 based on data such as navigation information, speed, engine condition, gear selection condition, and frequency of brake use. For example, image data taken with a camera is stored in the electronic component 700.

The electronic component 700 and/or the electronic component 730 can be incorporated into a television receiver (TV) device 7200, a smartphone 7210, a PC 7220 (personal computer), 7230, a game console 7240, a game console 7260, and the like.

For example, electronic component 730 built into TV device 7200 can function as an image engine. For example, the electronic component 730 performs image processing such as noise removal and resolution up-conversion.

Smartphone 7210 is an example of a mobile information terminal. The smartphone 7210 has a microphone, a camera, a speaker, various sensors, and a display section. Electronic components 730 control these peripheral devices.

PC7220 and PC7230 are examples of a notebook PC and a stationary PC, respectively. A keyboard 7232 and a monitor device 7233 can be connected to the PC 7230 wirelessly or by wire. Game machine 7240 is an example of a portable game machine. Game machine 7260 is an example of a stationary game machine. A controller 7262 is connected to the game machine 7260 wirelessly or by wire. Controller 7262 may also incorporate electronic components 700 and/or electronic components 730.

This embodiment mode can be implemented in appropriate combination with the structures described in other embodiment modes.

(Embodiment 6)
In this embodiment, an application example of a memory device using the semiconductor device shown in the previous embodiment will be described. The semiconductor device described in the above embodiments can be used, for example, as a storage device of various electronic devices (for example, information terminals, computers, smartphones, electronic book terminals, digital cameras (including video cameras), recording/playback devices, navigation systems, etc.). Applicable to Note that the computer here includes a tablet computer, a notebook computer, a desktop computer, and a large computer such as a server system. Alternatively, the semiconductor device described in the above embodiment is applied to various removable storage devices such as a memory card (for example, an SD card), a USB memory, and an SSD (solid state drive). FIG. 18 schematically shows several configuration examples of removable storage devices. For example, the semiconductor device shown in the previous embodiment is processed into a packaged memory chip and used in various storage devices and removable memories.

FIG. 18(A) is a schematic diagram of a USB memory. USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a board 1104. The board 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the substrate 1104. The semiconductor device described in the previous embodiment can be incorporated into the memory chip 1105 of the substrate 1104 or the like.

FIG. 18(B) is a schematic diagram of the external appearance of the SD card, and FIG. 18(C) is a schematic diagram of the internal structure of the SD card. The SD card 1110 has a housing 1111, a connector 1112, and a board 1113. The board 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113. By providing a memory chip 1114 also on the back side of the substrate 1113, the capacity of the SD card 1110 can be increased. Further, a wireless chip having a wireless communication function may be provided on the substrate 1113. Thereby, data can be read from and written to the memory chip 1114 through wireless communication between the host device and the SD card 1110. The semiconductor device described in the previous embodiment can be incorporated into the memory chip 1114 of the substrate 1113 or the like.

FIG. 18(D) is a schematic diagram of the external appearance of the SSD, and FIG. 18(E) is a schematic diagram of the internal structure of the SSD. SSD 1150 has a housing 1151, a connector 1152, and a board 1153. The board 1153 is housed in a housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are attached to the substrate 1153. The memory chip 1155 is a work memory of the controller chip 1156, and may be a DOSRAM chip, for example. By providing a memory chip 1154 also on the back side of the substrate 1153, the capacity of the SSD 1150 can be increased. The semiconductor device described in the previous embodiment can be incorporated into the memory chip 1154 of the substrate 1153 or the like.

This embodiment mode can be implemented in appropriate combination with the structures described in other embodiment modes.

100: Semiconductor device, 110: Voltage generation circuit, 120: Voltage holding circuit, 130: Temperature detection circuit, 131: Temperature sensor, 132: Analog-digital conversion circuit, 140: Voltage control circuit, 145: Logic circuit, 146: Voltage generation circuit

Claims (6)

A semiconductor device comprising a first circuit, a second circuit, a third circuit, a fourth circuit, and an output terminal,
The first circuit has a function of supplying voltage to the second circuit,
The second circuit has a function of supplying a first voltage to the output terminal and a function of holding the voltage of the output terminal,
The third circuit has a function of acquiring temperature information and a function of supplying a digital signal according to the temperature information to the fourth circuit,
The fourth circuit has a function of outputting a second voltage according to the digital signal,
The voltage of the output terminal is the sum of the first voltage and the second voltage,
the output terminal is electrically connected to the back gate of the first transistor,
A semiconductor device, wherein a channel length of a second transistor included in the second circuit is larger than a channel length of the first transistor. In claim 1,
The second circuit has a plurality of transistors including the second transistor,
A semiconductor device, wherein the plurality of transistors are connected in series . In claim 2,
A semiconductor device in which the second transistor includes an oxide semiconductor in a channel formation region. In any one of claims 1 to 3,
The output terminal is electrically connected to a back gate of a third transistor and a back gate of a fourth transistor,
A semiconductor device in which a channel length of the second transistor is larger than a channel length of the third transistor and a channel length of the fourth transistor. In any one of claims 1 to 4,
The fourth circuit includes a plurality of capacitive elements,
A semiconductor device, wherein each of the plurality of capacitive elements is electrically connected to the output terminal. In claim 5,
A semiconductor device, wherein each of the plurality of capacitive elements has a different capacitance value.

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