JP7418869B2 - Manufacturing method of semiconductor device - Google Patents

Description

The present invention relates to a manufacturing technology for solar cells and semiconductor devices, and is effective when applied to, for example, a solar cell in which an n-type diffusion layer and a p-type diffusion layer are formed on the back side of a semiconductor substrate opposite to the light-receiving surface. Regarding technology.

Renewable energy can be used without depleting energy resources and does not emit carbon dioxide, which causes global warming, during power generation, so it is used as a clean energy alternative to fossil fuels such as oil, coal, and natural gas. Attention has been paid.

One type of renewable energy is sunlight, and a power generation method that uses solar cells to directly convert sunlight into electricity is called solar power generation. A solar cell is a photoelectric conversion element that absorbs light energy and converts it into electrical energy.

There are various types of solar cells, including organic solar cells and multijunction solar cells, but crystalline silicon solar cells are the most popular. The biggest challenge for crystalline silicon solar cells is achieving both high efficiency and low cost. To improve the efficiency of crystalline silicon solar cells, research and development of various cells such as PERC cells (Passivated Emitter and Rear Cells) and bifacial cells are underway, but electrodes are only formed on the back side of the semiconductor substrate. The back electrode type cell, which has a larger light-receiving area on the front side of the semiconductor substrate, exhibits the highest photoelectric conversion efficiency.

For example, Non-Patent Document 1, Non-Patent Document 2, Non-Patent Document 3, and Patent Document 1 describe techniques related to back-electrode solar cells using back-electrode cells.

Evan Franklin et al., “Design, fabrication and characterization of a 24.4% efficient interdigitated back contact solar cell”, PROGRESS IN PHOTOVOLTAICS: RESEARCH AND APPLICATION vol. 24, (2016) 411-427 Nicholas Bateman et al., “High quality ion implanted boron emitters in an interdigitated back contact solar cell with 20% efficiency”, Energy Procedia 8 (2011) 509-514 R. Muller at al., “Back-junction back-contact n-type silicon solar cell with diffused boron emitter locally blocked by implanted phosphorus” Applied Physics Letters vol. 105, (2014) 103503-1-103503-4

JP 2019-161052 Publication

In the manufacturing process of a semiconductor device, patterning and etching by photolithography are used to form, for example, an n-type diffusion layer and a p-type diffusion layer having different conductivity types on the same surface of a semiconductor substrate. In this regard, photolithography techniques require numerous steps such as resist coating, exposure, development, and cleaning. In particular, when forming an n-type diffusion layer and a p-type diffusion layer with different conductivity types on the same surface of a semiconductor substrate, it is necessary to perform a photolithography process consisting of a large number of steps twice, which increases the number of steps. There are concerns that manufacturing costs will rise due to this. That is, in order to reduce manufacturing costs, a technology is desired that can form an n-type diffusion layer and a p-type diffusion layer of different conductivity types on the same surface of a semiconductor substrate without using photolithography technology.

A method for manufacturing a semiconductor device in one embodiment includes (a) preparing a mask having an opening, and (b) implanting phosphorus ions from the first surface side of a semiconductor substrate through the mask. (c) after the step (b), introducing phosphorus into the first region of the semiconductor substrate exposed from the opening, excluding the second region of the semiconductor substrate covered by the semiconductor substrate; and a step of oxidizing the first surface. Furthermore, the method for manufacturing a semiconductor device in one embodiment includes (d) etching the oxide film formed on the first surface of the semiconductor substrate so as to reduce the thickness of the oxide film, and (e) (d) ) After the step, a step of introducing boron into the second region excluding the first region by introducing boron from the first surface side of the semiconductor substrate using the oxide film formed on the first region as a mask. , (f) After the step (e), the step of removing the oxide film formed on the first surface is provided.

A solar cell in one embodiment includes a semiconductor substrate having a light-receiving surface and a back surface opposite to the light-receiving surface, a plurality of phosphorus diffusion layers formed in a plurality of first regions on the back surface, and a second region on the back surface. and a boron diffusion layer formed in. At this time, the plurality of phosphorus diffusion layers constitute a dot pattern in plan view.

According to one embodiment, manufacturing costs of semiconductor devices can be reduced.

FIG. 1 is a cross-sectional view showing a schematic configuration of a solar cell. It is a sectional view showing a manufacturing process of a solar cell in an embodiment. FIG. 3 is a cross-sectional view showing the solar cell manufacturing process following FIG. 2. FIG. FIG. 4 is a cross-sectional view showing the manufacturing process of the solar cell following FIG. 3 . FIG. 5 is a cross-sectional view showing the manufacturing process of the solar cell following FIG. 4 . FIG. 6 is a cross-sectional view showing the manufacturing process of the solar cell following FIG. 5 . FIG. 7 is a cross-sectional view showing the solar cell manufacturing process following FIG. 6 . FIG. 8 is a cross-sectional view showing the manufacturing process of the solar cell following FIG. 7 . It is a sectional view showing a manufacturing process of a solar cell in a modification. 10 is a cross-sectional view showing the solar cell manufacturing process following FIG. 9. FIG. 11 is a cross-sectional view showing the solar cell manufacturing process following FIG. 10. FIG. FIG. 12 is a cross-sectional view showing the manufacturing process of the solar cell following FIG. 11 . 7 is a graph showing the relationship between the thickness of a silicon oxide film and etching time. 2 is a table showing the results of verifying whether or not boron penetrates into the inside of a semiconductor substrate depending on the thickness of a silicon oxide film formed on the semiconductor substrate. (a) and (b) are scanning capacitance microscope images of an emitter layer and a BSF layer manufactured by the solar cell manufacturing method in the embodiment. (a) is a plan view showing an example of the planar layout on the back side of a solar cell, and (b) is a plan view showing an example of the configuration of a mask substrate used in the method for manufacturing the solar cell shown in (a). be. (a) is a plan view showing an example of the planar layout on the back side of a solar cell, and (b) is a plan view showing an example of the configuration of a mask substrate used in the method for manufacturing the solar cell shown in (a). be. FIG. 2 is a plan view showing a configuration example of a mask substrate that is difficult to manufacture.

In all the drawings for explaining the embodiment, the same members are designated by the same reference numerals in principle, and repeated explanations thereof will be omitted. Note that, in order to make the drawings easier to understand, hatching may be added even in a plan view.

The technical idea of this embodiment can be widely used in the manufacturing process of semiconductor devices, including, for example, the process of forming an n-type diffusion layer and a p-type diffusion layer of different conductivity types on the same surface of a semiconductor substrate. However, the technical idea of this embodiment will be explained below, particularly by taking as an example the manufacturing process of a back electrode type crystalline silicon solar cell.

<Room for improvement in the manufacturing process of back-electrode crystalline silicon solar cells>
A back electrode type crystalline silicon solar cell has an emitter layer and a BSF (Back Surface Field) layer on the back surface of a semiconductor substrate opposite to the light receiving surface. Generally, an n-type silicon substrate is used to form a boron diffusion layer, which is a p-type diffusion layer, which becomes an emitter layer, and a phosphorus diffusion layer, which is an n-type diffusion layer, which becomes a BSF layer. In this way, the back electrode type crystalline silicon solar cell has a very complicated manufacturing process because it is necessary to form diffusion layers of different conductivity types on the same surface (back surface). This is a factor that increases the cost of back electrode type crystalline silicon solar cells, and simplification of the manufacturing process is desired.

For example, patterning technology is required to form diffusion layers of different conductivity types on the same surface (back surface). Specifically, at least two patterning steps are required in the step of forming the boron diffusion layer constituting the emitter layer and the step of forming the phosphorus diffusion layer constituting the BSF layer (see Non-Patent Document 1). .

According to Non-Patent Document 1, after forming a first oxide film that functions as a phosphorus diffusion prevention film, openings are formed in the first oxide film in the BSF region using photolithography patterning and etching to prevent phosphorus diffusion. A phosphorus diffusion layer is formed by performing the diffusion. Next, after forming a second oxide film that functions as a boron diffusion prevention film, an opening is formed in the second oxide film in the emitter region using photolithography patterning and etching to diffuse boron. This forms a boron diffusion layer. Even when boron is diffused first, patterning using photolithography is required twice.

In this way, when forming a boron diffusion layer and a phosphorus diffusion layer using photolithography, highly accurate positioning is possible by using photolithography, and an appropriate An interval (hereinafter, this interval will be referred to as a gap in this specification) can be provided. However, the photolithography process includes a large number of steps, such as a resist coating process, an exposure process, a development process, and a cleaning process. For this reason, when manufacturing a back-electrode crystalline silicon solar cell, a very complicated photolithography process is performed twice to form an emitter layer and a BSF layer with different conductivity types on the back surface of a semiconductor substrate. There is a concern that manufacturing costs will rise due to the increase in the number of steps.

Regarding this point, for example, as shown in Non-Patent Document 2, a phosphorus diffusion layer and a boron diffusion layer having different conductivity types are formed on the same surface by an ion implantation method using a mask without using photolithography technology. A technique to do this has been proposed. Specifically, according to the technique described in Non-Patent Document 2, patterning is performed by photolithography using an ion implantation method using two masks that have openings only in the regions where the phosphorus diffusion layer or the boron diffusion layer is to be formed. An emitter layer (boron diffusion layer) and a BSF layer (phosphorus diffusion layer) can be formed without performing any steps. However, according to this technology, it is very difficult to align the phosphorus implantation mask and the boron implantation mask, and the phosphorus diffusion layer and the boron diffusion layer overlap, resulting in the formation of a back-electrode crystalline silicon solar cell. There is a concern that this may lead to performance deterioration.

In this regard, for example, as shown in Non-Patent Document 3, a technique has been proposed in which a phosphorus diffusion layer and a boron diffusion layer are formed using only a phosphorus implantation mask. Specifically, according to the technique described in Non-Patent Document 3, phosphorus is implanted by an ion implantation method using a mask with openings formed only in the phosphorus implantation region, and then a semiconductor is implanted without using a mask. By diffusing boron over the entire back surface of the substrate by a thermal diffusion method, a boron diffusion layer can be formed in areas other than the phosphorus diffusion layer formation region. However, according to this technology, boron of the opposite conductivity type also enters the inside of the phosphorus diffusion layer, resulting in counter-doping, and as a result, recombination centers are formed inside the phosphorus diffusion layer, resulting in the formation of back electrode type crystalline silicon solar cells. There is a concern that this may lead to performance deterioration.

Therefore, in this embodiment, a phosphorus diffusion layer and a boron diffusion layer having different conductivity types can be formed on the same surface (back surface) of a semiconductor substrate without using photolithography technology, and Efforts have been made to create a back-electrode crystalline silicon solar cell that can suppress the formation of boron-mixed regions. In the following, the technical idea of this embodiment, which has this contrivance, will be explained with reference to the drawings.

<Configuration of back electrode type crystalline silicon solar cell>
FIG. 1 is a cross-sectional view showing a schematic configuration of a back electrode type crystalline silicon solar cell.

In FIG. 1, a back electrode type crystalline silicon solar cell 1 has a semiconductor substrate 10 made of, for example, crystalline silicon into which n-type impurities are introduced. This semiconductor substrate 10 has a front surface 100a, which is a light-receiving surface, and a back surface 100b, which is opposite to the front surface 100a. The surface 100a of the semiconductor substrate 10 has an uneven structure called a texture structure, so that the surface 100a of the semiconductor substrate 10 is composed of an uneven surface. Thereby, the reflectance of sunlight entering from the surface 100a side of the semiconductor substrate 10 can be reduced. That is, the texture structure formed on the surface 100a of the semiconductor substrate 10 has a function of suppressing reflection of sunlight incident from the surface 100a side.

A phosphorus diffusion layer 11 into which phosphorus as an n-type impurity is introduced is formed on the surface 100a of the semiconductor substrate 10. The phosphorus diffusion layer 11 formed on the surface 100a has a function of suppressing hole recombination on the surface 100a. For example, when sunlight is irradiated into the semiconductor substrate 10 from the surface 100a side of the semiconductor substrate 10, the light energy of the sunlight is absorbed in the semiconductor substrate 10, and electrons in the valence band are excited to the conduction band. , electron-hole pairs are formed inside the semiconductor substrate 10. When holes, which are minority carriers generated at this time, recombine with electrons and disappear, the photoelectric conversion efficiency of the solar cell decreases. For this reason, the phosphorus diffusion layer 11 is provided to suppress recombination of holes and electrons on the surface 100a of the semiconductor substrate 10. Specifically, the phosphorus diffusion layer 11 is an n-type semiconductor layer and contains phosphorus as a donor (conductivity type impurity). Phosphorus, which is a donor, releases one electron into the conduction band and becomes positively charged. Therefore, since a large amount of phosphorus, which is a positively charged donor, exists inside the phosphorus diffusion layer 11, by forming this phosphorus diffusion layer 11 on the surface 100a of the semiconductor substrate 10, it is possible to The holes are repelled from the surface 100a of the semiconductor substrate 10 by the electrical repulsion between the holes and the positively charged donor. As a result, the holes are moved away from the surface 100a of the semiconductor substrate 10, so that recombination of electrons and holes on the surface 100a of the semiconductor substrate 10 is suppressed.

Subsequently, in FIG. 1, a texture structure is also formed on the back surface 100b of the semiconductor substrate 10. By forming the texture structure also on the back surface 100b of the semiconductor substrate 10 in this way, the current-voltage characteristics (IV characteristics) of the solar cell can be improved.

Next, as shown in FIG. 1, on the back surface 100b of the semiconductor substrate 10, a BSF (Back Surface Field) layer 12 made of a phosphorus diffusion layer and an emitter layer 13 made of a boron diffusion layer are formed. There is. An insulating layer 14 is formed to cover the back surface 100b of the semiconductor substrate 10, and the back electrode type crystalline silicon solar cell 1 has a BSF electrode 15 that penetrates this insulating layer 14 and reaches the BSF layer 12, and It has an emitter electrode 16a and an emitter electrode 16b that penetrate the layer 14 and reach the emitter layer 13.

Here, like the phosphorus diffusion layer 11 formed on the surface 100a, the BSF layer 12 composed of a phosphorus diffusion layer has a function of keeping holes away and suppressing recombination of holes and electrons. In addition, together with the BSF electrode 15, it also functions as an electrode for extracting electrons to the outside. On the other hand, the emitter layer 13 made of a boron diffusion layer which is a p-type semiconductor layer has a function of forming a pn junction with the semiconductor substrate 10, and also has the function of forming a pn junction with the semiconductor substrate 10. It functions as an electrode for extracting holes to the outside. In this way, the back electrode type crystalline silicon solar cell 1 is constructed.

In the back electrode type crystalline silicon solar cell 1 shown in FIG. , the back surface 100b of the semiconductor substrate 10 has the BSF electrode 15 and the emitter electrode 16a (16b). In other words, the back electrode type crystalline silicon solar cell 1 shown in FIG. 1 does not have an electrode on the front surface 100a side, which is the light-receiving surface of the semiconductor substrate 10. Thereby, in the back electrode type crystalline silicon solar cell 1, the light receiving area can be increased without being obstructed by the electrodes, so that the photoelectric conversion efficiency can be improved.

<Operation of back electrode type crystalline silicon solar cell>
The back electrode type crystalline silicon solar cell 1 is configured as described above, and the operation of the back electrode type crystalline silicon solar cell 1 will be described below.

First, in FIG. 1, when sunlight including visible light and infrared light is irradiated from above the surface 100a which is the light-receiving surface of the back electrode type crystalline silicon solar cell 1, the structure of the back electrode type crystalline silicon solar cell 1 is Sunlight irradiates the inside of the semiconductor substrate 10, which is an element. Specifically, sunlight enters the semiconductor substrate 10, the pn junction formed in the boundary region between the semiconductor substrate 10 and the emitter layer 16a (16b), and the BSF layer 12. At this time, out of sunlight, light having optical energy larger than the band gap of silicon is absorbed. Specifically, electrons existing in the valence band receive light energy supplied from sunlight and are excited to the conduction band. As a result, electrons are accumulated in the conduction band and holes are generated in the valence band. In this way, when the back electrode type crystalline silicon solar cell 10 is irradiated with sunlight, light having optical energy larger than the band gap of silicon contained in the sunlight is absorbed, and electrons are excited in the conduction band. At the same time, holes are generated in the valence band. Then, electrons are accumulated in the semiconductor substrate 10 and BSF layer 12 that constitute one side of the pn junction, while holes are accumulated in the emitter layer 13 that constitutes the other side of the pn junction. As a result, an electromotive force is generated between the BSF electrode 15 and the emitter electrode 16a (16b). For example, when a load is connected between the BSF electrode 15 and the emitter electrode 16a (16b), electrons flow from the BSF electrode 15 through the load to the emitter electrode 16a (16b). In other words, current flows from the emitter electrode 16a (16b) to the BSF electrode 15 through the load.

By operating the back electrode type crystalline silicon solar cell 1 in this manner, a load can be driven.

<Basic idea of embodiment>
As described above, in the back electrode type crystalline silicon solar cell, the BSF layer 12 and the emitter layer 13, which have different conductivity types, are formed on the same surface (back surface 100b) of the semiconductor substrate 10. In this embodiment, a phosphorus diffusion layer (BSF layer 12) and a boron diffusion layer (emitter layer 13) having different conductivity types are formed on the same surface (back surface) of the semiconductor substrate 10 without using photolithography technology. We have devised ways to realize a back-electrode crystalline silicon solar cell that can suppress the formation of a mixed region of phosphorus and boron. Below, we will explain the basic idea underlying this idea.

For example, a phosphorus diffusion layer in which phosphorus, which is an n-type impurity, is introduced into a crystalline silicon layer (semiconductor substrate) has a characteristic that it is more easily oxidized than a crystalline silicon layer in which phosphorus is not introduced. In other words, if the oxidation process is performed on both the phosphorus diffusion layer and the crystalline silicon layer under the same oxidation conditions, the thickness of the oxide film formed on the phosphorus diffusion layer will be the same as that of the oxide film formed on the crystalline silicon layer. It has the property of becoming thicker than it is. In this embodiment, this property is utilized to form a phosphorus diffusion layer and a boron diffusion layer on the same surface of a crystalline silicon layer without using a mask substrate. In other words, the basic idea of this embodiment is an idea that focuses on the property that the phosphorus diffusion layer is more easily oxidized than the crystalline silicon layer into which phosphorus is not introduced. In this basic idea, after forming a phosphorus diffusion layer on a crystalline silicon layer, an oxidation process is performed on the crystalline silicon layer and the phosphorus diffusion layer, and then a thick film formed on the phosphorus diffusion layer is formed. By using the oxide film as a mask instead of a mask substrate, boron is introduced into the crystalline silicon layer to form a boron diffusion layer in the crystalline silicon layer while preventing boron from being introduced into the phosphorus diffusion layer.

Hereinafter, a method for manufacturing a back electrode type crystalline silicon solar cell that embodies the basic idea of the present embodiment described above will be described with reference to the drawings.

<Manufacturing method of back electrode type crystalline silicon solar cell>
First, as shown in FIG. 2, a semiconductor substrate 10 is prepared, which has a front surface 100a on which a texture structure is formed and a back surface 100b on which a texture structure is formed, and is made of crystalline silicon into which an n-type impurity is introduced. . Then, by using, for example, an ion implantation method, phosphorus (P), which is an n-type impurity, is introduced into the entire surface 100a of the semiconductor substrate 10. Thereby, the phosphorus diffusion layer 11 can be formed over the entire surface 100a of the semiconductor substrate 10.

Next, as shown in FIG. 3, a mask substrate 20 having an opening OP is prepared. The mask substrate 20 may be, for example, a mask in which openings OP are formed by machining a carbon substrate, or a mask may be formed by forming through holes in a silicon substrate using photolithography and dry etching techniques. A stencil mask with a portion OP formed thereon can also be used. Particularly, from the viewpoint of fine-machining the diameter of the opening OP to about 200 μm, it is desirable to use a stencil mask having the opening OP formed by photolithography and dry etching techniques suitable for fine-fabrication. Then, as shown in FIG. 3, alignment is performed so that the opening OP formed in the mask substrate 20 overlaps the BSF layer formation region of the back surface 100b of the semiconductor substrate 10. Thereafter, phosphorus is introduced from the back surface 100b side of the semiconductor substrate 10 via the mask substrate 20 by an ion implantation method using the mask substrate 20 as a mask. As a result, phosphorus is introduced into the BSF layer formation region (first region) exposed from the opening OP on the back surface 100b of the semiconductor substrate 10, except for the region covered with the mask substrate 20 (second region). Ru. As a result, as shown in FIG. 3, a BSF layer (phosphorus diffusion layer) 12 can be formed in the BSF layer formation region on the back surface of the semiconductor substrate 10. Note that in this specification, a region of the back surface 100b of the semiconductor substrate 10 into which phosphorus is not introduced will be referred to as an unimplanted region.

Subsequently, as shown in FIG. 4, phosphorus introduced into the phosphorus diffusion layer 11 formed on the front surface 100a of the semiconductor substrate 10 and the BSF layer (phosphorus diffusion layer) 12 formed on the back surface 100b of the semiconductor substrate 10 is removed. In order to activate it, an activation annealing step is performed. Specifically, the activation annealing step consists of a heat treatment in an oxygen atmosphere, and is performed, for example, by a wet oxidation method in an atmosphere containing water vapor at a heating temperature of 900° C. and a heating time of 45 minutes.

As a result, as shown in FIG. 4, a silicon oxide film (oxide film) 30a is formed on the front surface 100a of the semiconductor substrate 10, and a silicon oxide film 30b is formed to cover the back surface 100b of the semiconductor substrate 10. . At this time, since the oxidation rate of the phosphorus diffusion layer 11 and the BSF layer (phosphorus diffusion layer) 12 is fast, the silicon oxide film is thicker than the unimplanted region of the back surface 100b of the semiconductor substrate 10 where the phosphorus diffusion layer is not formed. 30b is formed. Specifically, as shown in FIG. 4, since the phosphorus diffusion layer 11 is formed over the entire surface 100a of the semiconductor substrate 10, a thick film is formed on the phosphorus diffusion layer 11. A silicon oxide film 30a is formed. For example, the thickness of the silicon oxide film 30a formed on the phosphorus diffusion layer 11 is about 3800 Å. On the other hand, on the back surface 100b of the semiconductor substrate 10, there are a BSF layer formation region in which a BSF layer (phosphorus diffusion layer) 12 into which phosphorus is introduced and an unimplanted region in which phosphorus is not introduced. Therefore, as shown in FIG. 4, on the back surface 100b of the semiconductor substrate 10, there is a silicon oxide film 30b having a thick part covering the BSF layer formation region and a thin part covering the non-implanted region. It is formed. For example, a silicon oxide film 30b with a thickness of about 3800 Å is formed in the thick part covering the BSF layer formation region, while a silicon oxide film 30b with a thickness of about 1000 Å is formed in the thin part covering the non-implanted region. It is formed. Note that in the boundary region between the BSF layer forming region and the unimplanted region, the silicon oxide film 30b is formed such that the thickness of the silicon oxide film 30b gradually decreases from the BSF layer forming region toward the unimplanted region. .

Next, as shown in FIG. 5, the silicon oxide film 30b formed on the back surface 100b of the semiconductor substrate 10 is oxidized to reduce the thickness of the silicon oxide film 30b covering the unimplanted region formed on the back surface 100b of the semiconductor substrate 10. Etch the silicon film 30b. Specifically, after the semiconductor substrate 10 is immersed in dilute hydrofluoric acid with a concentration of 1%, the thickness of the silicon oxide film 30b is reduced by wet etching with an etching time of 460 seconds. At this time, the thickness of the silicon oxide film 30a formed on the surface 100a of the semiconductor substrate 10 also becomes thin. For example, the thickness of the silicon oxide film 30a after wet etching is about 3450 Å. On the other hand, also on the back surface 100b of the semiconductor substrate 10, the thickness of the silicon oxide film 30b becomes thinner. For example, a silicon oxide film 30b of about 3450 Å remains in the thick part covering the BSF layer formation region, while a silicon oxide film 30b of about 350 Å remains in the thin part covering the non-implanted region. I will do it. In FIG. 5, a silicon oxide film 30b of about 350 Å remains in the thin part covering the non-implanted region. Wet etching may be performed so that 30b is completely removed. Furthermore, dry etching can be used instead of wet etching.

Thereafter, as shown in FIG. 6, a BSG (Boron-Silicate Glass) film 40a containing boron is formed on the silicon oxide film 30a formed on the front surface 100a of the semiconductor substrate 10, and a back surface 100b of the semiconductor substrate 10 is formed. A BSG film 40b is formed to further cover the silicon oxide film 30b that covers the silicon oxide film 30b. Next, as shown in FIG. 7, the semiconductor substrate 10 is subjected to heat treatment (for example, at a heating temperature of 970° C.). As a result, since the silicon oxide film 30b covering the non-implanted region formed on the back surface of the semiconductor substrate 10 is thin, boron is transferred from the BSG film 40b covering the silicon oxide film 30b to the thin silicon oxide film. As a result of being introduced into the semiconductor substrate 10 through the semiconductor substrate 10b, an emitter layer (boron diffusion layer) 13 is formed on the back surface 100b of the semiconductor substrate 10.

On the other hand, since the silicon oxide film 30b covering the BSF layer formation region formed on the back surface of the semiconductor substrate 10 is thick, the boron diffused from the BSG film 40b covering the silicon oxide film 30b is absorbed into the inside of the semiconductor substrate 10. It does not reach the BSF layer (phosphorus diffusion layer) 12 formed in the. In this way, according to the present embodiment, the semiconductor substrate 10 can be processed without using a mask substrate and without implanting boron into the BSF layer (phosphorus diffusion layer) 12 formed on the back surface 100b of the semiconductor substrate 10. An emitter layer (boron diffusion layer) 13 can be formed on the back surface 100b of 10, which is spaced apart from the BSF layer (phosphorus diffusion layer) 12. That is, in this embodiment, even if a mask substrate is not used, the thick portion of the silicon oxide film 30b covering the BSF layer (phosphorus diffusion layer) 12 formed on the back surface 100b of the semiconductor substrate 10 is used as a mask. functions as As a result, according to the present embodiment, boron is introduced into the back surface 100b of the semiconductor substrate 10 to form the emitter layer (boron diffusion layer) 13 while preventing boron from being introduced into the BSF layer (phosphorus diffusion layer) 12. It is possible.

Note that also on the surface 100a side of the semiconductor substrate 10, a thick silicon oxide film 30a is formed on the phosphorus diffusion layer 11 formed over the entire surface of the surface 100a. From this, boron thermally diffused from the BSG film 40a formed on the silicon oxide film 30a cannot penetrate the thick silicon oxide film 30a, and as a result, it is formed in the lower layer of the silicon oxide film 30a. Injection of boron into the phosphorus diffusion layer 11 can be avoided.

Subsequently, as shown in FIG. 8, on the front surface 100a side of the semiconductor substrate 10, the silicon oxide film 30a and the BSG film 40a are removed, and on the back surface 100b side of the semiconductor substrate 10, the silicon oxide film 30b and the BSG film 40a are removed. Film 40b is removed. As a result, as shown in FIG. 8, a phosphorus diffusion layer 11 is formed on the front surface 100a of the semiconductor substrate 10, and a BSF layer 12 and an emitter layer 13 having different conductivity types are formed on the back surface 100b of the semiconductor substrate 10. A new structure can be obtained. Thereafter, by using a conventional technique, for example, as shown in FIG. Connected emitter electrodes 16a and 16b can be formed. In the manner described above, the back electrode type crystalline silicon solar cell in this embodiment can be manufactured.

<Modified example>
In the embodiment described above, for example, as shown in FIG. 7, the emitter layer 13 is formed by thermally diffusing boron from the BSG film 40b into the semiconductor substrate 10 through the thin silicon oxide film 30b. are doing. The method of diffusing boron into the interior of the semiconductor substrate 10 using such a thermal diffusion method has the advantage that boron can be diffused with a relatively low thermal load. In other words, by diffusing boron into the interior of the semiconductor substrate 10 using the thermal diffusion method, it is possible to suppress the thermal load applied to the semiconductor substrate 10 from increasing more than necessary. Characteristic deterioration can be suppressed.

However, the method for implanting boron into the inside of the semiconductor substrate 10 is not limited to the above-described thermal diffusion method, and for example, an ion implantation method can also be used. Specifically, when using the ion implantation method to implant boron, the thick silicon oxide film 30b formed to cover the BSF layer (phosphorus diffusion layer) 12 is not penetrated; ) The implantation energy of boron is adjusted so that it penetrates the thin silicon oxide film 30b in which the silicon oxide film 12 is not formed. As a result, not only the thermal diffusion method but also the ion implantation method can be used without using a mask substrate, while preventing boron from being implanted into the BSF layer (phosphorous diffusion layer) 12 formed on the back surface 100b of the semiconductor substrate 10. , an emitter layer (boron diffusion layer) 13 can be formed on the back surface 100b of the semiconductor substrate 10, spaced apart from the BSF layer (phosphorus diffusion layer) 12. An advantage of using the ion implantation method is that the boron implantation process can be simplified.

Furthermore, in the ion implantation method, the gap between the BSF layer (phosphorus diffusion layer) 12 and the emitter layer (boron diffusion layer) 13 formed on the back surface 100b of the semiconductor substrate 10 is reduced by going through the steps shown below. This can be ensured.

This process will be explained below.

After performing the steps shown in FIGS. 2 to 4, as shown in FIG. 9, the thin silicon oxide film 30b covering the unimplanted region formed on the back surface 100b of the semiconductor substrate 10 is removed. The silicon oxide film 30b formed on the back surface 100b of the semiconductor substrate 0 is etched. At this time, as shown in FIG. 9, the silicon oxide film 30b covering the BSF layer (phosphorous diffusion layer) 12 is thicker than the silicon oxide film 30b covering the non-implanted region, so the silicon oxide film 30b covering the non-implanted region Even if the film 30b is removed, the silicon oxide film 30b covering the BSF layer (phosphorous diffusion layer) 12 remains.

Next, the semiconductor substrate 10 is immersed in a potassium hydroxide solution to wet-etch the semiconductor substrate 10. Specifically, as shown in FIG. 10, the semiconductor substrate 10 is etched in the unimplanted region where the semiconductor substrate 10 is exposed on the back surface 100b of the semiconductor substrate 10. At this time, the BSF layer (phosphorous diffusion layer) 12 covered with the thick silicon oxide film 30b is not etched because the thick silicon oxide film 30b functions as a mask. However, as shown in FIG. 10, at the end of the silicon oxide film 30b that functions as a mask, as a result of wet etching wraparound, fine voids 50 are formed in the area covered by the end of the silicon oxide film 30b. is formed.

Subsequently, as shown in FIG. 11, boron is implanted into the back surface 100b of the semiconductor substrate 10 by an ion implantation method. At this time, boron is not implanted into the BSF layer (phosphorus diffusion layer) 12 because the thick silicon oxide film 30b covering the BSF layer (phosphorus diffusion layer) 12 functions as a mask. On the other hand, in the exposed unimplanted region, boron is implanted into the semiconductor substrate 10 to form an emitter layer (boron diffusion layer) 13. On the other hand, since a gap 50 is formed in the region covered by the end of the silicon oxide film 30b, boron is not implanted into the back surface 100b of the semiconductor substrate 10 exposed in the gap 50. Thereby, according to this modification, a gap can be ensured between the BSF layer (phosphorous diffusion layer) 12 and the emitter layer (boron diffusion layer) 13. After that, as shown in FIG. 12, a silicon oxide film 30a formed on the front surface 100a of the semiconductor substrate 10 and a silicon oxide film covering the BSF layer (phosphorus diffusion layer) 12 formed on the back surface 100b of the semiconductor substrate 10 are shown. Film 30b is removed. In this way, a back electrode type crystalline silicon solar cell in which a gap can be reliably secured between the BSF layer (phosphorous diffusion layer) 12 and the emitter layer (boron diffusion layer) 13 can be manufactured.

<Characteristics of the manufacturing method>
Next, the features of the manufacturing method in this embodiment will be explained.

A feature of the manufacturing method of this embodiment is, for example, as shown in FIG. 7 and FIG. The point is that boron is introduced into the back surface 100b of the semiconductor substrate 10 while the silicon film 30b remains. In other words, the feature of the manufacturing method of this embodiment is that the thick silicon oxide film 30b covering the BSF layer (phosphorus diffusion layer) 12 functions as a mask, so that the BSF layer can be layered without using a mask substrate. The emitter layer (boron diffusion layer) 13 is formed by introducing boron into the non-implanted region other than the (phosphorus diffusion layer) 12.

As a result, according to the present embodiment, with only one mask substrate 20 used when forming the BSF layer (phosphorus diffusion layer) 12, mutually conductive types can be formed on the same surface (back surface) of the semiconductor substrate 10. It is possible to realize a back-electrode crystalline silicon solar cell in which different BSF layers (phosphorus diffusion layer) 12 and emitter layers (boron diffusion layer) 13 can be formed, and in which formation of a mixed region of phosphorus and boron can be suppressed. can. This is because the thick silicon oxide film 30b covering the BSF layer (phosphorus diffusion layer) 12 functions as a mask without using a mask substrate when forming the emitter layer (boron diffusion layer) 13. be.

Therefore, according to the present embodiment, two layers are used to form the BSF layer (phosphorus diffusion layer) 12 and the emitter layer (boron diffusion layer) 13 having different conductivity types on the same surface (back surface) of the semiconductor substrate 10. There is no need to use a mask substrate. This means that there is no need to align the two mask substrates, which simplifies the manufacturing process and eliminates the need to align the two mask substrates. It is possible to suppress the increase in recombination centers due to the generation of a mixed region of boron and boron. As a result, according to the present embodiment, significant effects can be obtained in that the manufacturing cost can be reduced by simplifying the manufacturing process and the performance of the back electrode type crystalline silicon solar cell can be improved.

<Verification results>
Next, a verification result in which the thickness of the silicon oxide film formed on the phosphorus diffusion layer is thicker than the thickness of the silicon oxide film formed on the crystalline silicon layer into which phosphorus is not introduced will be explained. FIG. 13 is a graph showing the relationship between the thickness of the silicon oxide film and the etching time. The horizontal axis represents the etching time, while the vertical axis represents the thickness of the silicon oxide film. In FIG. 13, graph (1) shows the relationship between the thickness of the silicon oxide film formed on the phosphorus diffusion layer and the etching time, while graph (2) shows the relationship between the etching time and the thickness of the silicon oxide film formed on the phosphorus diffusion layer. It shows the relationship between the thickness of the silicon oxide film formed on the silicon layer and the etching time. As shown in FIG. 13, focusing on the thickness of the silicon oxide film when the etching time is "0", in graph (1) the thickness of the silicon oxide film is about 2000 Å, while in graph (2) ), it can be seen that the thickness of the silicon oxide film is about 400 Å. In other words, from graphs (1) and (2), it can be seen that the thickness of the silicon oxide film formed on the phosphorus diffusion layer is greater than the thickness of the silicon oxide film formed on the crystalline silicon layer into which phosphorus is not introduced. It can be seen that it is confirmed that the thickness increases. From graph (2), it can be seen that the thickness of the silicon oxide film formed on the crystalline silicon layer into which phosphorus is not introduced becomes almost zero after an etching time of about 250 seconds. On the other hand, it can be seen from graph (1) that when the etching time is about 250 seconds, the thickness of the silicon oxide film formed on the phosphorus diffusion layer remains about 1800 Å. From this, for example, by adjusting the etching time to about 250 seconds, it is possible to leave a thick silicon oxide film on the phosphorus diffusion layer while removing the silicon oxide film on the crystalline silicon layer to which no phosphorus has been introduced. It turns out that it can be removed.

Next, FIG. 14 is a table showing the results of verifying whether or not boron penetrates into the inside of the semiconductor substrate depending on the thickness of the silicon oxide film formed on the semiconductor substrate.

In FIG. 14, first, when a silicon oxide film is not formed on the n-type semiconductor substrate, boron is introduced into the n-type semiconductor substrate, and as a result, the sheet resistance of the n-type semiconductor substrate is 68 (Ω/□ ) to 71 (Ω/□). Next, when a silicon oxide film with a thickness of 270 Å is formed on an n-type semiconductor substrate, the sheet resistance of the n-type semiconductor substrate is 68 (Ω/□), which is still sufficient for boron to penetrate. It can be inferred that this is occurring. Next, when a silicon oxide film with a thickness of 650 Å is formed on an n-type semiconductor substrate, the sheet resistance of the n-type semiconductor substrate is 72 (Ω/□), and in this case as well, It can be inferred that boron penetration still occurs. On the other hand, when a silicon oxide film with a thickness of 1400 Å is formed on an n-type semiconductor substrate, the sheet resistance of the n-type semiconductor substrate decreases rapidly to 32 (Ω/□), and Considering that the sheet resistance of an n-type semiconductor substrate without introducing boron is 27.5 (Ω/□), it can be inferred that boron penetration does not occur.

From the above results, it can be seen that boron penetration becomes less likely to occur if a silicon oxide film having a thickness of 1400 Å or more is formed on an n-type semiconductor substrate. From this result, for example, referring to FIG. 13, it can be seen that with an etching time of about 250 seconds, the thickness of the silicon oxide film formed on the phosphorus diffusion layer remains about 1800 Å. It can be seen that if the thickness is large, the penetration of boron can be effectively suppressed. In other words, by setting the etching time to about 250 seconds, the silicon oxide film formed on the phosphorus diffusion layer can function as a mask to prevent boron from penetrating, and the crystalline silicon without phosphorus introduced It can be seen that the thickness of the silicon oxide film formed on the layer can be made almost zero.

FIG. 15 is a scanning capacitance microscope image of an emitter layer (boron diffusion layer) and a BSF layer (phosphorus diffusion layer) manufactured by the method for manufacturing a back electrode type crystalline silicon solar cell in this embodiment. As shown in FIG. 15A, it can be seen that an emitter layer (boron diffusion layer) 13 is formed in the semiconductor substrate 10. On the other hand, as shown in FIG. 15(b), a BSF layer (phosphorus diffusion layer) 12 is formed on the semiconductor substrate 10, and it is known that boron is not introduced into this BSF layer (phosphorus diffusion layer) 12. Recognize.

<Application example>
<<Application example 1>>
FIG. 16(a) is a plan view showing an example of the planar layout on the back surface of a back electrode type crystalline silicon solar cell. In FIG. 16(a), the back electrode type crystalline silicon solar cell 1A has a BSF layer (phosphorus diffusion layer) 12 having a rectangular planar shape, and the BSF layer (phosphorus diffusion layer) 12 is surrounded at a distance. An emitter layer (boron diffusion layer) 13 is formed therein.

By using the manufacturing method of this embodiment, the back electrode type crystalline silicon solar cell 1A configured as described above can be manufactured using, for example, one mask substrate 20A shown in FIG. 16(b). The mask substrate 20A shown in FIG. 16(b) has a slit-shaped opening OP1 in order to form a rectangular BSF layer (phosphorus diffusion layer) 12.

<<Application example 2>>
For example, the BSF layer (phosphorus diffusion layer) 12 has the function of keeping holes away from the back surface of the semiconductor substrate 10 and suppressing recombination of holes and electrons. It is desirable that the plane size is small. This is because although the BSF layer (phosphorus diffusion layer) 12 has the function of suppressing recombination of holes and electrons, the BSF layer (phosphorus diffusion layer) 12 itself does not have conductivity that is a donor. This is because it contains many type impurities, and there is a concern that these donors may function as recombination centers. In other words, from the viewpoint of reducing recombination centers, it is desirable that the planar size of the BSF layer (phosphorus diffusion layer) 12 be as small as possible. This finding is a new finding discovered by the present inventor, and based on this finding, the present inventor has proposed a back electrode type crystalline silicon solar cell having the planar layout shown below.

FIG. 17(a) is a plan view showing an example of a planar layout on the back surface of a back electrode type crystalline silicon solar cell. In FIG. 17(a), a back electrode type crystalline silicon solar cell 1B has a plurality of BSF layers (phosphorus diffusion layers) 12 having a circular planar shape, and the plurality of BSF layers (phosphorus diffusion layers) 12 are spaced apart. An emitter layer (boron diffusion layer) 13 is formed so as to surround it. At this time, the plurality of BSF layers (phosphorus diffusion layers) 12 each having a circular shape constitute a dot pattern. In the back electrode type crystalline silicon solar cell 1B configured in this manner, the planar size of the BSF layer (phosphorus diffusion layer) 12 can be reduced, and as a result, recombination of holes and electrons can be suppressed. Thereby, according to the back electrode type crystalline silicon solar cell 1B, the photoelectric conversion efficiency can be improved.

By using the manufacturing method of this embodiment, the back electrode type crystalline silicon solar cell 1B can be manufactured using, for example, one mask substrate 20B shown in FIG. 17(b). A plurality of openings OP2 each having a circular shape are formed in the mask substrate 20B shown in FIG. 17(b) in order to form a plurality of BSF layers (phosphorus diffusion layers) 12 having a dot pattern.

Here, the back electrode type crystalline silicon solar cell 1B in which the BSF layer (phosphorus diffusion layer) 12 constitutes a dot pattern is, for example, in the present embodiment using only one mask substrate 20B shown in FIG. 17(b). This structure can be manufactured only by the manufacturing method in this form. For example, in a manufacturing technique that uses two mask substrates, one for forming the BSF layer (phosphorous diffusion layer) 12 and the other for forming the emitter layer (boron diffusion layer) 13, the emitter layer (boron diffusion layer) 13 For example, a mask substrate 20C shown in FIG. 18 is required as a mask substrate for forming. As shown in FIG. 18, this mask substrate 20C needs to have a shielding pattern PT that shields the BSF layer formation region, and other regions are opened. However, the mask substrate 20C configured in this manner has a configuration in which the shielding pattern PT is suspended in the air, and it is difficult to manufacture the mask substrate 20C because a support portion that supports the shielding pattern PT cannot be formed. That is, for example, the back electrode type crystalline silicon solar cell 1B in which the BSF layer (phosphorus diffusion layer) 12 shown in FIG. 17(a) forms a dot pattern cannot be manufactured using the manufacturing technology that uses two mask substrates It is difficult to do so. On the other hand, for example, in the manufacturing method of this embodiment using only one mask substrate 20B shown in FIG. 17(b), there is no need to use the mask substrate 20C shown in FIG. The back electrode type crystalline silicon solar cell 1B in which the BSF layer (phosphorus diffusion layer) 12 shown in (a) forms a dot pattern can be easily manufactured. As described above, the manufacturing method according to the present embodiment provides a technical concept that allows easy manufacturing of the back electrode type crystalline silicon solar cell 1B that can improve the photoelectric conversion efficiency. It can be said that it is a thought.

The invention made by the present inventor has been specifically explained based on the embodiments thereof, but the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the gist thereof. Needless to say.

1 Back electrode type crystalline silicon solar cell 1A Back electrode type crystalline silicon solar cell 1B Back electrode type crystalline silicon solar cell 10 Semiconductor substrate 11 Phosphorus diffusion layer 12 BSF layer 13 Emitter layer 14 Insulating layer 15 BSF electrode 16a Emitter electrode 16b Emitter electrode 20 Mask substrate 20A Mask substrate 20B Mask substrate 20C Mask substrate 30a Silicon oxide film 30b Silicon oxide film 40a BSG film 40b BSG film 50 Cavity 100a Front surface 100b Back surface OP Opening OP1 Opening OP2 Opening PT Shielding pattern

Claims (10)

(a) preparing a mask having an opening;
(b) By ion-implanting phosphorus from the first surface side of the semiconductor substrate through the mask, the semiconductor is exposed from the opening except for the second region of the semiconductor substrate covered by the mask. introducing phosphorus into a first region of the substrate;
(c) oxidizing the first surface of the semiconductor substrate after the step (b);
(d) etching the oxide film so as to reduce the thickness of the oxide film formed on the first surface of the semiconductor substrate;
(e) After the step (d), the first region is removed by introducing boron from the first surface side of the semiconductor substrate using the oxide film formed on the first region as a mask. introducing boron into the second region;
(f) removing the oxide film formed on the first surface after the step (e);
A method for manufacturing a semiconductor device, comprising: The method for manufacturing a semiconductor device according to claim 1,
The method for manufacturing a semiconductor device, wherein the mask prepared in the step (a) is a silicon stencil mask. The method for manufacturing a semiconductor device according to claim 1,
The method for manufacturing a semiconductor device, wherein the step (c) is an activation annealing step for activating phosphorus introduced into the first region of the semiconductor substrate. The method for manufacturing a semiconductor device according to claim 1,
The method for manufacturing a semiconductor device, wherein the step (c) is a wet oxidation step in an atmosphere containing oxygen. The method for manufacturing a semiconductor device according to claim 1,
The method for manufacturing a semiconductor device, wherein the step (d) is a wet etching step. The method for manufacturing a semiconductor device according to claim 1,
In the step (e), a method for manufacturing a semiconductor device uses a thermal diffusion method. The method for manufacturing a semiconductor device according to claim 1,
In the step (e), a method for manufacturing a semiconductor device uses an ion implantation method. The method for manufacturing a semiconductor device according to claim 1,
The mask prepared in the step (a) has a plurality of the openings,
In a plan view, each of the plurality of openings has a slit shape. The method for manufacturing a semiconductor device according to claim 1,
The mask prepared in the step (a) has a plurality of the openings,
In a plan view, the plurality of openings constitute a dot pattern. The method for manufacturing a semiconductor device according to claim 1,
In the step (d), removing the oxide film formed on the second region,
Between the step (d) and the step (e), a step of wet-etching a part of the semiconductor substrate using an oxide film formed on the first region as a mask;
In the step (e), a method for manufacturing a semiconductor device uses an ion implantation method.