JP7416570B2 - Liquid ejection head control device - Google Patents

Description

Embodiments of the present invention relate to a liquid ejection head control device.

2. Description of the Related Art Liquid ejection apparatuses are known that perform printing or the like by ejecting liquid such as ink from a liquid ejection head. While the liquid ejection head is not ejecting liquid, the liquid near the nozzle may thicken or dry. This causes printing omissions and the like. As a countermeasure against this problem, the liquid ejection apparatus may control the liquid ejection head to perform a precursor operation that causes the liquid ejection head to vibrate slightly to the extent that the liquid is not ejected. However, in the liquid ejection apparatus, it takes time to switch the operation of the liquid ejection head to the precursor operation after printing.

Japanese Patent Application Publication No. 2012-140003

The problem to be solved by the embodiments of the present invention is to provide a liquid ejection head control device that shortens the time required to switch to precursor operation.

The liquid ejection head control device of the embodiment includes an input section, a first storage section , a selector , and a control section. The input unit inputs image data to be printed to the liquid ejection head. The first storage unit stores precursor data for causing the liquid ejection head to perform a precursor operation. The selector selects one of the image data input from the input section and the precursor data input from the first storage section and outputs the selected one to the liquid ejection head. The control unit may switch an input source of data input to the liquid ejection head from the input unit to the first storage unit by controlling the selector , and input the precursor data to the liquid ejection head. Then, the liquid ejection head is caused to perform the precursor operation.

FIG. 1 is a block diagram showing a main circuit configuration of a liquid ejection device according to an embodiment. FIG. 1 is a partially exploded perspective view of an inkjet head according to an embodiment. FIG. 2 is a vertical cross-sectional view of the front part of the inkjet head according to the embodiment. FIG. 3 is a cross-sectional view of the front part of the inkjet head according to the embodiment. FIG. 3 is a diagram for explaining the operating principle of the inkjet head according to the embodiment. FIG. 3 is a diagram for explaining the operating principle of the inkjet head according to the embodiment. FIG. 3 is a diagram for explaining the operating principle of the inkjet head according to the embodiment. FIG. 3 is a diagram for explaining the data flow of image data, SPIT data, and configuration data according to the embodiment. 2 is a flowchart showing an example of processing by the processor in FIG. 1. FIG. 2 is a flowchart showing an example of the operation of a state machine by the precursor assist circuit in FIG. 1. FIG. FIG. 2 is a state transition diagram of a state machine by the precursor assist circuit in FIG. 1. FIG. 2 is a state transition diagram showing an example of the operation of a state machine by the precursor assist circuit in FIG. 1. FIG.

Hereinafter, a liquid ejection device according to an embodiment will be described using the drawings. Note that in each of the drawings used to describe the embodiments below, the scale of each part may be changed as appropriate. Further, each drawing used in the description of the embodiments below may omit the configuration for the sake of explanation. Further, in each drawing and the following description, the same reference numerals indicate similar elements.

FIG. 1 is a block diagram showing a main circuit configuration of a liquid ejection device 1 according to an embodiment.
The liquid ejection device 1 is, for example, an inkjet printer that forms an image on an image forming medium using a liquid recording material such as ink. The image forming medium is, for example, a sheet of paper. The liquid ejection device 1 includes, for example, a control circuit 100, a liquid ejection head 200, and a temperature sensor 300. The liquid ejection device 1 is an example of a liquid ejection head control device.

First, the configuration of the liquid ejection head 200 according to the embodiment will be described using FIGS. 2 to 4. FIG. 2 is a partially exploded perspective view of the liquid ejection head 200 according to the embodiment. FIG. 3 is a longitudinal sectional view of the front part of the liquid ejection head 200. FIG. 4 is a cross-sectional view of the front part of the liquid ejection head 200.

The liquid ejection head 200 has a base substrate 209. In the liquid ejection head 200, a first piezoelectric member 201 is bonded to the upper surface on the front side of a base substrate 209, and a second piezoelectric member 202 is bonded onto the first piezoelectric member 201. The joined first piezoelectric member 201 and second piezoelectric member 202 are polarized in opposite directions along the thickness direction, as shown by arrows in FIG.

The material of the base substrate 209 has a small dielectric constant and a small difference in coefficient of thermal expansion between the first piezoelectric member 201 and the second piezoelectric member 202. Preferable materials for the base substrate 209 include, for example, aluminum oxide (Al ₂ O ₃ ), silicon nitride (Si ₃ N ₄ ), silicon carbide (SiC), aluminum nitride (AlN), lead zirconate titanate (PZT), and the like. On the other hand, the materials of the first piezoelectric member 201 and the second piezoelectric member 202 include lead zirconate titanate (PZT), lithium niobate (LiNbO ₃ ), lithium tantalate (LiTaO ₃ ), and the like.

The liquid ejection head 200 has a large number of elongated grooves 203 formed from the front end side to the rear end side of the first piezoelectric member 201 and the second piezoelectric member 202 that are joined together. Each groove 203 has a constant interval and is arranged in parallel. Each groove 203 has an open front end and an upwardly inclined rear end.

The liquid ejection head 200 includes an electrode 204 on the side wall and bottom surface of each groove 203. The electrode 204 has, for example, a two-layer structure of nickel (Ni) and gold (Au). The electrode 204 is uniformly formed in each groove 203 by, for example, a plating method. The method for forming the electrode 204 is not limited to the plating method, and may be a sputtering method, a vapor deposition method, or the like.

The liquid ejection head 200 includes an extraction electrode 210 extending from the rear end of each groove 203 toward the rear upper surface of the second piezoelectric member 202 . An extraction electrode 210 extends from the electrode 204 .

The liquid ejection head 200 includes a top plate 206 and an orifice plate 207. The top plate 206 closes the upper part of each groove 203. Orifice plate 207 closes the tip of each groove 203. The liquid ejection head 200 forms a plurality of pressure chambers 215 by each groove 203 surrounded by a top plate 206 and an orifice plate 207. The pressure chambers 215 have a shape of, for example, a depth of 300 μm and a width of 80 μm, and are arranged in parallel at a pitch of 169 μm. Such a pressure chamber 215 is also called an ink chamber or the like. Pressure chamber 215 contains liquid such as ink.

The top plate 206 includes a common ink chamber 205 at the rear inside thereof. The orifice plate 207 has nozzles 208 at positions facing each groove 203. Nozzle 208 is a hole that passes through orifice plate 207. The nozzle 208 communicates with the groove 203, that is, with the pressure chamber 215. The nozzle 208 has a tapered shape from the pressure chamber 215 side toward the opposite ink ejection side. For example, the nozzles 208 are formed by forming a set of three adjacent pressure chambers 215, with the nozzles 208 of the same set being shifted at regular intervals in the height direction of the groove 203 (in the vertical direction of the plane of the paper in FIG. 3). be done.

In the liquid ejection head 200, a printed circuit board 211 on which a conductive pattern 213 is formed is bonded to the rear upper surface of a base substrate 209. The liquid ejection head 200 has a drive IC 212 mounted on the printed circuit board 211 with a head drive circuit described later. Drive IC 212 is connected to conductive pattern 213. The conductive pattern 213 is connected to each extraction electrode 210 by a conductive wire 214 by wire bonding.

A set of the pressure chamber 215, electrode 204, and nozzle 208 that the liquid ejection head 200 has is called a channel. That is, the liquid ejection head 200 has the same number of channels ch.1, ch.2, . . . , ch.N as the number N of the grooves 203.

Next, the principle of operation of the liquid ejection head 200 configured as described above will be explained using FIGS. 5 to 7. 5 to 7 are diagrams for explaining the operating principle of the liquid ejection head 200. Note that in FIGS. 5 to 7, pressure chambers 215a to 215c are shown as examples of the pressure chambers 215. Further, the electrode 204 on the wall of the pressure chamber 215a is called an electrode 204a, the electrode 204 on the wall of the pressure chamber 215b is called an electrode 204b, and the electrode 204 on the wall of the pressure chamber 215c is called an electrode 204c.

FIG. 5 shows a state in which a positive voltage V is applied to each of the electrodes 204a to 204c. In this state, since the electrodes 204a to 204c are all at the same potential, no electric field is applied to the partition walls 216a and 216b. Therefore, the partition wall 216a sandwiched between the mutually adjacent pressure chambers 215a and 215b does not deform. Similarly, the partition wall 216b sandwiched between the adjacent pressure chambers 215b and 215c does not deform.

FIG. 6 shows a state in which the ground voltage GND is applied to the center electrode 204b, and the positive voltage V is applied to the electrodes 204a and 204c on both sides. In this state, a potential difference occurs between the center electrode 204b and the electrodes 204a and 204c on both sides. As a result, an electric field is generated between the partition walls 216a and the partition walls 216b due to the applied potential difference, and the partition walls 216a and 216b are sheared outward so as to expand the volume of the pressure chamber 215b. When the volume of pressure chamber 215b expands, the pressure of the liquid within pressure chamber 215b decreases.

FIG. 7 shows a state in which a positive voltage V is applied to the central electrode 204b, and a ground voltage GND is applied to the electrodes 204a and 204c on both sides. In this state, a potential difference opposite to that shown in FIG. 6 occurs between the center electrode 204b and the electrodes 204a and 204c on both sides. As a result, an electric field is generated in the partition wall 216a and the partition wall 216b in a direction opposite to that shown in FIG. 6 due to the applied potential difference, and the partition wall 216a and the partition wall 216b are shear-deformed inward so as to contract the volume of the pressure chamber 215b. When the volume of the pressure chamber 215b contracts, the pressure of the liquid within the pressure chamber 215b increases.

When the volume of the pressure chamber 215b is expanded or contracted, pressure vibrations occur within the pressure chamber 215b. This pressure vibration increases the pressure within the pressure chamber 215b, and ink droplets (liquid droplets) are ejected from the nozzle 208 communicating with the pressure chamber 215b.

As described above, the partition wall 216a and the partition wall 216b are an example of an actuator that changes the volume of the pressure chamber 215b whose walls are the partition wall 216a and the partition wall 216b. That is, each pressure chamber 215 shares an actuator with an adjacent pressure chamber 215. Therefore, the head drive circuit cannot drive each pressure chamber 215 individually. Therefore, the head drive circuit is an (n+1) division drive in which each pressure chamber 215 is divided into (n+1) groups every n (n is an integer of 2 or more) and driven. In this embodiment, a so-called three-division drive is exemplified in which the head drive circuit divides each pressure chamber 215 into three sets of every two pressure chambers and drives them in a divided manner. Note that the three-division drive is just an example, and four-division drive or five-division drive may be used.

Note that the method of applying voltage for ejecting ink from the nozzle corresponding to the central pressure chamber 215b is not limited to the examples shown in FIGS. 5 to 7. For example, the liquid ejection head 200 may apply the same voltage, such as the ground voltage GND, to each of the electrodes 204a to 204c so that the pressure chamber 215b is not deformed. For example, the liquid ejection head 200 may expand the volume of the pressure chamber 215b by applying a negative voltage -V to the central electrode 204b and applying a ground voltage GND to the electrodes 204a and 204c on both sides. For example, the liquid ejection head 200 expands the volume of the pressure chamber 215b by applying a negative voltage -V/2 to the central electrode 204b and applying a positive voltage V/2 to the electrodes 204a and 204c on both sides. You can let me. For example, the liquid ejection head 200 may contract the volume of the pressure chamber 215b by applying the ground voltage GND to the central electrode 204b and applying a negative voltage -V to the electrodes 204a and 204c on both sides. For example, the liquid ejection head 200 reduces the volume of the pressure chamber 215b by applying a positive voltage V/2 to the central electrode 204b and applying a negative voltage -V/2 to the electrodes 204a and 204c on both sides. You can let me.

Returning to the explanation of FIG.
The control circuit 100 is a circuit that controls the liquid ejection head 200. The control circuit 100 includes a processor 101, a memory 102, a memory controller 103, an auxiliary storage device 104, an input/output controller 105, a clock generation circuit 106, a control register 107, an image DMA (direct memory access) circuit 108, a line buffer 109, and an LUT ( Lookup Table) 110, SPIT writing circuit 111, SPIT_RAM (Random-Assess Memory) 112, Prikasa SPIT_RAM113, selector 114, selector 115, OR circuit 116, SDI transfer circuit 117, Config 8, Config_ram119, Pricasa CONFIG_RAM120, selector 121, a CDi transfer circuit 122, a precursor assist circuit 123, and an LVDS_DRV 124. The control circuit 100 is an example of a liquid ejection head control device.

The processor 101 corresponds to the central part of a computer that performs processing such as computation and control necessary for the operation of the liquid ejection device 1. The processor 101 controls each part of the liquid ejection apparatus 1 to realize various functions based on a program stored in the auxiliary storage device 104 or the like. Note that part or all of the program may be incorporated into the circuit of the processor 101. The processor 101 is, for example, a CPU (central processing unit), an MPU (micro processing unit), an SoC (system on a chip), a DSP (digital signal processor), a GPU (graphics processing unit), an ASIC (application specific integrated circuit), These include a PLD (programmable logic device) or an FPGA (field-programmable gate array). Alternatively, processor 101 is a combination of more than one of these.

The memory 102 corresponds to the main storage of a computer in which the processor 101 is the core. Further, the memory 102 is used as a so-called work area in which data temporarily used by the processor 101 in performing various processes is stored. Memory 102 is typically volatile memory. The memory 102 is, for example, a DDR (double data rate) 3 memory.
The memory controller 103 is a controller that controls the memory 102.

The auxiliary storage device 104 corresponds to an auxiliary storage device of a computer in which the processor 101 is the core. The auxiliary storage device 104 is, for example, an EEPROM, an HDD, or a flash memory. The auxiliary storage device 104 stores the above programs and the like. Further, the auxiliary storage device 104 stores data used by the processor 101 in performing various processes, data generated by processing by the processor 101, various setting values, and the like.

The input/output controller 105 controls communication with devices connected to the liquid ejection device 1 and the like. The input/output controller 105 is, for example, a UART (Universal Asynchronous Receiver Transmitter) controller.

The clock generation circuit 106 generates s_MIG_CLK and s_HCLK used for the operation of the liquid ejection apparatus 1. s_MIG_CLK and s_HCLK are clock signals. s_MIG_CLK is input to the memory controller 103. s_HCLK is input to the SDi transfer circuit 117, CDi transfer circuit 122, LVDS_DRV 124, and the like.

The control register 107 is a register that reads and controls the pointer-managed state of the line buffer 109, the operating state of the image DMA circuit, the transfer start state, the transfer end state, and the like.

The image DMA circuit 108 controls the transfer of image data stored in the memory 102 to the line buffer 109 via the memory controller 103 without going through the processor 101. Thereby, no load is placed on the processor 101. Further, the image DMA circuit 108 issues a direct read request to the memory controller 103. The read request includes the image data read start address, the number of read bytes, the number of burst transfers, and the like. When a read request is issued to the memory controller 103, a ready signal indicating that the request has been accepted becomes active. In this case, a ready signal is returned from the memory controller 103. After several clocks, the image data corresponding to the read request issued earlier is read from the memory 102, so the image DMA circuit 108 writes the read image data into the line buffer 109. The image DMA circuit 108 checks the free state of the line buffer 109, and if there is space, issues the next read request. If there is no free space in the line buffer 109, the image DMA circuit 108 does not issue the next read request and remains in an idle state until the line buffer 109 becomes free. The empty state of the line buffer 109 is managed by the pointer of the image DMA circuit 108. The image DMA circuit 108 increments the pointer when one line of image data corresponding to the read request is written into the line buffer 109. Similarly, the image DMA circuit 108 decrements the pointer when one line is read out from the line buffer 109 by an SDi read circuit 1172, which will be described later. By performing the above operations in the image DMA circuit 108, the time required for transfer is shortened. Note that the image DMA circuit 108 operates via the control register 107 under the control of the processor 101.
Note that, as described above, the image DMA circuit 108 operates as a master, and the memory controller 103 operates as a slave. The Master is the side that issues requests, and the Slave is the side that receives requests.

The line buffer 109 is, for example, DPRAM (dual-ported RAM). Thereby, the line buffer 109 can read data and write data simultaneously or almost simultaneously. The line buffer 109 divides the RAM address area into four areas and controls reading and writing by managing pointers. This pointer state can be read by control register 107. Line buffer 109 stores image data transferred from memory 102 by image DMA circuit 108. Further, the image data is transferred from the line buffer 109 to the LUT 110 by an SDi read circuit 1172, which will be described later.

The LUT 110 performs table conversion on the image data read from the memory 102 if table conversion is necessary due to the data structure. The LUT 110 then transfers the table-converted data to the selector 115 at the subsequent stage. On the other hand, when the image data read from the memory 102 does not require table conversion, the LUT 110 directly transfers the data transferred from the line buffer 109 to the selector 115 at the subsequent stage. The presence or absence of table conversion is controlled by the processor 101 via the control register 107.
Note that the image data that the LUT 110 reads from the memory 102 is, for example, 8 bits/pix. Of these 8 bits, for example, the upper 4 bits are actual drop tone data, and the lower 4 bits are fine tone data. This fine adjustment data can be combined, and may have a data configuration of 2 bits+2 bits out of 4 bits. In this case, the LUT 110 converts a 2-bit table into a 4-bit table.

The SPIT write circuit 111 writes the first SPIT data to the SPIT_RAM 112 under the control of the processor 101. Note that the first SPIT data is drop data when liquid is ejected from a specific nozzle of the liquid ejection head 200. Further, the SPIT writing circuit 111 writes the second SPIT data to the precursor SPIT_RAM 113 under the control of the processor 101. Note that the second SPIT data is SPIT data dedicated to the precursor. That is, the second SPIT data is drop data for performing a precursor operation. The second SPIT data is an example of precursor data for causing the liquid ejection head 200 to perform a precursor operation.

SPIT_RAM 112 is a memory that stores first SPIT data. SPIT_RAM 112 is, for example, DPRAM. Thereby, the SPIT_RAM 112 can read data and write data simultaneously or almost simultaneously.
The precursor SPIT_RAM 113 is a memory dedicated to the precursor. Precursor SPIT_RAM 113 is a memory that stores second SPIT data. Precursor SPIT_RAM 113 is an example of a first storage unit.

The selector 114 receives first SPIT data stored in the SPIT_RAM 112 and second SPIT data stored in the precursor SPIT_RAM 113 read from an SDi read circuit 1172 described later. The selector 114 selects and outputs one of the two input SPIT data based on the control by the precursor assist circuit 123. SPIT data output from selector 114 is input to selector 115.

The image data output from the LUT 110 and the SPIT data output from the selector 114 are input to the selector 115 . The selector 115 selects and outputs one of the two input data based on the signal output from the OR circuit 116. Data output from selector 115 is input to SDi transfer circuit 117.

The OR circuit 116 receives a signal output from a control register 1171 (described later) and a signal output from the precursor assist circuit 123. The OR circuit 116 ORs two input signals and outputs the result. The signal output from the OR circuit 116 is input to the selector 115.

The SDi transfer circuit 117 is a circuit for selecting either image data or SPIT data and transferring the selected data to the LVDS_DRV 124 by DMA. The SDi transfer circuit 117 includes, for example, a control register 1171, an SDi read circuit 1172, a FIFO 1173, and an SDi transfer DMA 1174. Note that SDi indicates drive waveform (config) data.

The control register 1171 stores the status etc. output by the SDi transfer DMA 1174. The control register 1171 controls the SDi read circuit 1172 and the SDi transfer DMA 1174 under the control of the processor 101.

The SDi read circuit 1172 issues a read enable and a read address to the line buffer 109, SPIT_RAM 112, and precursor SPIT_RAM 113. The data to be actually transferred to the subsequent FIFO 1173 is selected by the selector 114 and the selector 115. The SDi read circuit 1172 issues the next read enable and read address while managing the state of the FIFO 1173. If there is no free space in the FIFO 1173, the SDi read circuit 1172 enters an idle state without issuing the next read enable and read address. In this way, the SDi read circuit 1172 monitors the state of the FIFO 1173 and issues a read request to prevent the FIFO 1173 from being overwritten with data. The SDi read circuit 1172 repeats the above operation until the number of transfer lines set in the control register 1171 is reached. Furthermore, when the SDi read circuit 1172 reads one line of image data, it outputs a one line read completion signal to the image DMA circuit 108. The image DMA circuit 108 decrements a pointer for managing the state of the line buffer 109 based on this signal. The SDi read circuit 1172 is controlled by a signal output from the control register 1171.

The data output from the selector 115 is input to the FIFO 1173. The FIFO 1173 transfers the input data in response to a request from the SDi transfer DMA 1174.

The SDi transfer DMA 1174 is a circuit for transferring the data stored in the FIFO 1173 to the liquid ejection head 200 via the LVDS_DRV 124. After reading the data from the FIFO 1173, the SDi transfer DMA 1174 transfers the data to the liquid ejection head 200 in synchronization with Print_timing, and controls the ejection of the image data or SPIT data in the liquid ejection head 200, thereby reducing the time required for transfer. This is a circuit to make it shorter. Furthermore, when the data transfer is completed, the SDi transfer DMA 1174 outputs a status indicating that the data transfer has been completed to the control register 1171. Note that Print_timing is a timing signal for causing the liquid ejection head 200 to eject liquid. Print_timing is used for control as a starting point for data transfer to the liquid ejection head 200.

The configuration write circuit 118 writes the first configuration data to the CONFIG_RAM 119. The first configuration data is drive waveform data when the liquid ejection head 200 ejects liquid. Further, the configuration write circuit 118 writes the second configuration data to the precursor CONFIG_RAM 120. The second configuration data is configuration data dedicated to the precursor. That is, the second configuration data is drive waveform data for causing the liquid ejection head 200 to perform a precursor operation. The second configuration data is an example of setting data for changing the settings of the liquid ejection head 200 for precursor operation.

CONFIG_RAM 119 stores first configuration data. CONFIG_RAM 119 is, for example, DPRAM. Thereby, the CONFIG_RAM 119 can read data and write data simultaneously or almost simultaneously.
The precursor CONFIG_RAM 120 is a memory dedicated to the precursor. Precursor CONFIG_RAM 120 stores second configuration data. Precursor CONFIG_RAM 120 is an example of a second storage unit.

The selector 121 receives first configuration data stored in the CONFIG_RAM 119 and second configuration data stored in the precursor CONFIG_RAM 120 read from a CDi read circuit 1222 described later. The selector 121 selects and outputs one of the two input configuration data based on control by the precursor assist circuit 123. The configuration data output from the selector 121 is input to the CDi transfer circuit 122.

The CDi transfer circuit 122 is a circuit that transfers input configuration data to the liquid ejection head 200 via the LVDS_DRV 124 under the control of the processor 101. The CDi transfer circuit 122 includes, for example, a control register 1221, a CDi read circuit 1222, a FIFO 1223, and a CDi transfer DMA 1224. Note that CDi indicates configuration data.

The control register 1221 stores the status etc. output by the CDi transfer DMA 1224. The control register 1221 controls the CDi read circuit 1222, FIFO 1223, and CDi transfer DMA 1224 under the control of the processor 101.

The CDi read circuit 1222 issues read enable and read address to the CONFIG_RAM 119 and precursor CONFIG_RAM 120. The data to be actually transferred to the subsequent FIFO 1223 is selected by the selector 121. While managing the state of FIFO 1223, CDi read circuit 1222 issues the next read enable and read address. If there is no free space in the FIFO 1223, the CDi read circuit 1222 enters an idle state without issuing the next read enable or read address. In this way, the CDi read circuit 1222 monitors the state of the FIFO 1223 and issues a read request to the precursor CONFIG_RAM 120 so that the FIFO 1223 is not overwritten with data. The CDi read circuit 1222 repeats the above operation until the number of transfers set in the control register 1221 is reached. CDi read circuit 1222 is controlled by a signal output from control register 1221.

The data output from the selector 121 is input to the FIFO 1223. The FIFO 1223 transfers the input data in response to a request from the CDi transfer DMA 1224.

The CDi transfer DMA 1224 is a circuit that transfers the data stored in the FIFO 1223 to the liquid ejection head 200 via the LVDS_DRV 124. The CDi transfer DMA 1224 is a circuit that reads the data from the FIFO 1223 and then transfers it to the liquid ejection head 200 in synchronization with Print_timing, thereby shortening the time required for transfer. Furthermore, when the data transfer is completed, the CDi transfer DMA 1224 outputs a status indicating that the data transfer has been completed to the control register 1221.

The precursor assist circuit 123 is a circuit that operates as a state machine, which will be described later. The precursor assist circuit 123 stores internal settings in a register, for example. The internal settings can be changed, for example, by an operational input that instructs the liquid ejection device 1 to change the settings, or by an input that instructs the liquid ejection device 1 to change the settings from a device connected to the liquid ejection device 1. The precursor assist circuit 123 is, for example, an FPGA. Alternatively, precursor assist circuit 123 may be any other processor such as a CPU, MPU, SoC, DSP, GPU, ASIC, or PLD. The precursor assist circuit 123 is an example of a control section.

LVDS_DRV124 is a driver that uses LVDS as a data transfer method. LVDS is a differential transfer method that is less susceptible to external noise during transfer. The LVDS_DRV 124 converts input image data, SPIT data, and configuration data into differential signals, and transfers the data to the liquid ejection head 200.

The temperature sensor 300 is a sensor that measures the temperature of the drive IC 212. The temperature sensor 300 outputs measured temperature data. Temperature data output from the temperature sensor 300 is input to the control circuit 100 via the input/output controller 105.

As described above, the image data, SPIT data, and configuration data are transmitted in the order shown in FIG. 8. FIG. 8 is a diagram for explaining the data flow of image data, SPIT data, and configuration data.

That is, the image data is transmitted from the line buffer 109 to the liquid ejection head 200 via the LUT 110, selector 115, FIFO 1173, and SDi transfer DMA 1174. The first SPIT data and the second SPIT data are transmitted from the SPIT_RAM 112 to the liquid ejection head 200 via the selector 114, the selector 115, the FIFO 1173, and the SDi transfer DMA 1174. The first configuration data and the second configuration data are transmitted from the CONFIG_RAM 119 to the liquid ejection head 200 via the selector 121, FIFO 1223, and CDi transfer DMA 1224.
As described above, the line buffer 109 is an example of an input unit that inputs image data to the liquid ejection head 200.

The liquid ejection device 1 also includes a voltage control circuit 400 and a timing control circuit 500.
The voltage control circuit 400 is a circuit that generates and controls a voltage that drives the liquid ejection head.
The timing control circuit 500 is a circuit that generates and controls the timing at which the liquid ejection head ejects liquid.

Hereinafter, the operation of the liquid ejection device 1 according to the embodiment will be explained based on the drawings. Note that the contents of the processing in the following operation description are merely examples, and various processing that can obtain similar results can be used as appropriate.

The processor 101 of the liquid ejecting device 1 starts the process shown in the flowchart of FIG. 9, for example, when the liquid ejecting device 1 starts up or returns from sleep mode. FIG. 9 is a flowchart showing an example of processing by the processor 101 of the liquid ejection device 1. The processor 101 executes the process shown in FIG. 9 based on a program stored in, for example, the auxiliary storage device 104.

In ACT11, the processor 101 controls the SPIT write circuit 111 to write the second SPIT data to the precursor SPIT_RAM113. Furthermore, the processor 101 controls the configuration write circuit 118 to write the second configuration data to the precursor CONFIG_RAM 120. Note that the processor 101 performs the process of ACT11, for example, as an initial operation.

In ACT12, the processor 101 determines whether to start printing. For example, the processor 101 determines to start printing in response to an input instructing to start printing. The instruction is, for example, an operation input to the liquid ejection device 1. Alternatively, the instruction is transmitted to the liquid ejection device 1 from a PC (personal computer), a smart phone, a server device, or the like. If the processor 101 determines not to start printing, it determines No in ACT12 and repeats ACT12. If the processor 101 determines to start printing, it determines Yes in ACT12 and proceeds to ACT13.

In ACT13, the processor 101 controls each unit to start printing. That is, the processor 101 controls the image DMA circuit 108 to transfer image data to be printed to the line buffer 109. The image data is transferred from the line buffer 109 to the LUT 110. Further, the image data is transferred from the LUT 110 to the selector 115. The processor 101 controls the selector 115 via the control register 1171 to output the image data input from the LUT 110. The image data output from the selector 115 is transferred to the FIFO 1173, the SDi transfer DMA 1174, and the LVDS_DRV 124. As a result, the image data is printed by the liquid ejection head 200.

In ACT14, the processor 101 determines whether to end printing. For example, the processor 101 determines to end printing in response to completion of transfer of image data to be printed. If the processor 101 determines that printing is not to be completed, the processor 101 determines No in ACT14 and repeats ACT14. If the processor 101 determines to end printing, it determines Yes in ACT14 and returns to ACT12.

The state machine starts the process shown in the flowchart of FIG. 10, for example, when the liquid ejecting device 1 starts up or returns from sleep mode. FIG. 10 is a flowchart showing an example of the operation of the state machine by the precursor assist circuit 123. The precursor assist circuit 123 executes the process shown in FIG. 10, for example, by the operation of a circuit within the precursor assist circuit 123.

In ACT21 of FIG. 10, the state machine refers to the internal settings and determines whether the precursor assist function is set to be valid. If the precursor assist function is not set to be valid, the state machine determines No in ACT21 and ends the process shown in FIG. 10. On the other hand, if the precursor assist function is set to be valid, the state machine determines Yes in ACT21 and proceeds to ACT22. Note that the setting indicating whether the precursor assist function is enabled or disabled is an example of a function setting.

In ACT22, the state machine determines whether or not to cause the liquid ejection head 200 to start the precursor operation. For example, the state machine determines to start the precursor operation in response to the liquid ejection head 200 finishing the printing operation. For example, the state machine determines that the liquid ejection head 200 ends the printing operation in response to completion of transmission of image data to be printed to the liquid ejection head 200. If the state machine does not determine to start the precursor operation, it determines No in ACT22 and repeats ACT22. The state machine remains idle until it decides to initiate a precursor operation. If the state machine determines to start the precursor operation, it determines Yes in ACT22 and proceeds to ACT23.

In ACT23, the state machine controls the voltage control circuit 400 to set the drive voltage of the liquid ejection head 200 to the voltage for precursor operation. The state machine sets the voltage by transferring voltage setting data stored in the internal settings to the voltage control circuit 400.

In ACT24, the state machine changes the settings of the liquid ejection head 200 to execute the precursor operation. The state machine changes the settings by transferring the second configuration data stored in the precursor CONFIG_RAM 120 to the liquid ejection head 200 via the LVDS_DRV 124. To this end, the state machine controls the selector 121 so that the selector 121 outputs the second configuration data.

In ACT25, the state machine sets a drive cycle necessary for causing the liquid ejection head 200 to perform the precursor operation. The state machine sets the drive cycle by transferring drive cycle setting data stored in the internal settings to the timing control circuit 500.

In ACT26, the state machine causes the liquid ejection head 200 to perform the precursor operation by transferring the second SPIT data stored in the precursor SPIT_RAM 113 to the liquid ejection head 200 via the LVDS_DRV 124. To this end, the state machine controls the selector 114 so that the selector 114 outputs the second SPIT data. The state machine also controls the selector 115 so that the selector 115 outputs the second SPIT data.

In ACT27, the state machine determines whether or not to end the precursor operation of the liquid ejection head 200. The state machine determines to end the precursor operation in response to the start of the print operation. If the state machine does not determine to end the precursor operation, it determines No in ACT27 and returns to ACT26. On the other hand, if the state machine determines to end the precursor operation, it determines Yes in ACT27 and returns to ACT22.

The state machine transits through the states shown in FIG. 11 by repeating ACT22 to ACT27 as described above. FIG. 11 is a state transition diagram showing an example of the operation of the state machine by the precursor assist circuit 123.

Further, the state machine may perform the processing shown in the flowchart of FIG. 12 instead of the processing shown in FIG. 10. FIG. 12 is a flowchart showing an example of the operation of the state machine by the precursor assist circuit 123. The precursor assist circuit 123 executes the process shown in FIG. 12, for example, by the operation of a circuit within the precursor assist circuit 123.

In FIG. 12, the processing in ACT12 to ACT27 is the same as that in FIG. However, in FIG. 12, the state machine proceeds to ACT31 after processing ACT26.
In ACT31, the state machine determines whether the drive IC 212 is at a high temperature. For example, if the temperature of the drive IC 212 is equal to or higher than the threshold T1, the state machine determines that the drive IC 212 is at a high temperature. The threshold value T1 is determined in advance by, for example, a designer of the control circuit 100. Further, the threshold value T1 may be set and changeable by an operator of the liquid ejection device 1 or the like. If the state machine determines that the drive IC 212 is not at high temperature, it determines No in ACT31 and proceeds to ACT27. On the other hand, if the state machine determines that the drive IC 212 is at a high temperature, it determines Yes in ACT31 and proceeds to ACT32.

In ACT32, the state machine determines whether the temperature of the drive IC 212 has decreased and is no longer at a high temperature. For example, the state machine determines that the drive IC 212 is no longer at a high temperature if the temperature of the drive IC 212 is less than the threshold T2. The threshold value T2 is determined in advance by, for example, a designer of the control circuit 100. Further, the threshold value T2 may be set and changeable by the operator of the liquid ejection device 1 or the like. Note that the threshold value T1 and the threshold value T2 have a magnitude relationship of T2≦T1. If the state machine determines that the drive IC 212 remains at a high temperature, it determines No in ACT32 and proceeds to ACT33.

In ACT33, the state machine determines whether or not to end the precursor operation of the liquid ejection head 200, similarly to ACT27. If the state machine does not determine to end the precursor operation, it determines No in ACT33 and returns to ACT32. In this way, the state machine repeats ACT32 and ACT33 until it determines that the drive IC 212 is no longer at a high temperature or determines to terminate the precursor operation.
Since the state machine does not execute the process of ACT26 while repeating ACT32 and ACT33, the liquid ejection head 200 does not perform the precursor operation during this time.

If the state machine determines that the drive IC 212 is no longer hot in the standby state of ACT32 and ACT33, it determines Yes in ACT32 and returns to ACT26. As described above, the liquid ejection head 200 stops the precursor operation while the drive IC 212 is at high temperature, and stops the precursor operation when the drive IC 212 is no longer at high temperature.

If the state machine determines to end the precursor operation while in the standby state of ACT32 and ACT33, it determines Yes in ACT33 and returns to ACT22.

According to the liquid ejection apparatus 1 of the embodiment, the control circuit 100 transmits image data to the liquid ejection head 200. Thereby, the control circuit 100 causes the liquid ejection head 200 to perform a printing operation. Then, the control circuit 100 transmits the second SPIT data stored in the precursor SPIT_RAM 113 to the liquid ejection head 200 by switching the outputs of the selector 114 and the selector 115. Thereby, the control circuit 100 causes the liquid ejection head 200 to perform the precursor operation. The second SPIT data is stored in the precursor SPIT_RAM 113 in advance. Therefore, since the control circuit 100 performs the precursor operation by transmitting pre-stored data through the operation of the hardware, the speed at which the liquid ejection head 200 is switched from the printing operation to the precursor operation is faster than when switching is performed by software. It's fast. That is, the control circuit 100 uses hardware acceleration to increase the speed at which the liquid ejection head 200 is switched from printing operation to precursor operation.
Furthermore, since the control circuit 100 takes a short time to switch the liquid ejection head 200 from the printing operation to the precursor operation, the temperature rise of the drive IC 212 can be suppressed accordingly.

Further, according to the liquid ejection apparatus 1 of the embodiment, the control circuit 100 stops the precursor operation of the liquid ejection head 200 when the temperature of the drive IC is high. Thereby, the control circuit 100 prevents the temperature of the drive IC from rising too much.

Further, according to the liquid ejection device 1 of the embodiment, the control circuit 100 causes the liquid ejection head 200 to perform the precursor operation when the precursor assist function is enabled, and causes the liquid ejection head 200 to perform the precursor operation when the precursor assist function is disabled. , the liquid ejection head 200 is not caused to perform the precursor operation. Therefore, when the precursor operation is not required, the control circuit 100 can prevent the liquid ejection head 200 from performing the precursor operation by changing the settings.

Further, according to the liquid ejection apparatus 1 of the embodiment, the control circuit 100 causes the liquid ejection head 200 to start the precursor operation in response to completion of inputting image data to the liquid ejection head 200. Thereby, the control circuit 100 can cause the liquid ejection head 200 to perform the precursor operation immediately after the printing operation is finished.

Further, according to the liquid ejection apparatus 1 of the embodiment, the control circuit 100 transmits the second configuration data stored in the precursor CONFIG_RAM 120 to the liquid ejection head 200 by switching the output of the selector 121. Thereby, the control circuit 100 changes the setting of the liquid ejection head 200 to perform the precursor operation. The second configuration data is stored in the precursor CONFIG_RAM 120 in advance. Therefore, since the control circuit 100 changes the settings of the liquid ejection head 200 by transmitting pre-stored data through hardware operations, the time required to change settings is faster than when changing settings using software. .

The above embodiment can also be modified as follows.
In the control circuit of the embodiment, the SPIT_RAM 112 and the precursor SPIT_RAM 113 may be configured as one RAM. This RAM will hereinafter be referred to as "shared SPIT_RAM". The shared SPIT_RAM divides the RAM into two address spaces, one for normal operation and the other for precursor operation. Writing to and reading from the shared SPIT_RAM is performed by specifying an address. The address space for normal operation stores the same data as SPIT_RAM 112. The precursor operation address space stores the same data as the precursor SPIT_RAM 113. When making a read request to the shared SPIT_RAM, the SDi read circuit 1172 specifies an address in the address space for normal operation during normal operation, and specifies an address in the address space for precursor operation during precursor operation. Thereby, the SDi read circuit 1172 becomes a substitute for the selector 114. From the above, the shared SPIT_RAM is an example of the first storage unit.

In the control circuit of the embodiment, the CONFIG_RAM 119 and the precursor CONFIG_RAM 120 may be configured as one RAM. This RAM will hereinafter be referred to as "shared CONFIG_RAM". The shared CONFIG_RAM divides the RAM into two address spaces, one for normal operation and the other for precursor operation. Writing to and reading from the shared CONFIG_RAM is performed by specifying an address. The address space for normal operation stores the same data as CONFIG_RAM 119. The precursor operation address space stores the same data as the precursor CONFIG_RAM 120. When making a read request to the shared CONFIG_RAM, the CDi read circuit 1222 specifies an address in the address space for normal operation during normal operation, and specifies an address in the address space for precursor operation during precursor operation. Thereby, the CDi read circuit 1222 becomes a substitute for the selector 121. From the above, the shared CONFIG_RAM is an example of the second storage unit.

In the above embodiment, in the liquid ejection device 1, the pressure chambers 215 are continuously arranged. However, the liquid ejection device of the embodiment may include an air chamber. In this case, in the liquid ejection device of the embodiment, for example, pressure chambers and air chambers are arranged alternately.

In addition to the embodiments described above, the liquid ejection head 200 may have a structure in which ink is ejected by deforming a diaphragm using static electricity, or a structure in which ink is ejected from nozzles using thermal energy such as a heater. .

The liquid ejection device 1 of the embodiment is an inkjet printer that forms a two-dimensional image using a recording material on an image forming medium. However, the liquid ejection device of the embodiment is not limited to this. The liquid ejection device of the embodiment may be, for example, a 3D printer, an industrial manufacturing machine, a medical machine, or the like. When the liquid ejection device of the embodiment is a 3D printer, an industrial manufacturing machine, a medical machine, etc., the liquid ejection device of the embodiment includes, for example, a material that is a raw material or a binder for solidifying the material. A three-dimensional object is formed by ejecting liquid from a liquid ejection head.

In the above embodiment, the case where the liquid ejection head control device is used in the liquid ejection apparatus 1 has been described. However, the liquid ejection head control device of the embodiment may be used in other devices that operate the liquid ejection head 200. For example, the liquid ejection head control device of the embodiment may be used as an evaluation device that evaluates the characteristics of the liquid ejection head 200 or a recording material by operating the liquid ejection head 200.

The processor 101 may implement part or all of the processing implemented by the program in the above embodiments using a hardware configuration of a circuit.

Although several embodiments of the invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included within the scope and gist of the invention, as well as within the scope of the invention described in the claims and its equivalents.
Note that the claims of the present application as originally filed are appended below.
[C1]
an input unit for inputting image data to be printed into the liquid ejection head;
a first storage unit that stores precursor data for causing the liquid ejection head to perform a precursor operation;
By switching the input source of data input to the liquid ejection head from the input unit to the first storage unit and inputting the precursor data to the liquid ejection head, the precursor operation is performed on the liquid ejection head. A liquid ejection head control device comprising: a control unit for executing the liquid ejection head;
[C2]
The liquid ejection head control device according to claim 1, wherein the control unit stops the precursor operation of the liquid ejection head when the temperature of the drive IC is equal to or higher than a threshold value.
[C3]
The control unit causes the liquid ejection head to perform the precursor operation when the function setting is valid, and does not cause the liquid ejection head to perform the precursor operation when the function setting is not valid. 3. The liquid ejection head control device according to item 2.
[C4]
The liquid ejection device according to any one of claims 1 to 3, wherein the control unit causes the liquid ejection head to perform the precursor operation when inputting the image data to the liquid ejection head is completed. Head control device.
[C5]
further comprising a second storage unit that stores setting data for changing the liquid ejection head to settings for precursor operation;
The control unit changes the setting of the liquid ejection head to a precursor operation by switching the input source of data input to the liquid ejection head to the second storage unit. The liquid ejection head control device according to any one of the items.

1... Liquid ejection device, 101... Processor, 102... Memory, 103... Memory controller, 104... Auxiliary storage device, 105... Input/output controller, 106... Clock generation circuit, 107... Control register, 108...Image DMA circuit, 109...Line buffer, 110...LUT, 111...SPIT write circuit, 112...SPIT_RAM, 113...Precursor SPIT_RAM, 114, 115, 121...Selector, 116...OR Circuit, 117...SDi transfer circuit, 118...Config write circuit, 119...CONFIG_RAM, 120...Precursor CONFIG_RAM, 122...CDi transfer circuit, 123...Precursor assist circuit, 124...LVDS_DRV, 200... Liquid ejection head, 212... Drive IC, 300... Temperature sensor, 400... Voltage control circuit, 500... Timing control circuit, 1171, 1221... Control register, 1172... SDi read circuit, 1173, 1223... FIFO, 1174...SDi transfer DMA, 1222...CDi read circuit, 1224...CDi transfer DMA

Claims (5)

an input unit for inputting image data to be printed into the liquid ejection head;
a first storage unit that stores precursor data for causing the liquid ejection head to perform a precursor operation;
a selector that selects one of the image data input from the input unit and the precursor data input from the first storage unit and outputs the selected one to the liquid ejection head;
By controlling the selector to switch the input source of data input to the liquid ejection head from the input unit to the first storage unit and inputting the precursor data to the liquid ejection head, the liquid A liquid ejection head control device comprising: a control unit that causes the ejection head to perform the precursor operation. The liquid ejection head control device according to claim 1, wherein the control unit stops the precursor operation of the liquid ejection head when the temperature of the drive IC is equal to or higher than a threshold value. The control unit causes the liquid ejection head to perform the precursor operation when the function setting is valid, and does not cause the liquid ejection head to perform the precursor operation when the function setting is not valid. 3. The liquid ejection head control device according to item 2. The liquid ejection device according to any one of claims 1 to 3, wherein the control unit causes the liquid ejection head to perform the precursor operation when inputting the image data to the liquid ejection head is completed. Head control device. further comprising a second storage unit that stores setting data for changing the liquid ejection head to settings for precursor operation;
The control unit changes the setting of the liquid ejection head to a precursor operation by switching the input source of data input to the liquid ejection head to the second storage unit. The liquid ejection head control device according to any one of the items.