JP7407230B2 - キー値データ記憶デバイスのためのeccパリティ偏り - Google Patents
キー値データ記憶デバイスのためのeccパリティ偏り Download PDFInfo
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Description
Claims (16)
- データ記憶コントローラであって、
メモリとインターフェースするように構成されたメモリインターフェースと、
前記メモリに記憶されたデータに対してECC符号化を実行するように構成されたエラー訂正コード(ECC)エンジンと、
フラッシュ変換レイヤ(FTL)及び名前空間データベースを含むコントローラメモリと、
前記ECCエンジン及び前記コントローラメモリに通信可能に接続された電子プロセッサであって、前記電子プロセッサは、前記FTLを実行するときに、
記憶されるデータを受信し、
前記データを複数のサブコードブロックに分離し、
前記ECCエンジンによって生成されたパリティビットを、前記複数のサブコードブロックの各サブコードブロックに割り当てる、ように構成されている、電子プロセッサと
を備え、
前記複数のサブコードブロックは、空間結合低密度パリティ検査(SC-LDPC)構造の一部である複数のタイルである、データ記憶コントローラ。 - 前記パリティビットは、前記複数のタイルの各タイルに不均一に割り当てられる、請求項1に記載のデータ記憶コントローラ。
- 前記複数のタイルのうちの第1のタイルには、前記複数のタイルの最後のタイルよりも多くのパリティビットが割り当てられる、請求項2に記載のデータ記憶コントローラ。
- 前記電子プロセッサは、前記FTLを実行するときに、
前記パリティビットを前記複数のタイルの各タイルに割り当てた後、前記複数のタイルのうちの第1のタイルを前記メモリに書き込み、
前記複数のタイルの前記第1のタイルを前記メモリに書き込んだ後、前記複数のタイルのうちの最後のタイルを前記メモリに書き込む、ように更に構成されている、請求項1~3のいずれか一項に記載のデータ記憶コントローラ。 - 前記電子プロセッサは、前記FTLを実行するときに、
前記パリティビットを前記複数のタイルの各タイルに割り当てた後、前記複数のタイルを前記メモリに書き込み、前記複数のタイルは、メモリに順次書き込まれる、ように更に構成されている、請求項1~3のいずれか一項に記載のデータ記憶コントローラ。 - 前記電子プロセッサは、前記FTLを実行するときに、
スライディングウィンドウプロセスを使用して、前記複数のタイルが前記メモリに書き込まれた順序で前記メモリから前記複数のタイルを復号する、ように更に構成されている、請求項5に記載のデータ記憶コントローラ。 - 方法であって、
データ記憶コントローラの電子プロセッサを用いて、キー値(KV)データベースに記憶されるデータを受信することと、
前記データを複数のサブコードブロックに分離することと、
パリティビットを前記複数のサブコードブロックの各サブコードブロックに割り当てることと
を含み、
前記複数のサブコードブロックは、空間結合低密度パリティ検査(SC-LDPC)構造の一部である複数のタイルである、方法。 - 前記パリティビットは、前記複数のタイルの各タイルに不均一に割り当てられる、請求項7に記載の方法。
- 前記複数のタイルのうちの第1のタイルには、前記複数のタイルの最後のタイルよりも多くのパリティビットが割り当てられる、請求項8に記載の方法。
- 前記パリティビットを前記複数のタイルの各タイルに割り当てた後に、前記複数のタイルを前記キー値(KV)データベースに書き込むことと
を更に含む、請求項7~9のいずれか一項に記載の方法。 - 前記タイルを前記KVデータベースに書き込むことは、
前記複数のタイルのうちの第1のタイルを前記KVデータベースに書き込むことと、
前記複数のタイルの前記第1のタイルを前記KVデータベースに書き込んだ後、前記複数のタイルのうちの最後のタイルを前記KVデータベースに書き込むことと
を含む、請求項10に記載の方法。 - 前記複数のタイルが前記KVデータベースに書き込まれた順序で前記KVデータベースから前記複数のタイルを復号すること
を更に含み、前記複数のタイルは、スライディングウィンドウプロセスを使用して復号される、請求項11に記載の方法。 - キー値名前空間へのデータの記憶をサポートするメモリデバイスであって、前記メモリデバイスは、
キー値(KV)データベースを含むメモリと、
前記KVデータベースにユーザデータを書き込むときに、パリティを前記ユーザデータに割り当てる第1のエラー訂正コード(ECC)符号化プロセスを実行するように構成されたコントローラと
を備え、
前記コントローラは、前記ユーザデータを外部電子デバイス内に位置する第2のKVデータベースに書き込むときに、前記ユーザデータにパリティを割り当てる第2のECC符号化プロセスを実行するように更に構成されている、メモリデバイス。 - 前記第1のECC符号化プロセスは、前記ユーザデータの最初に、前記ユーザデータの最後よりも多くのパリティビットを割り当てる、請求項13に記載のメモリデバイス。
- キー値名前空間へのデータの記憶をサポートするメモリデバイスであって、前記メモリデバイスは、
キー値(KV)データベースを含むメモリと、
前記KVデータベースにユーザデータを書き込むときに、パリティを前記ユーザデータに割り当てる第1のエラー訂正コード(ECC)符号化プロセスを実行するように構成されたコントローラと
を備え、
前記ユーザデータを前記KVデータベースに書き込むときに、前記パリティを前記ユーザデータに割り当てる前記第1のECC符号化プロセスを実行するために、前記コントローラは、
前記ユーザデータを、空間結合低密度パリティ検査(SC-LDPC)構造の複数のタイルに分離する、メモリデバイス。 - 前記ユーザデータを前記KVデータベースに書き込むときに、前記パリティを前記ユーザデータに割り当てる前記第1のECC符号化プロセスを実行するために、前記コントローラは、
前記複数のタイルのうちの第1のタイルを前記KVデータベースに書き込み、
前記第1のタイルを前記KVデータベースに書き込んだ後、前記複数のタイルのうちの最後のタイルを前記KVデータベースに書き込む、ように更に構成されている、請求項15に記載のメモリデバイス。
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US17/531,975 US11934264B2 (en) | 2021-11-22 | 2021-11-22 | ECC parity biasing for Key-Value data storage devices |
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US20230161666A1 (en) | 2023-05-25 |
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