JP7405027B2 - Semiconductor device and its manufacturing method - Google Patents

Description

The technical field of this specification relates to a semiconductor device and a manufacturing method thereof.

Group III nitride semiconductors represented by GaN have a high dielectric breakdown electric field. Therefore, group III nitride semiconductors are expected to replace GaAs-based semiconductors as materials for high-output, high-frequency, high-temperature semiconductor devices. For this reason, HEMT devices using Group III nitride semiconductors are being researched and developed.

For example, Patent Document 1 discloses a technique of using a SiN film and a SiO ₂ film as a gate insulating film in a field effect transistor. A SiN film is formed on the Group III nitride semiconductor, and an SiO ₂ film is formed on the SiN film (paragraphs [0036] to [0038] of Patent Document 1 and FIG. 2D). It is disclosed that this reduces the nitrogen vacancy density between the source and drain (paragraph [0041] of Patent Document 1). Furthermore, it is disclosed that generation of surface charge between the source and drain is suppressed, and surface leakage current is suppressed (paragraph [0041] of Patent Document 1).

Japanese Patent Application Publication No. 2009-32796

In the technique disclosed in Patent Document 1, a SiN film is in contact with the surface of a group III nitride semiconductor. The SiN film is an insulating nitride film. The dielectric breakdown strength of an insulating nitride film tends to be lower than that of an insulating oxide film (SiO ₂ etc.). Further, in an insulating nitride film, electrons are easily injected into the film. When electrons are injected into the insulating nitride film, the operation of the semiconductor device becomes unstable.

However, when a SiO ₂ film is brought into direct contact with a group III nitride semiconductor, oxygen in the SiO ₂ film oxidizes the surface of the group III nitride semiconductor. Since the surface of the group III nitride semiconductor corresponds to the vicinity of the gate, if the surface of the group III nitride semiconductor is oxidized, the operation of the semiconductor device becomes unstable.

The problem to be solved by the technology of this specification is to provide a semiconductor device that suppresses injection of electrons from a group III nitride semiconductor into an insulating film and suppresses oxidation of the surface of a group III nitride semiconductor caused by the insulating film. An object of the present invention is to provide a manufacturing method thereof.

The method for manufacturing a semiconductor device according to the first aspect includes the steps of forming a first insulating oxide film on the group III nitride semiconductor layer, and forming a first insulating oxide film on the group III nitride semiconductor layer and the first insulating oxide film. A step of irradiating nitrogen plasma from the side of the insulating oxide film, a first heat treatment step of heat-treating the first insulating oxide film, and a step of forming a second insulating oxide film on the first insulating oxide film. and a second heat treatment step of heat treating the second insulating oxide film.

This method of manufacturing a semiconductor device includes forming a first insulating oxide film on a group III nitride semiconductor layer, forming a first insulating nitride film above the first insulating oxide film, and forming a first insulating nitride film on a group III nitride semiconductor layer. A second insulating oxide film may be formed on the nitride film. Since the group III nitride semiconductor layer is in contact with the first insulating oxide film, injection of electrons from the group III nitride semiconductor into the insulating film is suppressed. Since nitrogen is implanted into the group III nitride semiconductor layer, oxidation of the surface of the group III nitride semiconductor caused by the insulating film is suppressed.

The present specification provides a semiconductor device that suppresses injection of electrons from a group III nitride semiconductor into an insulating film and suppresses oxidation of the surface of a group III nitride semiconductor caused by the insulating film, and a method for manufacturing the same. .

FIG. 1 is a schematic configuration diagram of a semiconductor device 100 according to a first embodiment. FIG. 3 is a diagram showing a stacked structure of a gate insulating film F10 of the semiconductor device 100 of the first embodiment. 5 is a flowchart showing a method for forming an insulating film of the semiconductor device 100 of the first embodiment. FIG. 3 is a diagram showing a method for forming an insulating film of the semiconductor device 100 of the first embodiment. FIG. 2 is a schematic configuration diagram of a semiconductor device 200 according to a second embodiment. FIG. 3 is a schematic configuration diagram of a semiconductor device 300 according to a third embodiment. It is a graph showing the result of SIMS analysis of MIS capacitor. It is a graph showing a 1s spectrum of oxygen atoms of a structure (sample) irradiated with nitrogen plasma. It is a graph showing the 1s spectrum of oxygen atoms of a structure (sample) that was not irradiated with nitrogen plasma. It is a graph showing CV characteristics of a structure (sample) when the temperature of the first heat treatment step is 900°C. It is a graph showing CV characteristics of a structure (sample) when the temperature of the first heat treatment step is 700°C. It is a graph showing CV characteristics of a structure (sample) when the temperature of the first heat treatment step is 500°C.

Hereinafter, specific embodiments will be described using a semiconductor device and a method for manufacturing the same as an example. However, the technology herein is not limited to these embodiments. In this specification, the first conductivity type represents n-type, and the second conductivity type represents p-type. However, the first conductivity type may represent a p-type, and the second conductivity type may represent an n-type.

(First embodiment)
1. Semiconductor Device FIG. 1 is a schematic configuration diagram of a semiconductor device 100 of the first embodiment. The semiconductor device 100 is a MISFET. Semiconductor device 100 does not have a trench. The semiconductor device 100 includes a GaN substrate 110, a first semiconductor layer 120, a second semiconductor layer 130, a semiconductor region 140, a gate insulating film F10, a gate electrode G1, a body electrode B1, a source electrode S1, and a drain electrode D1.

The first semiconductor layer 120, the second semiconductor layer 130, and the semiconductor region 140 are group III nitride semiconductor layers. The first semiconductor layer 120 is, for example, a GaN layer. The second semiconductor layer 130 is, for example, a p-type GaN layer. The semiconductor region 140 is, for example, n ⁺ GaN. The semiconductor region 140 is a region in which ions are implanted into a part of the semiconductor.

The gate insulating film F10 is formed on the second semiconductor layer 130 and the semiconductor region 140. Gate electrode G1 is formed on gate insulating film F10. The gate electrode G1 faces the second semiconductor layer 130 and part of the semiconductor region 140 with the gate insulating film F10 interposed therebetween. Source electrode S1 and drain electrode D1 are formed on semiconductor region 140.

2. Gate insulating film 2-1. Laminated Structure FIG. 2 is a diagram showing a laminated structure of the gate insulating film F10 of the semiconductor device 100 of the first embodiment. The gate insulating film F10 is a gate insulating film that covers part of the surface of the group III nitride semiconductor layer. The gate insulating film F10 protects the surface of the group III nitride semiconductor layer. The gate insulating film F10 is arranged at a position between the second semiconductor layer 130 and the semiconductor region 140, and the gate electrode G1. The gate insulating film F10 includes an insulating oxynitride film, an insulating nitride film, and an insulating oxide film. The gate insulating film F10 includes a SiON film F11, a SiN film F13, and a SiO ₂ film F14.

The SiON film F11 covers at least a portion of the surfaces of the second semiconductor layer 130 and the semiconductor region 140. The SiON film F11 is formed on the second semiconductor layer 130 and the semiconductor region 140. The SiON film F11 is in contact with the second semiconductor layer 130 and the semiconductor region 140. The thickness of the SiON film F11 is, for example, 1 nm or more and 6 nm or less. Preferably, the thickness is 1 nm or more and 4 nm or less.

The SiN film F13 is formed at a position above the SiON film F11. The SiN film F13 is formed on the SiON film F11. The SiN film F13 is in contact with the SiON film F11. The thickness of the SiN film F13 is, for example, 1 nm or more and 3 nm or less. Preferably, the thickness is 1 nm or more and 2 nm or less.

The SiO ₂ film F14 is formed on the SiN film F13. The SiO ₂ film F14 is in contact with the SiN film F13. The thickness of the SiO ₂ film F14 is, for example, 40 nm or more and 100 nm or less.

2-2. Nitrogen Concentration In the gate insulating film F10, the nitrogen concentration increases from the semiconductor side toward the gate electrode G1, and decreases after being saturated. The SiON film F11 contains nitrogen atoms. The nitrogen atom content in the SiON film F11 is, for example, 1×10 ²¹ atm/cm ³ or more and less than 1×10 ²² atm/cm ³ . The nitrogen atom content in the SiON film F11 is greater than the nitrogen atom content in the SiO ₂ film F14. This is because the SiON film F11 is irradiated with nitrogen plasma, as will be described later.

3. Role of each layer of the gate insulating film The SiON film F11 is a diffusion prevention layer that prevents oxygen atoms from diffusing into the group III nitride semiconductor. The SiON film F11 is sufficiently thin and has been heat-treated at a high temperature. Therefore, oxygen atoms are difficult to move. Further, the SiON film F11 is a layer for suppressing injection of electrons from the group III nitride semiconductor into the insulating film. The SiON film F11 protects the group III nitride semiconductor in the insulating film forming method described later. Therefore, group III nitride semiconductors are hardly damaged by nitrogen plasma irradiation, which will be described later.

The SiN film F13 is a film for protecting the group III nitride semiconductor from moisture. Note that the SiON film F11 suppresses injection of electrons into the SiN film F13.

The SiO ₂ film F14 is a film for protecting the group III nitride semiconductor with high electrical insulation. Therefore, the SiO ₂ film F14 can suppress gate leakage current.

In this way, the gate insulating film F10 prevents the group III nitride semiconductor from being oxidized and suppresses the injection of electrons from the group III nitride semiconductor into the insulating film. Therefore, the semiconductor device 100 having the gate insulating film F10 has good CV characteristics (capacitance voltage characteristics).

4. Method for Forming an Insulating Film FIG. 3 is a flowchart showing a method for forming an insulating film of the semiconductor device 100 of the first embodiment. As shown in FIG. 3, this film formation method includes a step of forming a first insulating oxide film on the group III nitride semiconductor layer, and a step of forming a first insulating oxide film on the group III nitride semiconductor layer and the first insulating oxide film. A step of irradiating nitrogen plasma from the side of the first insulating oxide film, a first heat treatment step of heat-treating the first insulating oxide film, and forming a second insulating oxide film on the first insulating oxide film. and a second heat treatment step of heat treating the second insulating oxide film. Here, a case will be described in which the gate insulating film F10 is formed.

4-1. First Insulating Film Forming Step As shown in FIG. 4, a first insulating oxide film I1 is formed on the second semiconductor layer 130 and the semiconductor region 140 (S101). The film forming method is, for example, reactive sputtering, CVD method, or ALD method. In the case of reactive sputtering, metal mode is used. In the case of the CVD method, thermal CVD is used. In the case of the ALD method, H ₂ O or O ₃ is used in the oxidation method. The thickness of the first insulating oxide film I1 is, for example, 2 nm or more and 9 nm or less. Preferably, the thickness is 3 nm or more and 6 nm or less. As shown in FIG. 4, the first insulating oxide film I1 has a portion that is nitrided to become the SiON film F11 and a portion that is nitrided to become the SiN film F13.

4-2. Nitrogen Plasma Treatment Step Nitrogen plasma is applied to the second semiconductor layer 130, the semiconductor region 140, and the first insulating oxide film I1 from the first insulating oxide film I1 side (S102). For example, ECR plasma, ICP, and surface wave plasma can be used. The plasma gas is _N2 gas. The flow rate of nitrogen gas (N ₂ ) is, for example, 20 sccm or more and 100 sccm or less.

The substrate temperature is, for example, 0° C. or higher and 300° C. or lower. The bias power on the substrate side is, for example, 0 W or more and 20 W or less. In order not to damage the insulating film, the second semiconductor layer 130, and the semiconductor region 140, the bias power should be weak. The processing time is, for example, 10 minutes or more and 150 minutes or less. These numerical ranges are just examples, and numerical values other than those mentioned above may be used.

At this time, it is preferable to remove charged particles such as electrons and cations from the nitrogen plasma. For example, a metal net is placed in the path of nitrogen plasma movement. As a result, the first insulating oxide film I1 is irradiated with nitrogen radicals. Alternatively, charged particles may be removed by applying a magnetic field to the moving path of the nitrogen plasma. Alternatively, the distance between the nitrogen plasma generation region and the substrate may be increased, and the bias power on the substrate side may be weakened.

Since the first insulating oxide film I1 is sufficiently thin, nitrogen radicals are supplied to the surface side of the first insulating oxide film I1, the second semiconductor layer 130, and the semiconductor region 140. As a result, mainly the surface side of the first insulating oxide film I1 is nitrided, and nitrogen is implanted into the surface side of the second semiconductor layer 130 and the semiconductor region 140. This reduces the nitrogen vacancy density in the second semiconductor layer 130 and the semiconductor region 140. As shown in FIG. 4, the surface side of the first insulating oxide film I1 is sufficiently nitrided to become a SiN film F13, and the second semiconductor layer 130 and semiconductor region 140 side of the first insulating oxide film I1 is partially nitrided. It is nitrided to become a SiON film F11.

In this way, in the nitrogen plasma treatment step, nitrogen radicals are supplied to at least the surface of the group III nitride semiconductor layer to reduce the nitrogen vacancy density of the group III nitride semiconductor layer, thereby reducing the density of the first insulating oxide film I1. Nitrid the surface.

Note that since the first insulating oxide film I1 exists, nitrogen radicals hardly damage the second semiconductor layer 130 and the semiconductor region 140.

4-3. First heat treatment step Next, a first heat treatment step is performed on the semiconductor and insulating film irradiated with nitrogen plasma (S103). The heat treatment temperature in the first heat treatment step is, for example, 800°C or more and 1000°C or less. Preferably, the temperature is 900°C or higher. The heat treatment time is, for example, 10 minutes or more and 60 minutes or less. Preferably, it is 30 minutes or more. These numerical ranges are just examples, and numerical values other than those mentioned above may be used.

4-4. Second Insulating Film Forming Step Next, a second insulating oxide film (SiO ₂ film F14) is formed on the first insulating oxide film I1 (S104). The film forming method is, for example, reactive sputtering, CVD method, or ALD method. In the case of reactive sputtering, oxide mode is used. In the case of the CVD method, plasma may be used. In the case of the ALD method, plasma may be used for oxidation. The thickness of the SiO ₂ film F14 is, for example, 40 nm or more and 100 nm or less.

4-5. Second heat treatment step Next, a second heat treatment step is performed on the semiconductor and the insulating film (S105). As a result, the SiON film F11, the SiN film F13, and the SiO ₂ film F14 are formed in this order from the second semiconductor layer 130 and the semiconductor region 140. The heat treatment temperature in the second heat treatment step is, for example, 400°C or more and 600°C or less. The heat treatment temperature in the second heat treatment step is lower than the heat treatment temperature in the first heat treatment step. The heat treatment time is, for example, 10 minutes or more and 30 minutes or less. These numerical ranges are just examples, and numerical values other than those mentioned above may be used.

4-6. Other Processes Other processes may also be implemented. For example, before the first insulating oxide film forming step and the second insulating oxide film forming step, an organic cleaning step for organically cleaning the group III nitride semiconductor and the insulating film may be performed.

5. Manufacturing method of semiconductor device 5-1. Semiconductor Layer Formation Step The first semiconductor layer 120, the second semiconductor layer 130, and the semiconductor region 140 are grown in this order on the GaN substrate 110. For that purpose, for example, MOCVD method may be used. Alternatively, other vapor phase growth methods may be used. Alternatively, a liquid phase growth method may be used. Further, a semiconductor region 140 is formed by ion implantation.

5-2. Insulating Film Forming Step A gate insulating film F10 is formed on the second semiconductor layer 130 and the semiconductor region 140. The method for forming an insulating film described above may be used. Further, the gate insulating film F10 is not formed in the region where the source electrode S1 and the drain electrode D1 are to be formed. Therefore, for example, after forming a uniform insulating film on the surfaces of the second semiconductor layer 130 and the semiconductor region 140, the insulating film in the regions where the source electrode S1 and the drain electrode D1 are to be formed may be removed. For this purpose, for example, etching may be performed using a fluorine gas such as CF ₄ or C ₄ F ₆ .

5-3. Gate Electrode Formation Step A gate electrode G1 is formed on the gate insulating film F10. For this purpose, a film forming technique such as ALD method or sputtering may be used.

5-4. Source Electrode Formation Step Body electrode B1 and source electrode S1 are formed on second semiconductor layer 130 and semiconductor region 140. For this purpose, sputtering, EB evaporation, or resistance heating evaporation may be used.

5-5. Drain Electrode Formation Step A drain electrode D1 is formed on the semiconductor region 140. For this purpose, sputtering, EB evaporation, or resistance heating evaporation may be used.

5-6. Element Separation Process Then, the semiconductor devices 100 are cut out from the wafer, and each independent semiconductor device 100 is manufactured.

5-7. Other Steps Other steps such as a protective film forming step, a heat treatment step, etc. may be performed as appropriate. Through the above steps, the semiconductor device 100 is obtained. Furthermore, when the source electrode S1 and the drain electrode D1 have the same laminated structure, the source electrode S1 and the drain electrode D1 may be formed at the same time.

6. Effects of First Embodiment The semiconductor device 100 of the first embodiment has a gate insulating film F10. The SiON film F11 of the gate insulating film F10 suppresses injection of electrons from the second semiconductor layer 130 and the semiconductor region 140 into the gate insulating film F10. Since nitrogen radicals are supplied to the second semiconductor layer 130 and the semiconductor region 140, the nitrogen vacancy density in the second semiconductor layer 130 and the semiconductor region 140 is sufficiently low. In the second semiconductor layer 130 and the semiconductor region 140, oxidation of the semiconductor region 140 is suppressed by the gate insulating film F10.

The surface oxide layer acts as a donor for group III nitride semiconductors. Since oxidation of the semiconductor is suppressed in the semiconductor device 100, the semiconductor device 100 including the gate insulating film F10 has good CV characteristics. In the semiconductor device 100, the drain current rises satisfactorily.

The SiN film F13 of the gate insulating film F10 protects the group III nitride semiconductor from moisture.

Furthermore, since the SiO ₂ film F14 has a sufficient thickness, the gate insulating film of the semiconductor device 100 has high dielectric breakdown strength. Therefore, gate leakage current is suppressed.

7. Modification 7-1. Protective Film The technique of the first embodiment can be applied to protective films other than gate insulating films. Even in this case, the protective film has high insulating properties and can suppress oxidation of the group III nitride semiconductor. Further, the Group III nitride semiconductor can be protected from moisture.

7-2. Substrate Other substrates may be used instead of the GaN substrate 110. Examples include a sapphire substrate and a Si substrate. Of course, other substrates may also be used.

7-3. Insulating oxide film Other insulating oxide films may be used instead of the SiO ₂ film. For example, Al ₂ O ₃ is mentioned.

7-4. Insulating Nitride Film Other insulating nitride films may be used instead of the SiN film. For example, AlN can be mentioned.

7-5. Trench The semiconductor device 100 does not have a trench. The technique of the first embodiment is also applicable to HEMTs having trenches.

7-6. Combination The above variations may be freely combined.

(Second embodiment)
1. Semiconductor Device FIG. 5 is a schematic configuration diagram of a semiconductor device 200 of the second embodiment. The semiconductor device 200 is a vertical MISFET. As shown in FIG. 5, the semiconductor device 200 includes a GaN substrate 210, a first semiconductor layer 220, a second semiconductor layer 230, a third semiconductor layer 240, a gate insulating film F30, a gate electrode G2, and a source. It has an electrode S2, a drain electrode D2, and a body electrode B2.

The first semiconductor layer 220 is formed on the GaN substrate 210. The first semiconductor layer 220 is a group III nitride semiconductor layer of a first conductivity type. The first semiconductor layer 220 is, for example, n ⁻ GaN.

The second semiconductor layer 230 is formed on the first semiconductor layer 220. The second semiconductor layer 230 is a group III nitride semiconductor layer of a second conductivity type. The second semiconductor layer 230 is, for example, pGaN.

The third semiconductor layer 240 is formed on the second semiconductor layer 230. The third semiconductor layer 240 is a group III nitride semiconductor layer of the first conductivity type. The third semiconductor layer 240 is, for example, n ⁺ GaN.

The body electrode B2 is an electrode for extracting holes from the second semiconductor layer 230. Body electrode B2 is formed in recess R2. The recess R2 is a recess that penetrates the third semiconductor layer 240 and reaches halfway through the second semiconductor layer 230. Body electrode B2 is in contact with second semiconductor layer 230, third semiconductor layer 240, and source electrode S2.

Gate insulating film F30 covers trench T2. The gate insulating film F30 insulates the gate electrode G2 and the semiconductor layer. The gate insulating film F30 covers the bottom and side surfaces of the first semiconductor layer 220, the side surfaces of the second semiconductor layer 230, and a portion of the side and surface of the third semiconductor layer 240.

The stacked structure of the gate insulating film F30 is the same as that of the gate insulating film F10 of the first embodiment.

2. Effects of Second Embodiment The semiconductor device 200 of the second embodiment has a gate insulating film F30. The gate insulating film F30 has the same effect as the gate insulating film F10 of the first embodiment.

3. Modification 3-1. Protective Film The semiconductor device 200 may have a protective film. A laminated structure of the gate insulating film F30 may be adopted as the protective film.

(Third embodiment)
FIG. 6 is a schematic configuration diagram of a semiconductor device 300 according to the third embodiment. Semiconductor device 300 is a MIS capacitor. The semiconductor device 300 includes an n-type semiconductor 310, a gate insulating film F40, and a gate electrode G3. The n-type semiconductor 310 is an n-type group III nitride semiconductor. The gate insulating film F40 has the same laminated structure as the gate insulating film F10.

2. Effects of Third Embodiment The semiconductor device 300 of the third embodiment has a gate insulating film F40. The gate insulating film F40 has the same effect as the gate insulating film F10 of the first embodiment.

3. Modification 3-1. Protective Film The semiconductor device 300 may have a protective film. A laminated structure of the gate insulating film F40 may be adopted as the protective film.

(experiment)
1. Secondary ion mass spectrometry (SIMS)
1-1. Fabrication of Sample A structure was fabricated by forming a gate insulating film on n-type GaN. At that time, a SiO ₂ film was formed on the n-type GaN. Then, SIMS and XPS were compared depending on the presence or absence of nitrogen plasma irradiation. The structure irradiated with nitrogen plasma corresponds to the structure in which steps S101 to S103 in FIG. 3 were performed.

ECR plasma was used to generate nitrogen plasma. The microwave output was 500W. The bias power on the substrate side was 0W. The substrate temperature was room temperature. Treatment time was 60 minutes. Note that the heat treatment temperature of the SiO ₂ film was 900° C. except when the heat treatment temperature was changed. Further, a gate insulating film and a gate electrode were formed on n-type GaN, and a MIS capacitor was manufactured.

1-2. Measurement Results FIG. 7 is a graph showing the results of SIMS analysis. The horizontal axis in FIG. 7 is the distance (depth) from the surface of the gate insulating film. The vertical axis in FIG. 7 is the concentration of nitrogen atoms (atms/cm ³ ) or the detected intensity of oxygen atoms.

As shown in FIG. 7, it can be seen that the SiO ₂ film is nitrided from the surface by the nitrogen plasma treatment. Then, SiN, SiON, and SiO ₂ are present in this order from the side irradiated with nitrogen plasma. In a region with a depth of 6 nm or less, the nitrogen concentration increases and the oxygen concentration decreases due to nitrogen plasma irradiation. In other words, it is considered that under these conditions, nitrogen radicals or nitrogen ions reach up to about 6 nm. Furthermore, SiN is formed in a region with a depth of less than 2 nm, and SiON is formed in a region with a depth of 2 nm or more. From the viewpoint of electrical stability, SiON is more preferable than SiN as the insulating film formed on GaN. Note that in a region with a depth of 7 nm or more, the effect of nitrogen plasma and the effect of nitrogen diffusion from n-type GaN overlap and cannot necessarily be clearly distinguished.

The nitrogen concentration decreases from the insulating film side toward the n-type GaN, and then increases again. The nitrogen atom content in the SiO ₂ film is, for example, 1×10 ¹⁹ atm/cm ³ or more and less than 1×10 ²¹ atm/cm ³ . The nitrogen atom content in the SiON film is, for example, 1×10 ²¹ atm/cm ³ or more and less than 1×10 ²² atm/cm ³ . The nitrogen atom content in the SiN film is, for example, 1×10 ²² atm/cm ³ or more.

2. X-ray photoelectron spectroscopy 2-1. Preparation of Sample A structure in which a 3 nm thick SiO ₂ film was formed on n-type GaN was prepared. Thereafter, the bonding state with oxygen atoms was investigated by checking the presence or absence of nitrogen plasma irradiation.

2-2. Measurement Results The amount of chemical shift of Ga alone, Ga--O bond, and Ga--N bond is about 1 eV. For this reason, even if the light emitted from the 3d level of Ga is spectrally analyzed, it is difficult to separate the peaks. For this reason, light emitted from the 1s level of oxygen atoms (O) was spectrally analyzed.

FIG. 8 is a graph showing a 1s spectrum of oxygen atoms near the interface between GaN and SiO ₂ irradiated with nitrogen plasma. The horizontal axis in FIG. 8 is binding energy. The vertical axis in FIG. 8 is the number of counts per second.

In FIG. 8, the proportion of O--Ga bonds was about 3%. In other words, Ga is hardly oxidized.

FIG. 9 is a graph showing a 1s spectrum of oxygen atoms near the interface between GaN and SiO ₂ that were not irradiated with nitrogen plasma. The horizontal axis in FIG. 9 is binding energy. The vertical axis in FIG. 9 is the number of counts per second.

In FIG. 9, the proportion of O--Ga bonds was about 16%.

By irradiating with nitrogen plasma, O--Ga bonds are sufficiently reduced. In other words, as shown in FIG. 8, it can be seen that oxidation of Ga is suppressed near the interface between GaN and SiO ₂ . It is thought that the density of nitrogen vacancies in n-type GaN is low.

3. CV characteristics 3-1. Preparation of Sample A first SiO ₂ film with a thickness of 3 nm was formed on n-type GaN, which was then irradiated with nitrogen plasma, and then a second SiO ₂ film was further formed. The CV characteristics of the structure manufactured in this way were investigated.

3-2. Measurement Results FIG. 10 is a graph showing the CV characteristics of the structure when the temperature of the first heat treatment step is 900°C. The horizontal axis in FIG. 10 is the gate voltage. The vertical axis in FIG. 10 is capacitance. The capacitance is standardized by the capacitance value of the gate insulating film. As shown in FIG. 10, in this case, the capacitance changes smoothly with no step difference as the gate voltage increases.

FIG. 11 is a graph showing the CV characteristics of the structure when the temperature of the first heat treatment step is 700°C. The horizontal axis in FIG. 11 is the gate voltage. The vertical axis in FIG. 11 is capacitance. The capacitance is standardized by the capacitance value of the gate insulating film. As shown in FIG. 11, there is a step HP1 at a location where the gate voltage is about -2V. If the step HP1 exists, the threshold voltage will not be stabilized, and the operation of the semiconductor device will become unstable.

FIG. 12 is a graph showing the CV characteristics of the structure when the temperature of the first heat treatment step is 500°C. The horizontal axis in FIG. 12 is the gate voltage. The vertical axis in FIG. 12 is capacitance. The capacitance is standardized by the capacitance value of the gate insulating film. As shown in FIG. 12, there is a step HP2 at a location where the gate voltage is about -2V. If the step HP2 exists, the threshold voltage will not be stabilized, and the operation of the semiconductor device will become unstable.

In this way, by setting the heat treatment temperature in the first heat treatment step to 800° C. or higher, the threshold voltage of the gate voltage is stabilized.

(Additional note)
The method for manufacturing a semiconductor device according to the first aspect includes the steps of forming a first insulating oxide film on the group III nitride semiconductor layer, and forming a first insulating oxide film on the group III nitride semiconductor layer and the first insulating oxide film. A step of irradiating nitrogen plasma from the side of the insulating oxide film, a first heat treatment step of heat-treating the first insulating oxide film, and a step of forming a second insulating oxide film on the first insulating oxide film. and a second heat treatment step of heat treating the second insulating oxide film.

In the method for manufacturing a semiconductor device according to the second aspect, in the step of forming the first insulating oxide film, the thickness of the first insulating oxide film is set to be 2 nm or more and 9 nm or less.

In the method for manufacturing a semiconductor device according to the third aspect, the heat treatment temperature in the first heat treatment step is higher than the heat treatment temperature in the second heat treatment step.

In the method for manufacturing a semiconductor device according to the fourth aspect, the heat treatment temperature in the first heat treatment step is 800°C or more and 1000°C or less.

In the method for manufacturing a semiconductor device according to the fifth aspect, in the step of irradiating nitrogen plasma, nitrogen radicals are supplied to at least the surface of the group III nitride semiconductor layer.

In the method for manufacturing a semiconductor device according to the sixth aspect, in the step of irradiating nitrogen plasma, the surface of the first insulating oxide film is nitrided.

A semiconductor device in a seventh aspect includes a group III nitride semiconductor layer, a gate insulating film on the group III nitride semiconductor layer, and a gate electrode on the gate insulating film. The gate insulating film includes an SiON film on the group III nitride semiconductor layer, a SiN film on the SiON film, and an SiO ₂ film on the SiN film. The SiON film is in contact with the group III nitride semiconductor layer. The SiN film is in contact with the SiON film. The SiO ₂ film is in contact with the SiN film. The thickness of the SiON film is 1 nm or more and 4 nm or less.

100...Semiconductor device 110...GaN substrate 120...First semiconductor layer 130...Second semiconductor layer 140...Semiconductor region D1...Drain electrode S1...Source electrode G1...Gate electrode F10...Gate insulating film F11...SiON film F13...SiN film F14 ...SiO ₂ film

Claims (7)

forming a first insulating oxide film on the group III nitride semiconductor layer;
irradiating the Group III nitride semiconductor layer and the first insulating oxide film with nitrogen plasma from the first insulating oxide film side;
a first heat treatment step of heat treating the first insulating oxide film;
forming a second insulating oxide film on the first insulating oxide film;
a second heat treatment step of heat treating the second insulating oxide film;
A method for manufacturing a semiconductor device including: The method for manufacturing a semiconductor device according to claim 1,
In the step of forming the first insulating oxide film,
A method for manufacturing a semiconductor device, including setting the thickness of the first insulating oxide film to be 2 nm or more and 9 nm or less. In the method for manufacturing a semiconductor device according to claim 1 or 2,
The heat treatment temperature in the first heat treatment step is:
A method for manufacturing a semiconductor device, the method comprising: heating the heat treatment at a temperature higher than the heat treatment temperature in the second heat treatment step. In the method for manufacturing a semiconductor device according to any one of claims 1 to 3,
The heat treatment temperature in the first heat treatment step is:
A method for manufacturing a semiconductor device, the method comprising: 800°C or more and 1000°C or less. In the method for manufacturing a semiconductor device according to any one of claims 1 to 4,
In the step of irradiating the nitrogen plasma,
A method for manufacturing a semiconductor device, comprising supplying nitrogen radicals to at least the surface of the Group III nitride semiconductor layer. In the method for manufacturing a semiconductor device according to any one of claims 1 to 5,
In the step of irradiating the nitrogen plasma,
A method of manufacturing a semiconductor device, comprising nitriding a surface of the first insulating oxide film. GaN layer;
a gate insulating film on the GaN layer;
a gate electrode on the gate insulating film;
has
The gate insulating film is
a SiON film on the GaN layer;
a SiN film on the SiON film;
an SiO ₂ film on the SiN film;
has
The SiON film is
in contact with the GaN layer,
The SiN film is
is in contact with the SiON film,
The SiO ₂ film is
is in contact with the SiN film,
The thickness of the SiON film is
1 nm or more and 4 nm or less ,
The nitrogen concentration of the SiON film increases continuously from the GaN layer toward the SiN film,
The oxygen concentration of the SiON film continuously decreases from the GaN layer toward the SiN film,
semiconductor devices including

Images