JP7402897B2 - グラフィックスコンテキストバウンシング - Google Patents

グラフィックスコンテキストバウンシング Download PDF

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JP7402897B2
JP7402897B2 JP2021571386A JP2021571386A JP7402897B2 JP 7402897 B2 JP7402897 B2 JP 7402897B2 JP 2021571386 A JP2021571386 A JP 2021571386A JP 2021571386 A JP2021571386 A JP 2021571386A JP 7402897 B2 JP7402897 B2 JP 7402897B2
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JP2022534438A (ja
JP2022534438A5 (enExample
Inventor
エルドン マクラリー レックス
ルオ イー
ジェイ． ワイズ ハリー
フアド アシュカー アレクサンダー
マントル マイケル
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1009—Address translation using page tables, e.g. page table structures
    • G06F12/1018—Address translation using page tables, e.g. page table structures involving hashing techniques, e.g. inverted page tables
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
    • G06F16/20—Information retrieval; Database structures therefor; File system structures therefor of structured data, e.g. relational data
    • G06F16/24—Querying
    • G06F16/245—Query processing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a secondary processor, e.g. coprocessor
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/60—Memory management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Computational Linguistics (AREA)
  • Data Mining & Analysis (AREA)
  • Databases & Information Systems (AREA)
  • Image Generation (AREA)
  • Advance Control (AREA)
  • Devices For Executing Special Programs (AREA)
JP2021571386A 2019-05-30 2020-05-29 グラフィックスコンテキストバウンシング Active JP7402897B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US16/426,613 2019-05-30
US16/426,613 US11169811B2 (en) 2019-05-30 2019-05-30 Graphics context bouncing
PCT/US2020/035203 WO2020243482A1 (en) 2019-05-30 2020-05-29 Graphics context bouncing

Publications (3)

Publication Number Publication Date
JP2022534438A JP2022534438A (ja) 2022-07-29
JP2022534438A5 JP2022534438A5 (enExample) 2023-05-31
JP7402897B2 true JP7402897B2 (ja) 2023-12-21

Family

ID=73550703

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2021571386A Active JP7402897B2 (ja) 2019-05-30 2020-05-29 グラフィックスコンテキストバウンシング

Country Status (6)

Country Link
US (1) US11169811B2 (enExample)
EP (1) EP3977270A4 (enExample)
JP (1) JP7402897B2 (enExample)
KR (1) KR102682383B1 (enExample)
CN (1) CN113939843A (enExample)
WO (1) WO2020243482A1 (enExample)

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Publication number Priority date Publication date Assignee Title
US11694384B2 (en) * 2020-10-30 2023-07-04 Qualcomm Incorporated Fast incremental shared constants
US12137081B2 (en) * 2021-09-09 2024-11-05 Texas Instruments Incorporated Resource access in a microcontroller
US12406321B2 (en) * 2023-02-27 2025-09-02 Qualcomm Incorporated Elimination cache
US20240378790A1 (en) * 2023-05-09 2024-11-14 Advanced Micro Devices, Inc. Pipelined graphics state management
WO2025058851A1 (en) * 2023-09-13 2025-03-20 Qualcomm Incorporated Context merge with global event and dead draw merge
US20250299286A1 (en) * 2024-03-22 2025-09-25 Arm Limited Graphics processing systems

Citations (3)

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US20080313436A1 (en) 2007-06-13 2008-12-18 Advanced Micro Devices, Inc. Handling of extra contexts for shader constants
US8736624B1 (en) 2007-08-15 2014-05-27 Nvidia Corporation Conditional execution flag in graphics applications
US10397362B1 (en) 2015-06-24 2019-08-27 Amazon Technologies, Inc. Combined cache-overflow memory structure

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US20050195186A1 (en) * 2004-03-02 2005-09-08 Ati Technologies Inc. Method and apparatus for object based visibility culling
JP5631535B2 (ja) * 2005-02-08 2014-11-26 オブロング・インダストリーズ・インコーポレーテッド ジェスチャベースの制御システムのためのシステムおよび方法
US7545381B2 (en) * 2005-11-10 2009-06-09 Via Technologies, Inc. Interruptible GPU and method for context saving and restoring
US7634637B1 (en) * 2005-12-16 2009-12-15 Nvidia Corporation Execution of parallel groups of threads with per-instruction serialization
US8370383B2 (en) 2006-02-08 2013-02-05 Oblong Industries, Inc. Multi-process interactive systems and methods
US7979683B1 (en) 2007-04-05 2011-07-12 Nvidia Corporation Multiple simultaneous context architecture
US8139070B1 (en) * 2007-10-03 2012-03-20 Matrox Graphics, Inc. Systems for and methods of context switching in a graphics processing system
US9003389B2 (en) * 2010-05-25 2015-04-07 Red Hat, Inc. Generating an encoded package profile based on executing host processes
US9086813B2 (en) * 2013-03-15 2015-07-21 Qualcomm Incorporated Method and apparatus to save and restore system memory management unit (MMU) contexts
US9563466B2 (en) 2013-11-05 2017-02-07 Intel Corporation Method and apparatus for supporting programmable software context state execution during hardware context restore flow
CN105469354A (zh) 2014-08-25 2016-04-06 超威半导体公司 图形处理方法、系统和设备
US10437637B1 (en) * 2015-05-26 2019-10-08 Thin CI, Inc. Configurable scheduler for graph processing on multi-processor computing systems
US11416282B2 (en) * 2015-05-26 2022-08-16 Blaize, Inc. Configurable scheduler in a graph streaming processing system
GB2543866B (en) * 2016-03-07 2017-11-01 Imagination Tech Ltd Task assembly for SIMD processing
US20180191632A1 (en) * 2016-12-30 2018-07-05 Intel Corporation Flexible packet scheduling
US10572258B2 (en) 2017-04-01 2020-02-25 Intel Corporation Transitionary pre-emption for virtual reality related contexts
US12160369B2 (en) * 2019-02-15 2024-12-03 Intel Corporation Processor related communications
US10841225B2 (en) * 2019-03-06 2020-11-17 Arista Networks, Inc. Load balancing using dynamically resizable consistent hashing

Patent Citations (3)

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Publication number Priority date Publication date Assignee Title
US20080313436A1 (en) 2007-06-13 2008-12-18 Advanced Micro Devices, Inc. Handling of extra contexts for shader constants
US8736624B1 (en) 2007-08-15 2014-05-27 Nvidia Corporation Conditional execution flag in graphics applications
US10397362B1 (en) 2015-06-24 2019-08-27 Amazon Technologies, Inc. Combined cache-overflow memory structure

Also Published As

Publication number Publication date
JP2022534438A (ja) 2022-07-29
CN113939843A (zh) 2022-01-14
WO2020243482A1 (en) 2020-12-03
EP3977270A1 (en) 2022-04-06
US11169811B2 (en) 2021-11-09
KR20220003141A (ko) 2022-01-07
US20200379767A1 (en) 2020-12-03
EP3977270A4 (en) 2023-06-28
KR102682383B1 (ko) 2024-07-08

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