JP7397034B2 - gaming machine - Google Patents

Description

The present invention relates to gaming machines, and relates to technology that contributes to improving the performance of gaming machines.

In pinball game machines and rotary game machines, various effects are made using liquid crystal display screens, speakers, LEDs, accessories, vibrating bodies, blowers, etc. to enliven the game.
The following patent documents disclose techniques for controlling various performance operations.

Japanese Patent Application Publication No. 2014-64693

In such gaming machines, it is desirable to achieve more interesting performances without increasing the number of boards or complicating or making wiring as difficult as possible.
Therefore, it is an object of the present invention to propose a configuration that can obtain effective production effects without complicating these configurations.

The gaming machine of the present invention includes a first effect driving means using chip parts, a second effect driving means using chip parts, and a first system clock and effect driving control data inputted to the first effect driving means. At the same time, a first board is provided with a connector for inputting a second system clock and performance drive control data to the second performance drive means, and in the first board, the first performance drive The means, the second effect driving means, and the connector are arranged on the same surface, and when looking from the pattern wiring side to the chip side of each input terminal of the clock and effect driving control data in the first effect driving means. and the left-right relationship of each connector terminal of the first system clock and production drive control data in the connector, when looking in the direction in which the pattern wiring connected to each connector terminal is led from the connector terminal side. The left-right relationship is the same, and the left-right relationship of each input terminal of the clock and the effect drive control data in the second effect driving means when looking from the pattern wiring side to the chip side, and the The left-right relationships of the two systems of clocks and the connector terminals of the performance drive control data are the same when looking from the connector terminal side to the direction in which the pattern wiring connected to each connector terminal is led out.
In addition, in the connector, the left and right sides of each connector terminal for the first system clock and production drive control data are viewed from the connector terminal side to the direction in which the pattern wiring connected to each connector terminal is led out. and the left-right relationship of each connector terminal of the clock of the second system and the production drive control data when looking from the connector terminal side to the direction in which pattern wiring connected to each connector terminal is led out, may be the same.
In addition, in the connector, the left and right sides of each connector terminal for the first system clock and production drive control data are viewed from the connector terminal side to the direction in which the pattern wiring connected to each connector terminal is led out. and the left-right relationship of each connector terminal of the clock of the second system and the production drive control data when looking from the connector terminal side to the direction in which pattern wiring connected to each connector terminal is led out, may be the opposite.

According to the gaming machine of the present invention, highly entertaining performances can be realized with an efficient configuration.

1 is a front perspective view showing the appearance of a gaming machine according to an embodiment of the present invention. It is a diagram showing the configuration of a game board of a game machine according to an embodiment. It is a block diagram showing a control configuration of a gaming machine according to an embodiment. FIG. 3 is an explanatory diagram of an example of a look-ahead preview effect according to the embodiment. FIG. 2 is a perspective view of the gaming machine according to the embodiment with the door opened. FIG. 2 is a perspective view of the gaming machine according to the embodiment with the inner frame opened. FIG. 2 is an explanatory diagram of the board arrangement on the back side of the game board according to the embodiment. FIG. 2 is an explanatory diagram of the board arrangement of the door and inner frame of the gaming machine according to the embodiment. FIG. 2 is an explanatory diagram of the board arrangement of the inner frame of the gaming machine according to the embodiment. FIG. 3 is an explanatory diagram of the arrangement of various devices. FIG. 2 is a block diagram of a connection configuration of a board. FIG. 3 is an explanatory diagram of power supply system input/output for the power supply board 300. FIG. 4 is a circuit diagram of an inner frame LED relay board 400. FIG. 4 is a circuit diagram of an inner frame LED relay board 400. FIG. 5 is a circuit diagram of a front frame LED connection board 500. FIG. 5 is a circuit diagram of a front frame LED connection board 500. FIG. 5 is a circuit diagram of a front frame LED connection board 500. FIG. 5 is a circuit diagram of a front frame LED connection board 500. FIG. 5 is a circuit diagram of a front frame LED connection board 500. FIG. 5 is a circuit diagram of a front frame LED connection board 500. FIG. 5 is a block diagram showing a signal flow of a front frame LED connection board 500. FIG. 5 is a block diagram showing a signal flow of a front frame LED connection board 500. FIG. 5 is a circuit diagram of a relay board 550. FIG. It is a circuit diagram of the side unit upper right LED board 600. It is a circuit diagram of the side unit upper right LED board 600. It is a circuit diagram of the side unit upper right LED board 600. It is a circuit diagram of the side unit upper right LED board 600. It is a circuit diagram of the side unit upper right LED board 600. It is a circuit diagram of the side unit upper right LED board 600. It is a circuit diagram of the side unit lower right LED board 620. It is a circuit diagram of the side unit lower right LED board 620. 6 is a circuit diagram of a side unit upper LED board 630. FIG. 6 is a circuit diagram of a button LED connection board 640. FIG. 6 is a circuit diagram of a button LED board 660. FIG. 6 is a circuit diagram of a button LED board 660. FIG. 7 is a circuit diagram of an LED connection board 700. FIG. 7 is a circuit diagram of an LED connection board 700. FIG. 7 is a circuit diagram of an LED connection board 700. FIG. 7 is a circuit diagram of an LED connection board 700. FIG. 7 is a circuit diagram of an LED connection board 700. FIG. 7 is a circuit diagram of an LED connection board 700. FIG. It is a circuit diagram of the left relay board 720 on the back of the panel. 7 is a circuit diagram of a decorative board 740. FIG. 7 is a circuit diagram of a relay board 760. FIG. 7 is a circuit diagram of an LED board 780. FIG. 7 is a circuit diagram of an LED board 790. FIG. FIG. 8 is a circuit diagram of a board back lower relay board 800. 8 is a circuit diagram of a decorative board 820. FIG. FIG. 7 is a block diagram of another connection configuration of the board. 15 is a circuit diagram of an LED connection board 1500. FIG. 15 is a circuit diagram of an LED connection board 1500. FIG. 15 is a circuit diagram of an LED connection board 1500. FIG. 15 is a circuit diagram of an LED connection board 1500. FIG. 15 is a circuit diagram of an LED connection board 1500. FIG. 15 is a circuit diagram of an LED connection board 1500. FIG. 15 is a circuit diagram of an LED connection board 1500. FIG. 15 is a circuit diagram of an LED connection board 1500. FIG. 16 is a circuit diagram of an LED board 1600. FIG. FIG. 2 is an explanatory diagram of configuration A1-1. 7 is an explanatory diagram of a pattern of a surface layer of an LED board 780. FIG. FIG. 7 is an explanatory diagram of a pattern of a back layer of an LED board 780. FIG. 3 is an explanatory diagram of terminals of an LED driver. 7 is an explanatory diagram of a pattern of a surface layer of an LED board 790. FIG. FIG. 7 is an explanatory diagram of a pattern of a back layer of an LED board 790. FIG. 2 is an explanatory diagram of configuration A1-2. FIG. 6 is an explanatory diagram of a pattern of a surface layer of an LED board 630 on a side unit. FIG. 6 is an explanatory diagram of a pattern of the back layer of the side unit upper LED board 630. FIG. 3 is an explanatory diagram of configuration A2-1. It is an explanatory diagram of configuration A2-2. It is an explanatory diagram of configuration A3-1. FIG. 7 is an explanatory diagram of an example arrangement of surface layers of an LED connection board 1500. FIG. 7 is an explanatory diagram of an example arrangement of the back layer of the LED connection board 1500. FIG. 6 is an explanatory diagram of an example of the arrangement of surface layers of the upper right LED board 600 of the side unit. FIG. 6 is an explanatory diagram of an example arrangement of the back layer of the upper right LED board 600 of the side unit. FIG. 7 is an explanatory diagram of another arrangement example of the surface layer of the LED connection board 1500. It is an explanatory diagram of configuration A3-2. FIG. 3 is an explanatory diagram of configuration A4-1. FIG. 3 is an explanatory diagram of a pattern of a surface layer of an LED board 1600. FIG. 7 is an explanatory diagram of a pattern of a back layer of an LED board 1600. 16 is an explanatory diagram of terminals of an LED driver 1601. FIG. It is an explanatory diagram of configuration A5. It is a circuit diagram of LED connection board 1500A. It is an explanatory diagram of configuration A6. It is a circuit diagram of LED board 790A. It is an explanatory diagram of configuration A7-1. It is an explanatory diagram of configuration A7-2. FIG. 3 is an explanatory diagram of configuration A7-3. It is an explanatory diagram of configurations A8-1 and A8-2. It is an explanatory diagram of configurations A8-1 and A8-2. It is an explanatory diagram of configuration A9-1. It is an explanatory diagram of configuration A9-2. It is an explanatory diagram of configuration A9-3. It is an explanatory diagram of slave address setting. FIG. 3 is an explanatory diagram of wiring for slave address setting.

Hereinafter, embodiments of the present invention will be described in the following order with reference to the accompanying drawings.
<1. Structure of gaming machine>
<2. Control configuration of gaming machine>
[2.1 Main control board]
[2.2 Production control board]
<3. Overview of operation>
[3.1 Game status]
[3.2 Symbol variation display game]
[3.3 About winning]
[3.4 About the performance]
<4. Opening/closing structure and board arrangement>
<5. Board connection configuration>
[5.1 Connection status of each board]
[5.2 Inner frame LED relay board 400]
[5.3 Front frame LED connection board 500]
[5.4 Relay board 550]
[5.5 Side unit upper right LED board 600]
[5.6 Side unit lower right LED board 620]
[5.7 Side unit upper LED board 630]
[5.8 Button LED connection board 640]
[5.9 Button LED board 660]
[5.10 LED connection board 700]
[5.11 Back panel left relay board 720]
[5.12 Decorative board 740]
[5.13 Relay board 760]
[5.14 LED board 780]
[5.15 LED board 790]
[5.16 Bottom relay board 800]
[5.17 Decorative board 820]
<6. Other examples of board connection configurations>
[6.1 Connection status of each board]
[6.2 LED connection board 1500]
[6.3 LED board 1600]
<7. Explanation of notable configurations＞
[7.1 Relationship between the connector terminal and the terminal of the production driving means]
[7.2 Slave address]
[7.3 Others]

<1. Structure of gaming machine>

The structure of a pachinko gaming machine 1 as an embodiment of the present invention will be described with reference to FIGS. 1 and 2. FIG. 1 is a perspective view of the front side showing the external appearance of the pachinko game machine 1, and FIG. 2 is a view showing the front side of the game board 3 included in the pachinko game machine 1.
Note that the pachinko gaming machine 1 includes a frame member, a door member provided to be openable and closable with respect to the frame member, and a replacement member attached to the frame member so as to be replaceable.
The pachinko game machine 1 described below has an inner frame 2 as a structure corresponding to a frame member, a door 6 as a structure corresponding to a door member, and a game board 3 as a structure corresponding to a replacement member.

A pachinko gaming machine 1 (hereinafter sometimes abbreviated as "gaming machine 1") shown in FIG. A game board 3 (see FIG. 2) is installed in an attached game board storage frame (not shown), and a game area 3a formed on the surface of the game board 3 is exposed to the opening of the inner frame 2. have Since the game board 3 can be replaced and removed from the inner frame 2, it can be called a replacement member.
A door 6 supporting transparent glass is provided on the front side of the game area 3a. Further, on the back side of the game board 3, various control boards (see FIG. 3) for controlling game operations are arranged.

On the front side (player side) of the door 6, a side unit 10 is formed as a decorative unit that surrounds all or part of the circumference of the game board 3, for example.
The side unit 10 itself has a decorative shape that matches the theme of the gaming machine 1, and may also be provided with presentation elements such as LEDs and accessories inside, thereby creating a presentation effect that conveys the atmosphere of the game to the player. demonstrate. This side unit 10 is a unit that is replaceably attached to the door 6.

A key cylinder (not shown) for unlocking the door is provided on the front side of the door 6, and by inserting a key into this key cylinder and operating it to one side, the locked state of the door 6 with respect to the inner frame 2 is released. When the door 6 is operated to the other side, the locked state of the inner frame 2 relative to the outer frame 4 is released, and the inner frame 2 can be opened to the front.

A front operation panel 7 is disposed below the door 6 and is pivotally supported to the inner frame 2 by a hinge (not shown) so as to be openable and closable.
The front operation panel 7 is provided with an upper tray unit 8, and the upper tray unit 8 is formed with an upper tray 9 for storing ejected game balls.

The upper tray unit 8 also includes a ball removal button 14 for pulling out the game balls stored in the upper tray 9 below the gaming machine 1, and a ball removal button 14 for discharging game balls to a game ball lending device (not shown). A ball lending button 11 for making a request and a card return button 12 for requesting the return of the valuable medium inserted into the game ball lending device are provided.
Further, the upper tray unit 8 is provided with a performance button 13 (operating means) configured to be operable by the player. This production button 13 becomes operable (input accepted) when the built-in lamp (button LED 75) is lit during a predetermined input reception period, and a predetermined operation (pressing, repeated pressing, long pressing, etc.) is performed while the built-in lamp is lit. By doing this, it is possible to bring about changes in the performance.
The upper tray unit 8 also has a cross key 15a for users such as players and hall staff to select various items and give directions, and a decision button 15b for instructing to decide on a selected item. An operator is provided.

Further, on the right end side of the front operation panel 7, a firing operation handle 15 is provided for operating the firing device 32 (see FIG. 3).

Further, on both sides of the upper part of the door 6 and on the upper side of the firing operation handle 15, speakers 46 are provided to produce a sound production effect (sound effect) by sound. In FIG. 1, only two speakers 46 above the door 6 are shown.
The plurality of speakers 46 enable so-called stereo sound reproduction or multi-channel sound reproduction of sounds related to the performance.

In addition, a plurality of decorative lamps 45 (for example, full-color LED light effects, etc., see FIG. 3) are provided at appropriate locations on the door 6 to provide a light effect through light decoration. A plurality of full-color LEDs (LEDs for light production) serving as the decorative lamps 45 are provided around the pachinko game machine 1, for example, around the periphery of the door 6 or inside the side unit 10.

The configuration of the game board 3 will be explained with reference to FIG. 2.
On the illustrated game board 3, a ball guide rail 5 that guides the launched game balls is attached in an annular manner as a board partitioning member, and a generally circular area surrounded by the ball guide rail 5 is a game area 3a, The four corners are non-gaming areas.

Approximately in the center of the gaming area 3a, for example, three (left, middle, right) display areas (symbol variation display areas) independently display a plurality of types of decorative patterns (for example, numbers, characters, symbols, etc.). A liquid crystal display (LCD) 36 is equipped with a liquid crystal display device (LCD) 36 that is capable of variable display operation (fluctuating display and stop display) of left symbols (compatible with the left display area), middle symbols (compatible with the middle display area), and right symbols (compatible with the right display area). It is provided.
This liquid crystal display device 36 displays various effects in the form of images in addition to the variable display operation of decorative patterns under the control of the effect control board 30 which will be described later.

In addition, a center decoration 48 is provided in the game area 3a in a form that extends far around the display surface of the liquid crystal display device 36. The center decoration 48 is provided along the front side of the game board 3, and protects the display surface of the liquid crystal display device 36 from surrounding game balls. It acts as a channel distribution means that allows channels to be divided into left and right.
In this embodiment, the center decoration 48 is arranged approximately at the center of the game area 3a so that the presence of the center decoration 48 forms a flow path for the game ball on both upper sides (left and right sides) of the game area 3a. ing. The game ball shot into the upper side of the game area 3a by the firing device 32 is distributed to the left and right on the upper side of the armor frame 48b, and is divided into the left downstream path 3b on the left side of the center decoration 48 and the right downstream path 3c on the right side. flow down either.

In addition, the non-gaming area at the bottom of the game board 3 serves as a various function display section, and includes a special symbol display device 38a (first special symbol display means) using a dot display and a special symbol display device 38b (second special symbol display device). display means) is provided.
Note that various function display sections including the special symbol display devices 38a and 38b are shown enlarged in FIG.

In the special symbol display devices 38a and 38b, a special symbol variable display game is executed by a variable display operation of a "special symbol" expressed by a dot display. Then, the liquid crystal display device 36 displays a decorative pattern in the form of an image in a variable manner in synchronization with the variable display of special symbols by the special symbol display devices 38a and 38b, and displays the decorative pattern along with various preview effects (effect images). Symbol variation display games are to be executed (details regarding these symbol variation display games will be explained later).

Further, in the various function display sections, a composite display device (LED display for pending composite display) 38c, which is made of a dot display like the special symbol display devices 38a and 38b, is arranged. What is called "compound" is the five functions: special symbols 1 and 2, display of the number of pending balls for normal symbol operation, and status notification when the variable time reduction function is activated (time saving mode) and high probability state (high accuracy mode). This is because it is a holding/time-saving/high-accuracy composite display device (hereinafter simply referred to as a "compound display device") having a display function.

Further, the various function display sections are provided with a composite display device 38d, which also consists of a dot display.
In this composite display device 38d, the number of rounds is displayed to notify the specified number of rounds (maximum number of rounds) related to the jackpot by a combination of the lighting/extinguishing states of the four LEDs. For example, the specified number of rounds (maximum number of rounds) related to the jackpot is notified based on a combination of the lighting/extinguishing states of four LEDs.
Further, in the composite display device 38d, a normal symbol variable display game is executed by a variable display operation of a normal symbol expressed by one LED as a normal symbol display.
Further, the composite display device 38d is configured to perform right-handed display using three LEDs.

Below the center decoration 48 in FIG. 2, a starting port 34 (first special symbol starting port: first starting means) is provided inside. A detection sensor 34a (starting port sensor 34a, see FIG. 3) is formed inside the starting port 34 to detect passage of a game ball.
Further, the right downstream path 3c is provided with a starting port 35 (second special symbol starting port: second starting means) that opens and closes, and inside is provided with a detection sensor 35a (starting device) that detects passage of a game ball. A mouth sensor 35a (see FIG. 3) is formed.

The starting opening 34, which is the first special symbol starting opening, is the first special symbol in the special symbol display device 38a (hereinafter, the first special symbol will be referred to as "special symbol 1", and may also be referred to as "special symbol 1" in some cases). This is a winning opening related to the starting conditions for the variable display operation of (hereinafter referred to as abbreviated), and is configured as a winning rate fixed winning device that does not have a starting opening opening/closing means (means that allows the starting opening to be opened or enlarged). In this embodiment, due to the action of the game ball falling direction changing member (for example, the game nail, the windmill 44, the center decoration 48, etc.) in the game area 3a, the game balls that have flown down the left flow path 3b are transferred to the starting port 34. The structure is such that it is easy to enter the ball (win a prize), whereas the structure is such that it is difficult or impossible for the game ball that has flowed down the right flow path 3c to enter the ball.

The starting port 35 is for starting the variable display operation of the second special symbol (hereinafter, the second special symbol will be referred to as "special symbol 2", and may be abbreviated as "special symbol 2" in some cases) on the special symbol display device 38b. This is a winning opening according to the conditions, and the winning area of this starting opening 35 is configured to be openable and closable into an open state where winning is possible and a closed state where winning is not possible.

The starting opening 35 is a winning opening related to the starting condition for the variable display operation of the special symbol 2 in the special symbol display device 38b, and is configured as a variable starting opening that is controlled to open and close by the normal electric accessory 41.
The normal electric accessory 41 is controlled to be in an open state that allows the game ball to enter the starting port 35, and a closed state that makes it difficult or impossible to enter the game ball into the starting port 35.

Further, two general winning holes 43 are provided at the lower left and right sides of the gaming area 3a, and a general winning hole sensor 43a for detecting passage of a game ball is formed inside each of them.
Furthermore, within the area of the game board, a movable accessory (not shown) that provides a visual presentation effect is arranged at a position that does not obstruct the flow of the game ball.

Further, diagonally above the normal electric accessory 41, that is, above the middle part of the right downstream path 3c, there is a normal symbol starting port 37 (third starting means) consisting of a passing gate (specific passing area) through which a game ball can pass. ) is provided. This normal symbol starting hole 37 is a winning hole related to the variable display operation of the normal symbols of the composite display device 38d, and inside thereof, a normal symbol starting hole sensor 37a (see FIG. 3) that detects a passing game ball is installed. It is formed. In addition, in this embodiment, the normal symbol starting port 37 is formed only on the right downstream path 3c side, and is not formed on the left downstream path 3b side. However, the present invention is not limited to this, and may be formed only in the left downstream path 3b, or may be formed in both downstream paths, respectively.

A special variable winning device 52 (special electric accessory) configured to be able to open or enlarge the big winning opening 50 with an opening door 52b is provided in the middle of the path from the normal symbol starting opening 37 in the right downstream path 3c. A big winning hole sensor 52a (see FIG. 3) for detecting a game ball that enters the big winning hole 50 is formed inside the big winning hole sensor 52a (see FIG. 3).
Around the grand prize opening 50, a guide section 55 and a windmill 53 are provided that serve to draw the game balls flowing down toward the grand prize opening 50.

The process of entering the game ball into the grand prize opening 50 is as follows.
The game ball that has passed through the floating area between the upper surface of the center decoration 48 and the ball guide rail 5 and has passed through the right downstream path 3c is guided by the guide portion 55 in the direction of the big prize opening 50. If the grand prize opening 50 is in an open state (great winning opening state), the game ball is guided into the grand prize opening 50.

Note that in the gaming machine 1 of this embodiment, when the player aims the firing position toward the special variable prize winning device 52 side (when the player aims so that the game ball passes through the right downstream path 3c), the starting port 34 The game ball is configured to be difficult to or not guided to the side. Therefore, if the winning opening is in the "big winning opening closed state", it is difficult or impossible to enter the starting opening 34 to win a prize.
Further, the starting port 35 is configured to operate in an opening/closing pattern that is more advantageous than in the normal state when the game state is in a gaming state accompanied by a state with electric support, which will be described later.

In the case of this embodiment, the way the player plays to create an advantageous situation changes depending on the gaming state. Specifically, in a gaming state that involves the "state without electric support" described below, it is considered advantageous to "hit to the left" in which the game ball is aimed so that it passes through the left downstream path 3b; If the game state is accompanied by a "presence state", it is considered advantageous to "hit right" in which the game ball is aimed so that it passes through the right downstream path 3c.

In the gaming machine 1 of the present embodiment, when there is a winning in a winning opening other than the normal symbol start opening 37 among the various winning openings provided in the gaming area 3a, a promise is made for each winning opening. The number of prize balls per winning ball (for example, 3 balls for the starting hole 34 or 35, 13 balls for the big winning hole 50, and 10 balls for the general winning hole 43) is determined by the game ball payout device 19 (see FIG. 3). It is now paid out from The game balls that do not enter into each of the above-mentioned winning holes are discharged from the gaming area 3a through the out hole 49.

Here, "winning" refers to a winning opening that takes a game ball into its interior, or a winning opening that is not a structure that takes a gaming ball inside but is a pass-through type gate (for example, the normal symbol starting opening 37). If it is, it means that a game ball passes through that gate, and in reality, if a game ball is detected by each winning detection switch formed for each winning hole, a "winning" will occur in that winning hole. be treated as such. The game balls related to this winning are also referred to as "winning balls." In addition, if a game ball enters the winning hole, that game ball will be detected by the winning detection switch, so unless otherwise specified in this specification, it does not matter whether the gaming ball is detected by the winning detection switch or not. Regardless, the term "winning" may include the case where a game ball enters the winning opening.

<2. Control configuration of gaming machine>

A configuration (control configuration) for realizing gaming operation control of the gaming machine 1 will be explained with reference to the block diagram in FIG. 3.
The gaming machine 1 of this embodiment includes a main control board (main control means) 20 that centrally controls control related to overall gaming operations (gaming operation control), and a production means that receives production control commands from the main control board 20. A performance control board 30 (performance control means) that centrally controls the execution of the performance (appearance control), a payout control board (payout control means) 29 that controls the payout of prize balls, and an external power source (not shown). ) and a power supply board (power supply control means (not shown)) that generates and supplies the necessary power to the gaming machine 1.
Note that in FIG. 3, power supply routes to each part are omitted.

[2.1 Main control board]
The main control board 20 is equipped with a microprocessor with a built-in CPU (Central Processing Unit) 20a (main control CPU), and also stores various data necessary for controlling the gaming operations, in addition to control programs that describe gaming operation control procedures. It is equipped with a ROM (Read Only Memory) 20b (main control ROM) for storage, and a RAM (Random Access Memory) 20c (main control RAM) that functions as a work area and buffer memory, making up a microcomputer as a whole. .

Although not shown, the main control board 20 includes a CTC (Counter Timer Circuit) for realizing periodic interrupts, a constant period pulse output generation function (bit rate generator), and a time measurement function, and a main control board 20. An interrupt controller circuit that provides an interrupt enable/disable function such as a timer interrupt that provides an interrupt signal to the CPU 20a, and a main control circuit that outputs a system reset signal upon detecting power-on, power-off, power abnormality, etc. A reset circuit that can reset the CPU 20a, a watchdog timer (WDT) circuit that monitors abnormal operation of the control program, and a prohibition of running outside the designated area that monitors whether the program is being executed correctly within a preset address range. (IAT) circuit, and a counter circuit for generating random numbers within a certain range using hardware.

The counter circuit includes a random number generation circuit that generates random numbers and a sampling circuit that samples random numbers from the random number generation circuit at predetermined timing, and works as a 16-bit counter as a whole. The main control CPU 20a sends an instruction to the sampling circuit according to the processing state, and uses the numerical value indicated by the random number generation circuit as an internal lottery random number (random number for jackpot determination (random number size: 65536)). The random numbers are obtained and used for the jackpot lottery. Note that the internal lottery random number is obtained by adding a soft random number generated by appropriate software processing and a hard random number in order to prevent cheating such as trying to win.

The main control board 20 includes a starting hole sensor 34a that detects winning (ball entering) into the starting hole 34, a starting hole sensor 35a that detects winning into the starting hole 35, and a starting hole sensor 35a that detects passage of the normal symbol starting hole 37. The normal symbol starting hole sensor 37a that detects the winning hole, the big winning hole sensor 52a that detects the winning into the big winning hole 50, the general winning hole sensor 43a that detects the winning into the general winning hole 43, and the out hole 49. An OUT monitoring switch 49a for detecting game balls (out balls) is connected, and the main control board 20 is capable of receiving detection signals output from these. The main control board 20 is capable of grasping into which winning hole the game ball has entered based on the detection signals from each sensor.

In addition, the main control board 20 includes a normal electric accessory solenoid 41c for controlling the opening and closing of the movable wing pieces of the starting port 35, and a large winning opening solenoid 52c for controlling opening and closing of the opening door 52b of the large winning opening 50. are connected, and the main control board 20 is capable of transmitting control signals for controlling these.

Further, a special symbol display device 38a and a special symbol display device 38b are connected to the main control board 20, and the main control board 20 is capable of transmitting control signals for displaying and controlling the special symbols 1 and 2. . Furthermore, a composite display device 38c is connected to the main control board 20, and is capable of transmitting control signals for controlling the display of the number of reservations and the display of the status.

Further, a composite display device 38d is connected to the main control board 20, and the main control board 20 sends control signals for display-controlling the normal symbol display, right-handed display, and round display displayed on the composite display device 38d. Sending is possible.

Further, an external centralized terminal board 21 for the frame is connected to the main control board 20, and the main control board 20 connects to a predetermined hall computer HC provided outside the gaming machine via the external centralized terminal board 21 for the frame. It is possible to transmit game information (for example, jackpot information, prize ball number information, symbol variation execution information, etc.).
The hall computer HC is an information processing device (computer device) for monitoring gaming information from the main control board 20 and comprehensively managing the operating status of the gaming machines in the pachinko hall.

Furthermore, a payout control board (payout control unit) 29 is connected to the main control board 20, and when it is necessary to pay out prize balls, a control command regarding payout (number of prize balls) is sent to the payout control board 29. It is possible to send a payout control command that specifies a payout control command.

A launch control board (launch control unit) 28 that controls the launch device 32 and a game ball payout device (game ball payout means) 19 that pays out game balls are connected to the payout control board 29. The main roles of this payout control board 29 include receiving payout control commands from the main control board 20, controlling prize ball payout of the game ball payout device 19 based on the payout control commands, and transmitting status signals to the main control board 20. It is.

The game ball payout device 19 is provided with an out-of-supply detection sensor 19a that detects a lack of supply of game balls, and a ball count sensor 19b that detects the game balls (prize balls) to be paid out. It is possible to receive each detection signal. Further, the game ball payout device 19 is provided with a payout motor 19c that drives a ball payout mechanism (not shown) for paying out game balls, and a payout control board 29 is configured to control the payout motor 19c. control signals can be transmitted.

Further, the payout control board 29 includes a full detection sensor 60 that detects when the upper tray 9 is full of game balls (in this embodiment, a detection sensor that detects the stored state of game balls stored in the upper tray 9). , a front door open sensor 61 (for example, a detection sensor that detects the open state of the door 6 or the inner frame 2) is connected.

The payout control board 29 can send various status signals to the main control board 20 based on detection signals from the full detection sensor 60, the front door open sensor 61, the out-of-supply detection sensor 19a, and the ball counting sensor 19b. It becomes. This status signal includes a ball jam signal indicating a full state, a door open signal indicating that at least the inner frame 2 is open, an out-of-supply signal indicating an insufficient supply of game balls from the game ball payout device 19, and a prize ball signal. It is configured to be able to transmit various status signals, including a counting error signal indicating insufficient dispensing of balls or an abnormality occurring in the ball counting sensor 19b, and a dispensing completion signal indicating that dispensing operation has been completed. Based on these status signals, the main control board 20 determines the open state of the inner frame 2 (door open error), whether or not the payout operation of the game ball payout device 19 is normal (out of supply error), and whether the upper tray 9 is open or not. Monitor the full state (ball clogging error), etc.

Furthermore, a firing control board 28 is connected to the payout control board 29, and is capable of transmitting a permission signal for permitting firing to the firing control board 28. The firing control board 28 controls the energization of a firing solenoid (not shown) provided in the firing device 32 based on the output of the permission signal from the dispensing control board 29, and controls the operation of the firing operation handle 15. This realizes the firing action of the game ball. Specifically, it is detected that a firing permission signal is output from the payout control board 29 (firing permission signal ON state), and that the touch sensor provided on the firing operation handle 15 detects that the player is touching the handle. The firing operation of the game ball is permitted on the condition that the firing stop switch (not shown) provided on the firing operation handle 15 is not operated. Therefore, when the firing permission signal is not output (firing permission signal OFF state), no firing operation is performed even if the firing operation handle 15 is operated, and the game ball is not fired. Furthermore, the strength with which the game ball is launched can be changed according to the amount of operation of the firing operation handle 15.
Note that when the payout control board 29 detects the ball jamming error, it transmits a ball jamming signal to the main control board 20 and stops outputting the firing permission signal to the firing control board 28 (firing permission signal OFF), and the upper tray 9 Control is performed to stop the launching operation until the full state is resolved.
Further, the payout control board 29 outputs a firing permission signal to the firing control board 28 on the condition that firing permission is instructed by the main control board 20.

A RAM clear switch 98 is connected to the main control board 20, and detection signals from these switches can be received.

The RAM clear switch 98 is, for example, a push button type switch for inputting an instruction to initialize a predetermined area of the main control RAM 20c.

The RAM clear switch 98 is turned on/off in response to the operation of a RAM clear button that is operable with the inner frame 2 open.
The RAM clear switch 98 is provided at a suitable location inside the gaming machine 1. For example, it is placed on the main control board 20.

Further, a performance indicator 97 is connected to the main control board 20.
The performance display 97 is configured to have, for example, a 7-segment display, and functions as a display means capable of displaying performance information (described later). The performance display 97 is mounted, for example, on the main control board 20 at an easily visible position.

(About performance display)
The main control board 20 is capable of transmitting a control signal for displaying predetermined performance information on the performance display 97.
Performance information is information that pachinko halls and related agencies want to confirm, and typical examples include information regarding the presence or absence of fraudulent prize balls such as excessive prize balls for gaming machine 1, and the original ball output performance of gaming machine 1. It is. Therefore, the performance information itself is information that is not directly related to the progress of the game itself when the player plays the game, unlike preview effects and the like.

Therefore, the performance indicator 97 is installed inside the gaming machine 1, for example, on the main control board 20, the payout control board 29, the firing control board 28, the relay board, the production control board 30, or the board case (a protective cover that protects the board). ), etc., are provided at positions where the displayed information can be viewed when the inner frame 2 is in the open state.

Here, the following information can be specifically adopted as the performance information.

(1) The total number of balls paid out due to winnings during a specific state (total number of prize balls during a specific state: Information (specific ratio information) based on the value (α/β) divided by the number of pieces (β pieces) can be employed as the performance information.
The above-mentioned "total number of paid out balls" is the total value of game balls (prize balls) that are paid out when winning in the winning holes (starting hole 34, starting hole 35, general winning hole 43, big winning hole 50). . In the case of this embodiment, there are three starting holes 34 or 35, 13 big winning holes 50, and 10 general winning holes 43.
Further, which state to adopt as the specific state can be determined as appropriate depending on the state under which performance information is desired to be grasped. In the case of this embodiment, any state among the normal state, potential state, time saving state, variable probability state, and jackpot game can be adopted. Furthermore, multiple types of states may be measured. For example, the normal state, variable probability state, all gaming states except during winning games, etc., and the types to be measured can be determined as appropriate.
Further, as the period in the specific state, a period in which the jackpot lottery probability is either low probability state or high probability state may be adopted.
Alternatively, the total number of payouts may be determined by excluding one or more specific winning holes from the measurement target (total number of payouts excluding specific winning holes). For example, the total number of payouts may be determined by excluding the big winning hole 50 from the measurement target among the winning holes.

(2) Alternatively, only one of the total number of paid out balls, the total number of paid out balls excluding specific winning holes, and the total number of out pitches may be measured, and the measurement result may be used as performance information.

In this embodiment, the total number of pitches put out during the normal state (number of pitches put out at normal time) and the total number of out pitches during the normal state (number of pitches out at normal time) are measured in real time, and the number of pitches put out at normal time is calculated as the number of pitches out at normal time. The value obtained by multiplying the value divided by 100 by 100 (the value calculated as the number of pieces paid out during normal times÷ the number of pieces out during normal times×100) is displayed as performance information (hereinafter referred to as "normal time ratio information"). Note that the displayed value at this time is a value rounded off to the first decimal place.
Therefore, the respective data of the number of balls paid out during normal times, the number of out balls during normal times, and the ratio information during normal times are stored in the corresponding areas of the main control RAM 20c (total prize balls storage area during specified periods, storage area for the number of out balls during specified periods, and specified ratio information storage area). They are stored (memorized) in each. However, rather than simply permanently measuring and displaying performance information, the measurement is temporarily terminated when the total number of out pitches reaches a predetermined prescribed number (for example, 60,000). This prescribed number is not the total number of out pitches in the normal state, but the total number of out pitches during all game states (including during winning games) (hereinafter referred to as "all state out number"). This total state out number is also measured in real time and stored in the corresponding area (all state out number storage area) of the main control RAM 20c. Hereinafter, for convenience of explanation, the storage area for the total number of awarded pitches during the specific period, the storage area for the number of outs during the specific period, the specific ratio information storage area, and the storage area for the number of outs in all states will be abbreviated as the "measurement information storage area."

Then, the normal time ratio information at the end point is stored in a predetermined area (performance display storage area) of the main control RAM 20c (the current normal time ratio information is stored), and then the measurement information storage area (normal time payout number, normal time After clearing the number of out pitches and the number of out pitches in all states, start counting again (start measuring the number of pitches paid out in normal times, the number of out pitches in normal times, the normal time ratio information, and the number of out pitches in all states). The performance display 97 displays the previous normal time ratio information (measurement history information) and the normal time ratio information currently being measured. In addition, it is possible to display not only the previous information but also the history of the time before the last time or the time before that (three times ago), and it is possible to appropriately determine how many times before the information is to be displayed.

(Production control command)
The main control board 20 is capable of transmitting various performance control commands including information regarding the special symbol variation display game, information regarding errors, etc. to the performance control board 30 depending on the processing state. However, in order to prevent fraud such as cheating, the main control board 20 only transmits signals to the production control board 30, and has a one-way communication configuration in which it cannot receive signals from the production control board 30. It has become.

Here, the production control command defines the function with a 2-byte structure consisting of a 1-byte length mode (MODE) and a 1-byte length event (EVENT), and in order to distinguish between MODE and EVENT, Bit 7 is ON, and Bit 7 of EVENT is OFF. When transmitting this information as valid information, a strobe signal is output corresponding to each of the mode (MODE) and event (EVENT). That is, when there is a command to be transmitted, the main control CPU 20a sets and outputs mode (MODE) information for transmitting the command to the production control board 30, and sends the first strobe signal after a predetermined period of time has elapsed from this setting. Send. Further, event information is set and output after a predetermined time has elapsed since the strobe signal was transmitted, and a second strobe signal is transmitted after a predetermined time has elapsed from this setting. The strobe signal is controlled to be active by the main control CPU 20a for a predetermined period to ensure that the production control CPU 30a can receive commands.

[2.2 Production control board]
The performance control board 30 is equipped with a microprocessor that includes a performance control CPU 30a, a performance control ROM 30b that stores performance data required for performance control processing, and a performance control RAM 30c that functions as a work area and buffer memory. It is mainly composed of a computer, and is also equipped with a sound control section (sound source IC), an RTC (Real Time Clock) function section, a counter circuit, an interrupt controller circuit, a reset circuit, a WDT circuit, etc., and controls the overall production operation.

The performance control CPU 30a performs arithmetic processing for various performance operations and controls each performance means based on the performance control program and the performance control commands received from the main control section 20. In the case of the pachinko game machine 1 of this embodiment, the production means include the liquid crystal display device 36 (main liquid crystal display device 36M, sub liquid crystal display device 36S), optical display device 45a, sound generator 46a, and a movable device (not shown). It becomes a physical object.

The production control ROM 30b stores a control program for production operations by the production control CPU 30a and various data necessary for production operation control.
The performance control RAM 30c is used as a work area used by the performance control CPU 30a for various calculation processes, a table data area, a buffer area for various input/output data, processing data, etc.
Note that the production control board 30 has a configuration in which, for example, a 1-chip microcomputer and its peripheral circuits are mounted, but various configurations of the production control board 30 are possible. For example, in addition to the microcomputer, there is an interface circuit with each part, a random number generation circuit that generates random numbers for lottery for performances, a CTC for various time counting, a watchdog timer (WDT) circuit, and an interrupt signal to the performance control CPU 30a. In some cases, an interrupt controller circuit or the like is provided.

The main roles of the production control board 30 are to receive production control commands from the main control unit 20, to select and decide production based on the production control commands, to control the display of the liquid crystal display device 36 (supply display data), and to control the display of the sound generator 46a. This includes audio output control of the optical display device 45a (LED), operation control of the movable accessory (drive control of the movable accessory motor 80c), and the like.

Since this production control board 30 also has a function as a control device for the liquid crystal display device 36, the production control board 30 also has functions as a so-called VDP (Video Display Processor), image ROM, and VRAM (Video RAM). The production control CPU 30a also functions as a liquid crystal control section.
VDP refers to a function that controls overall video output processing such as image development processing and image drawing.
The image ROM refers to a memory in which image data (effect image data) on which the VDP performs image development processing is stored.
The VRAM is an image memory area that temporarily stores image data developed by the VDP.

With these configurations, the performance control board 30 generates various image data based on commands from the main control unit 20, and outputs it to the main liquid crystal display device 36M and the sub liquid crystal display device 36S. As a result, various effects images are displayed on the main liquid crystal display device 36M and the sub liquid crystal display device 36S.
Here, the "liquid crystal display device 36" shown in FIG. 2 is the "main liquid crystal display device 36M." The illustration of the sub-liquid crystal display device 36S in FIG. 2 is omitted.

The production control board 30 also has a sound control section (for example, the sound controller 230 in FIG. 4) for the sound generation device 46a including a plurality of speakers 46, and the sound signal outputted by the sound control section is amplified by the amplifier section 46d. and is supplied to the speaker 46. Although the sound controller 230 as a sound control section will be described as being built into the production control board 30, the sound control section may use a sound source IC separate from the production control board 30.
In addition, the effect control board 30 includes a lamp driver section 45d that functions as a light display control section for a light display device 45a including a decorative lamp 45 and various LEDs, and a movable object motor that operates a movable object (not shown). A motor driver section 80d (motor drive circuit) functioning as a drive control section for 80c is connected. The production control board 30 instructs the lamp driver section 45d and the motor driver section 80d to control the light display operation by the optical display device 45a and the operation of the movable accessory motor 80c.

The production control board 30 is also connected to an origin switch 81 and a position detection sensor 82 for monitoring the operation of the movable accessory.
The origin switch 81 is composed of, for example, a photo interrupter, and detects whether or not the movable accessory motor 80c is at the origin position. The origin position is, for example, a position where the movable body is not normally exposed on the board surface in FIG. 2. The performance control board 30 is capable of determining whether or not the movable accessory motor 80c is at the origin position based on the detection information of the origin switch 81.
Further, the performance control board 30 controls the operation mode of the movable accessory while monitoring the current operation position (for example, the amount of movement from the origin position) based on the detection information from the position detection sensor 82. Furthermore, the performance control board 30 monitors malfunctions in the operation of the movable accessory based on the detection information from the position detection sensor 82, and if any malfunctions occur, they are detected as errors.

Further, to the production control board 30, switches for the production button 13, the cross key 15a, and the decision button 15b shown as the operation unit 17 in the figure, that is, the operation detection switches for the production button 13, the cross key 15a, and the decision button 15b are connected, The performance control board 30 is capable of receiving operation detection signals from the performance button 13, cross key 15a, and determination button 15b, respectively.

Furthermore, the performance control board 30 is provided with a handle sensor 83 (touch sensor) for detecting whether or not the firing operation handle 15 shown in FIG. 1 is being touched by a user such as a player. The production control board 30 is capable of determining whether or not the firing operation handle 15 is touched by the user based on the detection information of the handle sensor 83.

Based on the performance control command sent from the main control unit 20, the performance control board 30 selects (determines) a performance pattern by lottery or uniquely from among multiple types of performance patterns prepared in advance, and selects (determines) a performance pattern uniquely from a plurality of types of performance patterns prepared in advance. Various presentation means are controlled at the right timing to bring out the desired presentation. As a result, it is possible to display a performance image on the liquid crystal display device 36 corresponding to the performance pattern, play sound from the speaker 46, and drive the decorative lamps 45 and LEDs to turn on and off. A ``performance scenario'' in a broad sense is realized by chronologically unfolding the preview performances, etc.).

Here, regarding the production control command, the production control board 30 (production control CPU 30a) generates an interrupt process based on the input of the above-mentioned strobe signal transmitted by the main control unit 20 (main control CPU 20a), and receives and analyzes the command. conduct. Specifically, the production control CPU 30a executes a control program for command reception interrupt processing based on the input of the strobe signal described above, acquires the production control command in the interrupt processing realized thereby, and reads the command content. Perform analysis.
At this time, if an interrupt occurs based on the input of the strobe signal, even if an interrupt process based on another interrupt (timer interrupt process that is executed periodically) is being executed, The command reception interrupt processing is performed by interrupting the processing, and even if other interrupts occur at the same time, the command reception interrupt processing is performed with priority.

<3. Overview of operation>
Next, an overview of the gaming operation of the gaming machine 1 realized by the control configuration as described above (FIG. 3) will be explained.

[3.1 Game status]
The gaming machine 1 is configured to be able to set a plurality of types of gaming states in addition to the jackpot game which is a special gaming state. In order to facilitate understanding of this embodiment, various game states will first be explained.

In the gaming machine 1, the game progresses in any one of the gaming states in which either the low probability state or the high probability state is combined with either the non-time saving state or the time saving state.

The low probability state is a state in which the probability of winning a jackpot lottery is relatively low, and the high probability state is a state in which the probability of winning a jackpot lottery is relatively high.
The non-time-saving state is a state in which it is relatively difficult for game balls to enter the starting port 35, and the time-saving state is a state in which it is relatively easy for game balls to enter the starting port 35. For example, the opening time of the starting port 35 is set longer in the time-saving state than in the non-time-saving state when the winning lottery is won. However, if it is easier for the game ball to enter the starting port 35 in the time-saving state than in the non-time-saving state, then for example, the probability of winning the regular drawing lottery will be higher in the time-saving state than in the non-time-saving state. Alternatively, the fluctuation time of the normal symbol may be shortened.

In this embodiment, the "normal state" refers to a low probability state and a non-time saving state, and corresponds to an initial state.

[3.2 Symbol variation display game]
The symbol variation display game will be explained.

(Special symbol fluctuation display game)
In the pachinko game machine 1 of this embodiment, based on a predetermined starting condition, specifically, a game ball enters the starting hole 34 or the starting hole 35 (winning), the main control board 20 generates a random number. A "jackpot lottery" will be held. The main control board 20 starts a special symbol variation display game by variably displaying special symbols 1 and 2 on the special symbol display devices 38a and 38b based on the lottery results, and after a predetermined period of time has elapsed, The symbols are derived and displayed on the symbol display device, thereby ending the special symbol variation display game.

Here, in this embodiment, the jackpot lottery based on winnings in the starting slot 34 and the jackpot lottery based on winnings in the starting slot 35 are performed separately and independently. Therefore, the jackpot lottery result regarding the starting opening 34 is derived on the special symbol display device 38a side, and the jackpot lottery result regarding the starting opening 35 is derived on the special symbol display device 38b side. Specifically, on the special symbol display device 38a side, on the condition that the game ball enters the starting port 34, the first special symbol variable display game is started by displaying the special symbol 1 in a variable manner, and the other side On the special symbol display device 38b side, on the condition that a game ball enters the starting port 35, the special symbol 2 is displayed in a variable manner and a second special symbol variable display game is started. . Then, when the special symbol variation display game on the special symbol display device 38a or the special symbol display device 38b is started, after a predetermined variation display time has elapsed, if the jackpot lottery result is "jackpot", a predetermined "jackpot" is displayed. In other cases, the special symbol being displayed in a variable manner is stopped and displayed in a predetermined "miss" manner, thereby deriving the game result (jackpot lottery result).

In this specification, for convenience of explanation, the first special symbol fluctuation display game on the special symbol display device 38a side is referred to as "special symbol fluctuation display game 1", and the second special symbol on the special symbol display device 38b side is referred to as "special symbol fluctuation display game 1". The variable display game will be referred to as "special symbol variable display game 2." In addition, unless otherwise necessary, "Special Symbol 1" and "Special Symbol 2" will simply be referred to as "Special Symbol" (sometimes abbreviated as "Special Symbol"), and "Special Symbol Variation Display Game 1" and ""Special symbol variation display game 2" is simply referred to as "special symbol variation display game."

(Decorative pattern variable display game)
Further, when the above-mentioned special symbol variable display game is started, the decorative symbol variable display game is started by variably displaying decorative symbols (ornamental game symbols) on the main liquid crystal display device 36M. Various performances will be held in conjunction with the event. When the special symbol variable display game ends, the decorative symbol variable display game also ends, a predetermined special symbol indicating the jackpot lottery result is displayed on the special symbol display device, and the jackpot lottery result is reflected on the main liquid crystal display device 36M. The decorative patterns that have been created are now derived and displayed. That is, the result of the special symbol variation display game is reflected and displayed by a decorative symbol variation display game that includes a decorative symbol variation display operation.

Therefore, for example, when the result of the special symbol variation display game is a "jackpot" (when the jackpot lottery result is a "jackpot"), an effect that reflects the result is developed in the decorative symbol variation display game. Then, in the special symbol display device, when the special symbol is stopped and displayed in a display mode indicating a jackpot (for example, 7 segments is displayed as "7"), "left", "middle", " In each display area of ``Right'', the decorative pattern reflects the ``jackpot'' (for example, in each display area of ``Left'', ``Middle'', and ``Right'', 3 decorative patterns are displayed as ``7'', ``7'', and ``7''). 7" display state).

When this "jackpot" occurs, specifically, the special symbol variation display game ends, the decorative symbol variation display game ends accordingly, and as a result, the "jackpot" symbol mode is derived and displayed. After that, the big winning hole solenoid 52c of the special variable winning device 52 is activated and the opening door 52b opens and closes in a predetermined pattern, thereby opening and closing the big winning hole 50, which is more advantageous to the player than in the normal gaming state. A special game state (jackpot game) occurs. In this jackpot game, the opening door 52b allows the jackpot to be opened until a predetermined time (maximum opening time: for example, 29.8 seconds) has elapsed or the number of game balls that have entered the jackpot (big jack 50 winning balls) is a predetermined number (maximum number of winning balls: the upper limit of the number of winning balls allowed for a winning opening whose entrance is opened or expanded by one activation of the accessory: for example, 9) A "round game" in which the winning area is opened or expanded until the winning area is reached, and the big winning opening is closed when any of these conditions is met, is played for a predetermined number of rounds (for example, up to 16 rounds). round) repeated.

When the jackpot game starts, an opening performance is first performed to notify that the jackpot has started, and after the opening performance ends, a round game is performed a plurality of times up to a predetermined number of rounds as an upper limit. After the specified number of rounds is completed, an ending effect is performed to notify that the jackpot has ended, thereby ending the jackpot game.

Regarding the information necessary to execute the above-mentioned decorative symbol variation display game, first, the main control board 20 determines whether the game ball has entered the starting hole 34 or the starting hole 35 (winning). A 'winning/losing lottery' in which a "big hit" or a "miss" is determined on the condition that a game ball is detected by the mouth sensor 34a or the starting mouth sensor 35a and a starting condition (starting condition regarding a special symbol) is established. (Win/Fail Type Lottery)' and 'Symbol Lottery (Win Type (Win Type) Lottery)' which draws the jackpot type if it is a 'jackpot', or the losing type if it is a 'loss'. A jackpot lottery is carried out (if there is only one type of lottery, the lottery can be omitted as there is no need to perform a type lottery for the winners), and based on the lottery result information, the fluctuation pattern of the special symbol and the winning type are determined. Accordingly, a special symbol to be finally stopped and displayed (hereinafter referred to as "special stop symbol") is determined.

Then, the main control board 20 sends a "variation pattern designation command" that includes at least special symbol variation pattern information (for example, information regarding the jackpot lottery result and special symbol variation time, etc.) as an effect control command that specifies the processing state. It is transmitted to the production control board 30 side. As a result, basic information required for the decorative symbol variable display game is sent to the performance control board 30. In this embodiment, in order to provide a rich variety of performances, a "decorative symbol designation command" including information on special stop symbols (symbol lottery result information (information regarding hit type)) is also transmitted to the performance control board 30. It looks like this.

The above-mentioned special symbol variation pattern information can include information specifying whether or not a specific advance notice effect (for example, a "reach effect" or a "pseudo-continuous effect" to be described later) will occur. To be more specific, the special symbol variation patterns are roughly divided into a "winning variation pattern" in the case of a hit and a "loss variation pattern" in the case of a loss, depending on the jackpot lottery result. These fluctuation patterns include, for example, a 'reach fluctuation pattern' that specifies the occurrence of a reach effect, which will be described later, a 'normal fluctuation pattern' that does not specify the occurrence of a reach effect, and the occurrence (overlapping occurrence) of a pseudo-continuous effect and a reach effect. A plurality of types of variation patterns are included, such as a ``reach variation pattern with pseudo-coupling'' that specifies, and a ``normal variation pattern with pseudo-coupling'' that specifies the occurrence of a pseudo-coupling effect but not specifying the occurrence of a reach effect. In addition, in order to secure the production time for the ready-to-reach effect and the pseudo-continuous effect, the variation time is usually set longer for the variation pattern that specifies the ready-to-reach effect or the pseudo-continuous effect than for the normal variation pattern.

The production control board 30 performs chronological display during the decorative pattern variation display game based on information included in the production control commands (here, the variation pattern designation command and the decorative pattern designation command) sent from the main control board 20. The content of the performance to be developed (performance scenario such as a preview performance) and the decorative pattern to be finally displayed (decorative stop pattern) are determined, and the decorative pattern is displayed in a variable manner according to the time schedule based on the variation pattern of the special symbol. A symbol variation display game is executed. As a result, the decorative symbols on the main liquid crystal display device 36M are displayed in a variable manner in synchronization with the variable display of the special symbols on the special symbol display devices 38a and 38b, and the period of the special symbol variable display game and the decorative symbol variable display game are changed. The middle period has substantially the same time width. Furthermore, the effect control board 30 controls the main liquid crystal display device 36M, the optical display device 45a, or the sound generator 46a, respectively, in accordance with the effect scenario, and develops various effects in the decorative symbol variation display game. Thereby, the reproduction of images (image production) on the main liquid crystal display device 36M, the reproduction of sound effects (sound production), and the lighting and blinking driving of the decorative lamps 45, LEDs, etc. (light production) are realized.

In this way, the special symbol variation display game and the decorative symbol variation display game have an inseparable relationship, and the display results of the special symbol variation display game are reflected in the decorative symbol variation display game. , these two symbol variation display games may be regarded as equivalent symbol games. In this specification, the above two symbol variation display games may be simply referred to as "symbol variation display games" unless otherwise necessary.

(Normal symbol fluctuation display game)
In addition, in the gaming machine 1, based on the fact that a game ball has passed through the normal symbol starting port 37 (winning), an "assistance winning lottery" is performed by a random number lottery on the main control board 20. Based on this lottery result, the normal symbol fluctuation display game is started by displaying the normal symbols represented by the LEDs in a variable manner on the composite display device 38d, and after a certain period of time has elapsed, the result is displayed in a combination of LED lighting and non-lighting. It is designed to stop display. For example, when the result of the normal symbol variation display game is "assistance win", the display section of the normal symbol of the composite display device 38d is set to a specific lighting state (for example, all two LEDs 39 are lit, or "○" Among the LEDs representing "X" and "X", the LED on the "O" side is lit (in a lit state).

When this "assistance hit" occurs, the normal electric accessory solenoid 41c (see Fig. 3) is activated, which opens the movable wing pieces and opens or enlarges the starting port 35, making it easier for game balls to flow in. state (starting door open state), and an auxiliary game state (hereinafter referred to as "normal power open game") that is more advantageous to the player than the normal game state occurs. In this normal power release game, the movable blades are used to control whether the starting port 35 is opened for a predetermined period of time (for example, 0.2 seconds) or until the number of game balls that have entered the starting port 35 reaches a predetermined number (for example, 4 balls). The winning area is opened or expanded until the winning area is reached, and when any of these conditions is met, the starting port 35 is closed, and so on.

(About suspension)
Here, in this embodiment, during a special/decorative symbol fluctuation display game, during a normal symbol fluctuation display game, during a jackpot game, or during a normal power release game, winning is won in the starting hole 34, the starting hole 35, or the normal symbol starting hole 37. If this occurs, that is, if a detection signal is input from the starting port sensor 34a, starting port sensor 35a, or normal symbol starting port sensor 37a, and the corresponding starting condition (symbol game starting condition) is established, this will be displayed in a variable manner. Data related to the right to start a game, excluding data related to variable display, is stored up to a predetermined upper limit, which is the maximum number of stored data (for example, a maximum of 4). The pending pending data that has not been subjected to this symbol variation display operation, or the game ball related to the pending data, is also referred to as an "operation pending ball." In order to make it clear to the player the number of balls on hold, a dedicated hold display (not shown) provided at a suitable location on the gaming machine 1 or a liquid crystal display device 36 (main liquid crystal display device 36M or sub-liquid crystal display device 36S) lights up the hold indicator provided as an icon image on the screen.

In addition, in this embodiment, up to four operation-reserved balls related to the special symbol 1, special symbol 2, and normal symbol are each stored in the corresponding storage area of the main control RAM 20c, and are reserved as the number of confirmed fluctuations of the special symbol or the normal symbol. do. In addition, the maximum number of stored balls (maximum number of reserved balls) regarding the special symbol 1, special symbol 2, and normal symbol is not particularly limited. Further, all or a part of the maximum number of reserved storage numbers for each symbol may be different, and the number can be determined as appropriate depending on the gaming nature.

[3.3 About winning]
Next, "winning" in the gaming machine 1 will be explained.
In the gaming machine 1 of this embodiment, a jackpot lottery (win lottery) is performed for a plurality of types of wins. In the case of this example, the winning types include each jackpot belonging to the jackpot types, such as "normal 4R", "normal 6R", "probable variable 6R", and "probable variable 10R".
Note that the above notation "R" means the specified number of rounds (maximum number of rounds).

The jackpot type is a hit that triggers the operation of the conditional device. Here, the "condition device" is a device whose operation is a necessary condition for the operation of the accessory continuous operation device for playing a round game, and a specific combination of special symbols is displayed or a game ball is displayed. This refers to something that activates when passing through a specific area within the grand prize opening.

The above probability variable state ends the high probability state and shifts to a low probability state when the special symbol variation display game has been executed a predetermined number of times (for example, 70 times: the specified ST number) without winning the jackpot type. This is a so-called "time-limiting definite change machine (ST machine)", and when the specified ST number ends, the game returns to the normal state from the next game. However, it may also be a "general probability changing machine" that continues until the next jackpot is won.

The number of executions of the special symbol variation display game may be the total number of executions of the special symbol variation display game 1 and the special symbol variation display game 2 (the total number of variations of the special symbol 1 and special symbol 2), It may be the number of executions of either one (for example, the number of executions of the special symbol variation display game 2). Furthermore, the number of time-saving states is not limited to 60 or 100, but can be determined as appropriate depending on the gameplay. Furthermore, there is no particular restriction on what kind of hit to provide, and it can be determined as appropriate.

Here, in this example, there are a plurality of types of "losses" as well as jackpot types. Specifically, three types of deviations are provided: "missing 1", "missing 2", and "missing 3".
As described above, if the result of the winning/losing lottery is "losing", a lottery of the losing type is performed in the symbol lottery.

[3.4 About the performance]
(Production mode)
Next, the performance mode (performance state) will be explained. The gaming machine 1 of this embodiment is provided with a plurality of types of performance modes for presenting performances related to the gaming state, and is configured to be able to switch between the performance modes. Specifically, a normal performance mode, a time-saving performance mode, a probability performance mode, and a probability variable performance mode are provided, each corresponding to a normal state, a time-saving state, a probability state, and a probability-variable state. In each production mode, the background display as the background of the fluctuating display screen of decorative symbols is displayed with a different background effect, so that the player can understand what kind of gaming state he or she is currently in. It has become.

The performance control board 30 (performance control CPU 30a) has a functional unit (performance state transition control means) that controls transition between multiple types of performance modes. The performance control board 30 (performance control CPU 30a) includes specific performance control commands sent from the main control board 20 (main control CPU 20a), specifically, game state information managed on the main control board 20 side. Based on the performance control command, the current game state is grasped in a form that maintains consistency with the game state managed on the main control board 20 side, and it is configured to be able to control transition between a plurality of types of performance modes. Examples of the above-mentioned specific performance control commands include a variation pattern designation command, a decorative symbol designation command, and a game state designation command sent when a change occurs in the game state.

(Preview performance)
Next, the preview performance will be explained. The performance control board 30 executes various operations related to the current performance mode and the jackpot lottery result based on the contents of the performance control command from the main control board 20, specifically, at least the fluctuation pattern information included in the fluctuation pattern designation command. It is configured to be able to control the appearance of "notice effects". This kind of preview performance is used as a "stimulation performance" to suggest (notice) the level of expectation as to whether or not the winning type has been won (hereinafter referred to as "win expectation level"), and to arouse the player's expectation of winning. work. Typical preview performances include "reach performance,""pseudo-continuationperformance," and even "pre-read preview performance." The performance control board 30 functions as a preview performance control means that can control the execution (appearance) of these performances.

"Reach effect" refers to a performance mode that involves a reach state (fluctuating display mode that involves a reach state: reach variation pattern), and specifically, a method that derives and displays the final game result via a reach state. It refers to the style of production. The reach effects include multiple types of reach effects associated with the degree of expectation of winning. For example, there are cases where the expectation of winning is relatively higher than when a normal reach effect appears. This kind of reach performance is called ``super reach performance.'' Many of these "super reaches" have a relatively longer production time (fluctuating time) than normal reaches in order to stimulate expectations of winning. In addition, normal reach and super reach include multiple types of reach effects. In this example, Super Reach includes multiple types of reach effects such as Super Reach 1, 2, 3, and 4, and the winning expectation of Super Reach 1 to 4 is expressed as "Super Reach 1 < Super Reach 2 < Super Reach". The relationship is “Reach 3 < Super Reach 4”.

"Pseudo-continuous performance" refers to a performance mode that involves a pseudo continuous variation display state (pseudo-continuous variation) of decorative symbols. It refers to a variable display mode in which a display operation is repeated one or more times, in which a part or all of a decorative pattern is temporarily stopped, and then the decorative pattern is re-variably displayed from the temporarily stopped state. In this respect, it is different from the later-described "pre-read preview performance (continuous preview performance)" which is developed over multiple symbol change display games. Basically, the occurrence rate (appearance rate) of such "pseudo-links" is determined so that the higher the number of pseudo fluctuations, the higher the expectation of winning.For example, depending on the number of pseudo fluctuations, It is made easier to select performances to arouse expectations such as reach.

"Pre-reading notice effect" (hereinafter sometimes abbreviated as "pre-reading notice" or "pre-reading effect") is, based on the result of pre-reading judgment, before the fluctuation display of the target symbol is performed. It means an effect that alerts you to the possibility of being controlled in an advantageous state. Note that "advantageous state" means a state advantageous to the player.
Specifically, the look-ahead performance in this example mainly displays pending balls (unexploited pending balls) that have not yet been used for the execution of the symbol variation display game (variable display operation of special symbols). It is performed in a presentation manner that can notify the winning expectation in advance before the operation pending ball is used in the symbol variation display game, using the pattern and background effects of the symbol variation display game to be executed first. . In addition, in the symbol variation display game, in addition to the above-mentioned "reach effect", there are various effects such as the so-called "SU (step up) notice effect", "timer notice effect", "resurrection effect", and "premier notice effect". It occurs and is designed to liven up the game content.

Here, with reference to FIG. 4, the "suspended change notice performance" as an example of the above-mentioned pre-read notice performance will be described.
In the case of the gaming machine 1 of the present embodiment, the upper display area of the screen of the main liquid crystal display device 36M includes a display area for displaying a decorative symbol variable display game (a display area for displaying a decorative symbol variable display effect and a preview effect). In addition, the display area on the lower side of the screen includes a hold display area 76 (hold display areas a1 to d1) that displays the number of active hold balls on the special symbol 1 side and a special hold display area 76 (hold display areas a1 to d1). A reservation display area 77 (reservation display parts a2 to d2) that displays the number of activated reservation balls on the symbol 2 side is provided. Regarding the presence or absence of an operation pending ball, this fact is notified by a predetermined pending display mode. In Fig. 5, the presence or absence of an operation-holding bulb is shown in the lighted state (with an operation-holding bulb: "○ (white circle mark)" shown in the figure) or in the off state (no operation-holding ball: a broken-line circle shown in the figure). An example is shown in which information regarding the number of pending pitches is reported.

Displays regarding the presence or absence of pending action balls (pending display) are displayed in order of occurrence (order of winning), and in each pending display area 76, 77, the leftmost action pending ball indicates that all actions in the pending display are displayed. It is displayed as the activated suspended ball that occurred first (that is, the oldest) among the suspended balls on the time axis. Further, on the left side of the holding display areas 76 and 77, a fluctuating display area 78 is provided to show the activated holding balls that are currently being used in the special symbol changing display game. In the case of the present embodiment, the changing display area 78 is configured so that an image in which an icon of a game currently being played pending K is displayed on top of the icon of the catch J. That is, when the variable display of the special symbol 1 or the special symbol 2 is started, the icon (icon image) of the oldest pending a1 or a2 displayed in the pending display areas 76 and 77 is changed to the icon (icon image) of the oldest pending K during game execution. As an icon, it moves onto the icon of the catch J in the changing display area 78, and this state is maintained for a predetermined display time.

When a pending ball occurs, the main control board 20 sends the pre-read judgment information related to the jackpot lottery result and the number of pending balls at the time of the pre-read judgment (the current number of pending balls, including the currently held ball) A "pending addition command" specifying this is sent to the production control board 30 (see steps S1309 to S1312 in FIG. 28).
In the case of this embodiment, the pending addition command is composed of 2 bytes, and the pending addition command includes data on the upper byte side that makes it possible to specify the number of active pending balls at the time of look-ahead judgment, and the look-ahead judgment information. It consists of lower byte side data.

Here, as understood from the above description, in the present embodiment, based on the occurrence of a winning in the starting hole 34 or the starting hole 35 and a new held ball, a pre-reading determination regarding the held ball is performed. , a jackpot lottery is held for the symbol variation display game related to the reserved ball. As will be described later, the main control board 20 holds and stores information representing the result of the jackpot lottery conducted as such a pre-read determination in the corresponding storage area of the main control RAM 20c.
The information on the jackpot lottery result obtained during the pre-reading determination is used to select (lottery) a symbol variation pattern in the symbol variation display game, and can be referred to as "variation pattern selection information". Therefore, it can be said that the main control board 20 performs a pre-read determination and stores the resulting "variation pattern selection information" in a predetermined area of the main control RAM 20c.

When the effect control board 30 receives the above-mentioned pending addition command transmitted by the main control board 20, based on the pre-read judgment information included therein, the effect control board 30 performs a "pre-read preview effect" as part of the display control process related to the above-mentioned pending display. Performs production control processing related to. Specifically, a "pre-read preview lottery" is held to determine whether or not the pre-read preview performance can be executed, and if the lottery is won, the pre-read preview performance is made to appear.

Here, the look-ahead determination information specifically refers to the jackpot lottery result (jackpot lottery result at the start of fluctuation) executed when the operation-reserved ball is used in the symbol fluctuation display game in the main control board 20; This is game information obtained by pre-reading and determining the fluctuation pattern at the start of fluctuation. In other words, this information includes at least information that pre-reads and determines the winning/losing lottery results at the start of fluctuation (pre-read winning/losing information), and also includes information that pre-reads and determines the symbol lottery results (pre-read symbol information) and fluctuations at the start of fluctuation. It is possible to include information on which a pattern has been pre-read and determined (pre-read variation pattern information). What kind of information to send the pending addition command to the production control board 30 can be determined as appropriate depending on the content to be notified in the advance notice.
In this example, it is assumed that the pending addition command includes pre-read win/loss information, pre-read symbol information, and pre-read variation pattern information.

In addition, the "pre-read fluctuation pattern" obtained by the pre-read judgment when the action-holding ball occurs does not necessarily have to be the "fluctuation pattern at the start of fluctuation" obtained when the action-holding ball is actually subjected to the fluctuation display operation. There isn't. For example, to describe a typical case where the fluctuation pattern at the start of the fluctuation is a fluctuation pattern that specifies "Super Reach 1", in this case, the content specified by the look-ahead fluctuation pattern is "Super Reach 1". Rather than specifying the type of reach performance itself, it is possible to specify the essential "super reach type".

In the case of the present embodiment, if you win the pre-read preview lottery, the pending icon that is the target of the pre-read preview among the pending icons in the pending display areas a1 to d1 and a2 to d2 will be displayed as a normal hold display, for example. "Pending display change" that can change from white (normal pending display mode) to a pending display (special pending display mode) with blue, green, red, and danger patterns (or special colors and patterns such as rainbow colors) for advance notice. A pre-read preview performance (also referred to as a "pending change notice") of "Kei" will be performed.
FIG. 5 shows an example in which the hatched operation reservation sphere of the reservation display section b1 has changed to a special reservation display. Here, the display of the pending icon in blue, green, red, and danger pattern means that the expectation of winning is high in this order.In particular, the display of the pending icon with the danger pattern indicates that the expectation of winning the jackpot is extremely high. It is said to be a premium hold icon that will be displayed.

(Direction means)
Various effects on the game machine 1 are produced by effect means provided in the game machine 1. This presentation means may be any stimulus transmission means that can produce a presentation effect by appealing to human senses such as visual, auditory, and tactile senses, and may be a light generating means such as a decorative lamp 45 or an LED device (light display device 45a: light production means), sound generation devices such as the speaker 46 (sound production device 46a: sound production means), production display devices (display means) such as the main liquid crystal display device 36M and the sub liquid crystal display device 36S, and contact with the operator's body. Typical examples include a pressure device that transmits pressure, a wind pressure device that applies wind pressure to the player's body, and a movable accessory that produces a visual performance effect by its operation. Here, the effect display device is a visually appealing display device like the image display device, but differs from the image display device in that it also includes devices that do not rely on images (for example, a 7-segment display). When referred to as an image display device, it mainly refers to a type that displays effects by displaying images, and devices that express effects by other than images, such as a 7-segment display, are included in the concept of effect display device.

<4. Opening/closing structure and board arrangement>

The configuration of FIG. 3 described above is actually realized via a plurality of substrates. Below, some of the boards mounted on the gaming machine 1 will be selected and their arrangement will be explained. The opening/closing structure of the gaming machine 1 will also be explained for the mounting position of the board.

FIG. 5 shows the door 6 in an open state.
When the door 6 is opened, the inner frame 2 and the game board 3 attached to the inner frame 2 are directly exposed.
Note that a wiring connection is made between the substrate placed on the door 6 and the substrate placed on the inner frame 2 by a harness serving as a transmission line H8.

Furthermore, the gaming machine 1 is configured so that the inner frame 2 can be opened relative to the outer frame 4.
FIG. 6 shows the inner frame 2 in an open state. When the inner frame 2 is opened, the game board 3 attached to the inner frame 2 is also released from the outer frame 4. FIG. 6 shows a state in which the back cover 18 attached to the back side of the game board 3 is visible. Although the game board 3 is not shown in FIG. 6, when the back cover 18 is removed (opened), the back side of the game board 3 is exposed. In fact, since the back cover 18 is transparent or semi-transparent, the back side of the game board 3 can be seen in the state shown in FIG.
Note that the game board 3 can be further removed from the inner frame 2.

In this way, the game machine 1 is roughly divided into an outer frame 4, an inner frame 2 attached to the outer frame 4, a game board 3 attached to the inner frame 2, and a front side of the game board 3 and the inner frame 2. It is composed of a door 6 located. Various boards are attached to either the game board 3, the inner frame 2, or the door 6.

FIG. 7 shows the positions of some of the boards attached to the game board 3. Note that FIG. 7 shows the board mounted on the back side of the game area 3a when the game board 3 is viewed from the back side. Therefore, the right side in the figure is the left side when the game board 3 is viewed from the front side. In the figure, the outline of the frame of the game board 3 is shown with a dashed-dotted line as a guide for the position.

As shown in the figure, on the back side of the game board 3, an effect control board 30 is arranged slightly above the center, and a main control board 20 is arranged below it. Further, a liquid crystal control board 901 is arranged so as to overlap the production control board 30, and a ROM board 902 and a liquid crystal interface board 903 are arranged in the vicinity thereof.

An LED connection board 700 is arranged on the left side of the back surface of the game board 3, and a power module board 904 is arranged near the top thereof.
Further, an upper connection board 905 is arranged above the game board 3.

Near the main control board 20, a relay board 760, a decorative board 740, a back left relay board 720, a game board connection board 906, a back bottom relay board 800, and a frame LED relay board 840 are arranged.

Further, as substrates attached to a movable accessory (not shown) attached to the game board, there are LED substrates 780, 790 and a decorative substrate 820.

FIG. 8 shows the positions of some of the boards attached to the door 6 as seen from the front side of the gaming machine 1. As for the internal structure of the gaming machine 1, the door 6, the production button 13, the firing operation handle 15, and the upper speaker 46 are shown with dashed lines for positional reference.

A relay board 550 is provided above the door 6.
Similarly, a side unit upper LED board 630 is provided above the door 6, a side unit upper right LED board 600 is provided at the upper right of the door 6, and a side unit lower right LED board 620 is provided below it. Note that these side unit upper right LED board 600, side unit lower right LED board 620, and side unit upper LED board 630 are installed inside the side unit 10 (see FIG. 1), and each board When installed, the position shown in FIG. 8 is achieved.

A frame left LED board 907 is arranged at the upper left side of the door 6, and a frame lower left LED board 908 is arranged below it.
Further, a front frame LED connection board 500 is arranged below the door 6.
Further, a button LED connection board 640 is arranged at the lower right, and a button LED board 660 is arranged inside the production button 13.

Next, the position of the board attached to the inner frame 2 will be explained. FIG. 9 is a diagram of the gaming machine 1 viewed from the back. Most of the back side of the gaming machine 1 is protected by a transparent or translucent back cover 18.
Below this rear side, a power supply board 300 and a payout control board 29 are arranged front and back.
Furthermore, an inner frame LED relay board 400 is attached to the lower right side when viewed from the back side.

FIG. 10 shows the positions of various devices placed on the door 6 and the game board 3. The outlines of the game board 3 and the door 6 are shown with dashed lines as a guide for the position of each device.

In FIG. 10, the devices provided in the side unit 10 of the door 6 include a side unit device 101, a side unit lower right movable part position detection switch 102, a side unit lower right movable part motor 103, and a side unit upper right movable part motor 104. , a side unit upper right movable solenoid 105, a blower 106, and photocouplers PC1F, PC2F, and PC3F are arranged at the positions shown, respectively. Photocouplers PC1F, PC2F, and PC3F are attached to the lower right LED board 620 of the side unit.

In FIG. 10, the devices attached to the game board 3 include a lower back movable object upper position detection switch 120, a lower back movable object right position detection switch 121, a sorting position detection switch 122, a lower front movable object position detection switch 123, Front movable object motor 124, lower back movable object left position detection switch 125, lower back movable object left motor 126, lower back movable object lower right position detection switch 127, lower back movable object lower left position detection switch 128, upper back movable object left The motor 129, the upper movable object left position detection switch 130, the left movable object motor 131, the upper movable object position detection switch 132, the upper movable object right motor 133, the left movable object position detection switch 134, and the lower back movable object right motor 135. Each is placed at the position shown in the figure.

Note that the boards shown in FIGS. 7, 8, and 9 above are only part of the boards provided in the gaming machine 1. In particular, it illustrates the main substrates that will be the subject of the following explanation.
Furthermore, the devices shown in FIG. 10 are only some of the devices provided in the gaming machine 1.

<5. Board connection configuration>
[5.1 Connection status of each board]

The connection configuration of each board arranged as described above will be explained, and the supply route of the power supply voltage will be mentioned.

FIG. 11 shows an example of boards arranged on the game board 3, the inner frame 2, and the door 6, respectively.
In this case, the boards mounted on the game board 3 include the main control board 20, the performance control board 30, the frame LED relay board 840, the LED connection board 700, the board back left relay board 720, the decoration board 740, the relay board 760, and the LED. A board 780, an LED board 790, a lower board relay board 800, and a decorative board 820 are shown.
As the boards mounted on the inner frame 2, a power supply board 300, a payout control board 29, and an inner frame LED relay board 400 are shown.
The boards mounted on the door 6 include a front frame LED connection board 500, a relay board 550, a side unit upper right LED board 600, a side unit lower right LED board 620, a side unit upper LED board 630, a button LED connection board 640, and a button. An LED board 660 is shown.

Each of these boards is a part of the board mounted on the game machine 1, and there are various boards mounted on the game board 3, the inner frame 2, and the door 6 other than those shown in the drawings. This FIG. 11 shows a connection system of selected boards for use in explaining the technology as an embodiment of the present invention, and does not show all the boards.

The power supply board 300 is a board that supplies DC voltage as an operating power source to each part based on an AC input power supply.
The main control board 20, production control board 30, and payout control board 29 are as described in FIG. 3.

The front frame LED connection board 500 is a board for supplying operation control signals and power supply voltage to the LED provided on the door 6, the motor of the movable body, the solenoid, the blower, and other performance means.

The upper right LED board 600 of the side unit, the lower right LED board 620 of the side unit, and the upper LED board 630 of the side unit are boards disposed within the side unit 10, and constitute a drive control system for the mode of the LEDs and movable objects. These boards also constitute a detection system that transmits detection signals from the motor position sensor, touch sensor, and other various sensors to the production control board 30.
As described above, the side unit 10 is attached to the door 6 as one of the decorative units, and the side unit 10 is detachable from the door 6 and can be replaced. The upper right LED board 600 of the side unit, the lower right LED board 620 of the side unit, and the upper LED board 630 of the side unit are attached and detached together with the side unit 10.
When the side unit 10 is attached and the relay board 550 and the transmission line H10 of the upper right LED board 600 of the side unit are connected, the electrical configuration shown in FIG. 11 is obtained.

The button LED board 660 constitutes the LED in the performance button 13 and its light emitting drive system, and also constitutes a circuit that transfers detection signals from various detection sensors.
The button LED connection board 640 relays control signals and power supply voltage to the button LED board 660, and also transfers detection signals from various sensors.

The inner frame LED relay board 400 relays between the frame LED relay board 840 connected to the production control board 30 and the front frame LED connection board 500, performs necessary signal processing, and also generates and supplies power supply voltage. .
The frame LED relay board 840 relays a signal path between the inner frame LED relay board 400 and the production control board 30.

The LED boards 780 and 790 are mounted with LEDs in the game board 3 and drive the LEDs to emit light. The relay board 760 relays the LED light emission drive signal. These LED boards 780, 790 and relay board 760 are attached to a movable accessory.
The decorative board 740 serves as a relay and drives other LED boards.
The back left relay board 720 performs relay.
The decorative board 820 is equipped with LEDs.
The board back lower relay board 800 performs relaying.
The LED connection board 700 performs various necessary signal processing for driving light emission of performance means such as LEDs and motors based on control signals from the performance control board 30.

These respective boards are electrically connected by a transmission line H using a harness and a cable. "Transmission line H" is a general term for the illustrated transmission lines H1, H2, . . . H31.
In each transmission line H, each wiring path for transmitting signals, power supply voltage, etc. is also simply referred to as a "line."
The transmission line H refers to one or a set of multiple lines.
The transmission line H includes various forms such as a flexible harness, a flexible substrate, and a wire harness. Further, the transmission line H may be one in which a plurality of lines are integrated, or may be one in which individual lines are held together with a binder, tape, or the like.
Further, when the connectors are directly connected to each other, the terminals of each connector become the transmission line H. In other words, even if a wire such as a harness does not exist, it is included in the "transmission line H".
That is, the transmission line H does not refer to a specific type or shape, but broadly refers to a line that forms electrical wiring between substrates or the like.

The power supply board 300 and the payout control board 29 are connected by a transmission line H1.
Further, the power supply board 300 and the inner frame LED relay board 400 are connected by a transmission line H3.
These transmission lines H1 and H3 are formed by harnesses or the like arranged within the inner frame 2.

The power supply board 300 and the production control board 30 are connected by a transmission line H2.
The payout control board 29 and the main control board 20 are connected by a transmission line H4.
The inner frame LED relay board 400 and the frame LED relay board 840 are connected by a transmission line H7.
These transmission lines H2, H4, and H7 are formed by harnesses or the like that straddle and connect between the inner frame 2 and the game board 3.

The main control board 20 and the production control board 30 are connected by a transmission line H5.
The production control board 30 and the frame LED relay board 840 are connected by a transmission line H6.
The production control board 30 and the LED connection board 700 are connected by a transmission line H20.
The LED connection board 700 and the back left relay board 720 are connected by a transmission line H21.
The back left relay board 720 and the decorative board 740 are connected by a transmission line H22.
The decorative board 740 and the relay board 760 are connected by a transmission line H23. It is conceivable that the transmission line H23 is a flexible cable for connection to the relay board 760 attached to the movable accessory.
The relay board 760 and the LED board 780 are connected by a transmission line H24.
The LED board 780 and the LED board 790 are connected by a transmission line H25.
The LED connection board 700 and the bottom relay board 800 are connected by a transmission line H30.
The lower relay board 800 and the decorative board 820 are connected by a transmission line H31.
These transmission lines H5, H6, H20, H21, H22, H23, H24, H25, H30, and H31 are formed by harnesses arranged within the game board 3.

The inner frame LED relay board 400 and the front frame LED connection board 500 are connected by a transmission line H8.
This transmission line H8 is formed by a harness or the like that straddles and connects between the inner frame 2 and the door 6.

The front frame LED connection board 500 and the relay board 550 are connected by a transmission line H9.
The relay board 550 and the upper right LED board 600 of the side unit are connected by a transmission line H10.
The side unit upper right LED board 600 and the side unit lower right LED board 620 are connected by a transmission line H11.
The upper right LED board 600 of the side unit and the upper LED board 630 of the side unit are connected by a transmission line H12.
The front frame LED connection board 500 and the button LED connection board 640 are connected by a transmission line H15.
The button LED connection board 640 and the button LED board 660 are connected by a transmission line H16.
These transmission lines H9, H10, H11, H12, H15, and H16 are formed by harnesses or the like arranged inside the door 6.

The power supply board 300 supplies power supply voltage to each part through transmission lines H1, H2, and H3.
FIG. 12 shows the power supply system input/output for the power supply board 300.
The power supply board 300 is equipped with connectors CN1A to CN7A.
Transmission line ends of transmission lines H40, H41, and H42, which are not shown in FIG. 11, are connected to the connectors CN5A, CN6A, and CN7A.

Hereinafter, the connectors CN1A to CN7A, including connectors appearing in other figures, will be collectively referred to as "connector CN."
In this specification, "connector CN" refers to a connector terminal component provided on a board. The terminal portion formed at the end of the transmission line H for connector connection will be referred to as a "transmission line end."
"Connector CN" is connected to "transmission line end". Alternatively, the "connector CN" may be directly connected to another connector CN of a corresponding shape.

AC 24V power from the power plug 301 of the gaming machine 1 is supplied to the three-terminal connector CN5A through the transmission line H40 (AC-IN(A), AC-IN(B)).
Further, an FG (frame ground) path (FG) is formed via the ground terminal 302, the transmission line H40, and the connector CN5A. The ground terminal 302 is connected, for example, to the outside of the gaming machine main body.

A transmission line H41 is connected to the two-terminal connector CN6A, and an FG path (FG-1) via ground terminals 303 and 304 is formed. The ground terminals 303 and 304 are connected to, for example, the gaming machine main body.
A transmission line H42 is connected to the two-terminal connector CN7A, and an FG path (FG-2) via ground terminals 305 and 306 is formed. The ground terminals 305 and 306 are connected to, for example, the gaming machine main body.

A transmission line H1-1 is connected to the connector CN1A having a 14-terminal configuration. Further, a transmission line H1-1 is connected to the three-terminal connector CN4A. The transmission lines H1-1 and H1-2 as these two harnesses are shown as the transmission line H1 in FIG. 11 described above.
A 35V DC voltage (DC35VA), a 12V DC voltage (DC12VA), and a 5V DC voltage (DC5VA) are supplied to the payout control board 29 through the transmission line H1-1, and a ground path (GND) is formed.
Two systems of 24V DC voltage (DC24VA, DC24VB) are supplied to the payout control board 29 through the transmission line H1-2, and an FG path (FG) is formed.

35V DC voltage (DC35VA), 12V DC voltage (DC12VA), and 5V DC voltage (DC5VA) are supplied to the main control board 20 via the payout control board 29, and a ground path (GND) is formed. .

A transmission line H2 is connected to the connector CN2A having a 20-terminal configuration.
5V DC voltage (DC5VB), 12V DC voltage (DC12VB), and 35V DC voltage (DC35VB) are supplied to the production control board 30 by the transmission line H2, and a ground path (GND) is formed.

Based on the power supply through the transmission line H2, 5V DC voltage (DC5VB), 12V DC voltage (DC12VB), and 35V DC voltage (DC35VB) are supplied from the production control board 30 to the LED connection board 700, and the LED connection board 700 and each downstream board (back panel left relay board 720, panel back lower relay board 800, etc.) as an operating power source.
On the other hand, the frame LED relay board 840 is a board that simply has relay wiring and does not require a power supply voltage, and is not supplied with power voltage from the effect control board 30.

For the purpose of explanation, the expressions "upstream" and "downstream" are used, but in terms of data and control signals, the main control board 20 is the most upstream, followed by the production control board 30, and from the production control board 30 the actual signals such as LEDs and motors are ``downstream'' toward the production device.
Regarding the power supply voltage, the power supply board 300 is the most upstream, and it is assumed that it is "downstream" toward the actual performance device.

A transmission line H3 is connected to the six-terminal connector CN3A.
A 12V DC voltage (DC12VB) is supplied to the inner frame LED relay board 400 through the transmission line H3, and a ground path (GND) is also formed.
In other words, the inner frame LED relay board 400 is a board controlled by the effect control board 30, but is configured to receive power supply voltage directly from the power supply board 300.
Each board (front frame LED connection board 500, etc.) provided on the door 6 downstream of the inner frame LED relay board 400 receives power supply voltage from the inner frame LED relay board 400.

[5.2 Inner frame LED relay board 400]

The circuit configurations of some of the boards shown in FIG. 11 will be described below. First, the inner frame LED relay board 400 will be explained using FIGS. 13 and 14.
13 and 14 separately show the circuit configuration provided on the inner frame LED relay board 400.

Connectors CN1B, CN2B, and CN3B shown in FIG. 13 and connector CN4B shown in FIG. 14 are mounted on the inner frame LED relay board 400.

The transmission line end of the transmission line H7 that connects the frame LED relay board 840 is connected to the connector CN1B.
The details of the frame LED relay board 840 will be omitted, but as described above, it is a board that simply has relay wiring. Therefore, the connector CN1B essentially forms wiring with the production control board 30 via the transmission line H7, the frame LED relay board 840, and the transmission line H6.

This connector CN1B has 28 terminals from the 1st pin to the 28th pin as indicated by numbers "1" to "28".
For convenience of explanation, the term "pin" of the connector CN does not refer only to pin-shaped male terminals, but also includes both male and female terminals, and also includes so-called planar contact patterns and corresponding It is also used to include terminals, etc.

The 1st pin, 3rd pin, 5th pin, 7th pin, 8th pin, 17th pin, and 18th pin are used as ground terminals. The second pin is assigned as a clock signal S_IN_CLK, the fourth pin is assigned as a load signal S_IN_LOAD, and the sixth pin is assigned as a serial data signal S_IN_DATA terminal.

9th pin is clear signal CLR_L, 10th pin is clear signal CLR_M, 11th pin is clock signal CLK_L, 12th pin is clock signal CLK_M, 13th pin is data signal DATA_L, 14th pin is data signal DATA_M, 15th pin The pin is assigned as the enable signal ENABLE_L, and the 16th pin is assigned as the enable signal ENABLE_M.
The 19th to 28th pins are assigned to the + terminal and - terminal of the upper right speaker, middle right speaker, lower right speaker, upper left speaker, middle left speaker, and lower speaker as the speaker 46, respectively.

Here, the serial data signal S_IN_DATA is serial data received from the front frame LED connection board 500 and transmitted from the inner frame LED relay board 400 to the production control board 30.
The clock signal S_IN_CLK and the load signal S_IN_LOAD are supplied from the production control board 30 to the inner frame LED relay board 400, and further sent to the front frame LED connection board 500. These are used for serial data transmission operation from the front frame LED connection board 500 on the downstream side.

Clear signals CLR_L, CLR_M, clock signals CLK_L, CLK_M, data signals DATA_L, DATA_M, and enable signals ENABLE_L, ENABLE_M are signals used for drive control of the production device supplied from the production control board 30.
For example, the data signals DATA_L and DATA_M are light emission drive signals and motor drive signals that indicate the gradation of the LED, and the clear signals CLR_L and CLR_M, etc., the clock signals CLK_L and CLK_M, etc., and the enable signals ENABLE_L and ENABLE_M are the LED driver and motor drive signals. This is a signal for controlling the operation of the motor driver.
Note that "_L" at the end of the clock signals CLK_L, CLK_M, etc. indicates a signal mainly used for controlling the operation of the LED, and "_M" indicates a signal mainly used for controlling the operation of the motor.

The transmission line end of the transmission line H8 that connects the front frame LED connection board 500 is connected to the connector CN2B.
This connector CN2B has 30 terminals from the 1st pin to the 30th pin as indicated by numbers "1" to "30".

The first pin and the third pin are terminals for a 5V direct current voltage (DC5VB).
Four pins from the 27th pin to the 30th pin are terminals for 12V DC voltage (DC12VB).
The 5th pin, the 7th pin, the 8th pin, the 17th pin, and the 18th pin are used as ground terminals.
Note that conductor points P1 and P2 on the housing of connector CN2B are connected to ground. This is for the mounting strength of the connector. Conductor points P1 and P2 are not connected to the ground terminal inside the connector.
In all other illustrated connectors CN, the conductor points P1 and P2 in the housing are not connected to the ground terminal inside the connector.

The second pin is assigned as a clock signal S_IN_CLK, the fourth pin is assigned as a load signal S_IN_LOAD, and the sixth pin is assigned as a serial data signal S_IN_DATA terminal.
9th pin is clear signal CLR_L, 10th pin is clear signal CLR_M, 11th pin is clock signal CLK_L, 12th pin is clock signal CLK_M, 13th pin is data signal DATA_L, 14th pin is data signal DATA_M, 15th pin The pins are assigned as general-purpose output ports, and the 16th pin is assigned as each terminal of the enable signal ENABLE_M.
The 19th to 26th pins are assigned to the + and - terminals of the upper right speaker, middle right speaker, lower right speaker, upper left speaker, and middle left speaker, respectively, as shown in the figure.

The connector CN3B is a connector for connection to a lower speaker, which is one of the speakers 46 not shown in FIG. The first and second pins of this connector CN3B with numbers "1" and "2" are assigned to the + terminal and - terminal of the lower speaker, and are connected to the 27th pin and 28th pin of the connector CN1B.

The connector CN4B in FIG. 14 is connected to the transmission line end of the transmission line H3 that connects with the power supply board 300, and is connected to the connector CN3A of the power supply board 300 shown in FIG. 12.
This connector CN4B has a six-terminal configuration from the first pin to the sixth pin as indicated by numbers "1" to "6", and is assigned in the same manner as the connector CN3A of the power supply board 300. That is, the first pin, the second pin, and the third pin are terminals to which 12V DC voltage (DC12VA) is supplied from the power supply board 300. The fourth pin, the fifth pin, and the sixth pin are used as ground terminals.

In this case, the inner frame LED relay board 400 is configured to input 12V DC voltage (DC12VA) from the first, second, and third pins to the voltage regulator 401 via the fuse F1B. A 5V direct current voltage (DC5VB) is obtained as an output. Capacitors C3B, C4B, C5B, and C6B are connected in parallel between the input terminal side of voltage regulator 401 and ground. A capacitor C7B and a resistor R24B are connected in parallel between the output terminal side of the voltage regulator 401 and the ground.
That is, a 5V generation section 410 is formed that generates a 5V DC voltage (DC5VB) from a 12V DC voltage (DC12VA).

From the first and third pins of the connector CN2B in FIG. 13, the 5V DC voltage (DC5VB) generated in the inner frame LED relay board 400 is supplied to the downstream board.
Note that the 12V DC voltage (DC12VB) supplied to the downstream board from the 27th pin to the 30th pin of the connector CN2B is supplied to the downstream board via the 1st, 2nd, and 3rd pins of the connector CN4B in Figure 14. This is the voltage supplied from the power supply board 300.

As shown in FIG. 13, buffer circuits 402 and 403 using ICs are arranged on the inner frame LED relay board 400.
As the buffer circuits 402 and 403, ICs are used that function as an inverter when the CONT terminal of the first pin is at L level, and as a buffer when it is at H level. It functions as a buffer.
Further, as an operating power supply, a 5V DC voltage (DC5VB) is applied to the 20th pin VCC terminal.

The buffer circuits 402 and 403 are Schmitt trigger buffers containing 8 CMOS circuits, and are buffers for signals input from the second pin (A1 terminal) to the ninth pin (A8 terminal), that is, signal compensation (deteriorated H/ (repair of the L signal waveform) and output from the 18th pin (Y1 terminal) to the 11th pin (Y8 terminal), respectively.
In other words, the signal input to the A1 terminal is buffered and output from the Y1 terminal, the signal input to the A2 terminal is buffered and output from the Y2 terminal,...the signal input to the A8 terminal is buffered. and output from the Y8 terminal.
Note that buffer processing refers to signal compensation processing using signal amplification, waveform shaping, etc., and since it mainly targets pulse signals as digital data, waveform shaping has a large meaning. Below, these processes will be referred to as "buffer processing", "signal compensation", etc.

The buffer circuit 402 performs signal compensation for the clock signal S_IN_CLK, the load signal S_IN_LOAD, and the serial data signal S_IN_DATA.
The clock signal S_IN_CLK from the second pin of the connector CN1B is input to the A3 terminal of the buffer circuit 402, output from the Y3 terminal, and supplied to the second pin of the connector CN2B.
The load signal S_IN_LOAD from the fourth pin of connector CN1B is input to the A1 terminal of the buffer circuit 402, output from the Y1 terminal, and supplied to the fourth pin of connector CN2B.
The serial data signal S_IN_DATA input from the downstream side to the sixth pin of the connector CN2B is input to the A5 terminal of the buffer circuit 402, output from the Y5 terminal, and supplied to the sixth pin of the connector CN1B.

The buffer circuit 402 also has a third pin (A2 terminal), a fifth pin (A4 terminal), a seventh pin (A6 terminal), an eighth pin (A7 terminal), a ninth pin (A8 terminal), and a tenth pin ( GND terminal) and the 19th pin (G￣ terminal) are connected to the ground. The 11th pin (Y8 terminal), 12th pin (Y7 terminal), 13th pin (Y6 terminal), 15th pin (Y4 terminal), and 17th pin (Y2 terminal) are open.

The buffer circuit 403 performs signal compensation for clear signals CLR_L, CLR_M, clock signals CLK_L, CLK_M, data signal DATA_L, data signal DATA_M, the 15th pin performs signal compensation for the enable signal ENABLE_L, and the 16th pin performs signal compensation for the enable signal ENABLE_M.
Each of these signals inputted from the 9th pin to the 16th pin of the connector CN1B is inputted to one of the A1 terminals to the A8 terminals of the buffer circuit 402, and outputted from the Y1 terminal to Y8 terminal to the 1st pin of the connector CN2B. It is supplied to pins 9 to 16.
Further, in the buffer circuit 403, the 10th pin (GND terminal) and the 19th pin (G terminal) are connected to the ground.

As described above, the inner frame LED relay board 400 has the following configuration.
- The clock signal S_IN_CLK and the load signal S_IN_LOAD supplied from the production control board 30 (frame LED relay board 840) to the connector CN1B are compensated by the buffer circuit 402 and transmitted to the downstream side by the connector CN2B.
- The serial data signal S_IN_DATA supplied from the downstream front frame LED connection board 500 to the connector CN2B is signal-compensated by the buffer circuit 402 and transmitted to the upstream side by the connector CN1B.
- Clear signals CLR_L, CLR_M, clock signals CLK_L, CLK_M, data signals DATA_L, DATA_M, and enable signals ENABLE_L, ENABLE_M supplied from the production control board 30 (frame LED relay board 840) to the connector CN1B are compensated by the buffer circuit 403. Then, it is transmitted to the downstream side via connector CN2B.

・Relay the audio signal to the speaker and send it directly to the downstream board or speaker unit.
- Power supply voltage is not supplied from the connector CN1B (transmission line H7) connected to the production control board 30 side (frame LED relay board 840).
- 12V DC voltage (DC12V) is received from the power supply board 300 through the connector CN4B, and the 12V DC voltage (DC12VB) is supplied to the downstream side via the fuse F1B.
- Using 12V DC voltage (DC12V), generate 5V DC voltage (DC5VB) for use in the inner frame LED relay board 400 and the downstream side, and use it as an operating power source for the buffer circuits 402 and 403 and supply it to the downstream side.

In addition to those mentioned above, in the inner frame LED relay board 400, as shown in FIGS. 13 and 14, resistors R1B to R26B, resistors by chip resistors RA1B and RA2B, and capacitors C1B to C17B are connected at required locations. .
For example, for the clock signal S_IN_CLK, load signal S_IN_LOAD, clear signals CLR_L, CLR_M, clock signals CLK_L, CLK_M, data signals DATA_L, DATA_M, enable signals ENABLE_L, ENABLE_M, resistors R25B, R26B, R8B are connected to the input side (connector CN1B side). R9B, R10B, R11B, R12B, R13B, R14B, and R15B are inserted as damping resistors. Furthermore, resistors R3B and R2B and chip resistors RA1B and RA2B are inserted as damping resistors on the output side (connector CN2B side).
In this case, if the wiring distance between the connector and the damping resistor is LA, and the wiring distance between the damping resistor and the buffer circuits 402 and 403 is LB,
LA<LB
The relationship is In other words, the damping resistor is arranged closer to the connector (CN1B or CN2B) than the buffer circuits 402, 403. This improves signal noise reduction performance.

[5.3 Front frame LED connection board 500]

The front frame LED connection board 500 will be explained using FIGS. 15, 16, 17, 18, 19, and 20. These figures separately show the circuit configuration provided on the front frame LED connection board 500.

The front frame LED connection board 500 has connectors CN2C, CN5C, CN6C, and CN8C shown in FIG. 15, connectors CN1C and CN4C shown in FIG. 16, connectors CN3C shown in FIG. 17, connectors CN7C and CN9C shown in FIG. 18, and connector CN10C shown in FIG. will be installed.

The transmission line end of the transmission line H8 that connects the connector CN2C of FIG. 15 with the connector CN2B of the inner frame LED relay board 400 of FIG. 13 is connected.
Therefore, this connector CN2C has a configuration of 30 terminals from the 1st pin to the 30th pin as indicated by the numbers "1" to "30", and the terminal assignments are the same as those of the connector CN2B described above. Conductor points P1 and P2 on the housing of connector CN2C are also connected to ground. This is due to the mounting strength of the connector, and the conductor points P1 and P2 are not connected to the ground terminal inside the connector.
Although not mentioned again, conductor points P1 and P2 in the housings of connectors CN1C, CN3C, CN4C, CN7C, CN8C, CN9C, and CN10C, which will be described later, are also connected to the ground for the purpose of mounting strength.

Connector CN5C is a connector for connection to the middle right speaker, which is one of the speakers 46. The 1st and 2nd pins of this connector CN3B, numbered "1" and 2, are assigned to the + and - terminals of the middle right speaker, and are connected to the 20th and 22nd pins of the connector CN2C. .

Connector CN6C is a connector for connection to the middle left speaker, which is one of the speakers 46. The 1st and 2nd pins of this connector CN6B, numbered "1" and 2, are assigned to the + and - terminals of the middle left speaker, and are connected to the 24th and 26th pins of the connector CN2C. .

Connector CN8C is a connector for connection with the upper right speaker and the upper left speaker, which are one of the speakers 46. The first and second pins numbered "1" and "2" of this connector CN6B are assigned to the + terminal and - terminal of the upper right speaker, and are connected to the 19th pin and 21st pin of the connector CN2C. Further, the third and fourth pins numbered "3" and "4" are assigned to the + and - terminals of the upper left speaker, and are connected to the 23rd and 25th pins of the connector CN2C.

Connector CN1C in FIG. 16 is a connector connected to an LED board not shown in FIG. 11.
The connector CN4C is also connected to an LED board inside the handle (not shown).

The connector CN1C has 13 terminals from the 1st pin to the 13th pin as indicated by numbers "1" to "13".
The 1st and 6th pins are ground terminals, the 2nd pin is a clock signal CLK terminal, the 3rd pin is a 5V DC voltage (DC5V) terminal, the 4th pin is a data signal DATA terminal, and the 5th pin is a reset signal RESET The 7th pin is a 12V DC voltage (DC12V) terminal.

The 8th to 13th pins are R, G, and B LED light emission drive currents (17-R6, 17- G6, 17-B6, 17-R7, 17-G7, 17B-7) input terminal.
This LED light emitting drive current (17-R6, 17-G6, 17-B6, 17-R7, 17-G7, 17B-7) is directly passed from the 2nd pin to the 7th pin of the connector CN4C to another device (not shown). is supplied to the LED board inside the handle on the downstream side.

That is, on the downstream side of the front frame LED connection board 500, an LED board (not shown) and an LED board in the handle are connected by connectors CN1C and CN4C, and an LED driver is mounted on the LED board. The LED driver operates using the clock signal CLK, 5V DC voltage (DC5V), data signal DATA, reset signal RESET terminal, and 12V DC voltage (DC12V) from the connector CN1C, and drives the LED on the LED board. At the same time, LED light emission drive currents (17-R6, 17-G6, 17-B6, 17-R7, 17-G7, 17B-7) for the LEDs on the LED board inside the handle are also generated. The LED light emitting drive current (17-R6, 17-G6, 17-B6, 17-R7, 17-G7, 17B-7) is supplied to the LED of the LED board inside the handle via the front frame LED connection board 500. That will happen.

In addition, each of the pins 2 to 7 of connector CN4C should be Zener diodes D8C to D15C are connected as a protection circuit.
Further, a 12V DC voltage (DC12VB) is applied to the first pin of the connector CN4C, and a power supply voltage is supplied to the LED board inside the handle (not shown).

Such a configuration is used to connect two LED boards downstream of the front frame LED connection board 500 and provide an LED driver only on one of them.
That is, the front frame LED connection board 500 outputs a clock signal CLK, a 5V DC voltage (DC5V), a data signal DATA, a reset signal RESET, and a 12V DC voltage (DC12V) for the operation of the LED driver. Then, the LED light emission drive current from the LED driver is returned and relayed to be sent to the other LED board.

In this case, only one LED driver is required to drive the two downstream LED boards. In particular, when controlling light emission using a common LED drive control signal, it is sufficient to transmit the LED drive control signal to only one LED board, which facilitates simplification of the wiring configuration. That is, it is not necessary to transmit the clock signal CLK, 5V DC voltage (DC5V), data signal DATA, reset signal RESET, and 12V DC voltage (DC12V) to both LED boards.
In addition, by relaying the LED light emission drive current (17-R6, 17-G6, 17-B6, 17-R7, 17-G7, 17B-7), a harness that transmits these between two downstream LED boards can be created. No longer needed.

The connector CN3C in FIG. 17 is connected to the transmission line end of the transmission line H9 that connects with the relay board 550 on the downstream side.
This connector CN3C has 22 terminals from the 1st pin to the 22nd pin as indicated by numbers "1" to "22".

Five pins, the 1st pin, the 3rd pin, the 11th pin, the 13th pin, and the 18th pin, are used as ground terminals.
The second pin is a 5V DC voltage (DC5VB) terminal.
Three pins, the 5th pin, the 7th pin, and the 9th pin, are terminals for a 12V DC voltage (DC12VB).

The fourth pin is assigned as a serial data signal S_IN_DATAx, the sixth pin as a load signal S_IN_LOAD, and the eighth pin as a clock signal S_IN_CLK.

The 10th pin is an enable signal ENABLE_L, the 12th pin is a clear signal CLR_P, the 14th pin is a reset signal RESET_P, the 15th pin is a clock signal CLK_M, the 16th pin is a data signal DATA_P, the 17th pin is a reset signal RESET_M, the 19th The pins are assigned as data signal DATA_M, the 20th pin as drive general-purpose signal 1, the 21st pin as enable signal ENABLE_M, and the 22nd pin as drive general-purpose signal 2.

The connector CN7C in FIG. 18 is connected to a board (not shown) for detecting the cross key 15a, enter key 15b, volume button (not shown), light amount button, etc. This connector CN7C has a 9-terminal configuration from the 1st pin to the 9th pin indicated by "1" to "9", the 1st pin is the ground terminal, and each pin from the 2nd pin to the 9th pin has a cross key. Sense signals SENS0 to SENS7, which are detection signals for operations such as 15a, are input.
Note that the sense signals SENS0 to SENS7 from the second pin to the ninth pin are pulled up by a 5V DC voltage (DC5VB) via chip resistors RA3C and RA4C.

The connector CN9C is connected to a touch sensor (not shown) provided on the firing operation handle 15. This connector CN9C has a two-terminal configuration indicated by "1" and "2", the first pin receives the sense signal SENS14 from the touch sensor, and the second pin is used as a ground terminal.
Note that the sense signal SENS14 is pulled up by a 5V DC voltage (DC5VB) via a resistor R26C.

The transmission line end of the transmission line H15 connecting between the connector CN10C in FIG. 20 and the button LED connection board 640 in FIG. 11 is connected.
This connector CN10C has 20 terminals from the 1st pin to the 20th pin numbered "1" to "20".

Five pins, the second pin, the fourth pin, the 12th pin, the 13th pin, and the 19th pin, are used as ground terminals.
The 8th pin is a 5V DC voltage (DC5VB) terminal.
The sixth pin is a 12V DC voltage (DC12VB) terminal.
The fifth and seventh pins are terminals for a 12V motor drive voltage (MOT12V).

The 1st pin is the motor drive signal MOTφ/2, the 3rd pin is the motor drive signal MOTφ/1, the 9th pin is the motor drive signal MOTφ2, the 10th pin is the motor drive signal DCMOT3, and the 11th pin is the motor drive signal MOTφ1. Assigned as a terminal.

The 14th pin is assigned as a clear signal CLR_L, the 16th pin is assigned as a clock signal CLK_L, and the 18th pin is assigned as a data signal DATA_L.
The 15th pin, the 17th pin, and the 20th pin are terminals into which sense signals SENS8, SENS9, and SENS11, which are detection signals from the downstream side, are input.
Note that the sense signals SENS8, SENS9, and SENS11 are pulled up by a 5V DC voltage (DC5VB) via a chip resistor RA5C.

The power supply voltage at this front frame LED connection board 500 will be explained.
The front frame LED connection board 500 includes, as ICs, buffer circuits 501, 502, 503, 507, and 508, which are 8-circuit Schmitt trigger buffers similar to the buffer circuit 402 previously explained in FIG. 13, and triple buffer gates. Certain buffer circuits 504, 512, and 513 are installed.
As the power supply voltage for these, 5V DC voltage (DC5VB) supplied from the first pin of connector CN2C is used.

Furthermore, as ICs, parallel/serial (hereinafter referred to as "P/S") conversion circuits 505 and 506 shown in FIG. ) is used.

Also, the S/P conversion circuit 509 (LED driver) shown in Fig. 19 is installed as an IC, and the power supply voltage for this is 12V DC voltage (DC12VB) supplied from the 27th pin to the 30th pin of the connector CN2C. It will be done.

Furthermore, motor drivers 510 and 511 shown in FIG. 19 are mounted as ICs, and these use a 12V motor drive voltage (MOT12V) and a 12V direct current voltage (DC12VS) as power supply voltages.
The 12V motor drive voltage (MOT12V) is used as a power supply voltage for driving the motor, and the 12V direct current voltage (DC12VS) is used as a power supply voltage for motor drivers such as motor drivers 510 and 511.

The 12V motor drive voltage (MOT12V) is separated from the 12V direct current voltage (DC12VB). As shown in FIG. 15, a capacitor C11 is inserted between the 27th pin to the 30th pin of the connector CN2C and the ground, and the anode side of a Schottky barrier diode D18C is connected to the positive electrode side of the capacitor C11. There is. A resistor R27C, capacitors C12C and C13C, and a chip varistor 515 are connected in parallel between the cathode side of the Schottky barrier diode D18C and the ground. With this configuration, the 12V motor drive voltage (MOT12V) is separated as a power supply voltage protected from overvoltage.
That is, a power separation/protection circuit 520 is formed that separates the 12V motor drive voltage (MOT12V) from the 12V DC voltage (DC12VA).

The 12V DC voltage (DC12VS) is separated from the 12V DC voltage (DC12VB) using a power supply separation/protection circuit 521 shown in FIG. 19, which includes a diode D19C, a resistor R34C, and a capacitor C21C.

The flow of various signals in the front frame LED connection board 500 will be explained below.
Clear signals CLR_L, CLR_M, clock signals CLK_L, CLK_M, data signals DATA_L, DATA_M, general-purpose output port signal (general-purpose signal HANYOU), and enable signal ENABLE_M are transmitted from the inner frame LED relay board 400 to connector CN2C in FIG. It will be done.
Each of these signals is input to terminals A1 to A8 of the buffer circuit 501, and signal compensation is performed.
Note that the clear signals CLR_L and CLR_M supplied from the inner frame LED relay board 400 are shown as reset signals RESET_L and RESET_M in the front frame LED connection board 500.

The clock signal CLK_L, the data signal DATA_L, and the reset signal RESET_L are signal-compensated in the buffer circuit 501 and then supplied to the buffer circuit 504 in FIG. 16 via the chip resistor RA1C. After being buffered, the signal is output from the connector CN1C to an LED board (not shown).

Furthermore, these clock signal CLK_L, general-purpose signal HANAYOU, data signal DATA_L, and reset signal RESET_L, which have been signal-compensated by the buffer circuit 501 in FIG. 15, are sent to the A5 terminal, A6 terminal, A7 terminal, and A8 terminal of the buffer circuit 502 in FIG. supplied to The signal-compensated outputs of the Y5, Y6, Y7, and Y8 terminals of the buffer circuit 502 are relayed from the connector CN3C as a clock signal CLK_P, an enable signal ENABLE_L (from the general-purpose signal HANYOU), a data signal DATA_P, and a reset signal RESET_P. It is output to the board 550.

In other words, to the downstream side after the relay board 550, signals for LED control etc. outputted from the upstream inner frame LED relay board 400 are transmitted after being signal compensated by the buffer circuits 501 and 502.

Note that the clock signal CLK_P is a constant voltage/protection circuit made up of a Zener diode D5C and a resistor R19C, the enable signal ENABLE_L is a constant voltage/protection circuit made up of a Zener diode D4C and a resistor R15C, and the data signal DATA_P is a constant voltage/protection circuit made up of a Zener diode D6C and a resistor R20C. The protection circuit and reset signal RESET_P are outputted from the connector CN3C via constant voltage/protection circuits each including a Zener diode D7C and a resistor R21C.

Further, the clock signal CLK_L, data signal DATA_L, and reset signal RESET_L whose signals have been compensated by the buffer circuit 501 in FIG. 15 are supplied to the buffer circuit 512 in FIG. 20. After being amplified, the signals are output from the connector CN10C to the button LED connection board 640 as a clock signal CLK_L, a data signal DATA_L, and a clear signal CLR_L (reset signal RESET_L).

Therefore, on the downstream side after the button LED connection board 640, signals for LED control etc. output from the upstream inner frame LED relay board 400 are transmitted after being signal compensated by the buffer circuits 501 and 512. Become.

Further, the clock signal CLK_L, data signal DATA_L, and general-purpose signal HANYOU_L whose signals have been compensated by the buffer circuit 501 in FIG. 15 are supplied to the serial/parallel (S/P) conversion circuit 509 in FIG. This S/P conversion circuit 509 is configured using a chip as an LED driver. The LED driver is a device that outputs a light emitting drive current according to a clock signal CLK_L and a data signal DATA_L, and in this case, it is mainly used for serial/parallel conversion for driving a motor. In other words, the LED driver chip is used as part of the motor drive means.

The S/P conversion circuit 509 configured by the LED driver chip has output terminals LEDR1, LEDG1, LEDB1...LEDR8, LEDG8, LEDB8 for light emission drive current, and can output drive current for 24 systems. In this case, seven output terminals are used: LEDR1, LEDG1, LEDB1, LEDR2, LEDG2, LEDB2, and LEDR3. As shown, the other output terminals are connected to ground.
And the output of output terminals LEDR1, LEDG1, LEDB1, LEDR2, LEDG2, LEDB2, LEDR3 (current 23-R1, 23-G1, 23-B1, 23-R2, 23-G2, 23-B2, 23-R3) is After being buffered by the buffer circuit 508, the signals are supplied to the input terminals IN1, IN2, IN3, and IN4 of the motor driver 510, and to the input terminals IN1, IN3, and IN4 of the motor driver 511.

Note that the output terminals LEDR1, LEDG1, LEDB1, LEDR2, LEDG2, LEDB2, LEDR3 are used to flow current 23-R1, 23-G1, 23-B1, 23-R2, 23-G2, 23-B2, 23-R3. is connected to a 5V DC voltage (DC5VB) via chip resistors RA6C and RA7C.

The motor driver 510 outputs motor drive signals MOT1-1, MOT1-/1, MOT1-2, MOT1-/2 from output terminals OUT1, OUT2, OUT3, and OUT4 based on the signals of input terminals IN1, IN2, IN3, and IN4. Output.
The motor driver 511 outputs motor drive signals MOT3-1, MOT3-3, and MOT3-4 from output terminals OUT1, OUT3, and OUT4 based on signals at input terminals IN1, IN3, and IN4.

The motor drive signals MOT1-1, MOT1-/1, MOT1-2, MOT1-/2, MOT3-1 are supplied to the connector CN10 in FIG. 20, and the motor drive signals MOTφ1, MOTφ/1, MOTφ2, It is output to the button LED connection board 640 as MOTφ/2 and DCMOT3.
The motor drive signals MOT3-3 and MOT3-4 are supplied to the connector CN3C in FIG. 17 and output to the relay board 550 as the above-mentioned general-purpose drive signal 1 and general-purpose drive signal 2.

The above is a circuit system in the front frame LED connection board 500 that uses the clock signal CLK_L-, the data signal DATA_L-, and the general-purpose signal HANYOU_L- to generate motor drive signals for the downstream button LED connection board 640 and the subsequent parts.

The clock signal CLK_M, data signal DATA_M, enable signal ENABLE_M, and clear signal CLR_M (reset signal RESET_M) input from the connector CN2C in FIG. The signal is supplied to the A1 terminal, A3 terminal, A5 terminal, and A7 terminal of the buffer circuit 503. The signal-compensated outputs of the Y1, Y3, Y5, and Y7 terminals of the buffer circuit 503 are output from the connector CN3C to the relay board 550 as a clock signal CLK_M, a data signal DATA_M, an enable signal ENABLE_M, and a reset signal RESET_M. .

Therefore, to the downstream side after the relay board 550, the signal for motor control from the upstream inner frame LED relay board 400 is transmitted after signal compensation by the buffer circuits 501 and 503.

Note that the clock signal CLK_M is a constant voltage/protection circuit made up of a Zener diode D12C and a resistor R22C, the enable signal ENABLE_M is a constant voltage/protection circuit made up of a Zener diode D16C and a resistor R24C, and the data signal DATA_M is a constant voltage/protection circuit made up of a Zener diode D14C and a resistor R23C. The protection circuit and reset signal RESET_M are output from the connector CN3C via constant voltage/protection circuits each including a Zener diode D17C and a resistor R25C.

The clock signal S_IN_CLK and load signal S_IN_LOAD input from the connector CN2C in FIG. 15 are supplied to the A3 terminal and A2 terminal of the buffer circuit 502 in FIG. 17. The signal-compensated outputs of the Y3 and Y2 terminals of the buffer circuit 502 are output from the connector CN3C to the relay board 550 as a clock signal S_IN_CLK and a load signal S_IN_LOAD.
Therefore, signals for serial data transmission are transmitted after being compensated by the buffer circuits 501 and 502 downstream after the relay board 550.

Note that the clock signal S_IN_CLK is output from the connector CN3C through a constant voltage/protection circuit including a Zener diode D3C and a resistor R11C, and the load signal S_IN_LOAD is output from a constant voltage/protection circuit including a Zener diode D2C and a resistor R9C.

The serial data signal S_IN_DATAx inputted from the relay board 550 on the downstream side through the connector CN3C in FIG. 17 is supplied to the A1 terminal of the buffer circuit 502. The signal-compensated output of the Y1 terminal of the buffer circuit 502 is input to the SI terminal (serial input terminal) of the P/S conversion circuit 505 in FIG.

The P/S conversion circuit 505 and the P/S conversion circuit 506 in the figure are CMOS 8-bit shift registers, have 8-bit parallel input/output, serial input, and serial output, and perform parallel-to-serial conversion of data. .
When the P/S CONT terminal = L, the 8 terminals from Q/D1 to Q/D8 become parallel outputs, and the data on the SI terminal is stored in each register at the rising edge of the input waveform on the CK terminal, and the Q/D1 terminal ～Output to Q/D8 terminal. Furthermore, by setting the CLR/LOAD terminal to L, each register is reset asynchronously to the input to the CK terminal.
When the P/S CONT terminal = H, the 8 terminals from Q/D1 to Q/D8 become parallel inputs, and when the CLR/LOAD terminal = L, input from the Q/D1 to Q/D8 terminals is asynchronous to the CK terminal input. Data is stored in each register.

In this example, the P/S conversion circuits 505 and 506 set the P/S CONT terminal = H by applying 5V DC voltage (DC5VB) to the P/S CONT terminal, and the Q/D1 terminal to Q The 8 terminals of the /D8 terminal are used as parallel inputs.
Further, the clock signal S_IN_CLK and the load signal S_IN_LOAD inputted from the connector CN2C in FIG. That is, the clock signal S_IN_CLK becomes an input to the CK terminal, and the load signal S_IN_LOAD becomes an input to the CLR/LOAD terminal.

For the Q/D1 to Q/D8 terminals, which are the parallel input terminals of the P/S conversion circuit 505, the Q/D1 terminal receives a sense signal SENS8, the Q/D2 terminal receives a sense signal SENS9, and the Q/D4 terminal receives a sense signal SENS11. , sense signal SENS14 is input to the Q/D7 terminal.
Q/D3, Q/D5, Q/D6, and Q/D8 terminals are connected to ground. That is, each input becomes "0" (L level).
Sense signals SENS8, SENS9, and SENS11 are input from the downstream button LED connection board 640 to the connector CN10C in FIG. 20, and are used to detect the switch sensor that detects button operations and the rotational position and origin position of the movable body inside the button. This is the detection signal of the sensor.
The sense signal SENS14 is a touch sensor detection signal input from the connector CN9C in FIG.

The P/S conversion circuit 505 converts the serial data signal S_IN_DATAx and the sense signals SENS8, SENS9, SENS11, and SENS14 input as described above into serial data and outputs the serial data signal SDT1 from the Q8C terminal. This serial data signal SDT1 is input to the SI terminal of the P/S conversion circuit 506.

For the Q/D1 to Q/D8 terminals, which are the parallel input terminals of the P/S conversion circuit 506, the Q/D1 terminal receives the sense signal SENS0, the Q/D2 terminal receives the sense signal SENS1, and the Q/D3 terminal receives the sense signal SENS2. , a sense signal SENS3 is input to the Q/D4 terminal, a sense signal SENS4 is input to the Q/D5 terminal, a sense signal SENS5 is input to the Q/D6 terminal, a sense signal SENS6 is input to the Q/D7 terminal, and a sense signal SENS7 is input to the Q/D8 terminal.
These sense signals SENS0 to SENS7 are detection signals for the cross key 15a, etc., which are input to the connector CN7C in FIG.
The sense signals SENS0 to SENS7 from the connector CN7C are signal compensated by the buffer circuit 507 and then input to the above-mentioned terminals of the P/S conversion circuit 506.

As described above, the P/S conversion circuit 506 collectively converts the serial data signal SDT1 from the P/S conversion circuit 505 inputted to the SI terminal and the sense signals SENS0 to SENS7 into serial data, and outputs the Q8 as the serial data signal SDT2. Output from the terminal. This serial data signal SDT2 is input to the buffer circuit 513 via a filter including a resistor R35C and a capacitor C27C, and is buffered. This output is transmitted to the upstream side from the connector CN2C in FIG. 15 as the serial data signal S_IN_DATA from the front frame LED connection board 500.

As described above, the front frame LED connection board 500 has the following configuration.
FIG. 21 shows clock signals CLK_L, CLK_M, clear signals CLR_L, CLR_M (reset signals RESET_L, RESET_M), data signals DATA_L, DATA_M, general-purpose signals HANYOU, and enable signals supplied from the upstream inner frame LED relay board 400 to the connector CN2C. The flow regarding ENABLE_M is summarized.

・Clock signal CLK_L, clear signal CLR_L (reset signal RESET_L), data signal DATA_L, and general-purpose signal HANYOU are sent to connector CN3C via buffer circuits 501 and 502 as clock signal CLK_P, reset signal RESET_P, data signal DATA_P, and enable signal ENABLE_L. Sent downstream.
- The clock signal CLK_L, the clear signal CLR_L (reset signal RESET_L), and the data signal DATA_L are transmitted to the downstream side by the connector CN1C via the buffer circuit 504 as the clock signal CLK, the reset signal RESET, and the data signal DATA.
- The clock signal CLK_L, the clear signal CLR_L (reset signal RESET_L), and the data signal DATA_L are transmitted via the buffer circuit 512 to the downstream side by the connector CN10C as the clock signal CLK_L, the clear signal CLR_L, and the data signal DATA_L.
- The clock signal CLK_L, the data signal DATA_L, and the general-purpose signal HANYOU are supplied to the S/P conversion circuit 509 and used to generate a motor drive current.

・Clock signal CLK_M, clear signal CLR_M (reset signal RESET_M), data signal DATA_M, and enable signal ENABLE_M are sent to connector CN3C via buffer circuits 501 and 503 as clock signal CLK_M, reset signal RESET_M, data signal DATA_M, and enable signal ENABLE_M. Sent downstream.

- Motor drive signals MOTφ1, MOTφ/1, MOTφ2, MOTφ/2, and DCMOT3 are generated by the S/P conversion circuit 509, buffer circuit 508, and motor drivers 510 and 511, which are configured as motor drive means, and are sent downstream from the connector CN10C. sent to.

Further, FIG. 22 summarizes the flow of the serial data signal S_IN_DATA, clock signal S_IN_CLK, load signal S_IN_LOAD, and sense signals SENS0 to SENS7, SENS8, SENS9, SENS11, and SENS14.

- The clock signal S_IN_CLK and the load signal S_IN_LOAD are transmitted from the connector CN3C to the downstream side via the buffer circuit 502.
- The clock signal S_IN_CLK and the load signal S_IN_LOAD are supplied to the P/S conversion circuits 505 and 506 via the buffer circuit 513 and used for parallel/serial conversion processing.

・The serial data signal S_IN_DATAx inputted to the connector CN3C from the downstream side is inputted to the P/S conversion circuit 505 via the buffer circuit 502, and is combined into sense signals SENS8, SENS9, SENS11, and SENS14 in the P/S conversion circuit 505. The signal is converted into serial data and input to the P/S conversion circuit 506 as the serial data signal SDT1. Furthermore, sense signals SENS0 to SENS7 inputted from the downstream side to the connector CN7C are inputted to the P/S conversion circuit 506 via the buffer circuit 507. In the P/S conversion circuit 506, the serial data signal SDT1 from the P/S conversion circuit 505 and the sense signals SENS0 to SENS7 are combined into serial data, and a serial data signal SDT2 is output. This serial data signal SDT2 is transmitted from the connector CN2C to the upstream side via the buffer circuit 513 as the serial data signal S_IN_DATA from the front frame LED connection board 500.

Further, the front frame LED connection board 500 further has the following configuration.
-Relays the audio signal to the speaker and sends it to the speaker unit.
- Receives 12V DC voltage (DC12VB) and 5V DC voltage (DC5VB) through connector CN2C and uses it as an operating power source.
- The 12V motor drive voltage (MOT12V) and 12V DC voltage (DC12VS) used for motor drive signal generation are separated from the 12V DC voltage (DC12VB). Separating the power supplies according to the application, such as 12V DC voltage (DC12VB) for LED and LED driver, 12V motor drive voltage (MOT12V) for motor drive, and 12V DC voltage (DC12VS) for motor driver, reduces the adverse effects of noise. is prevented.
- 12V DC voltage (DC12VB) and 5V DC voltage (DC5VB) are supplied to the downstream side as operating power supply voltages.

In addition, in the front frame LED connection board 500, as shown in FIGS. 15 to 20, including those mentioned above, resistors R1C, R2C, etc., resistors by chip resistors RA1C, RA2C, etc., and capacitor C1C are installed at required locations. , C2C . . . , diodes (including Zener diodes and Schottky barrier diodes) D1C, D2C .
As a damping resistor for signal lines such as clear signals CLR_L, CLR_M, clock signals CLK_L, CLK_M, data signals DATA_L, DATA_M, general-purpose output port signals (general-purpose signal HANYOU), and enable signal ENABLE_M, install a resistor on the connector CN2C side in Figure 15. R8C, R10C, R12C, R13C, R14C, R16C, R17C, and R18C are inserted, and chip resistors RA1C and RA2C are also inserted. In other words, the waveform is shaped by inserting a damping resistor near the connector CN2C and before the signal branch.
Further, as shown in the figure, taps TP1C to TP14C are provided and used for connection to required locations.
Although not shown, a capacitor for reducing power supply noise is appropriately placed between the 5V DC or 12V DC power supply line and the ground.

[5.4 Relay board 550]

The configuration of the relay board 550 is shown in FIG. Connectors CN1D and CN2D are mounted on the relay board 550.

The transmission line end of the transmission line H9 connecting between the connector CN1D and the connector CN3C of the front frame LED connection board 500 in FIG. 17 is connected.
Therefore, this connector CN1D has 22 terminals from the 1st pin to the 22nd pin as indicated by the numbers "1" to "22", and the terminal assignment is the same as that of the connector CN3C described above. Conductor points P1 and P2 on the housing of connector CN1D are also connected to ground for mounting strength.

The transmission line end of the transmission line H10 that connects the downstream side unit upper right LED board 600 is connected to the connector CN2D.
This connector CN2D has 20 terminals from the 1st pin to the 20th pin as indicated by numbers "1" to "20".

Four pins, the 3rd pin, the 9th pin, the 11th pin, and the 16th pin, are used as ground terminals.
The first pin is a 5V DC voltage (DC5VB) terminal.
Two pins, the fifth pin and the seventh pin, are terminals for a 12V direct current voltage (DC12VB).

The second pin is assigned as a serial data signal S_IN_DATAx, the fourth pin is assigned as a load signal S_IN_LOAD, and the sixth pin is assigned as a clock signal S_IN_CLK.

8th pin is enable signal ENABLE_L, 10th pin is clock signal CLK_P, 12th pin is reset signal RESET_P, 13th pin is clock signal CLK_M, 14th pin is data signal DATA_P, 15th pin is reset signal RESET_M, 17th pin The pins are assigned as data signal DATA_M, the 18th pin as drive general-purpose signal 1, the 19th pin as enable signal ENABLE_M, and the 20th pin as drive general-purpose signal 2.

In this relay board 550, the 12V DC voltage (DC12VB) assigned to the three terminals of the 5th pin, the 7th pin, and the 9th pin of the connector CN1D is applied to the 2 terminals of the 5th pin and the 7th pin on the connector CN2D side. The data are aggregated and transferred to the downstream side.
In addition, on the connector CN1D, the 5 terminals of the 1st pin, 3rd pin, 11th pin, 13th pin, and 18th pin are used as ground terminals, and on the connector CN2D side, the 3rd pin, 9th pin, 11th pin, It has four terminals, the 16th pin.
This reduces the number of terminals of the connector CN2D to the downstream side.
Furthermore, the connector CN1D and the connector CN2D are of different types. Connector CN2D has a larger rated current per pin, and therefore the number of power supply terminals and ground terminals of connector CN2D can be reduced.
Furthermore, the connector CN2D is easier to insert and remove than the connector CN1D, and has thicker terminals and a larger housing.

[5.5 Side unit upper right LED board 600]

The side unit upper right LED board 600 will be explained using FIGS. 24, 25, 26, 27, 28, and 29. These figures separately show the circuit configuration provided on the upper right LED board 600 of the side unit.

The side unit upper right LED board 600 is equipped with connectors CN1E shown in FIG. 24, connectors CN7E shown in FIG. 25, connectors CN2E and CN3E shown in FIG. 26, and connectors CN4E, CN5E, and CN6E shown in FIG. 28.

The transmission line end of the transmission line H10 connecting between the connector CN1E of FIG. 24 and the connector CN2D of the relay board 550 of FIG. 23 is connected.
Therefore, this connector CN1E has 20 terminals from the 1st pin to the 20th pin as indicated by the numbers "1" to "20", and the terminal assignment is the same as that of the connector CN2D described above.

The connector CN7E in FIG. 25 is connected to the sensor in the side unit device 101 shown in FIG. 10, and the sense signal SENS2X is input to the third pin. This sensor 101S is, for example, a sensor that detects a player's operation of the side unit device 101. The sense signal SENS2X of the sensor 101S is pulled up by a 5V direct current voltage (DC5V) via a resistor R64E.
A 12V DC voltage (DC12VB), which is the power supply voltage on the sensor 101S side of the side unit device 101, is applied to the first pin. The second pin is used as a ground terminal.

The connector CN2E in FIG. 26 is a six-terminal connector to which the transmission line end of the transmission line H12 connecting with the side unit upper LED board 630 on the downstream side is connected.
The 1st to 6th pins of this connector CN2E are assigned as a ground terminal, a clock signal CLK terminal, a data signal DATA terminal, a reset signal RESET terminal, a ground terminal, and a 12V DC voltage (DC12VB) terminal. .

The transmission line end of the transmission line H11 that connects the downstream side unit lower right LED board 620 is connected to the connector CN3E.
This connector CN3E has 16 terminals from the 1st pin to the 16th pin as indicated by numbers "1" to "16".

The first pin is a 5V DC voltage (DC5VB) terminal.
The 8th pin and the 13th pin are used as ground terminals.
The 15th pin is a 12V motor drive voltage (MOT12V) terminal. Note that a Zener diode D11E is connected between the 15th pin and the ground as a protection circuit.

The 2nd pin is a clock signal CLK, the 3rd pin is a sense signal SENS1X, the 4th pin is a data signal DATA, the 5th pin is a sense signal SENS_A, the 6th pin is a reset signal RESET, the 7th pin is a sense signal SENS_B, the 9th pin is a sense signal SENS_B The pins are assigned as each terminal of the sense signal SENS_C.
Note that, as shown in FIG. 25, the sense signal SENS1X is pulled up by a 5V direct current voltage (DC5V) via a resistor R13E.
Furthermore, the sense signal SENS_A, the sense signal SENS_B, and the sense signal SENS_C are also pulled up by a 5V DC voltage (DC5V) via resistors R29E, R27E, and R21E, respectively.

In addition, the connector CN3E in Figure 26 has the 10th pin as the motor drive signal MOT1-/2, the 12th pin as the motor drive signal MOT1-/1, the 14th pin as the motor drive signal MOT1-2, and the 16th pin as the motor drive signal. Assigned as each terminal of MOT1-1.
Note that Zener diodes D10E, D12E, D13E, and D14E are connected as protection circuits between the 10th pin, 12th pin, 14th pin, and 16th pin and the ground, respectively.

Connector CN4E in FIG. 28 is connected to the side unit upper right movable motor 104 (see FIG. 10). The first pin of this connector CN4E is a terminal for a 12V motor drive voltage (MOT12V), and the second pin is a terminal for a vibration control signal L_VIB.

Connector CN5E is connected to the side unit upper right movable solenoid 105 (see FIG. 10). The first pin of this connector CN5E is a terminal for a 12V motor drive voltage (MOT12V), and the second pin is a terminal for a solenoid control signal L_SOL_01.

Connector CN6E is connected to the blower 106 (see FIG. 10) on the side unit. The first pin of this connector CN6E is a terminal for a 12V motor drive voltage (MOT12V), and the second pin is a terminal for a blower control signal L_BRO.

Note that the conductor points P1 and P2 on the housings of the connectors CN2E, CN3E, CN4E, CN5E, CN6E, and CN7E are connected to the ground for the purpose of mounting strength.

The power supply voltage at the upper right LED board 600 of the side unit will be explained.
A buffer circuit 601 in FIG. 25, a buffer circuit 604 in FIG. 26, and a buffer circuit 607 in FIG. 28 are mounted as ICs on the upper right LED board 600 of the side unit. These are 8-circuit Schmitt trigger buffers similar to the buffer circuit 402 previously described with reference to FIG.
A 5V direct current voltage (DC5V) is used as the power supply voltage for these. The 5V DC voltage (DC5V) is the voltage on the positive electrode side of the capacitor C1E via the fuse F1E with respect to the 5V DC voltage (DC5VB) supplied from the first pin of the connector CN1E in FIG.

Furthermore, the P/S conversion circuits 602 and 603 shown in FIG. 25 are mounted as ICs, and the power supply voltage for these is also set to 5V direct current voltage (DC5V). P/S conversion circuits 602 and 603 are ICs similar to P/S conversion circuit 505 in FIG.

Furthermore, as ICs, an LED driver 605 shown in FIG. 27 and an S/P conversion circuit (LED driver) 606 shown in FIG. A direct current voltage (DC12VB) is used.
The 12V DC voltage (DC12VB) in this case is taken out from the fifth and seventh pins of the connector CN1E in FIG. 24 as a voltage on the positive side of the capacitor C2E via the fuse F2E.

Furthermore, motor drivers 608 and 609 shown in FIG. 28 are mounted as ICs, and these use a 12V motor drive voltage (MOT12V) and a 12V direct current voltage (DC12VS) as power supply voltages.

The 12V motor drive voltage (MOT12V) is separated from the 12V direct current voltage (DC12VB).
As shown in FIG. 29, the anode side of the Schottky barrier diode D8E is connected to the 12V DC voltage (DC12VB) line. A resistor R23E, capacitors C10E and C11E, and a chip varistor 611 are connected in parallel between the cathode side of the Schottky barrier diode D8E and the ground. With this configuration, the 12V motor drive voltage (MOT12V) is separated as a power supply voltage protected from overvoltage.
As shown in the figure, the 12V DC voltage (DC12VS) is separated from the 12V DC voltage (DC12VB) using a circuit including a diode D7E, a resistor R17E, and a capacitor C8E.

The flow of various signals in the upper right LED board 600 of the side unit will be explained below.
The load signal S_IN_LOAD, clock signal S_IN_CLK, enable signal ENABLE_L (reset signal RESET_M), clock signal CLK_P, reset signal RESET_P, and data signal DATA_P are input from the relay board 550 to the connector CN1E in FIG. 24, and these signals are damped. The signal is supplied to the buffer circuit 601 in FIG. 25 via resistors R66E, R9E, R11E, and R12E, and signal compensation is performed.
As shown in FIG. 24, the signal paths for these signals include a resistor R3E and a Zener diode D2E, a resistor R6E and a Zener diode D3E, a resistor R66E and a Zener diode D15E, a resistor R9E and a Zener diode D6E, and a resistor R11E and a Zener diode D5E. , a protection circuit including a resistor R12E and a Zener diode D15E is provided.

Clock signal CLK_P, data signal DATA_P, and reset signal RESET_P are signal-compensated in buffer circuit 601, and then output as clock signal CLK_A, data signal DATA_A, and reset signal RESET_A, and input to buffer circuit 604 in FIG. 26. In this case, the clock signal CLK_A is input to the A1 and A5 terminals, the data signal DATA_A is input to the A2 and A6 terminals, and the reset signal RESET_A is input to the A3 and A7 terminals.
The buffered signals output from the Y1, Y2, and Y3 terminals are output as a clock signal CLK, a data signal DATA, and a reset signal RESET from the connector CN2E via damping resistors R18E, R19E, and R20E.
Further, the buffered signals outputted from the Y5, Y6, and Y7 terminals are outputted as a clock signal CLK, a data signal DATA, and a reset signal RESET from the connector CN3E via damping resistors R24E, R25E, and R26E.

That is, the clock signal CLK_A, data signal DATA_A, and reset signal RESET_A shown in FIG. 26 are each branched into two systems before being input to the buffer circuit 604, and each is buffered. Then, they are output as a clock signal CLK, a data signal DATA, and a reset signal RESET to separate boards from connectors CN2E and CN3E, respectively. Therefore, the buffer circuit 604 performs buffer processing while branching into two systems, and appropriate buffer processing can be performed after each branch.
Furthermore, the clock signal CLK, data signal DATA, and reset signal RESET output from connectors CN2E and CN3E in this way are originally the clock signal CLK_P, data signal DATA_P, and reset signal RESET_P input from connector CN1E in FIG. . These are buffered by the buffer circuit 601 in FIG. 25 as described above, and then output as the clock signal CLK_A, data signal DATA_A, and reset signal RESET_A, and are branched into two systems at the stage of the buffer circuit 604 in FIG. 26. . In other words, by performing buffer processing before branching, the attenuation in the transmission path up to that point is compensated for before branching. A stable signal supply is achieved when a common signal is distributed to two boards.

The clock signal CLK_A, data signal DATA_A, and reset signal RESET_A output from the buffer circuit 601 in FIG. 25 are also supplied to the LED driver 605 in FIG. 27.
The LED driver 605 outputs a light emission drive current according to the clock signal CLK_A, the data signal DATA_A, and the reset signal RESET_A.
The LED driver 605 has output terminals LEDR1, LEDG1, LEDB1...LEDR8, LEDG8, LEDB8 for light emission drive current, and can output drive current for 24 systems, but in this case, the output terminals LEDR1, LEDG1, It uses 14 terminals: LEDB1, LEDR2, LEDG2, LEDB2, LEDR3, LEDG3, LEDB3, LEDR4, LEDG4, LEDB4, LEDR5, LEDG5. As shown, the other output terminals are connected to ground.

The output terminals LEDR1, LEDG1, LEDB1, LEDR2, LEDG2, LEDB2, LEDR3, LEDG3, LEDB3, LEDR4, LEDG4, LEDB4, LEDR5, and LEDG5 are connected to each of the 14 LED circuits formed as the light emitting section 612, Flow the light emission drive current (25-R1, 25-G1, 25-B1...25-R5, 25-G5, 25-B5).
As shown in the figure, each system of LED circuits of the light emitting section 612 is composed of two or three LEDs (LED1, LED2, . . . ) connected in series and a resistance element. The LED circuits of each system are connected in parallel, and a 12V DC voltage (DC12VB) is applied to each anode side.

In this configuration, the clock signal CLK_P, data signal DATA_P, and reset signal RESET_P input from the connector CN1E in FIG. 24 are buffered by the buffer circuit 601 in FIG. 25 and then branched. The buffered clock signal CLK_A, data signal DATA_A, and reset signal RESET_A are supplied to the LED driver 605 in FIG. 27 as one of the branches. The other branch is supplied to the buffer circuit 604 in FIG. 26, further branched, and after buffer processing is sent to the downstream board from connectors CN2E and CN3E.
In this case, by buffering the signal for light emission drive control in the buffer circuit 601 and then branching it for transmission to the LED driver and downstream board, stable transmission can be achieved and the buffer circuit configuration can be made more efficient. It has become

Further, the clock signal CLK_A, data signal DATA_A, and reset signal RESET_M output from the buffer circuit 601 in FIG. 25 are supplied to the S/P conversion circuit 606 in FIG. 28.
This S/P conversion circuit 606 is configured using a chip as an LED driver. The LED driver is a device that outputs a light emitting drive current according to a clock signal CLK_L and a data signal DATA_L, and in this case, it is mainly used for serial/parallel conversion for driving a motor. In other words, the LED driver chip is used as part of the motor drive means.

The S/P conversion circuit 606 composed of an LED driver chip is a device that outputs a light emission drive current according to a clock signal CLK_A, a data signal DATA_A, and a reset signal RESET_M. Functions as a serial/parallel conversion circuit. The S/P conversion circuit 606 has output terminals LEDR1, LEDG1, LEDB1...LEDR8, LEDG8, LEDB8 for light emission drive current, and can output drive current for 24 systems, but in this case, the output terminal LEDG1 , LEDB1, LEDR2, LEDG2, LEDB2, LEDR3, and LEDG3 are used. As shown, the other output terminals are connected to ground.
And the output of output terminals LEDG1, LEDB1, LEDR2, LEDG2, LEDB2, LEDR3, LEDG3 (current 30-G1, 30-B1, 30-R2, 30-G2, 30-B2, 30-R3, 30-G3) is After being buffered by a buffer circuit 607, the signals are supplied to input terminals IN2, IN3, IN4 of a motor driver 608 and input terminals IN1, IN2, IN3, IN4 of a motor driver 609.

Note that the output terminals LEDG1, LEDB1, LEDR2, LEDG2, LEDB2, LEDR3, and LEDG3 are connected to a 5V DC voltage (DC5V) via resistors R60E, R61E, R62E, R56E, R57E, R58E, and R59E. This is to flow currents 30-G1, 30-B1, 30-R2, 30-G2, 30-B2, 30-R3, and 30-G3 using a 5V direct current voltage (DC5V) as a power source.

The motor driver 608 outputs a blower control signal L_BRO, a solenoid control signal L_SOL01, and a vibration control signal L_VIB from output terminals OUT2, OUT3, and OUT4 based on the signals of input terminals IN2, IN3, and IN4. These blower control signal L_BRO, solenoid control signal L_SOL01, and vibration control signal L_VIB are supplied to connectors CN6E, CN5E, and CN4E, respectively.

The motor driver 609 outputs motor drive signals MOT1-1, MOT1-2, MOT1-/1, MOT1-/2 from output terminals OUT1, OUT2, OUT3, OUT4 based on the signals of input terminals IN1, IN2, IN3, IN4. Output. These motor drive signals MOT1-1, MOT1-2, MOT1-/1, and MOT1-/2 are supplied to connector CN3E in FIG. 26.
Therefore, the circuit from the LED driver 605 to the motor driver 609 becomes a circuit system that generates a motor drive signal for the lower right side unit LED board 620 on the downstream side within the upper right LED board 600 of the side unit.

The load signal S_IN_LOAD and clock signal S_IN_CLK input from the connector CN1E in FIG. 24 are compensated by the buffer circuit 601 in FIG. Input to CLR/LOAD pin and CK pin to control parallel/serial conversion processing.
In the P/S conversion circuits 602 and 603, the P/S CONT terminal is set to H by applying a 5V DC voltage (DC5V) to the P/S CONT terminal, and the 8 terminals of the Q/D1 to Q/D8 terminals are set to H. The terminals are used as parallel inputs.

For the Q/D1 terminal to Q/D8 terminal, which are the parallel input terminals of the P/S conversion circuit 603, the Q/D1 terminal receives the sense signal SENS_C, the Q/D2 terminal receives the sense signal SENS_B, and the Q/D4 terminal receives the sense signal SENS_A. , sense signal SENS1X is input to the Q/D4 terminal, and sense signal SENS2X is input to the Q/D5 terminal.
Q/D6, Q/D7, and Q/D8 terminals are connected to ground.
Sense signals SENS_A, SENS_B, SENS_C, and SENS1X are input from connector CN3E. Sense signal SENS2X is input from connector CN7E.

The P/S conversion circuit 603 converts the sense signals SENS_A, SENS_B, SENS_C, SENS1X, and SENS2X inputted as described above into serial data (serial data signal SDT3) and outputs it from the Q8C terminal. This serial data signal SDT3 is input to the SI terminal of the P/S conversion circuit 602.

In the Q/D1 terminal to Q/D8 terminal, which are the parallel input terminals of the P/S conversion circuit 602, 5V DC voltage (DC5V) is applied to the Q/D1 terminal, Q/D2 terminal, and Q/D8 terminal, and the other is connected to ground.
The P/S conversion circuit 602 collects the serial data signal SDT3 from the P/S conversion circuit 603 inputted to the SI terminal and the logic (H/L) of the Q/D1 to Q/D8 terminals and converts it into serial data (serial It is converted into a data signal SDT4) and output from the Q8 terminal. This serial data signal SDT4 is input to the buffer circuit 601 and buffered. This output is transmitted as a serial data signal S_IN_DATAx from the upper right LED board 600 of the side unit to the upstream side from the connector CN1E via the damping resistor R1E in FIG. 24.

As described above, the side unit upper right LED board 600 has the following configuration.
- Enable signal ENABLE_L (reset signal RESET_M), clock signal CLK_P, reset signal RESET_P, and data signal DATA_P are input, and the buffer circuit 601 performs buffer processing on these. The signal after buffer processing is used for LED light emission, used for generating a motor drive signal, or transferred to the downstream side.

- The clock signal S_IN_CLK and the load signal S_IN_LOAD are supplied to the P/S conversion circuits 602 and 603 via the buffer circuit 601 and used for parallel/serial conversion processing.
・The various sense signals SENS_A, SENS_B, SENS_C, SENS1X, and SENS2X are collectively converted into serial data to generate the serial data signal S_IN_DATAx. This serial data signal S_IN_DATAx is transmitted to the upstream side. As described above, this serial data signal S_IN_DATAx is further converted into serial data together with the sense signals SENS8, SENS9, SENS11, and SENS1 in the front frame LED connection board 500, and is used as the serial data signal S_IN_DATA to connect the inner frame LED relay board 400. It will be transmitted to the production control board 30 via.

- Receives 12V DC voltage (DC12VB) and 5V DC voltage (DC5VB) through connector CN1E and uses it as an operating power source.
- The 12V motor drive voltage (MOT12V) and 12V DC voltage (DC12VS) used for motor drive signal generation are separated from the 12V DC voltage (DC12VB).
- 12V DC voltage (DC12VB) and 5V DC voltage (DC5VB) are supplied to the downstream side as operating power supply voltages.

In addition, in the side unit upper right LED board 600, as shown in FIGS. 24 to 29, including those mentioned above, resistors R1E, R2E..., capacitors C1E, C2E..., and diodes (Zener diodes) are installed at required locations. ) D1E, D2E, etc. are connected.
Further, as shown in the figure, taps TP1E, TP2E, . . . are provided and used for connection to required locations.
Although not shown, a capacitor for reducing power supply noise is appropriately placed between the 5V DC or 12V DC power supply line and the ground.

[5.6 Side unit lower right LED board 620]

The lower right LED board 620 of the side unit will be explained using FIGS. 30 and 31. These figures separately show the circuit configuration provided on the lower right LED board 620 of the side unit.

Connectors CN1F, CN3F, and CN4F in FIG. 30 and connector CN2F in FIG. 31 are mounted on the lower right LED board 620 of the side unit as connectors.

The transmission line end of the transmission line H11 that connects the connector CN3F of FIG. 30 with the connector CN3E of the upper right side unit LED board 600 of FIG. 26 is connected.
Therefore, this connector CN3F has 16 terminals from the 1st pin to the 16th pin as indicated by the numbers "1" to "16", and the terminal assignments are the same as those of the connector CN3E described above.

Connector CN1F is connected to side unit lower right movable motor 103 shown in FIG.
A 12V motor drive voltage (MOT12V) is applied to the third and fourth pins. The motor drive signals MOT1-/2, MOT1-/1, MOT1-2, and MOT1-1 input from the connector CN3F are output from the first pin, second pin, fifth pin, and sixth pin.

Connector CN4F is connected to the side unit lower right movable object position detection switch 102 shown in FIG.
The first pin is a 12V DC voltage (DC12VB), and the second pin is a ground terminal. The third pin becomes an input terminal for the sense signal SENS1X from the connected position detection switch.

Connector CN2F in FIG. 31 is connected to an LED board (not shown) arranged in the side unit 10. The first pin is a 12V DC voltage (DC12VB) terminal. The second to fifth pins serve as terminals for light emission drive signals.

Note that the conductor points P1 and P2 on the housings of the connectors CN1F, CN2F, CN3F, and CN4F are connected to the ground for the purpose of mounting strength.

The power supply voltage at the lower right LED board 620 of the side unit will be explained.
Photocouplers PC1F, PC2F, and PC3F are mounted on the lower right LED board 620 of the side unit.
A 5V direct current voltage (DC5V) is used as the power supply voltage for these. 5V direct current voltage (DC5V) is supplied from the first pin of connector CN3F.

Furthermore, the LED driver 621 shown in FIG. 31 is mounted as an IC on the lower right LED board 620 of the side unit, and the 12V DC voltage (DC12VB) supplied from the 11th pin of the connector CN1E is used as the power supply voltage for this. .
Further, the 12V motor drive voltage (MOT12V) output from the connector CN1F in FIG. 30 is supplied from the 15th pin of the connector CN3F.

The flow of various signals in the lower right LED board 620 of the side unit will be explained.
A clock signal CLK, a data signal DATA, and a reset signal RESET are input to the connector CN3F from the upper right LED board 600 of the side unit, and these signals are supplied to the LED driver 621 in FIG. 31.
The LED driver 621 outputs a light emission drive current according to the clock signal CLK, the data signal DATA, and the reset signal RESET.

The LED driver 621 has output terminals LEDR1, LEDG1, LEDB1...LEDR8, LEDG8, LEDB8 for light emission drive current, and can output drive current for 24 systems, but in this case, the output terminals LEDR1, LEDG1, LED light emission is driven using 12 terminals: LEDB1, LEDR2, LEDG2, LEDB2, LEDR3, LEDG3, LEDB3, LEDR4, LEDG4, and LEDB4. Furthermore, the four output terminals LEDR7, LEDG7, LEDB7, and LEDR8 are used to drive the LED light emission of an unillustrated LED board connected to the connector CN2F. As shown, the other output terminals are connected to ground.

The output terminals LEDR1, LEDG1, LEDB1, LEDR2, LEDG2, LEDB2, LEDR3, LEDG3, LEDB3, LEDR4, LEDG4, and LEDB4 are connected to each of the 12 LED circuits formed as the light emitting section 622, and the light emission drive current ( 27-R1, 27-G1, 27-B1...27-R4, 27-G4, 27-B4).
As shown in the figure, each LED circuit of the light emitting section 622 is composed of one or three LEDs connected in series and a resistor element. The LED circuits of each system are connected in parallel, and a 12V DC voltage (DC12VB) is applied to each anode side.
The output terminals LEDR7, LEDG7, LEDB7, and LEDR8 are connected to four systems of the light emitting drive unit 623. The light emission drive section 623 outputs four systems of light emission drive currents (27-R7, 27-G7, 27-B7...27-R8) from the connector CN2F.

Sense signals SENS_A, SENS_B, and SENS_C are obtained by photocouplers PC1F, PC2F, and PC3F in FIG. 30. These are transmitted from the connector CN3F to the upper right LED board 600 of the side unit.
Further, the sense signal SENS1X obtained from the connector CN4F is also transmitted from the connector CN3F to the upper right LED board 600 of the side unit.
These sense signals SENS_A, SENS_B, SENS_C, and SENS1X are converted into serial data as described above.

In addition, in the side unit lower right LED board 620, electronic elements such as resistors R1F, R2F, etc., capacitors C1F, C2F, etc. are installed at required locations, as shown in FIGS. 30 and 31, including those mentioned above. is connected.
Further, as shown in the figure, taps TP1F, TP2F, . . . are provided and used for connection to required locations.

[5.7 Side unit upper LED board 630]

The side unit upper LED board 630 will be explained using FIG. 32.
A connector CN1T is mounted on the side unit upper LED board 630.
The transmission line end of the transmission line H12 connecting between the connector CN1T and the connector CN2E of the upper right LED board 600 of the side unit in FIG. 26 is connected.

Therefore, this connector CN1T has a 6-terminal configuration from the first pin to the sixth pin as indicated by the numbers "1" to "6", and the terminal assignment is the same as that of the connector CN2E described above.
Note that the conductor points P1 and P2 on the housing of the connector CN1T are connected to the ground for the purpose of mounting strength.

On this side unit upper LED board 630, an LED driver 631 is mounted as an IC, and a 12V DC voltage (DC12VB) supplied from the sixth pin of the connector CN1T is used as a power supply voltage for the LED driver 631.

The flow of various signals will be explained.
A clock signal CLK, a data signal DATA, and a reset signal RESET are input to the connector CN1T from the upper right LED board 600 of the side unit, and these signals are supplied to the LED driver 631.
The LED driver 631 outputs a light emission drive current according to the clock signal CLK, the data signal DATA, and the reset signal RESET.

The LED driver 631 has output terminals LEDR1, LEDG1, LEDB1...LEDR8, LEDG8, LEDB8 for light emission drive current, and can output drive current for 24 systems, but in this case, the output terminals LEDR1, LEDG1, LED light emission is driven using nine terminals: LEDB1, LEDR2, LEDG2, LEDB2, LEDR3, LEDG3, and LEDB3. As shown, the other output terminals are connected to ground.

The output terminals LEDR1, LEDG1, LEDB1, LEDR2, LEDG2, LEDB2, LEDR3, LEDG3, and LEDB3 are connected to each of the nine LED circuits formed as the light emitting section 632, and the light emitting drive current (27-R1, 27- G1, 27-B1...27-R3, 27-G3, 27-B3).
As shown in the figure, each LED circuit of the light emitting section 632 is composed of two LEDs connected in series and a resistor element. The LED circuits of each system are connected in parallel, and a 12V DC voltage (DC12VB) is applied to each anode side.

In addition, in the side unit upper LED board 630, electronic elements such as resistors R1T, R2T, . . . , capacitors C1T, C2T, . . . are connected at required locations, as shown in FIG. .
Further, as shown in the figure, taps TP1T, TP2T, . . . are provided and used for connection to required locations.

[5.8 Button LED connection board 640]

The button LED connection board 640 will be explained using FIG. 33.
The button LED connection board 640 is equipped with connectors CN1G, CN2G, CN3G, CN4G, CN5G, CN6G, and CN8G as connectors.

The transmission line end of the transmission line H15 connecting between the connector CN1G and the connector CN10C of the front frame LED connection board 500 in FIG. 20 is connected.
Therefore, this connector CN1E has 20 terminals from the 1st pin to the 20th pin as indicated by the numbers "1" to "20", and the terminal assignments are the same as those of the connector CN10C described above.

The transmission line end of the transmission line H16 that connects the button LED board 660 shown in FIG. 11 is connected to the connector CN2G.
A 12V DC voltage (DC12VB), which is the power supply voltage of the button LED board 660, is applied to the third and seventh pins. The first pin and the sixth pin are ground terminals.
The second pin, fourth pin, and fifth pin are used as terminals for a clock signal CLK, a data signal DATA, and a reset signal RESET, respectively.

Connector CN3G is connected to a motor (not shown).
The motor drive signals MOTφ1, MOTφ/1, MOTφ2, and MOTφ/2 input from the connector CN1G are output from the 6th pin, the 2nd pin, the 5th pin, and the 1st pin of the connector CN3G.
Further, a 12V motor drive voltage (MOT12V) input from the connector CN1G is applied to the third and fourth pins as the illustrated 12V motor drive voltage (MOT12VA).

Connector CN4G is connected to a vibration device (not shown). A 12V motor drive voltage (MOT12VA) is applied to the first pin as a power supply voltage for the vibration device, and a motor drive signal DCMOT3 input from the connector CN1G is outputted to the second pin as a drive signal for the vibration device. A DC motor is used for the vibration device.

Connector CN5G is connected to a push button sensor within production button 13.
The first pin is a 12V DC voltage (DC12VB), and the second pin is a ground terminal. The third pin becomes an input terminal for the sense signal SENS8 from the connected push button sensor.

Connector CN6G is connected to the rotation origin sensor.
The first pin is a 12V DC voltage (DC12VB), and the third pin is a ground terminal. The second pin becomes an input terminal for the sense signal SENS9 from the connected rotation origin sensor.

Connector CN8G is connected to the rotation effect light sensor.
The first pin is a 12V DC voltage (DC12VB), and the third pin is a ground terminal. The second pin becomes an input terminal for the sense signal SENS11 from the connected rotation effect light sensor.

Note that conductor points P1 and P2 in the housing of each connector CN1G, CN2G, CN3G, CN4G, CN5G, CN6G, and CN8G are connected to the ground for the purpose of mounting strength.

A buffer circuit 641 is mounted on this button LED connection board 640. As the power supply voltage for this, a 5V direct current voltage (DC5V) is used. 5V direct current voltage (DC5V) is supplied from the 8th pin of connector CN1G.

The flow of various signals in the button LED connection board 640 will be explained.
The clock signal CLK_L, clear signal CLR_L, and data signal DATA_L supplied from the upstream front frame LED connection board 500 to the connector CN1G are input to the buffer circuit 641 via the chip resistor RA1G and buffered. The signal is then sent to the connector CN2G via the chip resistor RA2G, and is sent to the button LED board 660 downstream.
Note that a capacitor C1G is inserted between the 5V DC voltage (DC5V) of the buffer circuit 641 and the ground.

Although not shown, in the button LED connection board 640, a capacitor for reducing power supply noise is appropriately placed between the 5V DC or 12V DC power line and the ground.

[5.9 Button LED board 660]

The button LED board 660 will be explained using FIGS. 34 and 35. These figures separately show the circuit configuration provided on the button LED board 660.

The button LED board 660 is equipped with the connector CN1H shown in FIG. 34.
The transmission line end of the transmission line H16 connecting between the connector CN1H and the connector CN2G of the button LED connection board 640 in FIG. 33 is connected.
Therefore, this connector CN1H has a 7-terminal configuration from the first pin to the seventh pin as indicated by the numbers "1" to "7", and the terminal assignment is the same as that of the connector CN2G described above.
Further, conductor points P1 and P2 on the housing of the connector CN1H are connected to ground for the purpose of mounting strength.

This button LED board 660 is supplied with 12V DC voltage (DC12VB) as a power supply voltage input to the connector CN1H.
The LED driver 661 in FIG. 34 and the LED driver 663 in FIG. 35 are mounted on the button LED board 660 as ICs, and a 12V DC voltage (DC12VB) is used as the power supply voltage for these.
A 12V DC voltage (DC12VB) is also used as the power supply voltage for the light emitting parts 664 and 662.

The flow of various signals on the button LED board 660 will be explained.
A clock signal CLK, a data signal DATA, and a reset signal RESET are inputted to the connector CN1H from the upper right LED board 600 of the side unit, and these signals are supplied to the LED driver 661 via the chip resistor RA1H shown in FIG.
The LED driver 661 outputs a light emission drive current according to the clock signal CLK, the data signal DATA, and the reset signal RESET.

The LED driver 661 drives 24 systems of LED light emission using output terminals LEDR1, LEDG1, LEDB1, . . . LEDR8, LEDG8, LEDB8 for light emission drive current.
That is, the output terminals LEDR1, LEDG1, LEDB1...LEDR8, LEDG8, LEDB8 are connected to each of the 24 LED circuits formed as the light emitting section 662, and the light emitting drive current (19-R1, 19-G1, 19 -B1...19-R8, 19-G8, 19-B8).
As shown in the figure, each LED circuit of the light emitting section 662 is composed of two or three LEDs connected in series and a resistor element. The LED circuits of each system are connected in parallel, and a 12V DC voltage (DC12VB) is applied to each anode side.

The clock signal CLK, data signal DATA, and reset signal RESET are also supplied to the LED driver 663 in FIG. 35.
The LED driver 663 drives six systems of LED light emission using three output terminals LEDR1, LEDG1, LEDB1, . . . LEDR6, LEDG6, LEDB6 for light emission drive current.
That is, the output terminals LEDR1, LEDG1, LEDB1...LEDR6, LEDG6, LEDB6 are connected to each of the six LED circuits formed as the light emitting section 664, and the light emitting drive current (20-R1, 20-G1, 20 -B1...20-R6, 20-G6, 20-B6).
As shown in the figure, each LED circuit of the light emitting section 664 is composed of two or three LEDs connected in series and a resistance element. A Zener diode is connected in parallel to each LED. The LED circuits of each system are connected in parallel, and a 12V DC voltage (DC12VB) is applied to each anode side.

In addition to the above-mentioned lower right side unit LED board 620, as shown in FIGS. 34 and 35, resistors R1H, R2H..., capacitors C1H, C2H..., diodes (Zener Electronic elements such as D1H, D2H, etc. (including diodes) are connected.
Further, as shown in the figure, taps TP1H, TP2H, . . . are provided and used for connection to required locations.

[5.10 LED connection board 700]

Next, we will explain the board placed on the game board 3 side.
First, the LED connection board 700 will be explained using FIGS. 36, 37, 38, 39, 40, and 41. These figures separately show the circuit configuration provided on the LED connection board 700.
As shown in FIG. 11, the LED connection board 700 is a board connected to the production control board 30 on the game board 3.

The LED connection board 700 includes connectors CN1J in FIG. 36, connectors CN5J and CN6J in FIG. 37, connectors CN2J, CN3J, CN4J, and CN12J in FIG. 38, connectors CN10J in FIG. 41 connectors CN8J and CN9J are installed.

The connector CN1J in FIG. 36 is connected to the transmission line end of the transmission line H20 that connects with the production control board 30 as shown in FIG.
This connector CN1J has 40 terminals from the 1st pin to the 40th pin as indicated by numbers "1" to "40".

1st pin, 2nd pin, 8th pin, 9th pin, 10th pin, 16th pin, 18th pin, 19th pin, 20th pin, 22nd pin, 29th pin, 31st pin of connector CN1J , the 32nd pin, the 33rd pin, the 34th pin, the 39th pin, and the 40th pin are connected to the ground.
The fourth pin and the sixth pin are terminals for a 5V direct current voltage (DC5VB).
The 12th pin, 14th pin, 24th pin, 26th pin, 28th pin, and 30th pin are terminals for 12V DC voltage (DC12VB).
The 11th pin, 17th pin, 35th pin, and 37th pin are unused.

The third pin is assigned as a clock signal P_S_IN_CLK, the fifth pin as a serial data signal P_S_IN_DATA, and the seventh pin as a load signal P_S_IN_LOAD.
The serial data signal P_S_IN_DATA is serial data sent from the LED connection board 700 to the performance control board 30, and the clock signal P_S_IN_CLK and load signal P_S_IN_LOAD are supplied from the performance control board 30 for transmitting the serial data signal P_S_IN_DATA. It's a signal.

The 13th pin is assigned as a clock signal P_S_OUT_CLK, and the 15th pin is assigned as a serial data signal P_S_OUT_DATA terminal.
The serial data signal P_S_OUT_DATA is serial data transmitted from the production control board 30 together with the clock signal P_S_OUT_CLK.

The 21st pin is the clear signal M_S_CLR (reset signal RESET_M), the 23rd pin is the clock signal M_S_OUT_CLK (clock signal CLK_M), the 25th pin is the serial data signal M_S_OUT_DATA (serial data signal DATA_M), and the 27th pin is the enable signal M_S_ENABLEP (latch It is assigned as each terminal of the signal LATCH_M).
The serial data signal M_S_OUT_DATA is serial data transmitted from the production control board 30 together with the clock signal M_S_OUT_CLK.

Note that conductor points P1 and P2 on the housing of connector CN1J and connectors CN2J, CN3J, CN4J, CN5J, CN6J, CN7J, CN8J, CN9J, CN10J, CN11J, and CN12J, which will be described later, are connected to ground for mounting strength.

Connector CN5J in FIG. 37 is connected to a motor of a movable object (not shown). A 18V DC voltage (MOT18VA), which is the power supply voltage of the motor, is applied to the third and fourth pins.
Assign the 1st pin as the motor drive signal MOT6-/2, the 2nd pin as the motor drive signal MOT6-/1, the 5th pin as the motor drive signal MOT6-2, and the 6th pin as the motor drive signal MOT6-1. has been done.

Connector CN6J in FIG. 37 is also connected to a motor of another movable object (not shown). A 18V DC voltage (MOT18VA), which is the power supply voltage of the motor, is applied to the third and fourth pins.
Assign the 1st pin as the motor drive signal MOT7-/2, the 2nd pin as the motor drive signal MOT7-/1, the 5th pin as the motor drive signal MOT7-2, and the 6th pin as the motor drive signal MOT7-1. has been done.

Connector CN2J in FIG. 38 is connected to the position detection switch of the accessory. A 12V DC voltage (DC12VB), which is a power supply voltage on the position detection switch side, is applied to the first pin. The third pin is used as a ground terminal.
For example, a sense signal SENSv0, which is a detection signal of the bottom movable object right position detection switch 121 (see FIG. 10), is input to the second pin of the connector CN2J. The sense signal SENSv0 is pulled up by a 5V direct current voltage (DC5V) via a resistor R5J.

Connector CN4J is also connected to the position detection switch of the accessory, the first pin is a terminal for 12V DC voltage (DC12VB) which is the power supply voltage on the position detection switch side, and the third pin is a ground terminal.
For example, a sense signal SENSv1, which is a detection signal of the bottom movable object left position detection switch 125 (see FIG. 10), is input to the second pin of this connector CN4J. The sense signal SENSv1 is pulled up by a 5V direct current voltage (DC5V) via a resistor R29J.

The connector CN12J is also connected to the position detection switch of the accessory, the first pin is a terminal for 12V DC voltage (DC12VB) which is the power supply voltage on the position detection switch side, and the third pin is a ground terminal.
For example, a sense signal SENSv9, which is a detection signal of the lower back movable object upper position detection switch 120 (see FIG. 10), is input to the second pin of this connector CN12J. The sense signal SENSv9 is pulled up by a 5V direct current voltage (DC5V) via a resistor R31J.

Connector CN3J is connected to power module board 904 in FIG. The 1st, 2nd, and 4th pins are 18V DC voltage Vout, the 7th, 9th, and 10th pins are 35V DC voltage (DC35V), and the 5th, 6th, and 8th pins are ground. Used as each terminal.

Connector CN10J in FIG. 39 is connected to a relay board (not shown). It has a 32-terminal configuration from the 1st pin to the 32nd pin as indicated by the numbers "1" to "32". The 1st pin is a terminal to which 12V DC voltage (DC12VB) is applied via fuse F6J, The 2nd pin is a terminal to which a 5V DC voltage (DC5V) is applied via the fuse F9J, and the 3rd, 4th, and 5th pins are terminals to which a 12V motor drive voltage (MOT12V) is applied.
The 9th pin, 13th pin, 17th pin, 21st pin, 25th pin, 27th pin, 29th pin, 30th pin, 31st pin, and 32nd pin are connected to ground.

Assign the 7th pin as the motor drive signal MOT1-/2, the 8th pin as the motor drive signal MOT1-/1, the 10th pin as the motor drive signal MOT1-2, and the 12th pin as the motor drive signal MOT1-1. has been done.
The 14th pin is assigned as the motor drive signal MOT2-/2, the 16th pin is the motor drive signal MOT2-/1, the 18th pin is the motor drive signal MOT2-2, and the 20th pin is assigned as the motor drive signal MOT2-1. has been done.
The 22nd pin is assigned as the motor drive signal MOT3-/2, the 24th pin is the motor drive signal MOT3-/1, the 26th pin is the motor drive signal MOT3-2, and the 28th pin is assigned as the motor drive signal MOT3-1. has been done.

The seventh pin is a terminal for the clock signal CLK_B, and the eleventh pin is a terminal for the data signal DATA_B. The 15th pin is a terminal for the sense signal SENSv2, the 19th pin is a terminal for the sense signal SENSv3, and the 23rd pin is a terminal for the sense signal SENSv4.
The sense signal SENSv2 is, for example, a detection signal of the upper movable object position detection switch 132 in FIG. It's a signal.

Connector CN7J in FIG. 40 is connected to an unillustrated LED board. The first pin is a 12V DC voltage (DC12VB) terminal. The fifth pin and the sixth pin are terminals for an 18V LED drive voltage (LED 18V). The 4th pin, the 7th pin, and the 8th pin are connected to ground.
The second pin is a terminal for the clock signal CLK_E, and the third pin is a terminal for the data signal DATA_E.

The connector CN11J is connected to the transmission line end of the transmission line H30 that connects with the lower relay board 800 shown in FIG. 11. It has a 16-terminal configuration from the 1st pin to the 16th pin as indicated by the numbers "1" to "16".

The 4th and 6th pins are terminals to which 12V DC voltage (DC12VB) is applied via fuse F10J, and the 7th and 9th pins are terminals to which 12V motor drive voltage (MOT12V) is applied via fuse F11J. It is.
The 1st pin, the 15th pin, and the 16th pin are connected to ground.

The 3rd pin is the motor drive signal MOT4-/2, the 5th pin is the motor drive signal MOT4-/1, the 11th pin is the motor drive signal MOT4-2, and the 13th pin is the motor drive signal MOT4-1. Ru.
The 14th pin is used as a terminal for the sense signal SENSv7. The sense signal SENSv7 is, for example, a detection signal of the lower front movable object position detection switch 123 in FIG.
The second pin, the eighth pin, the tenth pin, and the twelfth pin are terminals for outputting the light emission drive currents 13-B7, 13-R8, 13-G8, and 13-B8 to the relay board 800 side under the back of the panel.

Connector CN9J in FIG. 41 is connected to an unillustrated LED board. The first pin is a 12V DC voltage (DC12VB) terminal. The 10th pin is a 5V direct current voltage (DC5V) terminal. The fourth pin and the ninth pin are connected to ground.
The second pin is a terminal for the clock signal CLK_D, and the third pin is a terminal for the data signal DATA_D.

The 8th pin, 7th pin, 6th pin, and 5th pin are terminals for light emission drive currents 13-B7, 13-R8, 13-G8, and 13-B8. The light emission drive currents 13-B7, 13-R8, 13-G8, and 13-B8 are caused by LED drivers mounted on an LED board (not shown). The clock signal CLK_D and the data signal DATA_D from the second and third pins of the connector CN9J are supplied to the LED driver mounted on the LED board (not shown), and based on the clock signal CLK_D and the data signal DATA_D, the LED driver controls the light emission drive current 13-B7, 13-R8, 13-G8, and 13-B8 are washed away. The light emitting drive currents 13-B7, 13-R8, 13-G8, and 13-B8 are transmitted from the connector CN11J in FIG. (see), causing those LEDs to emit light.

The 11th pin of connector CN9J is used as a terminal for sense signal SENSv8. The sense signal SENSv8 is, for example, a detection signal of the distribution position detection switch 122 in FIG. 10.

The transmission line end of the transmission line H21 that connects between the connector CN8J in FIG. 41 and the back left relay board 720 shown in FIG. 11 is connected. It has a 24-terminal configuration from the 1st pin to the 24th pin as indicated by the numbers "1" to "24".

The 1st to 4th pins are terminals to which 18V motor drive voltage (MOT18VB) is applied via fuse F12J, and the 5th and 9th pins are terminals to which 12V DC voltage (DC12VB) is applied via fuse F7J. , the 11th pin is a terminal to which a 5V DC voltage (DC5VB) is applied via fuse F8J.
The 7th pin, 13th pin, 14th pin, 19th pin, and 20th pin are connected to ground.

The 15th pin is a terminal for the clock signal CLK_C, and the 17th pin is a terminal for the data signal DATA_C.
6th and 8th pins are motor drive signals MOT5-/2, 10th and 12th pins are motor drive signals MOT5-/1, 16th and 18th pins are motor drive signals MOT5-2, 22nd and 24th pins are each terminal of the motor drive signal MOT5-1. In this case, the motor to be driven is a high-torque motor and is driven at a 18V motor drive voltage (MOT18VB). Since the power consumption is large, two pins/lines are used for each of the motor drive signals MOT5-/2, MOT5-/1, MOT5-2, and MOT5-1.
The 21st pin is a terminal for the sense signal SENSv6, and the 23rd pin is a terminal for the sense signal SENSv5. The sense signal SENSv6 is, for example, a detection signal of the bottom left movable object lower left position detection switch 128 in FIG.

The power supply voltage at this LED connection board 700 will be explained.
The LED connection board 700 includes, as ICs, buffer circuits 703 and 704 in FIG. 36, which are 8-circuit Schmitt trigger buffers similar to the buffer circuit 402 previously explained in FIG. 13, and a buffer circuit in FIG. 39, which is a triple buffer gate. A circuit 705 and buffer circuits 707 and 708 shown in FIG. 41 are installed.
As the power supply voltage for these, as shown in FIG. 36, a 5V DC voltage (DC5V) based on a 5V DC voltage (DC5VB) from the connector CN1J is used.

P/S conversion circuits 701 and 702 shown in FIG. 36 are mounted as ICs, and a 5V direct current voltage (DC5V) is used as the power supply voltage for these circuits. The 5V DC voltage (DC5VB) is taken out from the positive electrode side of the capacitor C4J via the connector CN1J and the fuse F1J. Note that the P/S conversion circuits 701 and 702 are ICs similar to the P/S conversion circuit 505 in FIG.

Note that the 12V DC voltage (DC12VB) outputted downstream from connectors CN2J, CN4J, CN7J, CN8J, CN10J, CN11J, and CN12J is taken out from the positive electrode side of capacitor C5J from connector CN1J via fuse F2J.

Furthermore, motor drivers 710 to 713 shown in FIG. 37 are mounted as ICs on the LED connection board 700, and a 12V motor drive voltage (MOT12V) and a 12V direct current voltage (DC12VS) are used as power supply voltages for these.
Furthermore, motor drivers 714, 715, and 716 are mounted, and as power supply voltages for these, 18V motor drive voltage (MOT18VA) and 12V DC voltage (DC12VS) are used.

The 12V motor drive voltage (MOT12V) is separated from the 12V direct current voltage (DC12VB) by a power isolation/protection circuit 719.
As shown in FIG. 36, the anode side of the Schottky barrier diode D5J is connected to the 12th pin, 14th pin, 24th pin, 26th pin, 28th pin, and 30th pin of connector CN1J. . A resistor R6J, capacitors C14J and C15J, and a chip varistor 709 are connected in parallel between the cathode side of the Schottky barrier diode D5J and the ground. With this configuration as the power supply separation/protection circuit 719, the 12V motor drive voltage (MOT12V) is separated as a power supply voltage with overvoltage protection.

The 12V DC voltage (DC12VS) is separated from the 12V DC voltage (DC12VB) using a circuit including a diode D1J, a resistor R1J, and a capacitor C3J shown in FIG.

The 18V motor drive voltage (MOT18VA), the 18V motor drive voltage (MOT18VB), and the 18V LED drive voltage (LED18V) are separated from the 18V DC voltage Vout input from the connector CN3J, as also shown in FIG.
The anode side of the Schottky barrier diode D7J is connected to the first pin, second pin, and fourth pin to which the 18V DC voltage Vout is applied via the fuse F3J. A resistor R7J and capacitors C17J and C18J are connected in parallel between the cathode side of the Schottky barrier diode D7J and the ground. With this configuration, a 18V motor drive voltage (MOT18VA) is extracted.
Further, the anode side of the Schottky barrier diode D9J is connected to the first, second, and fourth pins to which the 18V DC voltage Vout is similarly applied via the fuse F4J. A resistor R8J and capacitors C20J and C21J are connected in parallel between the cathode side of the Schottky barrier diode D9J and the ground. With this configuration, 18V motor drive voltage (MOT18VB) is extracted.
Further, the anode side of the Schottky barrier diode D11J is connected to the first, second, and fourth pins to which the 18V DC voltage Vout is similarly applied via the fuse F5J. A resistor R9J and capacitors C23J and C24J are connected in parallel between the cathode side of the Schottky barrier diode D11J and the ground. With this configuration, an 18V LED drive voltage (LED18V) is extracted.

The flow of various signals in the LED connection board 700 will be explained below.
A clock signal P_S_OUT_CLK and a serial data signal P_S_OUT_DATA are transmitted from the production control board 30 to the connector CN1J in FIG. These are signals used to control operations downstream of the LED connection board 700.

The clock signal P_S_OUT_CLK and the serial data signal P_S_OUT_DATA are input to the A5 terminal and the A7 terminal of the buffer circuit 703, and signal compensation is performed as shown as the clock signal CLK_P and the serial data signal DATA_P in FIG.
The signals are outputted from the Y5 terminal and Y7 terminal of the buffer circuit 703, and are input to the buffer circuit 706 in FIG. 40 for buffer processing as shown as a clock signal CLK_A and a serial data signal DATA_A. The signal is then transmitted downstream from the connector CN7J as a clock signal CLK_E and a serial data signal DATA_E.

The clock signal CLK_A and serial data signal DATA_A output from the Y5 and Y7 terminals of the buffer circuit 703 are also input to the buffer circuit 705 in FIG. 39 for buffer processing, and the clock signal CLK_B and serial data signal Sent downstream as DATA_B.
Furthermore, the clock signal CLK_A and the serial data signal DATA_A are also input to the buffer circuit 707 in FIG. 41, where they are buffered and transmitted from the connector CN9J to the downstream side as the clock signal CLK_D and the serial data signal DATA_D.
Furthermore, the clock signal CLK_A and the serial data signal DATA_A are also input to the buffer circuit 708 in FIG. 41, where they are buffered and sent from the connector CN8J to the backside left relay board 720 on the downstream side as the clock signal CLK_C and the serial data signal DATA_C. be done.

The connector CN1J in FIG. 36 receives a clear signal M_S_CLR (reset signal RESET_M), a clock signal M_S_OUT_CLK (clock signal CLK_M), a serial data signal M_S_OUT_DATA (serial data signal DATA_M), and an enable signal M_S_ENABLEP (latch signal LATCH_M) from the production control board 30. ) will be sent.
These are used for controlling the motor drive.
These signals are input to the A7 terminal, A1 terminal, A3 terminal, and A5 terminal of the buffer circuit 704 and are compensated. The signals are then input to motor drivers 710 to 716 in FIG. 37, respectively, via chip resistor RA4J.
That is, in each of the motor drivers 710 to 716, the reset signal RESET_M is input to the RESET terminal, the latch signal LATCH_M is input to the LATCH terminal, the clock signal CLK_M is input to the SCLK terminal, and the serial data signal DATA_M is input to the SDIN terminal.

Motor drivers 710 to 713 each generate a 12V motor drive signal in response to these inputs.
That is, the motor driver 710 generates motor drive signals MOT1-/2, MOT1-/1, MOT1-2, and MOT1-1 output from the connector CN10J.
The motor driver 711 generates motor drive signals MOT2-/2, MOT2-/1, MOT2-2, and MOT2-1 output from the connector CN10J.
The motor driver 712 generates motor drive signals MOT3-/1, MOT3-2, and MOT3-1 output from the connector CN10J.
The motor driver 713 generates motor drive signals MOT4-/2, MOT4-/1, MOT4-2, and MOT4-1 output from the connector CN11J.

Further, the motor drivers 714 to 716 generate 18V motor drive signals, respectively, in response to the input of the reset signal RESET_M, latch signal LATCH_M, clock signal CLK_M, and serial data signal DATA_M.
That is, the motor driver 714 generates motor drive signals MOT5-/2, MOT5-/1, MOT5-2, and MOT5-1 output from the connector CN8J.
The motor driver 715 generates motor drive signals MOT6-/2, MOT6-/1, MOT6-2, and MOT6-1 output from the connector CN5J.
The motor driver 716 generates motor drive signals MOT7-/2, MOT7-/1, MOT7-2, and MOT7-1 output from the connector CN6J.

A clock signal P_S_IN_CLK and a load signal P_S_IN_LOAD are transmitted from the production control board 30 to the connector CN1J in FIG.
The clock signal P_S_IN_CLK and the load signal P_S_IN_LOAD are input to the A3 terminal and the A2 terminal of the buffer circuit 703, and the signals are compensated. The signal is then input from the Y3 terminal and Y2 terminal of the buffer circuit 703 to the CK terminal and CLR/LOAD terminal of the P/S conversion circuits 701 and 702 via the chip resistor RA1J.
In the P/S conversion circuits 701 and 702, 5V DC voltage (DC5V) is applied to the P/S CONT terminal, so that the P/S CONT terminal is set to H, and the Q/D1 to Q/D8 terminals are set to H. 8 terminals are used as parallel inputs. Then, the P/S conversion circuits 701 and 702 perform parallel-to-serial conversion according to the clock signal P_S_IN_CLK and the load signal P_S_IN_LOAD.

A sense signal SENSv8 from the connector CN9J in FIG. 41 is input to the Q/D1 terminal of the P/S conversion circuit 701. As shown in FIG. 36, this sense signal SENSv8 is pulled up by a 5V direct current voltage (DC5V) via a resistor R23J.
Furthermore, the sense signal SENSv9 from the connector CN12J in FIG. 38 is input to the Q/D2 terminal of the P/S conversion circuit 701.
The inputs of the Q/D3 terminal to Q/D7 terminal are set to ground level "0" (L level), and the Q/D8 terminal is set to 5V level "1" (H level).
The P/S conversion circuit 702 converts the above parallel input into serial data (serial data signal SDT5) and outputs it from the Q8C terminal. This serial data signal SDT5 is input to the SI terminal of the P/S conversion circuit 702.

Sense signals SENSv0 to SENSv7 are input to the eight terminals Q/D1 to Q/D8 of the P/S conversion circuit 702. Sense signal SENSv0 is input from connector CN2J. Sense signal SENSv1 is input from connector CN4J. Sense signals SENSv2 to SENSv4 are input from connector CN10J. Sense signals SENSv5 and SENSv6 are input from connector CN8J. Sense signals SENSv5 and SENSv7 are input from connector CN11J.
The sense signals SENSv2 to SENSv7 are each pulled up by a 5V direct current voltage (DC5V) via resistors R24J, R2J, and chip resistor RA3J.

As described above, the P/S conversion circuit 702 collectively converts the serial data signal SDT5 from the P/S conversion circuit 701 inputted to the SI terminal and the sense signals SENSv0 to SENSv7 into serial data (serial data signal SDT6). Output from Q8C terminal. This serial data signal SDT6 is input to the A1 terminal of the buffer circuit 703 and buffered. Then, the Y1 output is supplied to the third pin of the connector CN1J via the chip resistor RA1J, and is transmitted to the upstream production control board 30 as a serial data signal P_S_IN_DATA from the LED connection board 700.

As described above, the LED connection board 700 has the following configuration.
- Converts the sense signals SENSv0 to SENSv9 input from the downstream side into serial data, and transmits the serial data signal P_S_IN_DATA from the connector CN1J to the upstream side via the buffer circuit 703.
- Transfer the clock signal P_S_OUT_CLK and serial data signal P_S_OUT_DATA transmitted from the production control board 30 to the downstream side via the buffer circuit 703 and the buffer circuit (any one of 705, 706, 707, 708).

・The clear signal M_S_CLR (reset signal RESET_M), clock signal M_S_OUT_CLK (clock signal CLK_M), serial data signal M_S_OUT_DATA (serial data signal DATA_M), and enable signal M_S_ENABLEP (latch signal LATCH_M) sent from the production control board 30 are buffered. The motor drive signals (MOT1-/2, MOT1-/1, MOT1-2, MOT1-1...MOT7-/2, MOT7-/1, MOT7- 2. Generate MOT7-1) and send it to the downstream side (motor).

- Receives 12V DC voltage (DC12VB) and 5V DC voltage (DC5VB) through connector CN1J and uses it as an operating power source.
- Receives 18V DC voltage Vout through connector CN3J and uses it as an 18V system operating power source (operating power source for high-intensity LEDs and high-torque motors).
- 12V DC voltage (DC12VB), 5V DC voltage (DC5V), 12V motor drive voltage (MOT12V), 18V motor drive voltage (MOT18V), and 18V LED drive voltage (LED18V) are supplied as operating power supply voltages to the downstream side.

In addition, in the LED connection board 700, as shown in FIGS. 36 to 41, including those mentioned above, resistors R1J, R2J..., chip resistors RA1J, RA2J..., and capacitors C1J, C2J are installed at required locations. ..., diodes (including Zener diodes and Schottky barrier diodes) D1J, D2J, and the like are connected.
Further, as shown in the figure, taps TP1J, TP2J, . . . are provided and used for connection to required locations.
Although not shown, a capacitor for reducing power supply noise is appropriately placed between the 5V DC or 12V DC power supply line and the ground.

[5.11 Back panel left relay board 720]

The configuration of the back left relay board 720 is shown in FIG. Connectors CN1K and CN2K are mounted on the left relay board 720 on the back of the panel.

The transmission line end of the transmission line H21 connecting between the connector CN1K and the connector CN8J of the LED connection board 700 in FIG. 41 is connected to the connector CN1K.
Therefore, this connector CN1K has 24 terminals from the 1st pin to the 24th pin as indicated by the numbers "1" to "24", and the terminal assignment is the same as that of the connector CN8J described above.

The transmission line end of the transmission line H22 that connects the downstream decorative board 740 is connected to the connector CN2K.
This connector CN1B has 22 terminals from the 1st pin to the 22nd pin as indicated by numbers "1" to "22".

The 4th pin, the 7th pin, and the 10th pin are used as ground terminals.
The sixth pin is a 5V direct current voltage (DC5V) terminal.
The 8th pin and the 9th pin are terminals for 12V DC voltage (DC12VB).
The 11th pin, 12th pin, 13th pin, and 14th pin are terminals for a 18V motor drive voltage (MOT18VB).

The fifth pin is a terminal for the clock signal CLK_C, and the third pin is a terminal for the data signal DATA_C.
15th and 16th pins are motor drive signals MOT5-/2, 17th and 18th pins are motor drive signals MOT5-/1, 19th and 20th pins are motor drive signals MOT5-2, 21st and 22nd pins are each terminal of the motor drive signal MOT5-1.
The second pin is a terminal for the sense signal SENSv6, and the first pin is a terminal for the sense signal SENSv5.

Incidentally, conductor points P1 and P2 on the housings of the connectors CN1K and CN2K are connected to the ground for the purpose of mounting strength.

On the back left relay board 720, the ground terminals of the 7th pin, 13th pin, 14th pin, 19th pin, and 20th pin of connector CN1K are connected to the 4th pin, 7th pin, and 10th pin on the connector CN2K side. The 3-pin connector has been converted from a 24-pin connector to a 22-pin connector. This reduces the number of terminals of the connector CN2D to the downstream side.

[5.12 Decorative board 740]

The decorative substrate 740 will be explained using FIG. 43.
The decorative board 740 is equipped with connectors CN1L, CN2L, CN3L, CN4L, CN5L, and CN6L.

The transmission line end of the transmission line H22 connecting between the connector CN1L and the connector CN2K of the back panel left relay board 720 in FIG. 42 is connected to the connector CN1L.
Therefore, this connector CN1L has 22 terminals from the 1st pin to the 22nd pin as indicated by the numbers "1" to "22", and the terminal assignment is the same as that of the connector CN2K described above.
Note that conductor points P1 and P2 on the housings of the connectors CN1K to CN6K are connected to the ground for the purpose of mounting strength.

Connector CN2L is connected to a position detection switch of a movable object (not shown).
The first pin is a 12V DC voltage (DC12VB), and the third pin is a ground terminal. The second pin becomes an input terminal for the sense signal SENSv5 from the connected position detection switch.

Connector CN3L is connected to another position detection switch of a movable object (not shown).
The first pin is a 12V DC voltage (DC12VB), and the third pin is a ground terminal. The second pin becomes an input terminal for the sense signal SENSv6 from the connected position detection switch.

The transmission line end of the transmission line H23 connecting between the connector CN4L and the relay board 760 shown in FIG. 11 is connected to the connector CN4L. It has a 14-terminal configuration from the 1st pin to the 14th pin as indicated by the numbers "1" to "14".

The 1st pin, the 2nd pin, and the 3rd pin are terminals to which a 12V DC voltage (DC12VB) is applied, and the 12th pin, the 13th pin, and the 14th pin are terminals to which a 5V DC voltage (DC5V) is applied.
The 4th pin, 5th pin, 7th pin, 8th pin, 10th pin, and 11th pin are connected to ground.
The sixth pin is a terminal for the clock signal CLK_C, and the ninth pin is a terminal for the data signal DATA_C.
A flexible cable (for example, a flexible flat cable) is connected to the connector CN4L as the transmission line H23, but since the rated current of the flexible cable is small, the number of power supply terminals and ground terminals is greater than that of the connector CN1L.

Connector CN5L is connected to a motor of a movable object (not shown).
The third and fourth pins are terminals to which a 18V motor drive voltage (MOT18V) is applied.
The 1st pin is the motor drive signal MOT5-/2, the 2nd pin is the motor drive signal MOT5-/1, the 5th pin is the motor drive signal MOT5-2, and the 6th pin is the motor drive signal MOT5-1. Ru.

Connector CN6L is connected to an LED board of a movable object (not shown).
The first pin and the second pin are terminals to which a 12V DC voltage (DC12VB) is applied.
The 3rd pin to the 24th pin are light emission drive current terminals for 22 systems of light emission drive currents 09-R1, 09-G1, 09-B1...09-R8, and 09-G8.

A buffer circuit 741 which is a triple buffer gate is mounted on this decorative substrate 740. As the power supply voltage for this, a 5V direct current voltage (DC5V) is used. A 5V direct current voltage (DC5V) is supplied from the 6th pin of the connector CN1L.

Further, an LED driver 742 is mounted, and a 12V direct current voltage (DC12VB) is used as a power supply voltage for this. 12V DC voltage (DC12VB) is supplied from the 8th and 9th pins of the connector CN1L.

Note that the 18V motor drive voltage (MOT18V) supplied downstream from the connector CN5L is obtained from the 11th to 14th pins of the connector CN1L.

The flow of various signals on the decorative board 740 will be explained.
The clock signal CLK_C and data signal DATA_C supplied to the connector CN1L from the upstream back panel left relay board 720 are input to the buffer circuit 741 and buffered. The signal is then sent to connector CN4L and transmitted to downstream relay board 760.

The clock signal CLK_C and data signal DATA_C are also supplied to the LED driver 742.
The LED driver 742 drives 22 systems of LED light emission using output terminals LEDR1, LEDG1, LEDB1, . . . LEDR7, LEDG7, LEDR8, LEDG8 for light emission drive current.
These output terminals LEDR1, LEDG1, LEDB1...LEDR7, LEDG7, LEDR8, LEDG8 are connected to the 3rd pin to the 24th pin of the connector CN6L, and are connected to the 22 systems of LED circuits on the LED board of the movable object (not shown). The configuration is such that a light emission driving current (09-R1, 09-G1, 09-B1...09-R6, 09-G6, 09-B6) is passed through the LEDs.

As described above, the decorative substrate 740 has the following configuration.
- Transfer the clock signal CLK_C and data signal DATA_C transmitted from the upstream side to the downstream side via the buffer circuit 703.
- The clock signal CLK and data signal DATA are also used by the LED driver 742. The LED driver 742 drives the light emitting parts of other LED boards to emit light.

- Receives 12V DC voltage (DC12VB) and 5V DC voltage (DC5V) through connector CN1L and uses it as an operating power source.
- 12V DC voltage (DC12VB) and 18V motor drive voltage (MOT18VB) are supplied to the downstream side as operating power supply voltages.

In addition to those mentioned above, on the decorative board 740, as shown in FIG. 43, electronic elements such as resistors R1L, R2L, . . . , capacitors C1L, C2L, . . . are connected at required locations.
Further, as shown in the figure, taps TP1L and TP2L are provided and used for connection to required locations.

[5.13 Relay board 760]

The configuration of the relay board 760 is shown in FIG. Connectors CN1M, CN2M, and CN3M are mounted on the relay board 760.

The transmission line end of the transmission line H23 connecting between the connector CN1M and the connector CN4L of the decorative board 740 in FIG. 43 is connected.
Therefore, this connector CN1M has 14 terminals from the 1st pin to the 14th pin as indicated by the numbers "1" to "14", and the terminal assignment is the same as that of the connector CN4L described above.

Connector CN2M is connected to an LED board (not shown).
The fourth pin and the sixth pin are used as ground terminals.
The fifth pin is a 5V direct current voltage (DC5V) terminal.
The first pin is a 12V DC voltage (DC12VB) terminal.
The second pin is a terminal for the clock signal CLK, and the third pin is a terminal for the data signal DATA.

The transmission line end of the transmission line H24 that connects the downstream LED board 780 is connected to the connector CN3M.
This connector CN1B has a six-terminal configuration from the first pin to the sixth pin as indicated by numbers "1" to "6".
The fourth pin and the sixth pin are used as ground terminals.
The fifth pin is a 5V direct current voltage (DC5V) terminal.
The first pin is a 12V DC voltage (DC12VB) terminal.
The second pin is a terminal for the clock signal CLK, and the third pin is a terminal for the data signal DATA.

Note that conductor points P1 and P2 on the housings of the connectors CN1M, CN2M, and CN3M are connected to the ground for the purpose of mounting strength.

This relay board 760 is equipped with a buffer circuit 761 which is a Schmitt trigger buffer containing eight CMOS circuits, similar to the buffer circuit 402 in FIG. As the power supply voltage for this, a 5V direct current voltage (DC5V) is used. 5V direct current voltage (DC5V) is supplied from the 12th pin, 13th pin, and 14th pin of connector CN1M.

The clock signal CLK_C and data signal DATA_C supplied from the upstream decorative board 740 to the connector CN1M are input to the A1 terminal and A2 terminal of the buffer circuit 761, and are subjected to signal compensation. Then, it is outputted from the Y1 terminal and the Y2 terminal, and transmitted to the downstream side as a clock signal CLK and a data signal DATA by the connector CN2M.
Further, the clock signal CLK_C and the data signal DATA_C are also input to the A5 terminal and the A6 terminal of the buffer circuit 761, and the signals are compensated. Then, it is output from the Y5 terminal and the Y6 terminal, and is transmitted to the downstream LED board 780 as a clock signal CLK and a data signal DATA by the connector CN3M.

Therefore, the decorative board 740 buffers the clock signal CLK_C and the data signal DATA_C, and then sends them to the two downstream LED boards (LED board 780 and an unillustrated LED board).

[5.14 LED board 780]

FIG. 45 shows the configuration of the LED board 780. Connectors CN1N and CN2N are mounted on the LED board 780.

The transmission line end of the transmission line H24 that connects the connector CN1N to the connector CN3M of the relay board 760 in FIG. 44 is connected to the connector CN1N.
Therefore, this connector CN1N has a 6-terminal configuration from the first pin to the sixth pin as indicated by the numbers "1" to "6", and the terminal assignment is the same as that of the connector CN3M described above.

Connector CN2N is connected to LED board 790.
The first pin is a 12V DC voltage (DC12VB) terminal.
The fourth pin is used as a ground terminal.
The second pin is a terminal for the clock signal CLK, and the third pin is a terminal for the data signal DATA.

Note that conductor points P1 and P2 on the housings of the connectors CN1N and CN2N are connected to the ground for the purpose of mounting strength.

A buffer circuit 781 which is a triple buffer gate is mounted on the LED board 780. As the power supply voltage for this, a 5V direct current voltage (DC5V) is used. A 5V direct current voltage (DC5V) is supplied from the fifth pin of the connector CN1N.

Furthermore, an LED driver 782 is mounted, and a 12V DC voltage (DC12VB) is used as the power supply voltage for this. A 12V DC voltage (DC12VB) is supplied from the first pin of the connector CN1N.

The flow of various signals in the LED board 780 will be explained.
The clock signal CLK and data signal DATA supplied from the upstream relay board 760 to the connector CN1N are input to the buffer circuit 781 and buffered. The signal is then sent to connector CN2N and transmitted to the downstream LED board 790.

The clock signal CLK and data signal DATA are also supplied to the LED driver 782.
The LED driver 782 drives 22 systems of LED light emission using the light emission drive current output terminals LEDR1, LEDG1, LEDB1...LEDR7, LEDG7, LEDB7, LEDR8.
These output terminals LEDR1, LEDG1, LEDB1...LEDR7, LEDG7, LEDB7, LEDR8 are connected to each of the 22 systems of LED circuits formed as the light emitting section 783, and the light emitting drive current (03-R1, 03-G1, 03-B1...03-G7, 03-B7, 03-R8).
As shown in the figure, each system of LED circuits of the light emitting section 783 is composed of two or three LEDs (LED1, LED2, . . . ) connected in series and a resistance element. The LED circuits of each system are connected in parallel, and a 12V DC voltage (DC12VB) is applied to each anode side.

As described above, the LED board 780 has the following configuration.
- Transfers the clock signal CLK and data signal DATA transmitted from the upstream side to the downstream side via the buffer circuit 781.
- The clock signal CLK and data signal DATA are also used by the LED driver 782 to drive the light emitting section 783 to emit light.

- Receives 12V DC voltage (DC12VB) and 5V DC voltage (DC5V) through connector CN1N and uses it as an operating power source.
- 12V DC voltage (DC12VB) is supplied to the downstream side as the operating power supply voltage.

In addition to those mentioned above, on the LED board 780, as shown in FIG. 45, electronic elements such as resistors R1N, R2N, . . . , capacitors C1N, C2N, . . . are connected at required locations.
Further, as shown in the figure, taps TP1N and TP2N are provided and used for connection to required locations.

[5.15 LED board 790]

FIG. 46 shows the configuration of the LED board 790. A connector CN1X is mounted on the LED board 790.

The transmission line end of the transmission line H25 connecting between the connector CN1X and the connector CN2N of the LED board 780 in FIG. 45 is connected to the connector CN1X.
Therefore, this connector CN1X has a four-terminal configuration from the first pin to the fourth pin as indicated by the numbers "1" to "4", and the terminal assignments are the same as the above-mentioned connector CN2N.

Note that the conductor points P1 and P2 on the housing of the connector CN1X are connected to the ground for the purpose of mounting strength.

An LED driver 791 is mounted on the LED board 790. A 12V direct current voltage (DC12VB) is used as the power supply voltage for the LED driver 791. A 12V DC voltage (DC12VB) is supplied from the first pin of the connector CN1X.

The flow of various signals in the LED board 790 will be explained.
The clock signal CLK and data signal DATA supplied from the upstream LED board 780 to the connector CN1X are supplied to the LED driver 791.
The LED driver 791 drives 16 systems of LED light emission using output terminals LEDR1, LEDG1, LEDB1, . . . LEDR5, LEDG5, LEDB5, LEDR6 for light emission drive current.
These output terminals LEDR1, LEDG1, LEDB1, . 02-B1...02-G5, 02-B5, 02-R6).
As shown in the figure, each system of LED circuits of the light emitting section 792 is composed of two or three LEDs (LED1, LED2, . . . ) connected in series and a resistance element. The LED circuits of each system are connected in parallel, and a 12V DC voltage (DC12VB) is applied to each anode side.

The above LED board 790 has the following configuration.
- The LED driver 791 uses the clock signal CLK and data signal DATA transmitted from upstream to drive the light emitting section 792 to emit light.

- Receives 12V DC voltage (DC12VB) through connector CN1X and uses it as an operating power source.

In addition to those mentioned above, on the LED board 790, as shown in FIG. 46, electronic elements such as resistors R1X, R2X, . . . , capacitors C1X, C2X, . . . are connected at required locations. Further, as shown in the figure, taps TP1X and TP2X are provided and used for connection to required locations.

Note that an LED driver 791 and a light emitting section 792 are mounted on the LED board 790, but a buffer circuit is not mounted thereon. Therefore, only 12V DC voltage (DC12VB) is supplied from connector CN2N of LED board 780 to connector CN1X of LED board 790, and 5V DC voltage (DC5V) is not supplied. That is, the 5V DC voltage (DC5V) is applied to the LED board provided with the buffer circuit based on the 5V DC voltage (DC5VB) from the production control board 30 (see the 4th and 6th pins of the connector CN1J in FIG. 36). The configuration is such that up to 780 can be supplied.

[5.16 Bottom relay board 800]

FIG. 47 shows the structure of the lower relay board 800. Connectors CN1Q, CN2Q, CN3Q, and CN4Q are mounted on the relay board 800 under the back of the panel.

The transmission line end of the transmission line H30 connecting between the connector CN1Q and the connector CN11J of the LED connection board 700 in FIG. 40 is connected to the connector CN1Q.
Therefore, this connector CN1Q has a 16-terminal configuration from the 1st pin to the 16th pin as indicated by the numbers "1" to "16", and the terminal assignments are the same as those of the connector CN11J described above.

Connector CN2Q is connected to the movable motor.
The third and fourth pins are terminals to which a 12V motor drive voltage (MOT12V) is applied.
The 1st pin is the motor drive signal MOT4-/2, the 2nd pin is the motor drive signal MOT4-/1, the 5th pin is the motor drive signal MOT4-2, and the 6th pin is the motor drive signal MOT4-1. Ru.

The transmission line end of the transmission line H31 that connects the downstream decorative board 820 is connected to the connector CN3Q.
This connector CN3Q has a 10-terminal configuration from the 1st pin to the 10th pin as indicated by numbers "1" to "10".
The first to sixth pins are terminals for 12V direct current voltage (DC12VB).
The 7th pin, 8th pin, 9th pin, and 10th pin are terminals for light emission drive currents 13-B7, 13-R8, 13-G8, and 13-B8.
A flexible cable (for example, a flexible flat cable) is connected to this connector CN3Q as a transmission line H31, and since the rated current is small, the number of power supply terminals is larger than that of other connectors. For example, the number of terminals (six) for 12V DC voltage (DC12VB) of connector CN3Q is greater than the number of terminals (two) for 12V DC voltage (DC12VB) of connector CN1Q.

Connector CN4Q is connected to a position detection switch.
The first pin is a 12V DC voltage (DC12VB), and the second pin is a ground terminal. The third pin becomes an input terminal for the sense signal SENSv7 from the connected position detection switch.

Note that conductor points P1 and P2 on the housings of the connectors CN1Q, CN2Q, CN3Q, and CN4Q are connected to the ground for the purpose of mounting strength.

In this panel back lower relay board 800, signals and voltages supplied through connector CN1Q are distributed downstream through connectors CN2Q, CN3Q, and CN4Q.
In connector CN1Q, 12V DC voltage (DC12VB) is inputted through two terminals, 4th pin and 6th pin, but in connector CN3Q, 12V DC voltage (DC12VB) is input downstream through 6 terminals from 1st pin to 6th pin. Sending. As a result, the number of downstream terminals (the total number of terminals of connectors CN2Q, CN3Q, and CN4Q) is greater than the number of upstream terminals (the number of terminals of connector CN1Q).

[5.17 Decorative board 820]

The decorative substrate 820 will be explained using FIG. 48.
A connector CN1S is mounted on the decorative board 820.
The transmission line end of the transmission line H31 connecting between the connector CN1S and the connector CN3Q of the lower panel relay board 800 in FIG. 47 is connected to the connector CN1S.
Therefore, this connector CN1S has a 10-terminal configuration from the 1st pin to the 10th pin as indicated by the numbers "1" to "10", and the terminal assignments are the same as those of the connector CN3Q described above.

The decorative board 820 is provided with a light emitting section 821 having four LED circuits, each of which is driven to emit light by a light emitting drive current 13-B7, 13-R8, 13-G8, 13-B8 via a connector CN1S. A 12V DC voltage (DC12VB) supplied through the connector CN1S is applied to the anode side of the LED of the light emitting section 821.
This decorative board 820 is placed inside a movable body (not shown), and serves as a board for emitting LED light from a portion of the movable body.

Here, the light emitting unit 821 has nine LED chips as indicated by broken lines as LED1, LED2, . . . LED9. As can be seen from the figure, each LED chip is a full-color LED chip that emits light in each of R, G, and B colors. Note that "GA", "RA", and "BA" in the figure respectively mean the anode of the green LED, the anode of the red LED, and the anode of the blue LED in the full-color LED chip.

This decorative board 820 emits light in two colors, red and green, due to performance specifications. In this case, instead of using single-color red LED chips and green LED chips, full-color LED chips are used. As shown in the figure, the series circuit of blue LEDs that are not used in the full-color LED chip has both its anode and cathode connected to a 12V DC voltage (DC12VB) line, so that no light emitting drive current flows through it. For example, in a series circuit of LED1, LED2, and LED3, three blue LEDs are connected in series, and the anode and cathode sides of the series circuit are connected to a 12V DC voltage (DC12VB) line.

In this configuration, cost reduction can be achieved by arranging one full-color LED chip instead of the usual two single-color LED chips for red and green.
Furthermore, if a terminal for the light emission drive current is connected to each of the three terminals R, G, and B in a full-color LED chip, the number of terminals (pins) of the connector CN1S will increase, and the light emission drive current used in the LED driver will increase. The number of terminals will also increase. Therefore, as described above, no light emission driving current is supplied to unused blue LEDs. This simplifies the connector configuration, LED driver configuration, and wiring, and reduces costs.

In addition, if you leave the terminals (BA) of unused colors unconnected, there is a possibility that they will emit light unintentionally due to noise, etc., so connect the anode side and cathode side to the 12V DC voltage (DC12VB) line, and unintentionally emit light. is prevented.

Note that unused terminals (blue LED anode/cathode) in the full-color LED chip may be left unconnected.
Further, if the board has a ground, the ground may be connected to both ends of unused terminals in the full-color LED chip.

Furthermore, in the decorative board 820 of FIG. 48, resistors R1S, R3S, and R5S are connected to the green LED system of the full-color LED chip, and resistors R2S, R4S, and R6S are connected to the red LED system, but these are not used. Since no current flows through the terminal (BA) of the blue LED, no resistor is connected to the blue LED system. This also facilitates circuit simplification and cost reduction.

<6. Other examples of board connection configurations>
[6.1 Connection status of each board]

Here, an example replacing the connection configuration shown in FIG. 11 is shown in FIG.
In FIG. 49, blocks that are the same as those in FIG. 11 are given the same reference numerals and their explanations will be omitted. The example in FIG. 49 is an example in which an LED connection board 1500 is used instead of the LED connection board 700 on the game board 3 side in FIG.

The LED connection board 1500 is connected downstream of the production control board 30 by a transmission line H50. The LED connection board 1500 performs various necessary signal processing for driving the performance means such as LEDs and motors on the game board 3 to emit light based on control signals from the performance control board 30.

In FIG. 49, an LED board 1600 is illustrated as downstream of the LED connection board 1500. The LED board 1600 may be connected to the LED connection board 1500 via a relay board (not shown) or another LED board, or may be directly connected to the LED connection board 1500. In FIG. 49, it is assumed that the LED board 1600 is one of a plurality of boards connected downstream of the LED connection board 1500.
In the configuration shown in FIG. 49, downstream of the LED connection board 1500, each board from the back left relay board 720 to the LED board 790 shown in FIG. 11, the back bottom relay board 800 and the decorative board 820, etc. may be connected in parallel with the LED board 1600.

[6.2 LED connection board 1500]
The LED connection board 1500 will be explained using FIGS. 50, 51, 52, 53, 54, 55, 56, and 57. These figures separately show the circuit configuration provided on the LED connection board 1500.

The LED connection board 1500 includes connectors CN1V, CN2V, CN3V in FIG. 50, connectors CN4V to CN8V in FIG. 51, connectors CN9V to CN16V in FIG. 52 or 53, connectors CN17V to CN20V in FIG. 54, and connectors in FIG. CN21V to CN25V and connectors CN26V to CN28V shown in Figure 56 are installed.

The connector CN1V in FIG. 50 is connected to the transmission line end of the transmission line H50 that connects with the production control board 30 as shown in FIG. 49.
This connector CN1V has 40 terminals from the 1st pin to the 40th pin as indicated by numbers "1" to "40".

1st pin, 2nd pin, 8th pin, 9th pin, 10th pin, 16th pin, 18th pin, 19th pin, 20th pin, 22nd pin, 29th pin, 32nd pin of connector CN1V , the 33rd pin, the 34th pin, the 39th pin, and the 40th pin are connected to the ground.
The fourth pin and the sixth pin are terminals for a 5V direct current voltage (DC5VB).
The 12th pin, 14th pin, 24th pin, 26th pin, 28th pin, and 30th pin are terminals for 12V DC voltage (DC12VB).
The 36th pin and the 38th pin are terminals for 35V direct current voltage (DC35V).
The 17th pin is unused.

The third pin is the clock signal LSI_SCK for the LSI as the motor driver control unit 1530 in FIG. 55, the fifth pin is the SPI bus slave selection signal LSI_SS for the LSI, the seventh pin is the serial data signal LSI_MOSI for the LSI, and the eleventh pin is is assigned as a hardware reset signal LSI_RESET for the LSI, and the 35th pin is assigned as a serial data signal LSI_MISO output from the LSI.
The clock signal LSI_SCK and the serial data signal LSI_MOSI are signals sent from the production control board 30 for motor drive control.
The serial data signal LSI_MISO is serial data transmitted from this LED connection board 1500 to the upstream production control board 30.

The 13th pin is assigned as a clock signal CLK_P, and the 15th pin is assigned as a serial data signal DATA_P terminal.
The 31st pin is assigned as a terminal for the load signal S_IN_LOAD. The load signal S_IN_LOAD is a signal used for P/S conversion.

After passing through the buffer circuit 1501, the clock signal CLK_P and the serial data signal DATA_P are branched into the following four systems by the buffer circuit 1502.
Clock signal CLK_A, serial data signal DATA_A
Clock signal CLK_B, serial data signal DATA_B
Clock signal CLK_C, serial data signal DATA_C
Clock signal CLK_D, serial data signal DATA_D

The clock signal CLK_A and the serial data signal DATA_A are supplied to the LED drivers 1510 and 1511 in FIG. 52 as signals for effect control.
The clock signal CLK_B and the serial data signal DATA_B are supplied to the LED drivers 1520, 1521, and 1522 in FIGS. 53 and 54 as signals for effect control.

The clock signal CLK_C and the serial data signal DATA_C are signals for effect control that are sent to the effect driving means on the downstream board, and are sent from the connector CN2V in FIG. 50 to the downstream board.
The clock signal CLK_D and the serial data signal DATA_D are signals for effect control that are sent to the effect driving means on the downstream board, and are sent from the connector CN3V to the downstream board.

The 21st pin of the connector CN1V in FIG. 50 is assigned as a reset signal RESET_M, the 23rd pin as a clock signal CLK_M/S, the 25th pin as a serial data signal DATA_M, and the 27th pin as a latch signal LATCH_M.
The reset signal RESET_M, clock signal CLK_M/S, serial data signal DATA_M, and latch signal LATCH_M are signals used by the motor driver 1505 in FIG. 51. Note that the clock signal CLK_M/S is supplied to the motor driver 1505 as the clock signal CLK_M via the buffer circuit 1503 in FIG.

The 37th pin of connector CN1V is assigned as a terminal for serial data signal S_IN_DATA.
The serial data signal S_IN_DATA is serial data transmitted from this LED connection board 1500 to the production control board 30. Clock signal CLK_M/S is supplied as clock signal S_IN_CLK to P/S conversion circuit 1504 via buffer circuit 1503 to output serial data signal S_IN_DATA.

Note that the conductor points P1 and P2 on the housing of the connector CN1V and each of the other connectors CN2V to CN28V are connected to the ground for the purpose of mounting strength.

Connector CN2V in FIG. 50 is a connector connected to the downstream board.
The fourth, sixth, and eighth pins of connector CN2V are connected to ground.
The first pin is a 12V DC voltage (DC12VB) terminal.
The second pin is a 5V DC voltage (DC5VB) terminal.
The third pin is used as a terminal for the clock signal CLK (CLK_C).
The fifth pin is used as a terminal for serial data signal DATA (DATA_C).
The seventh pin is a terminal to which a sense signal +P0x from the downstream side is input.
The 9th pin, 10th pin, 11th pin, and 12th pin are terminals for motor drive signals MOTxA+, MOTxB-, MOTxA-, and MOTxB+.

Connector CN3V is also a connector connected to the downstream board, and is provided with terminals for 12V DC voltage (DC12VB), serial data signal DATA (DATA_D), clock signal CLK (CLK_D), and ground.

Connector CN4V in FIG. 51 is connected to a motor of a movable object (not shown). A 12V DC voltage (MOT12V), which is the power supply voltage of the motor, is applied to the third pin. Terminals for motor drive signals MOT1-/2, MOT1-/1, MOT1-/2, and MOT1-1 are provided.
Connectors CN6V, CN7V, and CN8V are connectors into which sense signals SENS0, SENS1, and SENS2 are input from various sensors, respectively.

Connectors CN9V to CN16V in FIG. 52 or 53 are connectors connected to a downstream LED board (not shown). These are each provided with a terminal for outputting a light emission drive current to the corresponding LED board.
Connectors CN17V to CN20V in FIG. 54 are also connectors connected to a downstream LED board (not shown). These are each provided with a terminal for outputting a light emission drive current to the corresponding LED board.

Connectors CN21V to CN25V in FIG. 57 are connectors to which sense signals +P0y, +P0z, +P0u, +P1z, and +P1u are input from various sensors, respectively.
Connectors CN26V to CN28V in FIG. 56 are connectors each connected to a downstream motor (not shown).
Connector CN26V is provided with terminals for motor drive signals MOTuA+, MOTuB-, MOTuA-, MOTuB+.
The connector CN27V is provided with terminals for motor drive signals MOTzB+, MOTzA-, MOTzB-, and MOTzA+.
Connector CN28V is provided with terminals for motor drive signals MOTyB+, MOTyA-, MOTyB-, and MOTyA+.

The power supply voltage in this LED connection board 1500 will be explained.
The LED connection board 1500 is equipped with buffer circuits 1501, 1502, 1503 in FIG. 50, which are 8-circuit Schmitt trigger buffers similar to the buffer circuit 402 previously explained in FIG. 13, and a buffer circuit 1540 in FIG. 57 as ICs. be done. Furthermore, a P/S conversion circuit 1504 shown in FIG. 50 is installed.
As the power supply voltage for these, a 5V DC voltage (DC5V) based on a 5V DC voltage (DC5VB) from the connector CN1V is used.
The 5V DC voltage (DC5VB) is taken out from the positive electrode side of the capacitor C3V from the connector CN1V via the fuse F1J. Note that the P/S conversion circuit 1504 is an IC similar to the P/S conversion circuit 505 in FIG.

Further, the motor driver 1505 of FIG. 51 is mounted as an IC on the LED connection board 1500, and a 12V motor drive voltage (MOT12V) and a 12V direct current voltage (DC12VS) are used as power supply voltages for this.

The 12V motor drive voltage (MOT12V) and the 12V DC voltage (DC12VS) are separated from the 12V DC voltage (DC12VB) by power separation/protection circuits 1551 and 1552 shown in FIG.

Further, a motor driver control section 1530 shown in FIG. 55 is mounted as an IC on the LED connection board 1500, and a 5V motor drive voltage (DC5V) is used as the power supply voltage for this.

Further, the LED connection board 1500 is equipped with a motor driver 1532 in FIG. 55 and motor drivers 1533, 1534, and 1535 in FIG. 56 as stepping motor drivers. As power supply voltages for these, 35V motor drive voltage (MOT35Vx) (MOT35Vy) (MOT35Vz) (MOT35Vu), 5V direct current voltage (DC5V), voltage VCCx, voltage VCCy, voltage VCCz, and voltage VCCu are used.

The 35V motor drive voltage (MOT35Vx) (MOT35Vy) (MOT35Vz) (MOT35Vu) is separated from the 35V direct current voltage (DC35V) by a power separation/protection circuit 1553 shown in FIG.
Voltage VCCx, voltage VCCy, voltage VCCz, and voltage VCCu are voltages obtained from the 34th terminal (internal regulator monitor terminal) of motor drivers 1532, 1533, 1534, and 1535, respectively.

Furthermore, LED drivers 1510, 1511, 1520, 1521, and 1522 shown in FIGS. 52, 53, and 54 are mounted as ICs on the LED connection board 1500, and the power supply voltage for these is 12V DC voltage (DC12VB). I am using it.

The flow of various signals in the LED connection board 1500 will be explained below.
A clock signal LSI_SCK, a serial data signal LSI_MOSI, a slave selection signal LSI_SS, and a hardware reset signal LSI_RESET are sent from the production control board 30 to the connector CN1V in FIG. 50 for motor drive control. .

After each of these signals is compensated by the buffer circuit 1501, it is supplied to the motor driver control section 1530 in FIG. 55 via the chip resistor RA1V or RA2V.
Motor driver control section 1530 controls motor drivers 1532, 1533, 1534, and 1535 based on clock signal LSI_SCK and serial data signal LSI_MOSI.

Specifically, motor driver control section 1530 outputs X-axis output pulses OUTx, DIRx, and P3x to motor driver 1532. Motor driver 1532 generates motor drive signals MOTxA+, MOTxB-, MOTxA-, and MOTxB+ in response to this, and supplies them to connector CN2V in FIG. 50.

Further, the motor driver control section 1530 outputs Y-axis output pulses OUTy, DIRy, and P3y to the motor driver 1533 in FIG. 56.
Note that the connections between FIG. 55 and FIG. 56 are indicated by "c2", "c3", and "c4".
The motor driver 1533 generates motor drive signals MOTyB+, MOTyA-, MOTyB-, and MOTyA+ according to the Y-axis output pulses OUTy, DIRy, and P3y, and supplies them to the connector CN28V.
The motor driver control section 1530 also outputs Z-axis output pulses OUTz, DIRz, and P3z to the motor driver 1534. The motor driver 1534 generates motor drive signals MOTzB+, MOTzA-, MOTzB-, and MOTzA+ in response to this, and supplies them to the connector CN27V.
Further, the motor driver control section 1530 outputs U-axis output pulses OUTu, DIRu, and P3u to the motor driver 1535. The motor driver 1534 generates motor drive signals MOTuA+, MOTuB-, MOTuA-, MOTuB+ in response to this, and supplies them to the connector CN26V.

Connectors CN26V, CN27V, and CN28V are connected to movable motors (not shown).
Furthermore, the connector CN2V in FIG. 50 is connected to a downstream board, and motor drive signals MOTxA+, MOTxB-, MOTxA-, MOTxB+ from the motor driver 1532 are supplied to a movable motor (not shown) via the downstream board.
Therefore, the motor driver control unit 1530 in FIG. 55 has a function of driving these movable motors based on the clock signal LSI_SCK and the serial data signal LSI_MOSI.

The motor driver control unit 1530 receives sense signals +P0x, +P0y, +P0z, +P0u, +P1z, +P1u from various sensors input from connector CN2V in FIG. 50 and connectors CN21V to CN25V in FIG. It is input via a buffer circuit 1540. Sense signals +P0x, +P0y, +P0z, +P0u, +P1z, and +P1u are signals for detecting the position of each movable body.
Note that the connection between FIG. 55 and FIG. 57 is indicated by "c1".
The motor driver control unit 1530 converts these sense signals +P0x, +P0y, +P0z, +P0u, +P1z, and +P1u into serial data and outputs the serial data signal LSI_MISO. In other words, the motor driver control section 1530 also functions as a P/S conversion circuit.
The serial data signal LSI_MISO obtained by the motor driver control unit 1530 is signal-compensated by the buffer circuit 1501 in FIG. 50 and is supplied to the connector CN1V.

Note that sense signals SENS0, SENS1, and SENS2 are input from connectors CN6V, CN7V, and CN8V in FIG. 51. These sense signals SENS0, SENS1, and SENS2 are also signals for detecting the position of each movable body. Note that the signal may be a signal from a motion sensor that detects a player's movement or a proximity sensor that detects a game ball.
The input sense signals SENS0, SENS1, SENS2 are input to the P/S conversion circuit 1504 in FIG. 50 and converted into the serial data signal S_IN_DATA.
This serial data signal S_IN_DATA is signal compensated by the buffer circuit 1503 and supplied to the connector CN1V.
These serial data signal LSI_MISO and serial data signal S_IN_DATA will be transmitted to the production control board 30 as signals obtained by converting detection signals of various sensors into serial data.

Clock signal CLK_P and serial data signal DATA_P input from connector CN1V are signal compensated by buffer circuit 1501 and then supplied to buffer circuit 1502 via chip resistor RA2V. As described above, the clock signal CLK_P and the serial data signal DATA_P are signal-compensated by the buffer circuit 1502 and then branched into four systems, two of which are the clock signal CLK_C, the serial data signal DATA_C, and the clock signal CLK_D. The serial data signal DATA_D is transmitted to the downstream board from connectors CN2V and CN3V, respectively.

Clock signal CLK_A and serial data signal DATA_A from buffer circuit 1502 are supplied to LED drivers 1510 and 1511 in FIG. 52.

The LED driver 1511 generates 20 systems of LED light emission using output terminals LEDR1, LEDG1, LEDB1...LEDR6, LEDG6, LEDB6 and output terminals LEDR8, LEDG8 for light emission drive current based on the clock signal CLK_A and the serial data signal DATA_A. Drive.

Among these output terminals, the output terminals LEDR1, LEDG1, LEDB1...LEDR3, LEDG3, LEDB3 are connected to the 2nd pin to the 10th pin of the connector CN10V, and are connected to the 9 systems of LED circuits on the LED board (not shown). The configuration is such that a light emission drive current (08-R1, 08-G1, 08-B1...08-R3, 08-G3, 08-B3) is passed through the LEDs.
In addition, the output terminals LEDR4, LEDG4, LEDB4...LEDR6, LEDG6, LEDB6 are connected to the 2nd pin to the 10th pin of the connector CN14V, and the light emission drive current ( 08-R4, 08-G4, 08-B4...08-R6, 08-G6, 08-B6).

Note that each of the first pins of the connectors CN10V and CN14V is a pin that supplies 5V direct current voltage (DC5V) to the downstream LED board.

The LED driver 1510 drives 21 LEDs to emit light based on the clock signal CLK_A and the serial data signal DATA_A using the output terminals LEDR1, LEDG1, LEDB1, . . . LEDR7, LEDG7, LEDB7 for emitting drive currents.

Among these output terminals, the output terminals LEDR1, LEDG1, LEDB1...LEDR4, LEDG4, LEDB4 are connected to the 2nd pin to the 13th pin of the connector CN9V, and are connected to the 12 systems of LED circuits on the LED board (not shown). The configuration is such that a light emission drive current (07-R1, 07-G1, 07-B1...07-R4, 07-G4, 07-B4) is passed through the LEDs.
Further, the output terminals LEDR5, LEDG5, LEDB5...LEDR7, LEDG7, LEDB7 are connected to the 2nd pin to the 10th pin of the connector CN13V. Output terminals LEDR8 and LEDG8 of the LED driver 1511 are connected to the 11th pin and the 12th pin. As a result, the light emitting drive current (07-R5, 07-G5, 07-B5...07-R7, 07-G7, 07-B7, and 08-R8 , 08-G8).
Note that each of the first pins of the connectors CN9V and CN13V is a pin that supplies 12V DC voltage (DC12VB) to the downstream LED board.

The clock signal CLK_B and serial data signal DATA_B from the buffer circuit 1502 in FIG. 50 are supplied to the LED drivers 1520, 1521, and 1522 in FIGS. 53 and 54.

The LED driver 1520 drives 24 LEDs to emit light based on the clock signal CLK_B and the serial data signal DATA_B using output terminals LEDR1, LEDG1, LEDB1, . . . LEDR8, LEDG8, LEDB8 for light emitting drive current.

Among these output terminals, the output terminals LEDR1, LEDG1, LEDB1...LEDR5, LEDG5, LEDB5 are connected to any of the 2nd pin to the 16th pin of the connector CN12V, and are connected to 15 systems of LEDs on an LED board (not shown). The configuration is such that a light emission drive current (09-R1...09-B5) flows through the circuit.
In addition, the output terminals LEDR6, LEDG6, LEDB6...LEDR8, LEDG8, LEDB8 are connected to the 2nd pin to the 10th pin of the connector CN16V, and the light emission drive current ( 09-R6, 09-G6, 09-B6...09-R8, 09-G8, 09-B8).

Note that each first pin of the connectors CN12V and CN16V is a pin that supplies 12V DC voltage (DC12VB) to the downstream LED board. A fuse F6V is connected to the first pin of the connector CN16V.

The LED driver 1521 drives 24 LEDs to emit light based on the clock signal CLK_B and the serial data signal DATA_B using output terminals LEDR1, LEDG1, LEDB1...LEDR8, LEDG8, LEDB8 for light emitting drive current.

Among these output terminals, the output terminals LEDR1, LEDG1, LEDB1...LEDR5, LEDG5, LEDB5 are connected to any of the 2nd pin to the 16th pin of the connector CN11V, and are connected to 15 systems of LEDs on an LED board (not shown). The configuration is such that a light emission drive current (10-R1...10-B5) is passed through the circuit.
In addition, the output terminals LEDR6, LEDG6, LEDB6...LEDR8, LEDG8, LEDB8 are connected to the 2nd pin to the 10th pin of the connector CN15V, and the light emission drive current ( 10-R6, 10-G6, 10-B6...10-R8, 10-G8, 10-B8).

Note that each first pin of the connectors CN11V and CN15V is a pin that supplies 12V DC voltage (DC12VB) to the downstream LED board. A fuse F5V is connected to the first pin of the connector CN15V.

The LED driver 1522 in FIG. 54 drives 17 systems of LED light emission using the light emission drive current output terminals LEDR1...LEDR4 and the output terminals LEDR5...LEDR7 based on the clock signal CLK_B and the serial data signal DATA_B. conduct.

The output terminals LEDR1...LEDR4 are connected to the 2nd pin to the 11th pin of the connector CN17V, and provide light emitting drive current (11-R1...11-R4) to the 10 systems of LED circuits on the LED board (not shown). ) is configured to flow.
In addition, the output terminals LEDR5, LEDG5, and LEDB5 are connected to the second to fourth pins of the connector CN19V, and the light emission drive current (11-R5, 11-G5, 11-B5).
In addition, the output terminals LEDR6, LEDG6, and LEDB6 are connected to the second to fourth pins of the connector CN20V, and the light emission drive current (11-R6, 11-G6, 11-B6).
Further, the output terminal LEDR7 is connected to the second pin of the connector CN18V, and is configured to flow a light emission drive current (11-R7) to one system of LED circuits on an LED board (not shown).

Note that each of the first pins of the connectors CN17V, CN18V, CN19V, and CN20V is a pin that supplies 12V DC voltage (DC12VB) to the downstream LED board.

The reset signal RESET_M, clock signal CLK_M/S (clock signal CLK_M), serial data signal DATA_M, and latch signal LATCH_M input from the connector CN1V in FIG. and is supplied to the motor driver 1505 in FIG.

The motor driver 1505 generates motor drive signals MOT1-/2, MOT1-/1, MOT1-/2, and MOT1-1 based on the clock signal CLK_M and the serial data signal DATA_M, and supplies them to the connector CN4V. Connector CN4V is connected to a movable motor (not shown).
Therefore, the motor driver 1505 drives the movable motor based on the clock signal CLK_M and the serial data signal DATA_M.

As described above, the LED connection board 1500 has the following configuration.
- Sense signals SENS0, SENS1, SENS2 inputted from the downstream side are converted into serial data by the P/S conversion circuit 1504, and transmitted as a serial data signal S_IN_DATA from the connector CN1V to the upstream side via the buffer circuit 1503.
- Sense signals +P0x, +P0y, +P0z, +P0u, +P1z, +P1u input from the downstream side are supplied to the motor driver control unit 1530 via the buffer circuit 1540 and converted into serial data. The serial data signal LSI_MISO is transmitted to the upstream side from the connector CN1V via the buffer circuit 1501.

- Transfer the clock signal CLK_P (CLK_C, CLK_D) and serial data signal DATA_P (DATA_C, DATA_D) transmitted from the production control board 30 to the downstream side via the buffer circuits 1501 and 1502.
- Supply clock signal CLK_P (CLK_A, CLK_B) and serial data signal DATA_P (DATA_A, DATA_B) sent from production control board 30 to LED drivers 1510, 1511, 1520, 1521, 1522 to drive LED light emission. Execute.

- Supply the clock signal LSI_SCK and serial data signal LSI_MOSI transmitted from the production control board 30 to the motor driver control unit 1530 to drive the motor. The drive system is bipolar.
- Supply the clock signal CLK_M and serial data signal DATA_M transmitted from the production control board 30 to the motor driver 1505, generate a motor drive signal, and send it to the downstream motor/board. The drive system is unipolar.
Bipolar drive and unipolar drive are used as motor drive systems, but bipolar drive with high torque is used for large movable objects, and unipolar drive with low cost is used for small movable objects. The aim is to reduce driving force and cost.

- Receives 12V DC voltage (DC12VB), 5V DC voltage (DC5VB), and 35V DC voltage (DC35V) through connector CN1V and uses it as an operating power source.
- 12V DC voltage (DC12VB) and 5V DC voltage (DC5V) are supplied to the downstream side as operating power supply voltages.

In addition, in the LED connection board 1500, as shown in FIGS. 50 to 57, including those mentioned above, resistors R1V, R2V, etc., chip resistors RA1V, RA2V, etc., and capacitors C1V, C2V are installed at required locations. ..., diodes (including Zener diodes and Schottky barrier diodes) D1V, D2V..., fuses F1V, F2V..., transistors (FET) Q1V, Q2V..., oscillator X1V, and other electronic elements are connected. be done. Further, as shown in the figure, taps TP1V, TP2V, . . . are provided and used for connection to required locations.
Some of the capacitors C1V, C2V, etc. are placed between the 5V DC or 12V DC power supply line and the ground in order to reduce power supply noise.

By the way, the 5V DC voltage (DC5VB) may be generated based on, for example, the 12V DC voltage (DC12VB) without receiving the 5V DC voltage (DC5VB) from the upstream board.

[6.3 LED board 1600]

FIG. 58 shows the configuration of the LED board 1600 shown in FIG. 49.
A connector CN1W is mounted on the LED board 1600.

The transmission line end of the transmission line connecting between the connector CN1W and the connector on the downstream board (not shown) of the LED connection board 1500 is connected.

This connector CN1W has 7 terminals from the 1st pin to the 7th pin as indicated by the numbers "1" to "7", and the terminals are assigned in order from the 1st pin to the ground terminal and the clock signal CLK. A terminal, a ground terminal, a 5V DC voltage (DC5V) terminal, a serial data signal DATA terminal, a reset signal RESET terminal, and a 12V DC voltage (DC12VB) terminal.

Note that the conductor points P1 and P2 on the housing of the connector CN1W are connected to the ground for the purpose of mounting strength.

An LED driver 1601 is mounted on the LED board 1600. A 12V direct current voltage (DC12VB) is used as a power supply voltage for the LED driver 1601. A 12V DC voltage (DC12VB) is supplied from the seventh pin of the connector CN1W.

The flow of various signals in the LED board 1600 will be explained.
The clock signal CLK, data signal DATA, and reset signal RESET supplied from the upstream board to the connector CN1W are supplied to the LED driver 1601.
The LED driver 1601 drives 15 systems of LED light emission using output terminals LEDR1, LEDG1, LEDB1, . . . LEDR5, LEDG5, LEDB5 for light emission drive current.
These output terminals LEDR1, LEDG1, LEDB1, . B1...20-R5, 20-G5, 20-B5).
As shown in the figure, each system of LED circuits of the light emitting section 1602 is composed of two LEDs (LED1, LED2, . . . ) connected in series and a resistive element. The LED circuits of each system are connected in parallel, and a 12V DC voltage (DC12VB) is applied to each anode side.

As described above, the LED board 780 has the following configuration.
- The LED driver 1601 drives the light emitting unit 1602 to emit light based on the clock signal CLK and data signal DATA transmitted from upstream.

- Receives 12V DC voltage (DC12VB) through connector CN1W and uses it as an operating power source.

In addition to those mentioned above, on the LED board 1600, as shown in FIG. 58, electronic elements such as resistors R1W, R2W, . . . , capacitors C1W, C2W, . . . are connected at required locations. Further, as shown in the figure, taps TP1W, TP2W, . . . are provided and used for connection to required locations.

<7. Explanation of notable configurations＞
Hereinafter, notable configurations among the configurations of the gaming machine 1 described so far will be sequentially explained.

[7.1 Relationship between the connector terminal and the terminal of the production driving means]

First, the relationship between the connector terminals on various boards and the terminals of the effect driving means will be explained.
Note that the effect driving means is a general term for circuit parts that drive the effect device, such as light emission driving means and motor driving means. Specifically, it collectively refers to an LED driver, a motor driver, a driver control unit that controls these, and a circuit portion that functions as an S/P conversion circuit for motor drive control.
In particular, the "terminal" of the effect driving means refers to the terminal of a chip that is mounted as a chip component (IC chip) and functions as an LED driver, motor driver, driver control section, S/P conversion circuit, etc.

The gaming machine 1 of the embodiment has the following (configuration A1-1).
(Configuration A1-1)
The gaming machine 1 is
a first board provided with a first effect driving means using a chip component, and a first connector for inputting a clock and effect driving control data to the first effect driving means;
a second board provided with a second effect driving means using a chip component and a second connector for inputting a clock and effect driving control data to the second effect driving means;
Equipped with
In the first substrate,
The first effect driving means and the first connector are arranged on the same surface of the board,
the left-right relationship of each input terminal of the clock and the control data for effect driving in the first effect driving means, when looking from the pattern wiring side to the chip side;
the left-right relationship of each connector terminal of the clock and production drive control data in the first connector when looking in the direction in which pattern wiring connected to each connector terminal is led from the connector terminal side;
are the same,
In the second substrate,
The second effect driving means and the second connector are arranged on the same surface of the board,
The left-right relationship of each connector terminal of the clock and production drive control data in the second connector when looking from the connector terminal side to the direction in which the pattern wiring connected to each connector terminal is led is as follows. It is the same as the connector of 1,
The left-right relationship of the input terminals of the clock and the control data for effect driving in the second effect driving means when viewed from the pattern wiring side to the chip side is the same as that of the first effect driving means.

FIG. 59 schematically shows the configurations of the first and second substrates.
Although various configurations are schematically shown below, each figure mainly shows the connector and the effect driving means as blocks, and also shows "clock CK", "data DT", and "pattern wiring PTH".
Specific examples of the clock CK and data DT will be described respectively, but these refer to the clock and effect drive control data supplied from the connector to the effect driving means on the board.
The same applies to each figure schematically showing the configurations of (configuration A1-2) to (configuration A9-3) to be described later.

The pattern wiring PTH refers to pattern wiring for supplying the clock CK and data DT from the connector to the performance driving means.
Note that there may be cases where a resistive element or the like is interposed between the connector and the effect driving means, but in such a case, the structure of the schematic diagram does not cease to apply. In other words, even if another element is interposed between the connector and the effect driving means, it is only necessary to satisfy the illustrated configuration between the connector and the effect driving means. To be more precise, as long as the left-right relationship between the clock CK and data DT wiring is not reversed in the element interposed between the connector and the production drive means, it can be considered to fall under the following configuration, ignoring them. It is something.
Further, the IC chip as a buffer circuit connected to the signal path between the connector and the effect driving means can be considered as part of the effect driving means, but there is also the idea that it is excluded from the effect driving means in a narrower sense. Even if the buffer circuit is not included in the effect driving means, as long as the buffer circuit is interposed between the connector and the effect driving means and the left-right relationship of the clock CK and data DT wiring is not reversed, the buffer circuit Ignoring this, it can be considered that the following configuration applies.
The above should be considered in the same way for (configuration A1-2) to (configuration A9-3), which will be described later.

As shown in FIG. 59, a first connector and a first effect driving means are mounted on the first board.
The first connector and the first effect driving means are arranged on the same surface on the first board. In the figure, the blocks of the first connector and the first effect driving means are shown by solid lines, which indicates that they are arranged on the plane shown in the figure.
In addition, "○" in the blocks used as connectors and effect driving means indicates terminals.

The first connector inputs a clock CK and performance drive control data (data DT) to the first performance drive means.
The clock CK and data DT are supplied to the first effect driving means by pattern wiring PTH on the board. The connection is not limited to the case where the connection is made only by the pattern wiring PTH as described above, but there is also a case where a resistance element or a chip is interposed. Furthermore, some wiring may be formed on the other surface of the substrate via through holes as necessary. Although these matters will not be mentioned repeatedly in each example, the same applies to the pattern wiring PTH in other configuration examples described later.

A second connector and a second effect driving means are mounted on the second board.
The second connector and the second effect driving means are arranged on the same surface on the second board.
The second connector inputs the clock CK and performance drive control data (data DT) to the second performance drive means.
The clock CK and data DT are supplied to the second effect driving means by pattern wiring PTH on the board.
The first effect driving means and the second effect driving means have the same left-right relationship between the clock CK and data DT terminals, so they are shown by the same rectangle.

In this case, attention is paid to directions DIR1, DIR2, DIR3, and DIR4 indicated by arrows.
Directions DIR1 and DIR3 are directions from the respective connector terminals of the clock CK and data DT to the direction in which the pattern wiring PTH connected to each connector terminal is led out.
Directions DIR2 and DIR4 are directions from the pattern wiring PTH side of each input terminal of the clock CK and data DT in the effect driving means toward the chip (=the chip that is the effect driving means) side.

The left-right relationship between the clock CK terminal and the data DT terminal when viewed in directions DIR1, DIR2, DIR3, and DIR4 is shown in the lower part of FIG.

What is the left-right relationship when viewed in directions DIR1 and DIR3?
"The left-right relationship of the clock CK and data DT connector terminals in the connector when looking from the connector terminal side to the direction in which the pattern wiring PTH connected to each connector terminal is led"
It is.
In the example of FIG. 59, as shown, the clock CK terminal is on the left and the data DT terminal is on the right.

Note that the left-right relationship when viewed in directions such as directions DIR1 and DIR3 can also be expressed as in the following examples, and any one of them may apply.
"The left-right relationship of the clock CK and data DT connector terminals in the connector when looking from the connector side to the pattern wiring PTH side"
"The left-right relationship of the clock CK and data DT connector terminals in the connector when looking in the direction of the connector side from which the pattern wiring PTH connected to each connector terminal is derived from the connector terminal side"

Also, the left-right relationship when viewed in directions DIR2 and DIR4 is
"The left-right relationship between the input terminals of the clock CK and the control data for driving the performance DT in the performance driving means, when looking from the pattern wiring PTH side to the chip (=chip of the performance driving means) side"
It is.
In the example of FIG. 59, as shown, the clock CK terminal is on the left and the data DT terminal is on the right.

Note that the left-right relationship when viewed in directions such as directions DIR2 and DIR4 can also be expressed as in the following examples, and it is sufficient if it corresponds to any one of them.
"The left-right relationship between the input terminals of the clock CK and data DT in the production driving means when viewed from the side of the chip where the input terminals are located"
"The left-right relationship between the input terminals of the clock CK and data DT in the performance driving means when looking at the chip side along the introduction direction of the pattern wiring PTH connected to each input terminal"

In these directions, when the left-right relationship between the connector terminals and the left-right relationship between the terminals of the effect driving means are the same, it is assumed that the connector and the effect driving means are placed on the same surface of the board, and their corresponding terminals are the same. Even if it is assumed that the terminals are placed facing each other and the wiring is connected with the shortest distance between each terminal, the left-right relationship can be said to be such that the wiring does not cross.

In the example of FIG. 59, the left-right relationship between the clock CK terminal and the data DT terminal is all the same when viewed in the directions DIR1, DIR2, DIR3, and DIR4.

Note that the left-right relationship is the same as in the case where the clock CK terminal is on the left and the data DT terminal is on the right, or even when the clock CK terminal is on the right and the data DT terminal is on the left. good. This point is also the same for each configuration described below other than (configuration A1-1).

The configuration shown in FIG. 59 corresponds to the above (configuration A1-1).
The following (specific example 1) is assumed as an example corresponding to this (configuration A1-1).

(Specific example 1)
・First board: LED board 780 (see Figure 45)
・Second board: LED board 790 (see Figure 46)
・Clock (CK) for the first performance driving means: clock signal CLK
- Effect driving control data (DT) for the first effect driving means: data signal DATA
・First effect driving means: LED driver 782
・Clock input terminal in the first production driving means: No. 2 terminal (SCLK terminal)
・Input terminal for control data for performance drive in the first performance drive means: No. 3 terminal (SDATA terminal)
・First connector: Connector CN1N
・Clock connector terminal of the first connector: 2nd pin ・Connector terminal of the control data for driving the effect of the first connector: 3rd pin ・Second effect driving means: LED driver 791
・Clock (CK) for the second performance driving means: clock signal CLK
- Effect driving control data (DT) for the second effect driving means: data signal DATA
・Clock input terminal in the second production driving means: No. 2 terminal (SCLK terminal)
・Input terminal for control data for performance drive in the second performance drive means: No. 3 terminal (SDATA terminal)
・Second connector: Connector CN1X
・Clock connector terminal of the second connector: 2nd pin ・Connector terminal of the production drive control data of the 2nd connector: 3rd pin

An LED board 780 corresponding to the first board in this (Specific Example 1) is shown in FIGS. 60 and 61.
60 shows a conductive pattern on the surface layer of an LED board 780 having the circuit configuration explained in FIG. 45, and FIG. 61 shows a conductive pattern on the back layer.
Note that the back layer in FIG. 61 is shown as a perspective view seen from the front layer side in FIG. 60, and is shown in a horizontally reversed state.
In FIGS. 60 and 61, identification numbers of parts printed on the board are omitted from illustration. The part indicated as "○○+XX△△" actually displays the board management number.

The plurality of light emitting elements mounted on the LED board 780 are light emitting elements LED1 to LED12 as color LED chips and light emitting elements LED14 to LED22 as monochrome LED chips, as shown in a light emitting section 783 in FIG.
"pLED1" to "pLED22" in FIG. 60 (surface layer) are positions (pads or lands serving as contacts, hereinafter collectively referred to as pads) where light emitting elements LED1 to light emitting element LED22 are arranged on the LED board 780, respectively. It shows.
Further, "p782" indicates the position (pad) where the LED driver 782 is arranged, and "pCN1N" and "pCN2N" indicate the positions (pad) where the connectors CN1N and CN2N are arranged. Further, "p781" indicates the position (pad) where the buffer circuit 781 is arranged.

In the connector CN1N, the pad on the upper left side in the drawing is on the first pin side.
In the connector CN2N, the pad on the left side of the drawing is on the first pin side.

As shown in FIGS. 60 and 61, a ground pattern 784 as a solid ground is formed on the front surface layer and the back surface layer, and pattern wiring realizing the circuit configuration of FIG. 45 is formed.
Note that the many small circular portions shown on the pattern represent through holes or vias. Also includes through-hole vias (interlayer wiring) with copper foil. These will also be collectively referred to as "through holes" for the purpose of explanation.

In addition, a power supply pattern 785 for 12V DC voltage (DC12VB) is formed mainly on the back layer from the contact (pad) of the first pin of the connector CN1N via the through hole TH10, as shown in FIGS. 60 and 61. There is.
This back layer power supply pattern 785 is connected to the SVCC terminal of the LED driver 782 through a through hole TH11. It is also connected to the VLED terminal of the LED driver 631 via a through hole TH12.

In the case of the LED board 780, in order to supply 5V DC voltage (DC5V) to the buffer circuit 781, a power supply pattern 786 is formed on the back layer from the contact (pad) of the fifth pin of the connector CN1N through the through hole TH15. It is connected to the buffer circuit 781 through a through hole TH16.

Here, regarding the connector CN1N, the first to sixth pins are shown in an enlarged manner at the lower left of FIG. The left-right relationship as seen in direction DIR1 is that the clock signal CLK terminal (second pin) is on the left, and the data signal DATA terminal (third pin) is on the right.

Further, the LED driver 782 placed at "p782" is placed in the direction (orientation) shown in the enlarged view at the upper left of FIG. 60.

A plan view of the LED driver 782 placed in "p782" is shown in FIG. The LED driver 782 is a rectangular chip component.
In this example, the chip component is approximately square, but it may of course be rectangular.
Also, the corners of the rectangular chip housing are chamfered as shown in the figure, so strictly speaking it is an octagon, but the chamfered parts should not be considered sides, but rather quadrilaterals. I want to be "Square shape" means that it is approximately square, ignoring trivial shapes such as chamfered parts.

Under the above premise, the chip as the LED driver 782 has a rectangular shape and has four sides. The respective sides are defined as side sd1, side sd2, side sd3, and side sd4. The sides sd1 and sd3 are opposite sides, and the sides sd2 and sd4 are opposite sides.
As for the terminals of the LED driver 631 shown in FIG. 62, terminals 1 (VREF) to 12 (A1) are provided on side sd1, and terminals 13 (A2) to 24 (LEDG3) are provided on side sd2. Terminals 25 (LEDB3) to 36 (LEDR6) are provided on side sd3, and terminals 37 (LEDG6) to 48 (SVCC) are provided on side sd4.

The first terminal (VREF) is a 5V reference voltage output terminal.
The second terminal (SCLK) is an input terminal for the clock signal CLK.
The third terminal (SDATA) is an input terminal for the data signal DATA.
The No. 4 terminal (SDEN) is an enable signal input terminal.
The fifth terminal (CTLSCT) is a serial bus communication setting terminal, and the reference voltage from the first terminal, that is, the H level, is input to set a predetermined mode.
The No. 6 terminal (OUTSCT) is an output method control terminal for the LED drive current, and in this example, it is set to the L level by being connected to the ground, and is set to a predetermined mode, for example, constant current output.
Terminal 7 (RESET) is an input terminal for the reset signal RESET.
Terminal 8 (RT1) is a resistor connection terminal for setting the reference current. In this example, a resistor R1T is connected.
Terminal 9 and terminal 31 (NC) are dummy terminals (no internal connection).
Terminal 10 (SGND) is the ground terminal.

Terminals 11 to 15 (A0 to A4) are address terminals for setting slave addresses. In this example, as shown in FIG. 75, A0, A1, and A2 are connected to the ground, and A3 and A4 are connected to the reference voltage of 5V, so that the slave address of the LED driver 631 becomes "00011."

From the 16th terminal to the 45th terminal (excluding the 30th and 31st terminals), LED light emission drive current terminals (LEDR1 to LEDB8) and ground terminals (PGND1 to PGND4) are formed.

The 46th and 47th terminals are used as test terminals and are grounded.
As described above, the 48th terminal (SVCC) is an operating power supply terminal, and the 30th terminal (VLED) is a protection terminal for the LED drive output.

Note that the same type of chip shown in FIG. 62 can also be used for LED drivers mounted on other boards, such as the LED driver 631 on the LED board on the side unit and the LED driver 791 on the LED board 790.

Applying the terminal arrangement of FIG. 62 to FIG. 60, the left-right relationship of the LED driver 782 when viewed in the direction DIR2 is that the clock signal CLK terminal (terminal 2 (SCLK terminal)) is on the left, and the data signal DATA The terminal (terminal 2 (SCLK terminal)) is on the right.

A clock pattern wiring 787 for the clock signal CLK and a signal pattern wiring 788 for the data signal DATA are formed between the connector CN1N and the LED driver 782.

Next, an LED board 790 corresponding to the second board in the above (Specific Example 1) is shown in FIGS. 63 and 64. 63 shows a conductor pattern on the surface layer of an LED board 790 having the circuit configuration explained in FIG. 46, and FIG. 64 shows a conductor pattern on the back layer.
Note that the back layer in FIG. 64 is shown as a perspective view seen from the front layer side in FIG. 63, and is shown in a horizontally reversed state.
In FIGS. 63 and 64, identification numbers of parts printed on the board are omitted from illustration. The part indicated as "X○+○○○" actually displays the board management number.

The plurality of light emitting elements mounted on the LED board 790 are light emitting elements LED1 to LED9 as color LED chips and light emitting elements LED10 to LED17 as monochrome LED chips, as shown in the light emitting section 792 of FIG. 46.
“pLED1” to “pLED17” in FIG. 63 (surface layer) indicate positions (pads) where light emitting elements LED1 to light emitting element LED17 are arranged, respectively, on the LED substrate 790. Further, "p791" indicates the position (pad) where the LED driver 791 is arranged, and "pCN1X" indicates the position (pad) where the connector CN1X is arranged.

As shown in FIGS. 63 and 64, a ground pattern 794 as a solid ground is formed on the front surface layer and the back surface layer, and pattern wiring and through holes for realizing the circuit configuration of FIG. 46 are formed.

Here, regarding the connector CN1X, the first to fourth pins are shown enlarged on the right side of FIG. The left-right relationship as seen in direction DIR3 is that the clock signal CLK terminal (second pin) is on the left, and the data signal DATA terminal (third pin) is on the right.

Further, the LED driver 791 placed at "p791" is placed in the directionality (posture) shown in the enlarged upper right corner of FIG. 63. The terminal arrangement of the LED driver 791 is shown in FIG. 62.
Therefore, when considering the terminal arrangement in FIG. 62 by applying it to FIG. 63, the left-right relationship of the LED driver 791 when viewed in the direction DIR4 is that the clock signal CLK terminal (terminal 2 (SCLK terminal)) is on the left, and the data signal DATA The terminal (terminal 3 (SDATA terminal)) is on the right.

Between the connector CN1X and the LED driver 791, a clock pattern wiring 795 for the clock signal CLK and a signal pattern wiring 796 for the data signal DATA are formed.

Looking at the LED boards 780 and 790 as described above, they have the following configuration.
- In the LED board 780, the connector CN1N and the LED driver 782 are arranged on the same surface on the board.
- In the LED board 790, the connector CN1X and the LED driver 791 are arranged on the same surface on the board.
- When viewed in directions DIR1, DIR2, DIR3, and DIR4, the left-right relationship between the clock signal CLK terminal and the data signal DATA terminal is all the same.

Therefore, it corresponds to the configuration shown in FIG.
The configuration of FIG. 59 provides the following effects.
The clock CK wiring and the production drive control data DT wiring between the first connector and the first performance drive means extend in the same direction from the connector and are continuous to the performance drive means without intersecting each other. This makes it possible to improve wiring efficiency and shorten the wiring length on the first substrate. This is advantageous when it is desired to perform wiring that does not pass through other layers.
Specifically, as shown in FIG. 60, the clock pattern wiring 787 and the signal pattern wiring 788 are formed without intersecting each other, thereby achieving higher wiring efficiency and shortening the wiring length.

Further, the clock CK wiring and the data DT wiring from the first connector can be led out in the same direction (from the same side of the connector housing). This means that one of the clock CK wiring and the data DT wiring is not a wiring that adjusts the left-right relationship by going around from the opposite side. This eliminates the need for wiring that goes around in the opposite direction from such a connector. This is effective in increasing wiring efficiency and shortening wiring length.

Since there is no need for unnecessary wiring, the length of the wiring can be shortened, and noise can be reduced. By reducing noise contamination, performance operations can be made more stable.
In particular, the clock CK and the data DT are signals that directly control the generation of the performance drive signal by the performance drive means at each time point. Therefore, at least regarding this pair of clock CK and data DT, the wiring is made more efficient and noise contamination is reduced, which has the effect of improving the stability of performance operations (LED light emission and movement of movable objects by motors). is obtained.
Note that other signal wiring such as a reset signal may be wired between the connector and the performance drive means, but the clock CK and data DT are always signals that directly affect the performance operation, and the average frequency is This is the highest signal. Making the wiring for the clock CK and data DT at least so that they do not cross each other to improve the efficiency of the wiring is effective in reducing the influence of noise and stabilizing the production operation.
The advantage of making the wiring more efficient for this pair of clock CK and data DT is the same in (configuration A1-2) to (configuration A9-3) described later.

The above effects can also be obtained in the second substrate.
By adopting the same left-right relationship of the terminals on the second board as on the first board, wiring from the connector to the driver can be made more efficient using multiple boards.
Specifically, as shown in FIG. 60, the clock pattern wiring 787 and the signal pattern wiring 788 are formed without crossing each other, and as shown in FIG. 63, the clock pattern wiring 795 and the signal pattern wiring 796 are formed without crossing each other. is formed.
This improves the wiring efficiency of multiple boards within the gaming machine 1, reduces noise contamination, improves design efficiency, and promotes stable presentation operations.

In addition, since the left-right relationship of the pins assigned to the clock CK and data DT of the connector is standardized on the plurality of boards as the first board and the second board, it becomes easier to draw a circuit diagram and to design the wiring. This improves design efficiency and is useful for developing new gaming machines.

Moreover, in the case of (Specific Example 1), by adopting the configuration shown in FIG. 59 between the boards connected successively as the LED boards 780 and 790, each of the above effects can be more easily exhibited. By standardizing the boards that are connected to each other, it is also suitable for circuit design and maintenance.

The gaming machine 1 of the embodiment has the following (configuration A1-2) in addition to (configuration A1-1).
(Configuration A1-2)
The gaming machine 1 is
comprising a third board provided with a third connector for inputting a clock and performance drive control data to the third performance drive means;
The left-right relationship of each connector terminal of the clock and production drive control data in the third connector when looking from the connector terminal side to the direction in which pattern wiring connected to each connector terminal is led is as follows. This connector is the same as No. 1 connector.

FIG. 65 schematically shows the first substrate, second substrate, and third substrate in this (configuration A1-2). The first and second substrates are the same as those shown in FIG. 59, and FIG. 65 shows that a third substrate has been added.

A third connector is mounted on the third board.
Pattern wiring PTH for clock CK and data DT is derived from the third connector.

In this figure, the third effect driving means is not shown on the third board, but it may be one of the following.
- The third effect driving means is mounted on the same surface as the third connector on the third board. - The third effect driving means is mounted on the third board on a different surface from the third connector. The effect driving means of No. 3 is mounted on another board downstream from the third board.

Direction DIR5 is a direction facing the direction in which pattern wiring PTH connected to each connector terminal of the clock CK and data DT is derived from the connector terminal side of the clock CK and data DT with respect to the third connector. In this case, the left-right relationship is such that the clock CK terminal is on the left and the data DT terminal is on the right.

The left-right relationship between the clock CK terminal and the data DT terminal when viewed in the directions DIR1, DIR2, DIR3, DIR4, and DIR5 is shown at the bottom of FIG. 65. All relationships are the same.

As an example corresponding to (configuration A1-2) as shown in FIG. 65, the above (specific example 1) is assumed for the first and second substrates, and the following (specific example 2) is assumed for the third substrate. be done.

(Specific example 2)
- Third board: side unit upper LED board 630 (see Figure 32)
・Clock (CK) for the third performance driving means: clock signal CLK
- Effect driving control data (DT) for the third effect driving means: data signal DATA
・Third connector: Connector CN1T
・Clock connector terminal of the third connector: 2nd pin ・Connector terminal of the production drive control data of the 3rd connector: 3rd pin

In this (Specific Example 2), a side unit LED board 630 corresponding to the third board is shown in FIGS. 66 and 67.
FIG. 66 shows a conductor pattern on the surface layer of the LED board 630 on the side unit, and FIG. 67 shows a conductor pattern on the back layer.

Note that the back layer in FIG. 67 is shown as a perspective view seen from the front layer side in FIG. 66, and the conductor pattern and board management number are shown in a horizontally reversed state from the state in which the back surface of the board is normally viewed. . In FIGS. 66 and 67, identification numbers of parts printed on the board are omitted. The part indicated as “○○+×××△” actually displays the board management number.

In the front surface layer of FIG. 66 and the back surface layer of FIG. 67, a ground pattern 633 as a solid ground and pattern wiring realizing the circuit configuration of FIG. 32 are formed.
“pLED1” to “pLED10” in FIG. 66 (surface layer) indicate positions (pads) where the light emitting elements LED1 to LED10 in FIG. 32 are arranged, respectively.
"p631" in FIG. 67 (back layer) indicates the position (pad) where the LED driver 631 is arranged, and "pCN1T" indicates the position (pad) where the connector CN1T is arranged.

Regarding the pads for the connector CN1T, as shown in an enlarged view at the top of the figure, the first pin side is the pad on the right side in the drawing, and the sixth pin side is the pad on the left side.
Therefore, regarding the connector CN1T, the left-right relationship as seen in the direction DIR5 is such that the clock signal CLK terminal (second pin) is on the left and the data signal DATA terminal (third pin) is on the right.

The LED driver 631 arranged at "p631" in FIG. 67 is the rectangular chip component described in FIG. 62.

Looking at the above side unit LED board 630, it has the following configuration.
- Equipped with a connector CN1T for inputting a clock signal CLK and a data signal DATA to the third effect driving means (LED driver 631).
The left-right relationship between the clock signal CLK terminal and the data signal DATA terminal when viewed in the direction DIR5 with respect to the connector CN1T is the same as the left-right relationship with respect to the connector CN1N (first connector) of the LED board 780 when viewed in the direction DIR1. are the same.

Therefore, the LED boards 780, 790 and the side unit LED board 630 correspond to (configuration A1-2) in FIG. 65.
With such (configuration A1-2), it is possible to promote commonization of the terminal settings of the connectors of each board, and to promote improvement in design efficiency.

Furthermore, in the board corresponding to the third board, the left-right relationship of the input terminals for the clock and the control data for driving the performance in the third performance driving means (for example, the LED driver 631) when looking from the pattern wiring side to the chip side is as follows. It may be made to be the same as the first effect driving means.

FIG. 67 shows an example in which an LED driver 631 as a third effect driving means is arranged at "p631", and each terminal of this LED driver 631 is shown enlarged in the upper part of the figure. The LED driver 631 is as shown in FIG. 62, but since FIG. 67 shows the back layer seen through from the front layer side, the terminal arrangement is reversed from FIG. 60 and FIG. 63. In the case of the example shown in FIG. 67, when looking from the pattern wiring side to the chip side, the left-right relationship between the clock signal CLK terminal and the data signal DATA terminal is different from that of the first effect driving means, for example, the LED driver 782. It's the other way around.

This is an example that is not desirable for improving wiring efficiency. That is, while the connector CN1T and the LED driver 782 are arranged on the same surface, the left-right relationship between the clock signal CLK terminal and the data signal DATA terminal is reversed.
The figure shows a clock pattern wiring 635 for the clock signal CLK and a signal pattern wiring 636 for the data signal DATA, but since the left-right relationship is reversed, the signal pattern wiring 636 is connected via a through hole as shown in FIG. A portion is formed on the surface layer side, thereby correcting the left-right relationship on the back layer in FIG. 67.

Therefore, in such a case, the LED driver 631 may be arranged on a different surface from the connector CN1T, that is, on the surface layer side. By forming the clock pattern wiring 635 and the signal pattern wiring 636 so as to reach the front side through the through holes, the left-right relationship can be corrected, so that inefficient wiring can be prevented.
Alternatively, if the LED driver 631 is placed on the same surface as the connector CN1T, it is also preferable to use another chip as the LED driver 631 in which the left-right relationship between the clock signal CLK terminal and the data signal DATA terminal is reversed. It is.
By employing these configurations, it is possible to improve wiring efficiency on a plurality of substrates, reduce noise contamination, and further improve design efficiency. In other words, the effect of (configuration A1-1) can be made more pronounced.

The gaming machine 1 of the embodiment has the following (configuration A2-1).
(Configuration A2-1)
The gaming machine 1 is
a first board provided with a first light emitting drive means using a chip component, and a first connector for inputting a clock and light emission drive control data to the first light emitting drive means;
a second board provided with a second connector for inputting a clock and light emission drive control data to the second light emission driving means;
Equipped with
In the first substrate,
The first light emission driving means and the first connector are arranged on the same surface of the board,
a left-right relationship of each input terminal of the clock and light emission drive control data in the first light emission driving means when looking from the pattern wiring side to the chip side;
a left-right relationship of each connector terminal of the clock and light emission drive control data in the first connector when looking from the connector terminal side to the direction in which pattern wiring connected to each connector terminal is led;
are the same,
In the second substrate,
The left-right relationship of each connector terminal of the clock and light emission drive control data in the second connector when looking from the connector terminal side to the direction in which the pattern wiring connected to each connector terminal is led is as follows. This connector is the same as No. 1 connector.

FIG. 68 schematically shows the structures of the first and second substrates.
A first connector and a first light emitting drive means are mounted on the first board.
The first connector and the first light emitting drive means are arranged on the same surface on the first substrate (each shown by a solid line).

The first connector inputs a clock CK and light emission drive control data (data DT) for the first light emission driving means.
The clock CK and data DT are supplied to the first light emission driving means by pattern wiring PTH on the substrate.

A second connector is mounted on the second board.
In the figure, the second light emission driving means is not shown on the second substrate, but it may be one of the following.
- The second light emitting driving means is mounted on the second board on the same surface as the second connector. - The second light emitting driving means is mounted on the second board on a different surface from the second connector. The second light emitting driving means is mounted on another board downstream of the second board.

In this case, the directions DIR11 and DIR13 indicated by the arrows are the same directions as the directions DIR1 and DIR3 described in (configuration A1-1) above, from the respective connector terminal sides of the clock CK and data DT to the respective connector terminals. This is a direction facing the direction in which the pattern wiring PTH to be connected is led out.
The direction DIR12 is the same direction as the above-mentioned direction DIR2, and is the direction of each input terminal of the clock CK and data DT in the light emission driving means, when looking from the pattern wiring PTH side to the chip (=the chip that is the light emission driving means) side. It is the direction.

The left-right relationship between the clock CK terminal and the data DT terminal when viewed in directions DIR11, DIR12, and DIR13 is shown at the bottom of the figure.
In the example of FIG. 68, the clock CK terminal is on the left, the data DT terminal is on the right, and the left-right relationship is the same in all cases.

As an example corresponding to (configuration A2-1) in FIG. 68, the following (specific example 3) is assumed.

(Specific example 3)
・First board: LED board 780 (see Figure 45)
・Second board: LED board 790 (see Figure 46)
- Clock (CK) for the first light emission driving means: clock signal CLK
- Light emission drive control data (DT) for the first light emission driving means: data signal DATA
- First light emission driving means: LED driver 782
- Clock input terminal in the first light emission driving means: No. 2 terminal (SCLK terminal)
・Input terminal for control data for light emission drive in the first light emission drive means: No. 3 terminal (SDATA terminal)
・First connector: Connector CN1N
・Clock connector terminal of first connector: 2nd pin ・Connector terminal of light emission drive control data of first connector: 3rd pin ・Second connector: Connector CN1X
・Clock (CK): Clock signal CLK
・Control data for light emission drive (DT): data signal DATA
・Clock connector terminal of the second connector: 2nd pin ・Connector terminal of the light emission drive control data of the 2nd connector: 3rd pin

In this (Specific Example 3), the LED substrates 780 and 790 corresponding to the first substrate and the second substrate are as described in FIGS. 60 to 64.
Note that the directions DIR1, DIR2, and DIR3 shown in FIGS. 60 to 64 respectively correspond to the directions DIR11, DIR12, and DIR13 in this (configuration A2-1).
Then, the LED boards 780 and 790 have the following configuration.

- In the LED board 780, the connector CN1N and the LED driver 782 are arranged on the same surface on the board.
- When viewed in directions DIR11, DIR12, and DIR13, the left and right relationships between the clock signal CLK terminal and the data signal DATA terminal are all the same.

Therefore, it corresponds to the configuration shown in FIG. 68.
The configuration of FIG. 68 provides the following effects.
The clock CK wiring and the light emission drive control data DT wiring between the first connector and the first light emission drive means extend in the same direction from the connector and are continuous to the light emission drive means without crossing. This makes it possible to improve wiring efficiency and shorten the wiring length on the first substrate.
Further, the clock CK wiring and the data DT wiring from the first connector can be led out in the same direction (from the same side of the connector housing). Therefore, it is effective in increasing the efficiency of wiring and shortening the wiring length.

Furthermore, since there is no need for unnecessary wiring, noise contamination can also be reduced. By reducing noise contamination, performance operations can be made more stable.
LEDs are arranged in various places in the game machine 1, and there are many boards on which LED drivers serving as light emission driving means are arranged. This technique is particularly suitable for use in substrates placed in areas with a lot of high-frequency noise.

In addition, since the left-right relationship of the pins assigned to the clock CK and data DT of the connector is standardized on the plurality of boards as the first board and the second board, it becomes easier to draw a circuit diagram and to design the wiring. This improves design efficiency and is useful for game machine development.

Furthermore, the gaming machine 1 of the embodiment has the following (configuration A2-2) in addition to (configuration A2-1).
(Configuration A2-2)
The second board has a second light emitting drive means made of a chip component that inputs a clock and light emitting drive control data via pattern wiring from the second connector,
In the second board, the second light emitting drive means and the second connector are arranged on the same surface of the board,
The left-right relationship between the input terminals of the clock and the control data for light emission driving in the second light emission driving means when viewed from the pattern wiring side to the chip side is the same as that of the first light emission driving means.

FIG. 69 schematically shows the first substrate and second substrate in this (configuration A2-2). FIG. 69 is similar to FIG. 68 regarding the first substrate, except that the second light emission driving means is shown on the second substrate. In the second board, the clock CK and data DT are supplied from the second connector to the second light emission driving means through the pattern wiring PTH on the board.
In the configuration of FIG. 69, the second light emitting drive means is arranged on the same surface as the second connector on the second board. Direction DIR14 is a direction defined in the same way as direction DIR4 described above.

As an example corresponding to (configuration A2-2) in FIG. 69, in addition to the above (specific example 3), the following (specific example 4) is assumed.

(Specific example 4)
・Second light emission driving means: LED driver 791
- Clock input terminal in the second light emission driving means: No. 2 terminal (SCLK terminal)
・Input terminal for control data for effect driving in the second light emission driving means: No. 3 terminal (SDATA terminal)

The LED substrates 780 and 790 corresponding to the first and second substrates of (Specific Example 3) and (Specific Example 4) described above are as described in FIGS. 60 to 64. Note that the direction DIR4 shown in FIG. 63 corresponds to DIR14 in FIG. 69.
Therefore, the LED board 790 corresponding to the second board has the following configuration.

- In the LED board 790, the connector CN1X and the LED driver 791 are arranged on the same surface on the board.
- The left-right relationship between the clock signal CLK terminal and the data signal DATA terminal when viewed in the direction DIR14 is the same as when viewed in the direction DIR11.
Therefore, it corresponds to the configuration shown in FIG. 69.

In this way, the same left-right relationship of the terminals as on the first board is adopted on the second board, and by using multiple boards, wiring from the connector to the light emitting drive means can be made more efficient. It improves wiring efficiency for multiple boards, reduces noise contamination, and improves design efficiency, promoting stable light emission operation.

The gaming machine 1 of the embodiment has the following (configuration A3-1).
(Configuration A3-1)
The gaming machine 1 is
a first board provided with a first motor drive means using a chip component and a first connector for inputting a clock and motor drive control data to the first motor drive means;
a second board provided with a second connector for inputting a clock and motor drive control data to a second motor drive means;
Equipped with
In the first substrate,
the first motor drive means and the first connector are arranged on the same side of the board;
a left-right relationship between each input terminal of the clock and motor drive control data in the first motor drive means when looking from the pattern wiring side to the chip side;
a left-right relationship between the clock and motor drive control data connector terminals in the first connector when looking from the connector terminal side to the direction in which pattern wiring connected to the connector terminals is led;
are the same,
In the second substrate,
The left-right relationship of each connector terminal for the clock and motor drive control data in the second connector when looking from the connector terminal side to the direction in which the pattern wiring connected to each connector terminal is led is as follows. This connector is the same as No. 1 connector.

FIG. 70 schematically shows the configurations of the first and second substrates.
A first connector and a first motor drive means are mounted on the first board.
The first connector and the first motor drive means are arranged on the same surface on the first substrate (each shown by a solid line).

The first connector inputs a clock CK and motor drive control data (data DT) for the first motor drive means.
Clock CK and data DT are supplied to the first motor driving means through pattern wiring PTH on the substrate.

A second connector is mounted on the second board.
In the figure, the second motor driving means is not shown on the second board, but it may be one of the following.
- The second motor driving means is mounted on the second board on the same surface as the second connector. - The second motor driving means is mounted on the second board on a different surface from the second connector. The second motor driving means is mounted on another board downstream from the second board.

In this case, the directions DIR21 and DIR23 indicated by the arrows point in the direction in which the pattern wiring PTH connected to each connector terminal of the clock CK and data DT is derived from the connector terminal side of the clock CK and data DT, similarly to the directions DIR1 and DIR3 described above. This is the direction I tried.
Direction DIR22, like the above-mentioned direction DIR2, is the direction of each input terminal of the clock CK and data DT in the motor driving means when looking from the pattern wiring PTH side to the chip (=chip that is the motor driving means) side. be.

The left-right relationship between the clock CK terminal and the data DT terminal when viewed in directions DIR21, DIR22, and DIR23 is shown at the bottom of the figure.
In the example of FIG. 70, the clock CK terminal is on the left, the data DT terminal is on the right, and the left-right relationship is the same in all cases.

As an example corresponding to (configuration A3-1) in FIG. 70, the following (specific example 5) is assumed.

(Specific example 5)
・First board: LED connection board 1500 (see Figures 50 to 57)
・Second board: Side unit upper right LED board 600 (see Figures 24 to 29)
・Clock (CK) for the first motor drive means: clock signal LSI_SCK
- Motor drive control data (DT) for the first motor drive means: serial data signal LSI_MOSI
- First motor drive means: motor driver control unit 1530 (Although there is a buffer circuit 1501 in the signal path, the left-right relationship is not reversed by the input and output of the buffer circuit 1501, so the buffer circuit 1501 can be ignored with respect to the left-right relationship. ).
is considered to be the first motor drive means. )
・Clock input terminal in the first motor drive means: No. 5 terminal (SCK terminal)
・Input terminal for motor drive control data of the first motor drive means: No. 7 terminal (MOSI terminal)
・First connector: Connector CN1V (see Figure 50)
・Clock connector terminal of the first connector: 3rd pin ・Connector terminal of the motor drive control data of the first connector: 7th pin ・Second connector: Connector CN1E (see Figure 24)
・Clock (CK): Clock signal CLK_A (CLK_P)
・Motor drive control data (DT): data signal DATA_A (DATA_P)
・Second connector clock connector terminal: 10th pin ・Second connector motor drive control data connector terminal: 14th pin

In this (Specific Example 5), examples of component arrangement on the LED connection board 1500 corresponding to the first board are shown in FIGS. 71 and 72.
FIG. 71 schematically shows the arrangement of main electronic components on the surface layer of an LED connection board 1500 having the circuit configuration described in FIGS. 50 to 57, and FIG. 72 schematically shows the arrangement of the back layer. Note that the back layer in FIG. 72 is shown as a perspective view seen from the front layer side in FIG. 71, and is shown in a horizontally reversed state.

Connectors CN1V to CN28V in the LED connection board 1500 are all arranged on the surface layer in FIG. 71. The positions where the connectors CN1V to CN28V are arranged (positions where pads are formed: the same applies hereinafter) are shown as "pCN1V" to "pCN28V".

Further, the positions where the buffer circuits 1501, 1502, and 1503 are arranged are shown as "p1501,""p1502," and "p1503."
Further, the position where the motor driver control section 1530 corresponding to the chip of the first motor drive means is arranged is indicated as "p1530".
Further, the position where the P/S conversion circuit 1504 is arranged is shown as "p1504".
Further, the position where the buffer circuit 1540 is arranged is shown as "p1540".

In the back layer of FIG. 72, the positions where the motor drivers 1532, 1533, 1534, and 1535 are arranged are indicated as "p1532,""p1533,""p1534," and "p1535."
Further, the position where the motor driver 1505 is arranged is shown as "p1505".
Further, the positions where the LED drivers 1510, 1511, 1520, 1521, and 1522 are arranged are shown as "p1510,""p1511,""p1520,""p1521," and "p1522."

In FIG. 71, some terminal numbers in the connector CN1V, motor driver control section 1530, buffer circuits 1501, 1502, 1503, P/S conversion circuit 1504, and buffer circuit 1540 are shown. These correspond to the terminal numbers shown in FIGS. 50 to 57.
Connector CN1V (see position pCN1V) corresponding to the first connector is a connector with two rows of terminals, with the lower right side of the drawing being the first pin side.
In the motor driver control unit 1530 (see position p1530) corresponding to the first motor driving means, the terminals on the lower side of the diagram are terminals 1 to 12 in order from the left.

Further, in FIG. 72, some terminal numbers are shown for the motor driver 1505 and the LED drivers 1510, 1511, 1520, 1521, and 1522 (see positions p1510, p1511, p1520, p1521, and p1522). These also correspond to the terminal numbers shown in FIGS. 50 to 57.

As shown in FIG. 71, a clock pattern wiring 1561 for the clock signal CLK and a clock pattern wiring 1561 for the data signal DATA are connected between the connector CN1V and the motor driver control unit 1530 via the buffer circuit 1501 (see position p1501). A signal pattern wiring 1562 is formed for this purpose. Note that illustration of the chip resistor RA1V, etc. on the wiring route is omitted.

Here, in FIG. 71, the directions DIR21 and DIR22 shown in FIG. 70 are shown for the connector CN1V and the motor driver control section 1530.
Regarding the directions DIR21 and DIR22 shown in FIG. 71, if the terminal numbers shown in the figure are made to correspond to the terminal assignments of the connector CN1V in FIG. 50 and the terminal types of the motor driver control unit 1530 in FIG. It can be seen that the left-right relationship between the clock CK and the data DT is the same as the left-right relationship in the directions DIR21 and DIR22 shown in FIG.
A clock pattern wiring 1561 and a signal pattern wiring 1562 corresponding to the pattern wiring PTH in FIG. 70 are formed between the connector CN1V and the motor driver control unit 1530, and transmit the clock signal LSI_SCK and the serial data signal LSI_MOSI.

Next, FIGS. 73 and 74 show examples of component arrangement in the upper right LED board 600 of the side unit corresponding to the second board in the above (specific example 5).
FIG. 73 schematically shows the arrangement of main electronic components in the surface layer of the side unit upper right LED board 600 having the circuit configuration described in FIGS. 24 to 29, and FIG. 74 schematically shows the arrangement of the back surface layer. Note that the back layer in FIG. 74 is shown as a perspective view seen from the front layer side in FIG. 73, and is shown in a horizontally reversed state.

Connectors CN1E to CN7E in the upper right LED board 600 of the side unit are all arranged on the back layer in FIG. 74. The positions where connectors CN1E to CN7E are arranged (positions where pads are formed; the same applies hereinafter) are shown as "pCN1E" to "pCN7E".

Further, in FIG. 73 or 74, the positions where the buffer circuits 601, 604, and 607 are arranged are shown as "p601", "p604", and "p607".
Further, the positions where the P/S conversion circuits 602 and 603 are arranged are shown as "p602" and "p603".
Further, the position where the LED driver 605 is arranged is shown as "p605".
Further, the position where an S/P conversion circuit 606 corresponding to a chip of a second motor driving means, which will be described later, is arranged is indicated as "p606".
Further, the positions where the motor drivers 608 and 609 are arranged are shown as "p608" and "p609".

73 and 74 show some terminal numbers in the connector CN1E, the S/P conversion circuit 606 (see position p606), and the buffer circuit 601 (see position p601). These correspond to the terminal numbers shown in FIGS. 24 to 29.
Connector CN1E (see position pCN1E) corresponding to the second connector is a connector with two rows of terminals, with the upper right side of the drawing being the first pin side.
In the S/P conversion circuit 606, the terminals on the left side of the figure are terminals 1 to 12 from bottom to top.

Between the connector CN1E and the S/P conversion circuit 606, there is a clock pattern wiring 681 for the clock signal CLK_P (CLK_A) and a signal pattern wiring for the data signal DATA_P (DATA_A) as wiring via the buffer circuit 601. 682 is formed. Note that illustration of resistors R9E, R12E and other elements on the wiring path is omitted.

In FIG. 74, the direction DIR23 shown in FIG. 70 is shown. Regarding the direction DIR23 shown in FIG. 74, if the terminal numbers shown in the figure correspond to the terminal assignments of the connector CN1E in FIG. The same thing can be said about relationships.

Therefore, the LED connection board 1500 mentioned in (Specific Example 5) and the upper right LED board 600 of the side unit correspond to the first board and second board of (configuration A3-1) in FIG. 70.

The configuration of FIG. 70 provides the following effects.
The wiring for the clock CK and the wiring for the motor drive control data DT between the first connector and the first motor drive means can extend in the same direction from the connector and be continuous to the motor drive means without intersecting. This makes it possible to improve wiring efficiency and shorten the wiring length on the first substrate.
Further, the clock CK wiring and the data DT wiring from the first connector can be led out in the same direction (from the same side of the connector housing). Therefore, it is effective in increasing the efficiency of wiring and shortening the wiring length.

Furthermore, since there is no need for unnecessary wiring, noise contamination can also be reduced. By reducing noise contamination, performance operations can be made more stable.
Since the motors that execute the actions of accessories require high precision, this technology is extremely important to ensure the stability of the motor's operation, especially in circuit boards that are placed in areas with a lot of high-frequency noise. It becomes suitable.

In addition, since the left-right relationship of the pins assigned to the clock CK and data DT of the connector is standardized on the plurality of boards as the first board and the second board, it becomes easier to draw a circuit diagram and to design the wiring. This improves design efficiency and is useful for developing new gaming machines.

Furthermore, the gaming machine 1 of the embodiment has the following (configuration A3-2) in addition to (configuration A3-1).
(Configuration A3-2)
The second board has a second motor drive means made of a chip component that inputs a clock and motor drive control data via pattern wiring from the second connector,
In the second board, the second motor drive means and the second connector are arranged on the same surface of the board,
The left-right relationship between the clock and motor drive control data input terminals in the second motor drive means when viewed from the pattern wiring side to the chip side is the same as in the first motor drive means.

FIG. 76 schematically shows the first substrate and second substrate in this (configuration A3-2).
In FIG. 76, the first board is similar to that in FIG. 70, except that the second motor driving means is shown on the second board. In the second board, the clock CK and data DT are supplied from the second connector to the second motor driving means through the pattern wiring PTH on the board.
In the configuration of FIG. 76, the second motor driving means is arranged on the same surface as the second connector on the second board. Direction DIR24 is a direction defined similarly to direction DIR4 described above.

As an example corresponding to (configuration A3-2) in FIG. 76, in addition to the above (specific example 5), the following (specific example 6) is assumed.

(Specific example 6)
・Second motor drive means: S/P conversion circuit 606
・Clock input terminal in the second motor drive means: No. 2 terminal (SCLK terminal)
・Input terminal for control data for performance drive in the second motor drive means: No. 3 terminal (SDATA terminal)

The component arrangement in the LED connection board 1500 corresponding to the first board and second board and the side unit upper right LED board 600 in (Specific Example 5) and (Specific Example 6) above is as explained in FIGS. 71 to 74. be. Note that the direction DIR24 shown in FIG. 74 corresponds to DIR24 in FIG. 76. Therefore, the side unit upper right LED board 600 corresponding to the second board has the following configuration.

- In the upper right LED board 600 of the side unit, the connector CN1E and the S/P conversion circuit 606 are arranged on the same surface of the board.
- When viewed in the direction DIR24, the left-right relationship between the terminals of the clock signal CLK_A and the terminals of the data signal DATA_A is the same as in the direction DIR22. Between the connector CN1E and the S/P conversion circuit 606, pattern wiring for the clock signal CLK_A and data signal DATA_A (clock pattern wiring 681 and signal pattern wiring 682) is formed as pattern wiring PTH as shown in FIG. . Therefore, this corresponds to the configuration shown in FIG.

In this way, the same left-right relationship of the terminals as on the first board is adopted for the second board, and by using multiple boards, the wiring from the connector to the motor drive means can be made more efficient, so that the wiring inside the gaming machine 1 can be made more efficient. It improves the wiring efficiency of multiple boards, reduces noise contamination, and improves design efficiency, and promotes stable performance of movable objects such as accessories.

Note that FIG. 75 shows examples of different configurations of the surface layer of the LED connection board 1500.
The above-mentioned FIG. 71 shows a wiring example in the case of a circuit configuration in which the connector CN1V and the motor driver control section 1530 are connected via the buffer circuit 1501, but FIG. The line between the lines is an example of wiring that is connected without going through the buffer circuit 1501.

In the example of FIG. 75, the arrangement direction of the connector CN1V is different from that of FIG. 71, and the first pin is on the left side of the upper side of the figure.
In this case, clock pattern wiring 1561 and signal pattern wiring 1562 are formed as shown. FIG. 75 shows the directions DIR21 and DIR22 in this case, which also have the same left-right relationship as the examples in FIGS. 70 and 76. In other words, such an example can be considered as the first substrate of (configuration A3-1) or (configuration A3-2).

Similarly, in FIG. 74, dashed lines indicate a clock pattern wiring 681' for the clock signal CLK_P (CLK_A), a clock pattern wiring 681' for the clock signal CLK_P (CLK_A), and a data signal DATA_P between the connector CN1E and the S/P conversion circuit 606 as an example of wiring that does not go through the buffer circuit 601. An example is shown in which a signal pattern wiring 682' for (DATA_A) is formed.
Such an example can also be considered as the second substrate of (configuration A3-2).

The gaming machine 1 of the embodiment has the following (configuration A4-1).
(Configuration A4-1)
The gaming machine 1 is
a first board provided with a first effect driving means using a chip component, and a first connector for inputting a clock and effect driving control data to the first effect driving means;
a second board provided with a second effect driving means using a chip component and a second connector for inputting a clock and effect driving control data to the second effect driving means;
Equipped with
In the first substrate,
The first effect driving means and the first connector are arranged on the same surface of the board,
the left-right relationship of each input terminal of the clock and the control data for effect driving in the first effect driving means, when looking from the pattern wiring side to the chip side;
the left-right relationship of each connector terminal of the clock and production drive control data in the first connector when looking in the direction in which pattern wiring connected to each connector terminal is led from the connector terminal side;
are the same,
In the second substrate,
The left-right relationship of each connector terminal of the clock and production drive control data in the second connector when looking from the connector terminal side to the direction in which the pattern wiring connected to each connector terminal is led is as follows. It is the same as the connector of 1,
The left-right relationship of each input terminal of the clock and the control data for effect driving in the second effect driving means when viewed from the pattern wiring side to the chip side is opposite to that of the first effect driving means,
The second performance driving means and the second connector are arranged on different surfaces of the second board.

FIG. 77 schematically shows the structures of the first and second substrates.
A first connector and a first effect driving means are mounted on the first board.
The first connector and the first effect driving means are arranged on the same surface on the first board (in the figure, the blocks of the first connector and the first effect driving means are both shown by solid lines).

The first connector inputs a clock CK and performance drive control data (data DT) to the first performance drive means.
The clock CK and data DT are supplied to the first effect driving means by pattern wiring PTH on the board.

A second connector and a second effect driving means are mounted on the second board.
The second connector and the second effect driving means are arranged on different surfaces on the second board. In the figure, the second effect driving means and part of the pattern wiring PTH are shown by broken lines, indicating that they are arranged on the back side of the second connector shown by solid lines. Pattern wiring PTH is formed on both sides via through holes TH.
Further, the second effect driving means is shown as an octagon (a rectangle with a chamfer), but this is different from the first effect driving means shown as a rectangle on the left and right terminals of the clock CK and data DT. This indicates that the chips have different relationships.
Furthermore, the characters "CK" and "DT" at the terminals for the second effect driving means are shown in a mirror-inverted state. This represents the state in which "CK" and "DT" are normally seen when viewed from the back side. Although the letters "CK" and "DT" are not actually written on the chip, it is clearly shown in the drawing that the second effect driving means is placed on the back side when viewed from the second connector. It is the intention to express. In other words, from the perspective of the diagram, the first effect driving means and the second effect driving means appear to have the same left-right relationship of "CK" and "DT", but since the arrangement planes are reversed, the chips are This expresses that the left-right relationship between CK and DT is reversed.

The second connector inputs the clock CK and performance drive control data (data DT) to the second performance drive means. The clock CK and data DT are supplied to the second effect driving means through the pattern wiring PTH.

In this case, the left-right relationship between the clock CK and data DT terminals in the directions DIR31, DIR32, DIR33, and DIR34 indicated by arrows is shown at the bottom of the figure. Directions DIR31, DIR32, DIR33, and DIR34 are directions defined similarly to the above-mentioned directions DIR1, DIR2, DIR3, and DIR4, respectively.
Note that the direction DIR34 has the same definition as the direction DIR4, but in this case, the second effect driving means is arranged on the back side when viewed from the second connector, so when the front and back of the board are reversed, Think of it in terms of line of sight (it's easier to understand if you think of it as the line of sight when looking through the paper on which this diagram is printed from the back). Therefore, the left-right relationship as seen in the direction DIR 34 is such that the left is the data DT terminal and the right is the clock CK terminal, as shown in the lower right of the figure.
This directionality of observation is because the left-right relationship in the present invention should be considered based on the surface on which the pattern wiring PTH is formed.

In the case of FIG. 77, the left-right relationship when viewed in the directions DIR31, DIR32, and DIR33 is the same, with the clock CK terminal on the left and the data DT terminal on the right, but the left-right relationship when viewed in the direction DIR34. is reversed.
In other words, the chip serving as the second effect driving means has a structure in which the left-right relationship between the clock CK and data DT terminals is opposite to that of the first effect driving means chip.

As an example corresponding to (configuration A4-1) in FIG. 77, the following (specific example 7) is assumed.

(Specific example 7)
・First board: LED connection board 1500 (see Figures 50 to 57)
・Second board: LED board 1600 (see Figure 58)
・Clock (CK) for the first performance driving means: clock signal LSI_SCK
- Effect driving control data (DT) for the first effect driving means: serial data signal LSI_MOSI
- First effect driving means: motor driver control section 1530 (see FIG. 55)
・Clock input terminal in the first production driving means: No. 5 terminal (SCK terminal)
・Input terminal for control data for performance drive in the first performance drive means: No. 7 terminal (MOSI terminal)
・First connector: Connector CN1V
・Clock connector terminal of the first connector: 3rd pin ・Connector terminal of the first connector's performance drive control data: 7th pin ・Second performance driving means: LED driver 1601 (see FIG. 58)
・Clock (CK) for the second performance driving means: clock signal CLK
- Effect driving control data (DT) for the second effect driving means: data signal DATA
・Clock input terminal in the second production driving means: No. 48 terminal (SCLK terminal)
・Input terminal for control data for driving the performance of the second performance driving means: No. 47 terminal (SDATA terminal)
・Second connector: Connector CN1W
・Clock connector terminal of the second connector: 2nd pin ・Connector terminal of the production drive control data of the 2nd connector: 5th pin

In this (Specific Example 7), the component arrangement of the LED connection board 1500 corresponding to the first board is as described with reference to FIGS. 71 and 72.
Regarding the LED board 1600 corresponding to the second board, FIG. 78 schematically shows the arrangement of main electronic components in the front layer, and FIG. 79 schematically shows the arrangement in the back layer. Note that the back layer in FIG. 79 is shown as a perspective view seen from the front layer side in FIG. 78, and is shown in a horizontally reversed state.

Connector CN1W in LED board 1600 is arranged at position "pCN1W" in the surface layer in FIG. 78.
In addition, in the surface layer, LED1 to LED10 in the light emitting section 1602 in FIG. 58 are arranged at positions "pLED1" to "pLED10".
In the back layer of FIG. The LED driver 1601 is placed at the "p1601" position.

FIG. 78 shows some terminal numbers of the connector CN1W (see position pCN1W), and FIG. 79 shows some terminal numbers of the LED driver 1601 (see position p1601). These correspond to the terminal numbers shown in FIG.
Note that the LED driver 1601 has a terminal configuration as shown in FIG. 80A, for example. Although detailed description of the terminal configuration will be avoided here, the 48th terminal is the SCLK terminal, and the 47th terminal is the SDATA terminal.
FIG. 79 is a perspective view from the surface layer side, and the terminal numbers shown in FIG. 79 correspond to the mirror-inverted state (viewed from the bottom side of the chip) as shown in FIG. 80B.

Between the connector CN1W and the LED driver 1601, a clock pattern wiring 1611 for the clock signal CLK and a signal pattern wiring 1612 for the data signal DATA in FIG. 79 are formed. This is connected to the second and fifth pins of the connector CN1W via through holes TH11 and TH12 shown in FIGS. 78 and 79. Note that the illustration of the resistors R1W and R2W (see FIG. 58) on the wiring path is omitted.

Here, in FIGS. 78 and 79, directions DIR33 and DIR34 shown in FIG. 77 are shown for the connector CN1W and the LED driver 1601.
Regarding the directions DIR33 and DIR34 shown in FIGS. 78 and 79, if the terminal numbers shown in the figures are made to correspond to the terminal assignments of the connector CN1W in FIG. 58 and the terminal configuration of the LED driver 1601, the clock CK of the connector CN1W and the LED driver 1601 is It can be seen that the left-right relationship between and data DT is the same as the left-right relationship in directions DIR33 and DIR34 shown in FIG.
Clock pattern wiring 1611 and signal pattern wiring 1612 for clock signal SLK and data signal DATA are formed between connector CN1W and LED driver 1601, corresponding to pattern wiring PTH in FIG. 76.

Therefore, the LED connection board 1500 and the LED board 1600 mentioned in (Specific Example 7) correspond to the first board and the second board of (configuration A4-1) in FIG. 77.

The configuration of FIG. 77 provides the following effects.
Regarding the first substrate, the same effects as in the above-mentioned (configuration A1-1) can be obtained (reduction in wiring length, improvement in wiring efficiency, reduction in noise contamination, improvement in design efficiency, etc.).
In addition, this (configuration A4-1) is suitable when ICs having different left and right terminals are used as the first and second effect driving means.
In the LED driver 1601 mentioned as the second effect driving means, the left-right relationship between the clock CK and data DT terminals is opposite to that of the connector CN1W. In this case, the effect of the second substrate mentioned above (configuration A1-1) cannot be obtained. In this case, the second effect driving means is arranged on a different surface from the second connector. By being on a different surface from the second connector, the left-right relationship that occurs in the wiring from the second connector can be adapted to the second effect driving means at the stage of passing through the through hole TH. In other words, it is possible to form a pattern wiring PTH that deals with the difference in left-right relationship without unnecessary wiring. In addition, even if different types of ICs are used as performance driving means on the first and second boards, the pin arrangement on the connector side (left-right relationship of pins assigned to clock CK and data DT) can be changed between the first and second boards. You can enjoy the benefits of commonality.

The gaming machine 1 of the embodiment has the following (configuration A5-1).
(Configuration A5-1)
The gaming machine 1 is
A first performance driving means using chip components;
a second performance driving means using chip components;
a connector for inputting a clock and performance drive control data to the first performance driving means and the second performance driving means;
a first substrate provided with
In the first substrate,
the left-right relationship of each input terminal of the clock and the control data for effect driving in the first effect driving means, when looking from the pattern wiring side to the chip side;
the left-right relationship of each connector terminal of the clock and production drive control data in the connector, when looking from the connector terminal side to the direction in which pattern wiring connected to each connector terminal is led;
are the same,
A left-right relationship between the clock and the input terminals of the control data for driving the effect in the second effect driving means when looking from the pattern wiring side to the chip side;
the left-right relationship of each connector terminal of the clock and production drive control data in the connector, when looking from the connector terminal side to the direction in which pattern wiring connected to each connector terminal is led;
is the opposite,
The first effect driving means is arranged on the same surface as the connector,
The second performance driving means is arranged on a different surface from the connector.

FIG. 81 schematically shows the structure of this first substrate.
A connector, a first effect driving means, and a second effect driving means are mounted on the first board.
The connector and the first performance driving means are arranged on the same surface on the first board. In the figure, the blocks of the first connector and the first effect driving means are both shown by solid lines.
The connector and the second performance driving means are arranged on different surfaces on the first board. In the figure, the second effect driving means and part of the pattern wiring PTH are shown by broken lines, indicating that they are arranged on the back side of the connector shown by solid lines. The pattern wiring PTH is formed over both surfaces via the through hole TH.
This FIG. 81 also has the same meaning as the previous FIG. 77, and the second effect driving means is shown in a different shape (octagonal), and the letters "CK" and "DT" are mirror-reversed.

The connector inputs a clock CK and performance drive control data (data DT) to the first and second performance drive means.
The clock CK and data DT are supplied to the first effect driving means by pattern wiring PTH on the board.
The clock CK and data DT are also supplied to the second effect driving means through the pattern wiring PTH.

In this case, the left-right relationship between the clock CK and data DT terminals in the directions DIR51, DIR52, and DIR53 indicated by the arrows is shown at the bottom of the figure. The direction DIR51 is a direction defined similarly to the above-mentioned direction DIR1, and the directions DIR52 and DIR53 are directions respectively defined similarly to the above-mentioned direction DIR2.
Note that the direction DIR53 is considered to be the line of sight direction when the front and back of the board are reversed from the direction DIR2. This is due to the reason stated in the explanation of direction DIR34 in FIG.

In this case, the left-right relationship when viewed in the directions DIR51 and DIR52 is the same, but the left-right relationship when viewed in the direction DIR53 is reversed.
In other words, the second effect driving means has a structure in which the right and left relationship between the clock CK and data DT terminals is opposite to that of the first effect driving means.

As an example corresponding to (configuration A5-1) as shown in FIG. 81, the following (specific example 8) is assumed.

(Specific example 8)
・First board: LED connection board 1500 (see Figures 50 to 57)
・Clock (CK) for the first performance driving means: clock signal LSI_SCK
- Effect driving control data (DT) for the first effect driving means: serial data signal LSI_MOSI
- First effect driving means: motor driver control section 1530 (see FIG. 55)
・Clock input terminal in the first production driving means: No. 5 terminal (SCK terminal)
・Input terminal for control data for performance drive in the first performance drive means: No. 7 terminal (MOSI terminal)
・Connector: Connector CN1V
・Connector clock connector terminal: 3rd pin (or 3rd pin and 13th pin)
・Connector terminal for control data for driving the performance of the connector: 7th pin (or 7th pin and 15th pin)
・Second effect driving means: LED drivers 1510, 1511, 1520, 1521, 1522 (see FIGS. 52, 53, and 54)
・Clock (CK) for the second performance driving means: clock signals CLK_A, CLK_B
- Effect driving control data (DT) for the second effect driving means: data signals DATA_A, DATA_B
・Clock input terminal in the second production driving means: No. 48 terminal (SCLK terminal)
・Input terminal for control data for driving the performance of the second performance driving means: No. 47 terminal (SDATA terminal)

In this (Specific Example 8), the arrangement of the front layer and back layer of each component of the LED connection board 1500 corresponding to the first board is as described in FIGS. 71 and 72. That is, the connector CN1V and the motor driver control unit 1530 corresponding to the first effect driving means are arranged on the surface layer, and the LED drivers 1510, 1511, 1520, 1521, 1522 corresponding to the second effect driving means are arranged on the back layer. has been done.

The connections between the 3rd and 5th pins of the connector CN1V and the 5th terminal (SCK terminal) and the 7th terminal (MOSI terminal) of the motor driver control unit 1530 are as explained in FIG. 71, and the direction DIR51 in FIG. , DIR52 (directions DIR51 and DIR52 correspond to directions DIR21 and DIR22 in FIG. 71).

The LED driver 1521 will be explained as an example of the second effect driving means. A direction DIR53 is shown for the arrangement of the LED driver 1521 shown in FIG. 72. Since FIG. 72 is a perspective view, when considered with the back layer facing up, each of the clock CK and data DT as the 48th terminal (SCLK terminal) and the 47th terminal (SDATA terminal) of the LED driver 1521 seen in the direction DIR53. The left-right relationship of the terminals is as shown in FIG.

Therefore, in the LED connection board 1500, the connector CN1V, motor driver control section 1530, LED driver 1521, etc. correspond to the configuration shown in FIG. 81.
In the case of this configuration, in addition to obtaining the same effects as the above-mentioned (configuration A1-1) (reduction in wiring length, improvement in wiring efficiency, and reduction in noise contamination), there is the following effect.

That is, it is suitable for the case where ICs having different left-right relationships between the clock CK and data DT terminals are used as the first and second effect driving means.
The second performance driving means has the clock CK and data DT terminals in the opposite left-right relationship to the connector, but by placing it on a different surface from the connector, the wiring from the connector can be routed through the through-hole. can adapt the left-right relationship. Therefore, wiring does not become complicated.

Note that (configuration A5-1), like the above LED connection board 1500, separate clock CK (3rd pin and 13th pin) and data DT (7th pin and 15th pin) are input to the connector. There is a configuration in which the clock CK and data DT input to the connector are separately supplied to the first and second effect driving means, but the one clock CK and data DT are branched and supplied to the first and second effect driving means. A configuration is also envisaged. This will be explained as the following (configuration A5-2).

The gaming machine 1 of the embodiment has the following (configuration A5-2) in addition to (configuration A5-1).
(Configuration A5-2)
The clock input to the connector is branched and supplied to the first effect driving means and the second effect driving means,
The effect driving control data input to the connector is branched and supplied to the first effect driving means and the second effect driving means.

FIG. 82 shows an example of a configuration in which one clock CK and one data DT are branched and supplied to the first and second effect driving means.
FIG. 82 shows an example in which a part of the portion shown in FIG. 50 of the LED connection board 1500 shown in FIGS. 50 to 57 is modified, and is referred to as an LED connection board 1500A. Note that FIGS. 51 to 57 may be considered to be the same.

The circuit example in FIG. 82 is an example in which the clock signal LSI_SCK from the third pin of the connector CN1V in FIG. 81 and the serial data signal LSI_MOSI from the seventh pin are branched by a buffer circuit 1501.
The clock signal LSI_SCK is input to the A1 terminal (terminal 2) and the A6 terminal (terminal 7) of the buffer circuit 1501, and is output as the clock signal LSI_SCK to the motor driver control unit 1530 from the Y1 terminal (terminal 18). The clock signal CLK_P is output from the Y6 terminal (terminal 13). Clock signal CLK_P is supplied to LED driver 1521 and the like through buffer circuit 1502 as clock signals CLK_A and CLK_B.
The serial data signal LSI_MOSI is input to the A4 terminal (terminal 5) and the A7 terminal (terminal 8) of the buffer circuit 1501, and is output as the serial data signal LSI_MOSI to the motor driver control unit 1530 from the Y4 terminal (terminal 15). At the same time, it is output as a data signal DATA_P from the Y7 terminal (terminal 12). The data signal DATA_P is supplied to the LED driver 1521 and the like via the buffer circuit 1502 as data signals DATA_A and DATA_B.

In other words, as shown in FIG. 81, the clock CK and data DT are branched and supplied to the first effect driving means on the front layer and the second effect driving means on the back layer, and the clock CK and data DT are branched and supplied to the first effect driving means on the front layer and the second effect driving means on the back layer. The left-right relationship between the clock CK and data DT terminals is reversed.
As a result, in the case where one system of clock CK and data DT is branched and supplied to a plurality of effect driving means, the first and second effect driving means are able to detect that the clock CK and data DT are in a horizontal relationship with each other. In the case of a reverse IC, there is an effect that the pattern wiring is not complicated.

Such a configuration can also be applied to a case where the LED driver 605 and the S/P conversion circuit 606 are provided as the effect driving means, such as the upper right LED board 600 of the side unit. The upper right LED board 600 of the side unit has a configuration in which the clock signal CLK_P (CLK_A) and the data signal DATA_P (DATA_A) input to the connector CN1E are branched and supplied to the LED driver 605 and the S/P conversion circuit 606. In this case, if a chip is used as the S/P conversion circuit 606 in which the left-right relationship between the terminals of the clock signal CLK_A and the data signal DATA_A is opposite to that shown in FIG. Place it in This makes it possible to avoid complicating the wiring.

The gaming machine 1 of the embodiment has the following (configuration A6-1).
(Configuration A6-1)
The gaming machine 1 is
A first effect driving means using a chip component, a first input connector for inputting a clock and effect driving control data to the first effect driving means, and an output connector for outputting the clock and effect driving control data are provided. a first substrate,
a second board provided with a second effect driving means using a chip component, and a second input connector for inputting a clock and effect driving control data to the second effect driving means;
Equipped with
the left-right relationship of each input terminal of the clock and the control data for effect driving in the first effect driving means, when looking from the pattern wiring side to the chip side;
A left-right relationship between the clock and the input terminals of the control data for driving the effect in the second effect driving means when looking from the pattern wiring side to the chip side;
a left-right relationship of each connector terminal of the clock and production drive control data in the first input connector when looking from the connector terminal side to the direction in which the pattern wiring connected to each connector terminal is led;
the left-right relationship of each connector terminal of the clock and production drive control data in the output connector when looking in the direction of each connector terminal from the pattern wiring side connected to each connector terminal;
are the same,
The output connector and the second input connector are connected by a cross cable,
The assignment of each terminal of the second input connector is set in the reverse order of the assignment of each terminal of the first input connector,
In the first board, the first effect driving means and the first input connector are arranged on the same surface of the board,
In the second board, the second effect driving means and the second input connector are arranged on different sides of the board.

FIG. 83 schematically shows the structures of the first and second substrates.
A first input connector, a first effect driving means, and an output connector are mounted on the first board.
The first connector and the first effect driving means are arranged on the same surface on the first board (in the figure, the blocks of the first connector and the first effect driving means are both shown by solid lines).

The first connector inputs a clock CK and performance drive control data (data DT) to the first performance drive means.
The clock CK and data DT are supplied to the first effect driving means by pattern wiring PTH on the board.

A second input connector and a second effect driving means are mounted on the second board.
The second input connector and the second effect driving means are arranged on different surfaces on the second board. In the figure, the second effect driving means and part of the pattern wiring PTH are shown by broken lines, indicating that they are arranged on the back side of the second connector shown by solid lines. Pattern wiring PTH is formed on both sides via through holes TH.
In this case, the second effect driving means is shown in the same rectangle as the first effect driving means because the left and right relationship between the clock CK and data DT terminals is the same. . Also, since it is on the back side, the letters "CK" and "DT" are mirror-reversed.

The second input connector inputs the clock CK and the effect driving control data (data DT) to the second effect driving means. The clock CK and data DT are supplied to the second effect driving means through the pattern wiring PTH.

The second input connector is connected to the output connector of the first board by a cross cable 2000.
In this case, it is assumed that the output connector has a four-terminal configuration from the first pin to the fourth pin, and for example, the first pin is assigned to "power supply voltage VC", "clock CK", "data DT", and "ground GND" in order.
The second input connector also has a four-terminal configuration, but since it is connected with a cross cable 2000, the first pin is assigned to "ground GND", "data DT", "clock CK", and "power supply voltage VC" in order. will be done.

The left-right relationship between the clock CK and data DT terminals in the directions DIR61, DIR62, DIR63, DIR64, and DIR65 indicated by the arrows is shown at the bottom of the figure.
Directions DIR61 and DIR62 are directions defined similarly to the above-mentioned directions DIR1 and DIR2, respectively. Directions DIR64 and DIR65 are directions defined similarly to the above-mentioned directions DIR3 and DIR4, respectively. The direction DIR65 is considered as the viewing direction in the same state with respect to the direction DIR4 and the top and bottom of the chip, as described in the explanation of the direction DIR34 in FIG. 77.
The direction DIR63 is a direction from the pattern wiring side connected to each connector terminal of the output connector toward each connector terminal.

In this case, the left-right relationship between the clock CK and the data DT is the same when viewed in the directions DIR61, DIR62, DIR63, and DIR65, but the left-right relationship when viewed in the direction DIR64 is reversed. This is because they are connected by a cross cable 2000.

As an example corresponding to (configuration A6-1) as shown in FIG. 77, the following (specific example 9) is assumed.

(Specific example 9)
・First board: LED board 780 (see Figure 45)
・Second board: LED board 790A (see Figure 84)
・Clock (CK) for the first performance driving means: clock signal CLK
- Effect driving control data (DT) for the first effect driving means: data signal DATA
・First effect driving means: LED driver control unit 782
・Clock input terminal in the first production driving means: No. 2 terminal (SCLK terminal)
・Input terminal for control data for performance drive in the first performance drive means: No. 3 terminal (SDATA terminal)
・First input connector: Connector CN1N
・Clock connector terminal of the first input connector: 2nd pin ・Connector terminal of the production drive control data of the 1st input connector: 3rd pin ・Output connector: Connector CN2N
・Connector terminal for clock of output connector: 2nd pin ・Connector terminal for control data for driving performance of output connector: 3rd pin ・Second performance driving means: LED driver 791
・Clock (CK) for the second performance driving means: clock signal CLK
- Effect driving control data (DT) for the second effect driving means: data signal DATA
・Clock input terminal in the second production driving means: No. 2 terminal (SCLK terminal)
・Input terminal for control data for performance drive in the second performance drive means: No. 3 terminal (SDATA terminal)
・Second input connector: Connector CN1XA
・Clock connector terminal of the second input connector: 3rd pin ・Connector terminal of the production drive control data of the 2nd input connector: 2nd pin

In this (Specific Example 9), the circuit configuration of the LED board 780 corresponding to the first board is as explained in FIGS. It is located.

FIG. 84 shows a circuit configuration of an LED board 790A corresponding to the second board.
The electrical connection configuration in FIG. 84 is the same as that of the LED board 780 in FIG. 46. In this case, since the connector is connected by a cross cable 2000, the order of terminal assignment from the first pin to the fourth pin in the connector CN1XA in FIG. 84 is reversed from that in the connector CN1X in FIG. 46. That is, from the first pin, the terminals are, in order, a ground terminal, a data signal DATA terminal, a clock signal CLK terminal, and a 12V DC voltage (DC12VB) terminal.
Further, it is assumed that the LED driver 791 in FIG. 84 and the LED driver 791 in FIG. 46 are the same IC.

Therefore, when viewed in the direction DIR64 and when viewed in the direction DIR65, the left-right relationship between the data signal DATA terminal and the clock signal CLK terminal is reversed as shown in FIG. 83.

Therefore, in the example of FIG. 84, the LED driver 791 is arranged on a different surface from the connector CN1XA. For example, when the connector CN1XA is on the front layer, the LED driver 791 is arranged on the back layer. Of course, the opposite is also possible.

Since the left-right relationship between the terminal of the data signal DATA and the terminal of the clock signal CLK is reversed, when shown in a circuit diagram, a cross occurs in the wiring as shown by the broken line CRS in FIG. 84.
In this case, since the connector CN1XA and the LED driver 791 are on different surfaces, the left-right relationship of the wiring is adapted to the LED driver 791 at the stage of wiring via the through hole TH as shown in FIG.

According to (configuration A6-1) like the above (specific example 9), the following effects are obtained.
By connecting the first board and the second board with the cross cable 2000, the pin assignment of the second input connector must be reversed, and the pin assignment of the second input connector must be reversed. When using ICs with the same left-right relationship on the first and second boards, it is possible to improve wiring efficiency, shorten wiring length, reduce noise contamination, and simplify design on the first and second boards. .
On the first board, by matching the left-right relationship of the output connector with the first input connector, the wiring up to the output on the first board does not become complicated.
On the second board, the left-right relationship between the terminals of the second input connector and the second effect driving means is reversed, but the second input connector and the second effect driving means are on different surfaces, and wiring is done before and after the through hole. Wiring does not become complicated by making it compatible.
In the gaming machine 1, a cross cable such as an FFC (flexible flat cable) is mainly used for wiring to a movable body. The same IC is often used as an LED driver and a motor driver for a board (second board) inside the movable body and a board (first board) upstream thereof. In such a case, this configuration is effective.
For example, the above configuration is useful when the LED board 780 and the LED board 790A are connected via a movable part of a movable accessory.

It is also conceivable that the second effect driving means on the second board side is an IC in which the left-right relationship between the clock CK and data DT terminals is opposite to that of the first input connector and the first effect driving means.
In such a case, it is preferable to arrange the second input connector and the second effect driving means on the same surface of the second board.
In this way, when looking at the connector CN1XA whose terminal assignment order has been reversed by using the cross cable 2000 and the second effect driving means, in the direction of the clock CK and data DT terminals DIR64 and DIR65. The left and right relationships of are the same.
Therefore, pattern wiring on the same surface can be prevented from becoming complicated.

The gaming machine 1 of the embodiment has the following (configuration A7-1).
(Configuration A7-1)
The gaming machine 1 is
a first board provided with a first effect driving means using a chip component, and a first connector for inputting a clock, effect driving control data, and power supply voltage to the first effect driving means;
a second board provided with a second connector for inputting a clock, performance drive control data, and power supply voltage to the second performance drive means;
Equipped with
In the first substrate,
The first effect driving means and the first connector are arranged on the same surface of the board,
a left-right relationship between the input terminals of the clock, the control data for driving the performance, and the power supply voltage in the first performance driving means when looking from the pattern wiring side to the chip side;
The left-right relationship between the connector terminals of the clock, production drive control data, and power supply voltage in the first connector when looking in the direction in which the pattern wiring connected to each connector terminal is led from the connector terminal side. ,
are the same,
In the second substrate,
The left-right relationship of the clock, production drive control data, and power supply voltage connector terminals in the second connector when viewed from the connector terminal side to the direction in which the pattern wiring connected to each connector terminal is led out is , is the same as the first connector.

FIG. 85 schematically shows the structures of the first and second substrates.
In addition, "power supply voltage VC" refers to the power supply voltage supplied to the effect driving means.

A first connector and a first effect driving means are mounted on the first board.
The first connector and the first effect driving means are arranged on the same surface on the first board.
The first connector inputs the power supply voltage VC, clock CK, and performance drive control data (data DT) for the first performance drive means.
The power supply voltage VC, clock CK, and data DT are supplied to the first effect driving means through pattern wiring PTH on the board.

A second connector is mounted on the second board.
The second connector inputs the power supply voltage VC, clock CK, and performance drive control data (data DT) to the second performance drive means.
In the figure, the second effect driving means is not shown on the second board, but it may be one of the following.
- The second effect driving means is mounted on the second board on the same surface as the second connector. - The second effect driving means is mounted on the second board on a different surface from the second connector. The second production driving means is mounted on another board downstream from the second board.

In this case, directions DIR71, DIR72, and DIR73 indicated by arrows are directions defined similarly to the above-mentioned directions DIR1, DIR2, and DIR3, respectively.
The left-right relationship among the power supply voltage VC terminal, clock CK terminal, and data DT terminal when viewed in directions DIR71, DIR72, and DIR73 is shown in the lower part of FIG. In this example, the power supply voltage VC terminal, the clock CK terminal, and the data DT terminal are arranged in this order from left to right in the figure, and the left and right relationships are all the same.
As an example corresponding to (configuration A7-1) as shown in FIG. 85, the following (specific example 10) is assumed.

(Specific example 10)
・First board: LED board 780 (see Figure 45)
・Second board: LED board 790 (see Figure 46)
・Power supply voltage for the first performance driving means: 12V DC voltage (DC12VB)
・Clock (CK) for the first performance driving means: clock signal CLK
- Effect driving control data (DT) for the first effect driving means: data signal DATA
・First effect driving means: LED driver 782
・Input terminal of power supply voltage in first performance driving means: No. 48 terminal (SVCC terminal)
・Clock input terminal in the first production driving means: No. 2 terminal (SCLK terminal)
・Input terminal for control data for performance drive in the first performance drive means: No. 3 terminal (SDATA terminal)
・First connector: Connector CN1N
・Connector terminal for the power supply voltage of the first connector: 1st pin ・Connector terminal for the clock of the first connector: 2nd pin ・Connector terminal for the production drive control data of the first connector: 3rd pin ・2nd Connector: Connector CN1X
・Connector terminal for the power supply voltage of the second connector: 1st pin ・Connector terminal for the clock of the second connector: 2nd pin ・Connector terminal for the production drive control data of the 2nd connector: 3rd pin

The LED board 780 corresponding to the first board in this (Specific Example 10) has been described with reference to FIGS. 45, 60, and 61. Further, the LED board 790 corresponding to the second board has been described with reference to FIGS. 46, 63, and 64. The terminal configuration of the LED driver 782 has been described with reference to FIG. 62.

In this specific example, the left-right relationships corresponding to the directions DIR71, DIR72, and DIR73 are all as in the example shown in FIG. 85. In the LED driver 782, the 48th terminal (SVCC terminal) is on a different side of the chip from the 2nd terminal (SCLK terminal) and the 3rd terminal (SDATA terminal), but if you look at the left-right relationship, they are as shown in Figure 85. becomes.

In the case of this configuration, the same effects as the above (configuration A1-1) can be obtained (reduced wiring length, improved wiring efficiency, and reduced noise contamination), and in addition, these effects can also be obtained for the power supply wiring. .

Furthermore, the gaming machine 1 of the embodiment has the following (configuration A7-2) in addition to (configuration A7-1).
(Configuration A7-2)
The second board has a second effect driving means made of a chip component that inputs a clock and control data for effect driving through pattern wiring from the second connector,
In the second board, the second effect driving means and the second connector are arranged on the same surface of the board,
The left-right relationship of the input terminals of the clock, the control data for effect driving, and the power supply voltage in the second effect driving means when viewed from the pattern wiring side to the chip side is the same as that of the first effect driving means.

FIG. 86 schematically shows the first substrate and second substrate in this (configuration A7-2).
FIG. 86 is similar to FIG. 85 regarding the first board, except that the second effect driving means is shown on the second board. In the second board, the power supply voltage VC, clock CK, and data DT are supplied from the second connector to the second effect driving means through the pattern wiring PTH on the board.
In this second board, the second light emitting drive means is arranged on the same surface as the second connector. Direction DIR74 is a direction defined similarly to direction DIR14 described above.

As an example corresponding to (configuration A7-2) in FIG. 86, in addition to the above (specific example 10), the following (specific example 11) is assumed.

(Specific example 11)
・Second effect driving means: LED driver 791
・Input terminal of power supply voltage in second performance driving means: No. 48 terminal (SVCC terminal)
・Clock input terminal in the second production driving means: No. 2 terminal (SCLK terminal)
・Input terminal for control data for performance drive in the second performance drive means: No. 3 terminal (SDATA terminal)

Note that the terminal configuration of the LED driver 791 is as described in FIG. 62.
Therefore, the LED board 790 corresponding to the second board has the following configuration.
- In the LED board 790, the connector CN1X and the LED driver 791 are arranged on the same surface on the board.
- The left-right relationship of the SVCC terminal to which the 12V DC voltage (DC12VB) is input, the clock signal CLK terminal, and the data signal DATA terminal is as shown as the direction DIR74 in FIG. 86. Therefore, the left-right relationships in the directions DIR71, DIR72, DIR73, and DIR74 for the power supply voltage VC terminal, clock CK terminal, and data DT terminal are all the same.

Therefore, the configurations of (Specific Example 10) and (Specific Example 11) correspond to (Configuration A7-2) in FIG. 86.
In this way, by adopting the same left-right relationship of the terminals on the second board as on the first board, and making it possible to streamline the wiring from the connector to the performance drive means, including the power supply voltage wiring, using multiple boards, It is possible to improve the wiring efficiency of multiple boards within the game machine 1, reduce noise contamination, and improve design efficiency, and promote stable performance operations.

Furthermore, the gaming machine 1 of the embodiment has the following (configuration A7-3) in addition to (configuration A7-1) and (configuration A7-2).
(Configuration A7-3)
The gaming machine 1 is
A third board is provided with a third connector for inputting a clock, control data for driving the performance, and power supply voltage to the third performance driving means,
The left-right relationship of the clock, production drive control data, and power supply voltage connector terminals in the third connector when viewed from the connector terminal side to the direction in which the pattern wiring connected to each connector terminal is led out is , is the same as the first connector.

FIG. 87 schematically shows the first substrate, second substrate, and third substrate in this (configuration A7-3). The first and second substrates are similar to those shown in FIG. 86, and FIG. 87 shows that a third substrate is added.

A third connector is mounted on the third board.
Pattern wiring PTH for power supply voltage VC, clock CK, and data DT is derived from the third connector.
In this figure, the third effect driving means is not shown on the third board, but it may be one of the following.
- The third effect driving means is mounted on the same surface as the third connector on the third board. - The third effect driving means is mounted on the third board on a different surface from the third connector. The effect driving means of No. 3 is mounted on another board downstream from the third board.

Direction DIR75 is a direction defined similarly to direction DIR5 described above.
The left-right relationship of the power supply voltage VC terminal, clock CK terminal, and data DT terminal when viewed in the directions DIR71, DIR72, DIR73, DIR74, and DIR75 is shown at the bottom of FIG. 87, but they are all the same. It has become.

As an example corresponding to (configuration A7-3) as shown in FIG. Example 12) is assumed.

(Specific example 12)
- Third board: relay board 760 (see Figure 44)
・Clock (CK) for the third performance driving means: clock signal CLK_C
- Effect driving control data (DT) for the third effect driving means: data signal DATA_C
・Third connector: Connector CN1M
・Connector terminals for the power supply voltage of the third connector: 1st pin, 2nd pin, 3rd pin ・Connector terminals for the clock of the 3rd connector: 6th pin ・Connector for the control data for driving the performance of the 3rd connector Terminal: 9th pin

In addition, considering the third effect driving means in (Specific Example 12), for example, an LED driver of an LED board (not shown) connected to the connector CN2M in FIG. 44 is assumed.

According to such (configuration A7-3), it is possible to improve wiring efficiency on a plurality of substrates, reduce noise mixing, and further improve design efficiency. In other words, the effects of (configuration A7-1) and (configuration A7-2) can be made more pronounced.

The gaming machine 1 of the embodiment has the following (configuration A8-1).
(Configuration A8-1)
The gaming machine 1 is
A first performance driving means using chip components;
a second performance driving means using chip components;
a connector for inputting a first system clock and performance drive control data to the first performance drive means and inputting a second system clock and performance drive control data to the second performance drive means;
a first substrate provided with
In the first board, the first effect driving means, the second effect driving means, and the connector are arranged on the same surface,
the left-right relationship of each input terminal of the clock and the control data for effect driving in the first effect driving means, when looking from the pattern wiring side to the chip side;
a left-right relationship between each connector terminal of the first system clock and production drive control data in the connector, when looking from the connector terminal side to the direction in which pattern wiring connected to the connector terminal is led;
are the same,
A left-right relationship between the clock and the input terminals of the control data for driving the effect in the second effect driving means when looking from the pattern wiring side to the chip side;
a left-right relationship between each connector terminal of the second system clock and production drive control data in the connector, when looking from the connector terminal side to the direction in which pattern wiring connected to the connector terminal is led;
are the same gaming machines.

Furthermore, the gaming machine 1 of the embodiment may have the following (configuration A8-2) in addition to (configuration A8-1).
(Configuration A8-2)
In the connector,
a left-right relationship of each connector terminal of the first system clock and production drive control data when looking from the connector terminal side to the direction in which pattern wiring connected to each connector terminal is led;
a left-right relationship between the second system clock and each connector terminal of the production drive control data when looking from the connector terminal side to the direction in which the pattern wiring connected to the connector terminal is led;
are the same.

Alternatively, the gaming machine 1 of the embodiment may have the following (configuration A8-3) in addition to (configuration A8-1).
(Configuration A8-3)
In the connector,
a left-right relationship of each connector terminal of the first system clock and production drive control data when looking from the connector terminal side to the direction in which pattern wiring connected to each connector terminal is led;
a left-right relationship between the second system clock and each connector terminal of the production drive control data when looking from the connector terminal side to the direction in which the pattern wiring connected to the connector terminal is led;
is the opposite.

FIGS. 88 and 89 schematically show the configuration of the first substrate (configuration A8-1).
Note that FIG. 88 is an example corresponding to (configuration A8-1) or (configuration A8-2).
Further, FIG. 89 is an example corresponding to (configuration A8-1) or (configuration A8-3).

First, in FIG. 88, a connector, a first effect driving means, and a second effect driving means are mounted on the first board. The connector, the first effect driving means, and the second effect driving means are arranged on the same surface on the first board.
The connector inputs a clock CK and performance drive control data (data DT) to the first performance drive means. The clock CK and data DT are supplied to the first effect driving means through the pattern wiring PTH1.
Further, the connector separately inputs a clock CK and performance drive control data (data DT) for the second performance drive means. This clock CK and data DT are supplied to the second effect driving means through pattern wiring PTH2.
The first effect driving means and the second effect driving means have the same left-right relationship between the clock CK and data DT terminals, so they are shown by the same rectangle.

In this case, directions DIR81-1 and DIR81-2 indicated by arrows are directions defined similarly to the above-mentioned direction DIR1, and DIR82 and DIR83 are directions defined similarly to direction DIR2.
The left-right relationship between the clock CK terminal and the data DT terminal when viewed in the directions DIR81-1, DIR81-2, DIR82, and DIR83 is shown in the lower part of FIG. In this example, the clock CK terminal is on the left and the data DT terminal is on the right, and the left-right relationship is the same.

In other words, - The left-right relationship when viewed in directions DIR81-1 and DIR82 is the same. - The left-right relationship when viewed in directions DIR81-2 and DIR83 is the same, so it corresponds to configuration A8-1. In addition,
・Since the left-right relationship is the same when viewed in directions DIR81-1 and DIR81-2, it also corresponds to configuration A8-2.

Next, FIG. 89 will be explained. FIG. 89 has the same configuration as FIG. 88 in that the connector, the first effect driving means, and the second effect driving means are arranged on the same surface on the first board.
However, in FIG. 89, the left-right relationship between the clock CK terminal and the data DT terminal when viewed in the directions DIR81-1 and DIR82 is as follows: the clock CK terminal is on the left, and the data DT terminal is on the right. On the other hand, when viewed in the directions DIR81-2 and DIR83, the left-right relationship between the clock CK terminal and the data DT terminal is as follows: the data DT terminal is on the left, and the clock CK terminal is on the right. ing.
Since the first effect driving means and the second effect driving means have different left-right relationships between the clock CK and data DT terminals, the first effect driving means is shown as a rectangle, and the second effect driving means is shown as an octagon. There is.

In other words, - The left-right relationship when viewed in directions DIR81-1 and DIR82 is the same. - The left-right relationship when viewed in directions DIR81-2 and DIR83 is the same, so it corresponds to configuration A8-1. In addition, - Direction DIR81-1, Since the left-right relationship when viewed with DIR81-2 is reversed, it also corresponds to configuration A8-3.

Specific examples of FIGS. 88 and 89 above will be given.
First, the following (specific example 13) is assumed as a specific example of (configuration A8-1) or (configuration A8-2) in FIG.

(Specific example 13)
・First board: LED connection board 1500 (see Figures 50 to 57)
・Clock (CK) for the first performance driving means: clock signal LSI_SCK
- Effect driving control data (DT) for the first effect driving means: serial data signal LSI_MOSI
- First effect driving means: motor driver control section 1530 (see FIG. 55)
・Clock input terminal in the first production driving means: No. 5 terminal (SCK terminal)
・Input terminal for control data for performance drive in the first performance drive means: No. 7 terminal (MOSI terminal)
・Connector: Connector CN1V
・Connector terminal of the first system clock of the connector: 3rd pin ・Connector terminal of the first system performance drive control data of the connector: 7th pin ・Second performance driving means: motor driver 1505 (see FIG. 50). However, the arrangement is different from the example in FIG. 72, in which it is arranged on the surface layer)
・Clock (CK) for the second performance driving means: clock signal CLK_M
- Effect driving control data (DT) for the second effect driving means: data signal DATA_M
・Clock input terminal in the second performance driving means: No. 13 terminal (SCLK terminal)
・Input terminal for control data for performance drive in the second performance drive means: No. 14 terminal (SDIN terminal)
・Connector terminal for the second system clock of the connector: 23rd pin ・Connector terminal for the control data for driving the performance of the second system of the connector: 25th pin

In the arrangement example of the LED connection board 1500 shown in FIGS. 71 and 72, the motor driver 1505 is arranged on the back layer, but in this specific example 13, the motor driver 1505 is arranged on the front layer, and thereby This is an example in which the connector CN1V, the motor driver control unit 1530, and the motor driver 1505 are all arranged on the surface layer.

The left-right relationship of the 3rd and 7th pins, which are the connector terminals of the first system clock CK and data DT of the connector CN1V, as seen in the direction DIR83-1, and the 5th terminal (SCK terminal) and 7th terminal of the motor driver control unit 1530. The left-right relationship of the number terminal (MOSI terminal) as seen in the direction DIR82 is the same as the left-right relationship seen in the directions DIR21 and DIR22 as described above in the explanation of (configuration A3-1).

Also, the left-right relationship of the 23rd and 25th pins, which are the connector terminals for the second system clock CK and data DT of the connector CN1V, as seen in the direction DIR83-2 is that the left is the clock CK terminal and the right is the data DT terminal. Become.
Also, as shown in FIG. 51, the motor driver 1505 inputs the clock signal CLK_M to the 13th terminal (SCLK terminal) and the data signal DATA_M to the 14th terminal (SDIN terminal), so when viewed from the direction of the terminals DIR83. The left and right terminals are the clock CK terminal and the right terminal is the data DT terminal.

From the above, it is understood that the above (specific example 13) has the configuration shown in FIG. 88.
In the case of this (configuration A8-1), in addition to obtaining the same effects as the above-mentioned (configuration A1-1) (reduction in wiring length, improvement in wiring efficiency, and reduction in noise contamination), there is the following effect.

First, since efficient wiring can be realized for the first and second plural systems of clock CK and data DT, the same effect as in (configuration A1-1) becomes noticeable.
In addition, in the case of (configuration A8-1), the pin assignments of the clock CK and data DT of multiple systems are matched to the respective drivers in the connector, so it is possible to prevent crosses and large detours from occurring in each system. , Wiring from the connector to each performance drive means can be made more efficient. This is also suitable for reducing noise mixing. Therefore, this configuration is effective for a board in which a plurality of effect driving means are arranged on the same surface as the connector.

Furthermore, (configuration A8-2) is suitable when using a plurality of performance driving means in which the clock CK and data DT terminals have the same left-right relationship.
In addition, since the left-right relationship of pin assignments is unified between the first system and the second system in the connector, there is an advantage that design can be made more efficient.

Next, (Specific Example 14) will be given as a specific example of (Configuration A8-1) or (Configuration A8-3). In (Specific Example 14), the first board is the same LED connection board 1500, the connector is the connector CN1V, the motor driver control unit 1530 is mentioned as the first effect driving means, and the first system is as described above (Specific Example 13). ).

(Specific example 14)
・Second effect driving means: LED drivers 1510, 1511, 1520, 1521, 1522 (see FIGS. 52, 53, and 54. However, the arrangement is different from the example shown in FIG. 72 and is arranged on the surface layer)
・Clock for the second performance driving means: clock signals CLK_A, CLK_B
- Effect driving control data for the second effect driving means: data signals DATA_A, DATA_B
・Clock input terminal in the second production driving means: No. 48 terminal (SCLK terminal)
・Input terminal for control data for driving the performance of the second performance driving means: No. 47 terminal (SDATA terminal)
・Connector: Connector CN1V (However, the pin assignment is different from that in Figure 50)
・Connector terminal of the second system clock of the connector: 15th pin (example different from Figure 50)
・Connector terminal for control data for performance drive of the second system of the connector: 13th pin (example different from Fig. 50)

Figure 50 shows an example in which the 13th pin of connector CN1V is assigned to the clock signal CLK_P (=CLK_A) and the 15th pin is assigned to the data signal DATA_P (=CLK_B), but in this (specific example 14), this is reversed. Here is an example of assigning. In other words, assume that the 15th pin is assigned to the clock signal CLK_P (=CLK_A) and the 13th pin is assigned to the data signal DATA_P (=CLK_B).
In this case, when viewed in the direction DIR81-2 in FIG. 89, the left side is the connector terminal for data DT and the right side is the connector terminal for clock CK, as shown.

Furthermore, as a representative example of the second effect driving means, the LED driver 1521 in FIG. The left-right relationship between the clock CK and data DT terminals as terminals (SDATA terminals) is such that when viewed in the direction DIR83 in FIG. 89, the left terminal is the data DT terminal and the right terminal is the clock CK terminal, as shown in the figure. . It is assumed that such an LED driver 1521 is arranged on the same surface as the connector CN1V.

Then, (Specific Example 14) has the configuration shown in FIG. 89.
In the case of this (configuration A8-3), in addition to the same effect as the above-mentioned (configuration A8-1), multiple effect driving means with clock terminals and data terminals with opposite left-right relationships are arranged on the same surface. In such cases, the effect of increasing the efficiency of pattern wiring can be obtained by dealing with this on the connector side.

In (Specific Example 14), the first system was used as a drive system for the motor, and the second system was used as a drive system for the LED. In this way, (configuration A8-1), (configuration A8-2), and (configuration A8-3) are suitable even when a motor performance driving means and a light emitting performance driving means are arranged as a plurality of performance driving means.
In particular, in the motor effect driving means and the light emitting effect driving means, the clock CK and data DT may be provided in different systems, thereby making it possible to further diversify the light emitting effects and effects such as ornaments. In such a case, if the left-right relationship between the clock CK and data DT terminals is reversed between the IC of the motor effect driving means and the IC of the light emitting effect driving means arranged on the same plane, the first system on the connector side As the assignment of the second system, by reversing the left-right relationship between the connector terminals of the clock CK and the data DT, wiring efficiency can be realized.

The gaming machine 1 of the embodiment has the following (configuration A9-1).
(Configuration A9-1)
The gaming machine 1 is
A first performance driving means using chip components;
a second performance driving means using chip components;
an input connector for inputting a first system clock and performance drive control data to the first performance drive means, and inputting a second system clock and performance drive control data to the second performance drive means;
a first substrate provided with
In the first substrate,
The first effect driving means is arranged on the same surface as the input connector,
The second effect driving means is arranged on a different surface from the input connector,
the left-right relationship of each input terminal of the clock and the control data for effect driving in the first effect driving means, when looking from the pattern wiring side to the chip side;
The left-right relationship of each connector terminal of the first system clock and production drive control data in the input connector when looking from the connector terminal side to the direction in which the pattern wiring connected to each connector terminal is led out. ,
The left-right relationship of each connector terminal of the second system clock and production drive control data in the input connector when looking from the connector terminal side to the direction in which pattern wiring connected to each connector terminal is led out. ,
are the same,
A gaming machine, wherein the left-right relationship of the input terminals of the clock and performance drive control data in the second performance driving means when viewed from the pattern wiring side to the chip side is opposite to that of the first performance driving means.

FIG. 90 schematically shows the structure of this first substrate.
The first board is equipped with an input connector, a first effect driving means, and a second effect driving means.
The input connector and the first effect driving means are arranged on the same surface on the first board (in the figure, the blocks of the first connector and the first effect driving means are both shown by solid lines).
The input connector and the second effect driving means are arranged on different surfaces on the first board (in the figure, the second effect driving means is shown by a broken line, and is arranged on the back side of the connector shown by a solid line). It shows that
Further, the second effect driving means is shown as an octagon to indicate that it is a chip having a different left-right relationship between the clock CK and data DT terminals than the first effect driving means shown as a rectangle. Furthermore, since it is on the back side, the letters "CK" and "DT" of the second effect driving means are mirror-inverted.

The input connector inputs a first system clock CK and performance drive control data (data DT) to the first performance drive means. The first system clock CK and data DT are supplied to the first effect driving means through pattern wiring PTH1 on the board.
The input connector also inputs a second system clock CK and performance drive control data (data DT) to the second performance drive means. The second system clock CK and data DT are supplied to the second effect driving means through pattern wiring PTH2 on the board. The pattern wiring PTH2 is formed over both surfaces via the through hole TH.

In this case, directions DIR91-1 and DIR91-2 indicated by arrows are directions defined similarly to the above-mentioned direction DIR1, and DIR92 and DIR93 are defined similarly to directions DIR52 and DIR53 described in FIG. This is the direction in which
The left-right relationship between the clock CK terminal and the data DT terminal when viewed in the directions DIR91-1, DIR91-2, DIR92, and DIR93 is shown in the lower part of FIG. In this example, when viewed in the directions DIR91-1, DIR91-2, and DIR92, the left side of the figure is the clock CK terminal, and the right side is the data DT terminal. On the other hand, when viewed from the DIR 93, the right side of the figure is the clock CK terminal, and the left side is the data DT terminal.

As an example corresponding to (configuration A9-1) as shown in FIG. 90, the following (specific example 15) is assumed.

(Specific example 15)
・First board: LED connection board 1500 (see Figures 50 to 57)
・Clock (CK) for the first performance driving means: clock signal LSI_SCK
- Effect driving control data (DT) for the first effect driving means: serial data signal LSI_MOSI
- First effect driving means: motor driver control section 1530 (see FIG. 55)
・Clock input terminal in the first production driving means: No. 5 terminal (SCK terminal)
・Input terminal for control data for performance drive in the first performance drive means: No. 7 terminal (MOSI terminal)
・Input connector: Connector CN1V
・Connector terminal for the first system clock of the input connector: 3rd pin ・Connector terminal for the control data for driving the first system of the input connector: 7th pin ・Second performance driving means: LED driver 1510, 1511, 1520, 1521, 1522 (see Figure 52, Figure 53, Figure 54)
・Clock (CK) for the second performance driving means: clock signals CLK_A, CLK_B
- Effect driving control data (DT) for the second effect driving means: data signals DATA_A, DATA_B
・Clock input terminal in the second production driving means: No. 48 terminal (SCLK terminal)
・Input terminal for control data for driving the performance of the second performance driving means: No. 47 terminal (SDATA terminal)
・Connector terminal for the second system clock of the input connector: 13th pin ・Connector terminal for the control data for driving the performance of the second system of the input connector: 15th pin

Regarding each of these components, repeated explanations will be avoided as they overlap with the explanation of (Specific Example 8) given in (Configuration A5-1) above, but (Specific Example 15) is schematically shown in FIG. 90. This corresponds to the configuration shown.
In the case of this configuration, in addition to obtaining the same effects as the above-mentioned (configuration A1-1) (reduction in wiring length, improvement in wiring efficiency, and reduction in noise contamination), there is the following effect.

In other words, in (configuration A9-1), in a board where one input connector has a plurality of sets of clock CK and data DT, when the left-right relationship between the clock CK and data DT terminals of the production driving means is reversed, the connector The terminals are assigned in a configuration that matches the first performance drive means on the same surface.

For example, when using old and new driver chips as multiple performance drive means, placing driver chips with opposite left and right relationships on the back side of the input connector will prevent wiring crosses and large turns in each system. This allows wiring from the input connector to each performance drive means to be made more efficient. It is also suitable for reducing noise mixing.
In addition, since the left and right pin assignments are unified for the first system and the second system in the input connector, design can be made more efficient.

Furthermore, the gaming machine 1 of the embodiment has the following (configuration A9-2) in addition to (configuration A9-1).
(Configuration A9-2)
The first board includes an output connector that outputs a clock and production drive control data,
In the first substrate,
the output connector is disposed on the same plane as the input connector,
the left-right relationship of each connector terminal of the clock and production drive control data in the input connector when looking from the connector terminal side to the direction in which pattern wiring connected to each connector terminal is led;
the left-right relationship of each connector terminal of the clock and production drive control data in the output connector when looking in the direction of each connector terminal from the pattern wiring side connected to each connector terminal;
are the same.

FIG. 91 schematically shows the first substrate in this (configuration A9-2). Note that the configuration is the same as that in FIG. 90 except that it includes an output connector.
The output connector in FIG. 91 is a connector for transmitting the clock CK and data DT to the downstream board.
The direction DIR94 is the direction when looking toward each connector terminal from the pattern wiring side connected to each connector terminal of the output connector, and the left-right relationship is as shown at the bottom of the figure, with the clock CK on the left. The data DT terminals are arranged on the right. In other words, the left-right relationship is the same as seen in the directions DIR91-1, DIR91-2, and DIR92.

As a specific example, the following (specific example 16) regarding the output connector may be added to the above (specific example 15).

(Specific example 16)
・Output connector: Connector CN2V (see Figure 50)
・Output connector clock connector terminal: 3rd pin ・Input connector production drive control data connector terminal: 5th pin

In the case of the connector CN2V, the left-right relationship between the respective terminals of the clock signal CLK_C and the serial data signal DATA_C as seen in the direction DIR94 is as shown in FIG.
Therefore, the LED connection board 1500 having the configurations of (Specific Example 15) and (Specific Example 16) has the configuration of FIG. 91.
According to such (configuration A9-2), it is possible to realize wiring efficiency including wiring to the output connector on the first board.

Furthermore, the gaming machine 1 of the embodiment has the following (configuration A9-3) in addition to (configuration A9-1) and (configuration A9-2).
(Configuration A9-3)
comprising a second board provided with an input connector for inputting a clock and performance drive control data to the third performance drive means;
The left-right relationship of each connector terminal for the clock and production drive control data in the input connector on the second board when looking from the connector terminal side to the direction in which the pattern wiring connected to each connector terminal is led is as follows: These connector terminals are the same as those for the first system clock and performance drive control data in the input connector of the first board.

FIG. 92 schematically shows the first substrate in this (configuration A9-3). Note that the configuration of the first substrate in FIG. 92 is the same as that in FIG. 91.

The second board is equipped with an input connector for inputting the clock CK and data DT to the third effect driving means. Pattern wiring PTH for clock CK and data DT is derived from this input connector.

In this figure, the third effect driving means is not shown on the second board, but it may be one of the following.
- The third effect driving means is mounted on the same surface as the input connector on the second board. - The third effect driving means is mounted on the second board on a different surface from the input connector. - The third effect driving means The means is mounted on another board downstream of the second board.

The direction DIR95 is the direction of the input connector on the second board when looking from the connector terminal side of the clock CK and data DT toward the direction in which the pattern wiring PTH connected to each connector terminal is led out. In this case, in this example, the clock CK terminal is on the left, and the data DT terminal is on the right.

The left-right relationship between the clock CK terminal and the data DT terminal when viewed in the directions DIR91-1, DIR91-2, DIR92, DIR93, DIR94, and DIR95 is shown at the bottom of the figure. The left-right relationship of the terminals of the DT is the same except when viewed in the direction DIR93.

As an example corresponding to (configuration A9-3) as shown in FIG. Example 17) is assumed.

(Specific example 17)
・Second board: LED board 1600 (see Figure 58)
・Second board input connector: Connector CN1W
・Clock connector terminal in the input connector of the second board: 2nd pin ・Connector terminal for production drive control data in the input connector of the 2nd board: 5th pin

In the case of the connector CN1W, the left-right relationship between the respective terminals of the clock signal CLK and the data signal DATA as seen in the direction DIR95 is as shown in FIG.
Therefore, the gaming machine 1 having the LED connection board 1500 and the LED board 1600 having the configurations of (Specific Example 15), (Specific Example 16), and (Specific Example 17) has the configuration shown in FIG.
According to such (configuration A9-3), there is an advantage that the design can be made more efficient by making the assignment of the clock CK and data DT of the input connector common between the first board and the second board.

Up to this point, we have explained (Configuration A1-1) to (Configuration A9-3), but the following (Configuration A100), (Configuration A101), (Configuration A102), and (Configuration A103) are applied to each of these configurations. can do.

(Configuration A100)
The chip components in (configuration A1-1) to (configuration A9-3) above are surface-mounted chips.

In the above (configuration A1-1) to (configuration A9-3), the first effect driving means, the second effect driving means, and the third effect driving means are mentioned as chip components. Note that the presentation drive means also includes a light emission drive means and a motor drive means.

That is, the chip components include, for example, the LED drivers 782 and 791 in (Specific Example 1). The LED drivers 782 and 791 described in FIG. 62 are surface-mounted chips. It can be seen from the pad shapes of "p782" in FIG. 60 and "p791" in FIG. 63 that this is a surface mount type chip.

The motor driver control unit 1530, the S/P conversion circuit 606, the LED driver 1601, the LED drivers 1510, 1511, 1520, 1521, 1522, the motor driver 1505, etc. are also illustrated as the effect driving means. These are also surface mount chips.

For dip parts that are not surface-mounted, that is, chips whose leads are fixed by passing them through holes (vias/through holes) on the board, by reversing the wiring relationship left and right on the back side of the board, the left-right relationship between the terminals of the connector and the directing drive means can be adjusted. However, this is not possible with surface-mounted chips.
In other words, when using a surface-mounted chip as the effect driving means, if the above-mentioned left-right relationship between the clock CK and the data DT is reversed between the connector and the effect driving means, unnecessary wiring paths will increase and the wiring will become complicated. I end up.
Considering this point, when surface-mounted chips are used as the first effect driving means, the second effect driving means, etc., the effects of (Configuration A1-1) to (Configuration A9-3) will become significant. be understood.

(Configuration A101)
The chip components in (configuration A1-1) to (configuration A9-3) above are approximately rectangular chips with terminals formed on four sides.

Effect drive means (light emission drive means, The chip exemplified as the motor drive means (motor drive means) is a substantially rectangular chip with terminals formed on four sides.

For example, the LED drivers 782 and 791 are approximately rectangular chips having terminals formed on four sides, as described with reference to FIG. Further, as described with reference to FIG. 80, the LED driver 1601 and the like are also substantially rectangular chips with terminals formed on four sides.

In the case of a rectangular chip with terminals formed on each of the four sides, even if the wiring is routed around it, it is difficult or impossible to deal with the case where the left-right relationship of the terminals between the connector and the LED driver is reversed. . This is because if you try to reverse the left-right relationship by running wires around it, it will interfere with the wires to other terminals.
In other words, in the case of a chip in which terminals are formed on four sides, if any of the configurations from (Configuration A1-1) to (Configuration A9-3) is adopted, the wiring will be routed around and the left-right relationship will be reversed. It is no longer necessary to deal with this, and the effect of improving wiring efficiency becomes significant.

(Configuration A102)
The first substrate, second substrate, third substrate, etc. in the above (configuration A1-1) to (configuration A9-3) are substrates with two-layer wiring on the front surface and the back surface of the substrate.

For example, the LED connection board 1500 corresponding to the first board of (configuration A4-1) is a board with two-layer wiring on the front surface of the board and the back surface of the board, as described with reference to FIGS. 71 and 72. The LED board 1600 corresponding to the second board is also a board with two-layer wiring on the front surface and the back surface of the board, as described with reference to FIGS. 78 and 79.

A board with two layers of wiring on the front and back sides is cheaper than a board with multilayer wiring provided with an inner layer. On the other hand, since there are only two layers for forming pattern wiring, more efficient pattern design is required. In such a case, the techniques from (configuration A1-1) to (configuration A9-3) are effective, and can also promote cost reduction of the substrate.

(Configuration A103)
In the above (configuration A1-1) to (configuration A9-3), the clock CK and data DT from the connector are transferred to the effect driving means (light emitting driving means) through a buffer circuit that does not change the left-right relationship between the clock CK and data DT. , motor drive means).
In this case, the buffer circuit is a chip component, and the left-right relationship does not change.
・The left-right relationship of each input terminal of the clock and production drive control data in the buffer circuit when looking from the pattern wiring side to the chip side,
・The left-right relationship of each output terminal of the clock and production drive control data in the buffer circuit when looking in the direction of derivation of the pattern wiring connected to each output terminal,
This means that they are the same.

For example, buffer circuits 1501, 1502, 1503, etc. in FIG. 50 have such a configuration. For example, in configurations such as (configuration A3-1) and (configuration A5-1) that use the LED connection board 1500 as a specific example, the clock CK and data DT are supplied to the effect driving means via a buffer circuit.

By doing so, signal compensation of the clock CK and data DT is performed on the board, and stable signal transmission is realized on the board. It also improves noise resistance.
Since the left-right relationship between the input terminal and the output terminal of the buffer circuit is not changed, the effects of the configurations (configuration A1-1) to (configuration A9-3) can be obtained.

[7.2 Slave address]
In the game machine 1 of the embodiment, setting of a slave address for the effect driving means as a chip component mounted on the board will be explained.

The gaming machine 1 of the embodiment has the following (configuration B1-1).
(Configuration B1-1)
The gaming machine 1 is
It has a plurality of effect driving means of the same configuration made of chip parts that are approximately rectangular and have terminals formed on two or more sides,
The performance driving means is
X terminals formed by consecutive terminal numbers from the first side to the second side, which are two consecutive sides, are taken as address terminals for setting the slave address,
(x1) address terminals are formed on the first side,
(x2) address terminals are formed on the second side,
(x1)+(x2)=X, and (x1)<(x2),
All of the plurality of effect driving means have at least one of the (x2) address terminals on the second side, and a specific address terminal common to the plurality of effect driving means is It is set to L level. However, X, x1, and x2 are natural numbers.

It should be noted that the plurality of effect driving means having the "same configuration" may be interpreted in any of the following ways.
・Multiple effect driving means using the same IC chip (IC chip with the same model number) ・Multiple effect driving means using IC chips with the same number of terminals for slave address setting even if they are not all the same IC chip

From the viewpoint of the same configuration as described above, for example, effect driving means (for example, LED drivers) with "different configurations" may coexist in the gaming machine 1. In such a case, the effect driving means with "different configurations" are not included in "'all' of the plurality of effect driving means" in (configuration B1-1). In other words, (configuration B1-1) defines the configuration of a plurality of effect driving means having the same configuration.
In addition, "all" means all of the performance driving means that are individually assigned slave addresses and are distinguished from each other. Therefore, it does not necessarily refer to all performance driving means within the gaming machine 1. "All of the plurality of effect driving means" refers to at least a plurality of the same configurations that receive the effect control signal of one channel from one effect control means (for example, the effect control board 30) and drive the effect. This means all of the production driving means.
The above meanings of "same configuration" and "all" also apply to (configuration B2-1) and (configuration B3-1) described later.

Examples of slave address settings include the LED drivers 1510, 1511, 1520, 1521, 1522 (FIGS. 52, 53, and 54) of the LED connection board 1500 and the LED driver 1601 (FIG. 58) of the LED board 1600.

The terminal arrangement of the LED drivers 1510, 1511, 1520, 1521, 1522, and 1601 is as shown in FIG. 80A.
The terminal arrangement in FIG. 80A is that terminals 1 (SVCC) to 12 (A1) are provided on side sd21, terminals 13 (A2) to 24 (LEDR3) are provided on side sd22, and terminals 13 (A2) to 24 (LEDR3) are provided on side sd23. The 25th terminal (LEDG3) to the 36th terminal (LEDG6) are provided, and the 37th terminal (LEDB6) to the 48th terminal (SCLK) are provided on the side sd24.

Terminal 1 (SVCC) is a power supply terminal.
The second terminal (VREF) is a 5V reference voltage output terminal.
The third terminal (CTLSCT) is a setting terminal for serial signal control.
The No. 4 terminal (CTLSCT) is a setting terminal for the LED output method.
Terminal 5 (RESET) is a reset signal input terminal.
The 6th terminal (Ilef_B), the 7th terminal (Ilef_G), and the 8th terminal (Ilef_R) are resistance connection terminals for setting B, G, and R LED currents.
Terminal 9 (SGND) is the ground terminal.
Terminal 10 is used as a test terminal and is connected to ground.

Terminals 11 to 16 (A0 to A5) are address terminals for setting slave addresses. In this case, the slave address can be set using 6 bits.

From the 17th terminal to the 44th terminal (excluding the 34th terminal), terminals for LED light emission drive current (LEDR1 to LEDB8) and ground terminals for LED output (PGND1 to PGND3) are formed.
Terminal 34 (LVCC) is the terminal for the protection circuit power supply for the LED output terminal.

Terminal 45 (SDO) is a dummy terminal.
Terminal 46 (SDEN) is an input terminal for an enable signal.
The 47th terminal (SDATA) is an input terminal for the data signal DATA.
The 48th terminal (SCLK) is an input terminal for the clock signal CLK.

Here, the slave addresses of the LED drivers 1510, 1511, 1520, 1521, 1522, and 1601 set from the 11th terminal to the 16th terminal (A0 to A5) can be seen from FIGS. 52, 53, 54, and 58. As follows:
Note that the 11th terminal (A0) is the LSB (least significant bit), and the 16th terminal (A5) is the MSB (most significant bit). The bit corresponding to the terminal connected to the ground is set to "0", and the bit corresponding to the terminal connected to the VREF terminal (terminal 2) of the 5V reference voltage is set to "1".

LED driver 1510:000111 (see Figure 52)
LED driver 1511:001000 (see Figure 52)
LED driver 1520:001001 (see Figure 53)
LED driver 1521:001010 (see Figure 53)
LED driver 1522:001011 (see Figure 54)
LED driver 1601:001100 (see Figure 58)

Although the above is an example, here, six of the LED drivers on the board arranged on the game board 3 side in FIG. 49 are shown. In addition to this, there are also LED drivers mounted on a board (not shown).
Further, a plurality of LED drivers are also mounted on a board placed on the door 6 side in FIG. 49.

The performance control board 30 in FIG. 49 transmits serial data to the game board 3 side and the door 6 side using two channels as serial data output channels.
A clock and serial data, that is, the above-mentioned clock CK and data DT, are transmitted from the production control board 30 to the plurality of LED drivers on the game board 3 side via a transmission line H50. This serial data output channel to the game board 3 side is referred to as a first channel.
A clock and serial data, that is, the above-mentioned clock CK and data DT, are transmitted to the plurality of LED drivers on the door 6 side from the production control board 30 via the transmission line H6. This serial data output channel to the door 6 side is defined as a second channel.

In the following description, it is assumed that each of the first channel and second channel LED drivers uses a driver IC (for example, the IC in FIG. 80A) in which the slave address is set with 6 bits.

In the gaming machine 1 of this embodiment, slave addresses are set for a plurality of LED drivers as shown in FIG. 93.
In FIG. 93, the slave address is shown in decimal notation, hexadecimal notation, and 6-bit notation from bit (A5) to bit (A0).

In this example, in decimal notation, "0" to "15" are slave addresses assigned to the first channel LED driver, and "16" to "31" are slave addresses assigned to the second channel LED driver. "32" to "63" are unused.
As a result, slave addresses can be assigned to each of the 16 LED drivers in the first channel and the second channel.

By doing this, all bits (A5) can be set to "0". In other words, the 16th terminal (A5) can be set to "0" for all LED drivers having the same configuration in the first channel and the second channel.

However, this does not mean that the slave address, which can be set with 6 bits, is simply used with 5 bits from bit (A4) to bit (A0).
If five bits are used, for example, all bits (A0) may be set to "0", or bits (A1) may be set to all "0". Similarly, bit (A2) or bit (A3) may be used. In other words, the slave address can be set in accordance with the number of LED drivers without using any one of bits (A5) to (A0).

Under these circumstances (configuration B1-1), when using an LED driver with the terminal arrangement shown in Figure 80A, all LED drivers use bits (A5) to () instead of bit (A0) or bit (A1). Adopt the design policy of setting one of A2) to "0". FIG. 93 shows an example in which bit (A5) is selected.

Hereinafter, the LED drivers 1510, 1511, 1520, 1521, 1522, 1601 and other LED drivers (not shown) will be referred to as "LED drivers 1510 and the like."
As shown in FIG. 80A, the LED driver 1510 and the like have six terminals (terminal 11 to terminal 16 (A0 terminal ~A5 pin)) is used as the address pin to set the slave address.

Since side sd1 has the A0 terminal and A1 terminal, and side sd2 has the A2 terminal to A5 terminal, X, x1, x2 in (configuration B1-1) are X=6, x1=2, x2=4. be.
Then, at least one address terminal (for example, A5 terminal) on side sd2 that is common to all of the LED drivers 1510 and the like is set to the L level.

FIG. 94 schematically shows the connection state of the address terminals of the LED drivers 1510, 1511, 1520, 1521, 1522, and 1601.
A reference voltage from the VREF terminal is applied to the terminal of the bit set to H level (“1”) in the slave address.
The terminal of the bit set to L level (“0”) in the slave address is connected to ground.
FIG. 94 shows the connection state for realizing the above-mentioned slave address value. For example, the solid line shows the pattern wiring on the mounting surface of the chip such as the LED driver 1510, and the broken line shows the connection state of the chip connected via the through hole. It shows the pattern wiring on the back side of the mounting surface.
For example, the ground is wired to a solid ground on the chip mounting surface of the LED driver 1510, etc. The wiring pattern varies depending on the shape of the solid ground, and each terminal is not necessarily connected with a common pattern. It is not necessary, and it is sufficient if the pattern is formed along a short path to the solid ground.

An example of wiring for a reference voltage for setting the H level (“1”) of the slave address as shown by the broken line in FIG. 94 will be shown.
This is an example of LED drivers 782, 791, and 631 having a different number of slave address terminals from the LED driver 1510, etc., but the reference voltage wiring shown by the broken line in FIG. 63 and the LED board 790 in FIG. 64, and the LED board 630 on the side unit in FIGS. 66 and 67.
Note that in these LED drivers 782, 791, and 631, as shown in FIG. 62, the 1st terminal is the VREF terminal, and the 11th to 15th terminals (A0 terminal to A4 terminal) are address terminals for setting the slave address.

In the case of the LED board 780, from the 1st terminal of the LED driver 782, there is a reference voltage wiring 789a (Fig. 60), a through hole TH50 (Fig. 60, 61), a reference voltage wiring 789b (Fig. 61), a through hole TH51 (Fig. 61, 60), the H level (“1”) of the slave address is set on the reference voltage wiring 789a (FIG. 60).

In the case of the LED board 790, from the 1st terminal of the LED driver 791, there is a reference voltage wiring 799a (Fig. 63), a through hole TH60 (Fig. 63, 64), a reference voltage wiring 799b (Fig. 64), a through hole TH61 (Fig. 64, 63), the H level (“1”) of the slave address is set on the reference voltage wiring 799c (FIG. 63).

In the case of the LED board 630 on the side unit, from the No. 1 terminal of the LED driver 631, there is a reference voltage wiring 639a (Fig. 67), a through hole TH70 (Fig. 67, Fig. 66), a reference voltage wiring 639b (Fig. 66), a through hole TH71 ( 66 and 67), the H level (“1”) of the slave address is set on the reference voltage wiring 639c (FIG. 67).

For each LED driver 1510 etc. in FIG. 94, a slave address is set by pattern wiring on the chip mounting surface and the surface on the back side thereof, as in the above examples of LED drivers 782, 791, and 631.

In the example of FIG. 94, the A5 terminal is connected to ground in both cases.
Such a configuration is realized as follows.
First, while it is possible to set an address of, for example, X bits (or X×Y bits if one terminal can set Y bits) using X terminals, a slave address is set using (X-1) terminals. For this purpose, it is desirable that the total number of LED drivers 1510, etc. for all channels be such that the slave address can be set using (X-1) terminals.

However, setting the total number of LED drivers 1510, etc. to be less than or equal to (X-1) may be considered to be the total number of at least one serial data output channel.
The example in FIG. 93 is an example in which the number of LED drivers 1510 and the like is 32 or less in total for the first channel and the second channel (that is, for all channels), but the number is not limited thereto.
Since the first channel and the second channel are independent serial data communication channels, there is no problem even if the same slave address exists between the first channel and the second channel. Therefore, in at least one channel, the number of LED drivers 1510, etc. may be as long as it is possible to set a slave address using (X-1) terminals.

When setting the slave address using (X-1) terminals, set a specific terminal (for example, A5 terminal) to L level on the second side (side sd2 in the above example), which has the largest number of address terminals. Set. This setting is common to all LED drivers that allocate slave addresses within at least one serial data output channel. The example in FIG. 93 is an example in which a common setting is applied to all the LED drivers 1510 and the like across the first channel and the second channel.

In this way, by setting the slave address so that one common terminal is at L level on the side sd2 with more terminals, it is possible to provide some margin for the wiring around the LED driver 1510, etc. It becomes easier. This makes it possible to improve wiring efficiency and facilitate wiring design.
The wiring around each LED driver differs depending on the slave address value and peripheral circuit, but by fixing at least one to the L level on the side sd2 where there are many address wirings, an LED driver with easy wiring is generated. You can increase the probability.

Note that the first side and the second side in (configuration B1-1) to (configuration B3-3) to be described later are not limited to the sides sd1 and sd2. There are cases where the sides are sd2 and sd3, there are cases where the sides are sd3 and sd4, and there are cases where the sides are sd4 and sd1.
Further, the first side and the second side are not arranged in the order of terminal numbers. The first side may correspond to the side sd2 and the second side may correspond to the side sd1.
In the case of (configuration B1-1), the first side and the second side are continuous sides, and the side with more address terminals becomes the second side.
Further, the present invention is not limited to IC chips having terminals on four sides.

For example, in the LED driver 742 of the decorative board 740 (FIG. 43), the LED driver 782 of the LED board 780 (FIG. 45), the LED driver 791 of the LED board 790 (FIG. 46), etc. in the configuration of FIG. 11, the slave address is set to 5. An example using a driver IC chip that is set using bits was given.
Even when using driver IC chips such as these, the idea of (configuration B1-1) can be realized by setting a terminal common to a plurality of LED drivers to the L level.

By the way, in the case of the LED driver 1510 etc. in the above example, it was stated that all LED drivers adopt a design policy in which any of bits (A5) to (A2) are set to "0", but in particular, as shown in FIG. It is most desirable to set bit (A5) to "0".
This is because the A5 terminal is the farthest corner from the A5 to A2 terminals and the farthest from the VREF terminal, so if this becomes H level, the reference voltage wiring length will be the longest. . In order to make the wiring length of the reference voltage as short as possible, it is desirable to set the bit (A5) to "0" so that the A5 terminal is connected to the ground of any LED driver.

Note that the plurality of effect driving means in the gaming machine 1 (configuration B1-1) include those using chip components mounted on the first board and those using chip parts mounted on the second board. .

Among the LED drivers 1510 and the like mentioned above, the LED drivers 1510, 1511, 1520, 1521, and 1522 are chip components mounted on the LED connection board 1500, and the LED driver 1601 is a chip component mounted on the LED board 1600. It is. Therefore, the first substrate and the second substrate include the LED connection substrate 1500 and the LED substrate 1600.

In this way, one terminal on the second side is commonly set to the L level for the effect driving means on a plurality of boards, thereby facilitating wiring efficiency and wiring design on a plurality of boards.

The gaming machine 1 of the embodiment has the following (configuration B2-1).
(Configuration B2-1)
The gaming machine 1 is
It has a plurality of effect driving means of the same configuration made of chip parts that are approximately rectangular and have terminals formed on two or more sides,
The effect driving means includes an address terminal which is a plurality of terminals with consecutive terminal numbers spanning two consecutive sides from a first side to a second side and which sets a slave address, and an address terminal formed on the first side. and a setting voltage terminal for setting the voltage to H level,
For all of the plurality of effect driving means, at least one of the address terminals on the second side and a specific address terminal common to the plurality of effect driving means is set to L level.

In addition, the meanings of "same configuration" and "all" in this case are as described above in the explanation of (configuration B1-1), and do not necessarily refer to all the effect driving means in the gaming machine 1. .

A specific example will be described using the LED driver 1510 and the like shown in FIG. 80A.
The set voltage terminal is a VREF terminal which is an output terminal of a 5V reference voltage.
Therefore, in this case, the first side is the side sd1 and the second side is the side sd2.
According to the example shown in FIG. 93, the A5 terminal on the side sd2 is set to the L level.

By doing so, wiring from the VREF terminal to the side sd2 side can be facilitated. This is because at least the wiring will not reach the A5 terminal. Therefore, it is possible to improve wiring efficiency and facilitate wiring design.
In particular, by setting it as a terminal (bit) on the side sd2 side, depending on the assigned slave address value, wiring of the VREF terminal on the side sd2 side may become unnecessary. Therefore, in the gaming machine 1 as a whole, the number of boards that can facilitate wiring for setting slave addresses can be increased.

Furthermore, the gaming machine 1 of the embodiment has the following (configuration B2-2) in addition to (configuration B2-1).
(Configuration B2-2)
The address terminal to be set to H level and the set voltage terminal are connected on the board via pattern wiring on a surface different from the mounting surface of the effect driving means,
The address terminal set to L level is connected to the ground of the mounting surface.

As described with reference to FIG. 94, the L level terminal is connected to the solid ground on the mounting surface of a chip such as the LED driver 1510, and the H level terminal is wired using the back side of the chip mounting surface. By doing so, it is possible to facilitate H level wiring on a surface other than the chip mounting surface. Furthermore, by providing a margin for the wiring on the chip mounting surface, it is possible to improve wiring efficiency and simplify design. This is particularly suitable for a configuration in which the length of the pattern wiring to the ground on the mounting surface is short.

In addition to (configuration B2-1), the gaming machine 1 of the embodiment can also have the following (configuration B2-3).
(Configuration B2-3)
The address terminal to be set to H level and the set voltage terminal are connected on the board by pattern wiring on the mounting surface of the effect driving means,
The address terminal set to L level is connected to the ground on a surface different from the mounting surface.

This is contrary to the above (configuration B2-2), the L level terminal is connected to the solid ground on the back side of the mounting surface of the chip such as the LED driver 1510, and the H level terminal is connected to the ground on the back side of the chip mounting surface. This is an example of wiring using . Contrary to the above description of FIG. 94, the broken lines may be considered as wiring on the chip mounting surface, and the solid lines may be considered as wiring on the back surface.

For example, if a solid ground is formed on a surface other than the chip mounting surface, adopt such a configuration and connect the address terminal set to L level to the solid ground on a surface other than the chip mounting surface. This allows for extra wiring on the mounting surface, resulting in more efficient wiring and easier design.

The gaming machine 1 of the embodiment has the following (configuration B3-1).
(Configuration B3-1)
The gaming machine 1 is
It has a plurality of effect driving means of the same configuration made of chip parts that are approximately rectangular and have terminals formed on two or more sides,
The performance driving means is
A plurality of terminals formed by consecutive terminal numbers from the first side to the second side, which are two consecutive sides, are considered as address terminals for setting the slave address,
From the first distance from the set voltage terminal for setting the address terminal to H level, which traces around the chip and reaches any address terminal on the first side at the shortest distance, the second The second distance that reaches any address terminal on the side at the shortest distance is longer,
All of the plurality of effect driving means have at least one of the address terminals on the second side, and a specific address terminal common to the plurality of effect driving means is set to L level. Ru.

In addition, the meanings of "same configuration" and "all" in this case are as described above in the explanation of (configuration B1-1), and do not necessarily refer to all the effect driving means in the gaming machine 1. .

A specific example will be described using the LED driver 1510 and the like shown in FIG. 80A.
The set voltage terminal is a VREF terminal which is an output terminal of a 5V reference voltage.
Also, depending on the distance from the VREF terminal, the first side is the side sd1, and the second side is the side sd2. The first distance to reach any address terminal on side sd1 by tracing around the chip from the VREF terminal is the distance dst1 from the VREF terminal to the A0 terminal shown in FIG. 80A. This is because the shortest second distance to reach any address terminal on side sd2 is the distance dst2 from the VREF terminal to the A2 terminal, and dst1<dst2.
Note that the distance dst1 and the distance dst2 are schematically shown in FIG. 80, but they are the shortest wiring length when a wiring pattern is formed between the VREF terminal and the A0 terminal, and the VREF terminal and the A2 terminal, respectively. It's something to think about.

As described above, in the LED driver 1510 and the like, the side sd2 is the second side in (configuration B3-1). According to the example shown in FIG. 93, the terminal A5 on the side sd2 is set to the L level.

In this way, one of the address terminals on side sd2, where the wiring is far from the terminal VREF, is set to the L level, making it easier to wire between the terminal VREF terminal and the address terminal, improving wiring efficiency and facilitating wiring design. can be realized.
In particular, by setting it as a terminal (bit) on the side sd2 side, depending on the assigned slave address value, wiring of the terminal VREF on the side sd2 side may become unnecessary. Therefore, in the gaming machine 1 as a whole, the number of boards that can facilitate wiring for setting slave addresses can be increased.

Furthermore, the gaming machine 1 of the embodiment may have the following (configuration B3-2) in addition to (configuration B3-1).
(Configuration B3-2)
The address terminal to be set to H level and the set voltage terminal are connected on the board via pattern wiring on a surface different from the mounting surface of the effect driving means,
The address terminal set to L level is connected to the ground of the mounting surface.

In addition to (configuration B3-1), the gaming machine 1 of the embodiment can also have the following (configuration B3-3).
(Configuration B3-3)
The address terminal to be set to H level and the set voltage terminal are connected on the board by pattern wiring on the mounting surface of the effect driving means,
The address terminal set to L level is connected to the ground on a surface different from the mounting surface.

These (configuration B3-2) (configuration B3-3) are similar to the above-mentioned (configuration B2-2) and (configuration B2-3), and the above-mentioned effects can be obtained.

The gaming machine 1 of the embodiment has the following (configuration B4-1).
(Configuration B4-1)
The gaming machine 1 is
Production control means having a first channel and a second channel as a serial data output channel for outputting serial data for production operation control;
a plurality of first effect driving means for driving the effect means based on the serial data of the first channel;
a plurality of second effect driving means for driving the effect means based on the serial data of the second channel;
Equipped with
Each of the first effect driving means and the second effect driving means is constituted by a chip component in which a slave address is set by X or more address terminals,
Each of the plurality of first effect driving means is set with a unique slave address with a value within a first numerical range among address value ranges that can be set by the X address terminals,
Each of the plurality of second effect driving means has a value within a second numerical range that does not overlap with the first numerical range among the address value ranges that can be set by the X address terminals. A unique slave address is set. However, X is a natural number.

The configuration (specific example 18) corresponding to this configuration B4-1 is as follows.

(Specific example 18)
・Production control means: Production control means 30 (see FIG. 49)
- Plurality of first performance driving means: each LED driver on the game board 3 side - Plurality of second performance driving means: each LED driver on the door 6 side - Chip parts: driver IC chip in Figure 80A - First numerical value Within range: "0" to "15" (decimal) in Figure 93
- Within the second numerical range: "16" to "31" (decimal) in Figure 93

That is, the effect control board 30 transmits and outputs the clock CK and data DT through a plurality of serial data output channels as described above. Parallel output from multiple channels, ie, the first channel and the second channel, enables high-speed control of a large number of LED drivers 1510 and the like.

Furthermore, since the LED driver corresponding to the first channel and the LED driver corresponding to the second channel are different serial data output channels, there is no problem even if the same slave address is used. It is also ensured that no overlap occurs between the first and second channels.
By doing this, even if the design is changed later to use a common channel for control, the same slave address settings can be used as is. This is suitable for ensuring versatility in consideration of future design changes. For example, in the game machine 1, when the board on the door 6 side is used to develop another model, the design becomes more efficient.

Furthermore, the gaming machine 1 of the embodiment has the following (configuration B4-2) in addition to (configuration B4-1).
(Configuration B4-2)
The gaming machine 1 is
a frame member;
a door member provided to be openable and closable with respect to the frame member;
a game board replaceably attached to the frame member;
has
The first channel is a channel for transmitting serial data to the first effect driving means arranged on a board attached to the game board,
The second channel is a channel for transmitting serial data to the second effect driving means arranged on a board attached to the door member or the frame member.

As explained so far, the first channel is a channel that transmits serial data to the LED driver placed on the board attached to the game board 3, and the second channel is a channel that sends serial data to the LED driver placed on the board attached to the door 6. This is a channel that transmits serial data to the arranged LED driver.

By distributing the first channel and the second channel to the game board 3 side and the door 6 side in this way, versatility can be increased. For example, even when using the inner frame 2 and door 6 and replacing the game board 3, the settings of the second channel can be used as is since the slave addresses do not overlap.

Note that the second channel is not limited to the LED driver of the door 6. For example, when the inner frame 2 is provided with an effect driving means such as an LED driver, the LED driver of the inner frame 2 may be supported by the second channel.

Furthermore, the gaming machine 1 of the embodiment has the following (configuration B4-3) in addition to (configuration B4-1) or (configuration B4-2).
(Configuration B4-3)
The gaming machine 1 is
Among the address value ranges that can be set using the X address terminals, address values greater than or equal to a predetermined value are neither included in the first numerical range nor in the second numerical range, and are not used as slave addresses. be done.

In the example of FIG. 93, "32" to "63" in decimal notation are unused.
For example, a value whose most significant bit is "1" is considered unused. If it is 6 bits, the address value range is "100000" or more.
By doing so, the terminal A5 corresponding to the highest among the six address terminals (A0) to (A5) of the LED driver 1510 etc. can be fixed at the L level. Therefore, as described above, the wiring around the chip can be made more efficient.

[7.3 Others]
Although the embodiments have been described above, each of the configuration examples from (Configuration A1-1) to (Configuration A103) and (Configuration B1-1) to (Configuration B4-3) can be combined in various ways. , by arbitrarily combining them, it is possible to create a gaming machine 1 that has the effects described in each configuration.
In addition, it is also possible to combine the configurations and operations described in the embodiments.
Moreover, the various illustrated specific examples are only one mode of realizing each configuration. There are various possible specific examples that are not specifically specified.

Although (Specific Example 1) to (Specific Example 17) are shown in the configurations (Configuration A1-1) to (Configuration A9-3) above, other specific examples are also envisioned for each configuration.
A board equipped with a chip that functions as a performance drive means, such as an LED driver, a motor driver, a driver control unit that controls these, an S/P conversion circuit for motor drive control, or a connector CN. The substrate can take the configurations from (configuration A1-1) to (configuration A9-3). For example, each of the substrates shown in FIGS. 11 and 49 may adopt a configuration corresponding to any one of the first substrate, second substrate, and third substrate in (configuration A1-1) to (configuration A9-3). can.

Further, in the above (configurations B1-1) to (configuration B4-3), the LED driver 1510 and the like are used as an example of the effect driving means, but these configurations can also be applied when a motor driver is targeted.

Further, although the embodiment has been described using a pachinko game machine, the present invention can also be applied to a reel type game machine such as a so-called slot game machine.
The drum type game machine also has a frame member, a door member provided to be openable and closable with respect to the frame member, and a replacement member attached to the frame member so as to be replaceable.
For example, a reel type gaming machine has a frame housing as a structure corresponding to a frame member, a door as a structure corresponding to a door member, and a reel unit as a structure corresponding to a replacement member. For example, the frame casing constitutes the main body of the reel-type gaming machine, and the reel unit is attached to the frame casing directly or via a sheet metal or the like by screwing, so that it can be replaced. The door is attached to the frame housing so that it can be opened and closed.
Even in such a reel type gaming machine, the board configuration, circuit configuration, connector configuration, power supply configuration, slave address setting, etc. described in each configuration example can be adopted.

1 Gaming machine 300 Power supply board 400 Inner frame LED relay board 500 Front frame LED connection board 550 Relay board 600 Side unit upper right LED board 620 Side unit lower right LED board 625 LED board 630 Side unit upper LED board 640 Button LED connection board 660 Button LED board 661, 663 700 LED connection board 720 Back left relay board 740 Decorative board 760 Relay board 790 LED board 800 Back bottom relay board 820 Decorative board 1500 LED connection board 1600 LED board

Claims (1)

A first performance driving means using chip components;
a second performance driving means using chip components;
a connector for inputting a first system clock and performance drive control data to the first performance drive means and inputting a second system clock and performance drive control data to the second performance drive means;
a first substrate provided with
In the first board, the first effect driving means, the second effect driving means, and the connector are arranged on the same surface,
the left-right relationship of each input terminal of the clock and the control data for effect driving in the first effect driving means, when looking from the pattern wiring side to the chip side;
a left-right relationship between each connector terminal of the first system clock and production drive control data in the connector, when looking from the connector terminal side to the direction in which pattern wiring connected to the connector terminal is led;
are the same,
A left-right relationship between the clock and the input terminals of the control data for driving the effect in the second effect driving means when looking from the pattern wiring side to the chip side;
a left-right relationship between each connector terminal of the second system clock and production drive control data in the connector, when looking from the connector terminal side to the direction in which pattern wiring connected to the connector terminal is led;
are the same,
In the connector,
a left-right relationship of each connector terminal of the first system clock and production drive control data when looking from the connector terminal side to the direction in which pattern wiring connected to each connector terminal is led;
a left-right relationship between the second system clock and each connector terminal of the production drive control data when looking from the connector terminal side to the direction in which the pattern wiring connected to the connector terminal is led;
is the opposite
Game machine.

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