JP2023034143A - game machine - Google Patents

Abstract

To enhance efficiency of a substrate configuration for driving various performances.SOLUTION: In a game machine, in a first substrate, first performance driving means and a first connector are arranged on the same surface of the substrate, and a right and left relationship of respective input terminals for a clock, performance driving control data, and power supply voltage in the first performance driving means when a chip side is viewed from a pattern wiring side and a right and left relationship of respective connector terminals for a clock, performance driving control data, and power supply voltage in the first connector when viewed from the respective connector terminal sides toward a lead-out direction of the pattern wiring connected to the respective connector terminals are the same. In a second substrate, a right and left relationship of respective connector terminals for a clock, performance driving control data, and power supply voltage in a second connector when viewed from the respective connector terminal sides toward the lead-out direction of the pattern wiring connected to the respective connector terminals are the same as that of the first connector.SELECTED DRAWING: Figure 85

Description

TECHNICAL FIELD The present invention relates to a game machine, and more particularly to a technique for improving the performance of a game machine.

In pinball game machines and rotating game machines, liquid crystal display screens, speakers, LEDs, accessories, vibrating bodies, blowers, etc. are used to perform various effects to make the game lively.
The following patent documents disclose techniques for controlling various performance operations.

JP 2014-64693 A

In such a game machine, it is desirable to realize a more interesting presentation without increasing the number of boards and complicating or making wiring difficult as much as possible.
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to propose a configuration capable of obtaining an effective presentation effect without complicating the configuration.

The gaming machine of the present invention is provided with a first performance driving means by a chip component, and a first connector for inputting a clock for the first performance driving means, control data for driving performance, and a power supply voltage. a substrate; and a second substrate provided with a second connector for inputting a clock for a second effect driving means, control data for driving effect, and a power supply voltage; The effect drive means and the first connector are arranged on the same surface of the substrate, and the input terminals of the clock, effect drive control data, and power supply voltage in the first effect drive means are connected from the pattern wiring side to the chip side. and the lead-out direction of the pattern wiring connected to each connector terminal from each connector terminal side of each connector terminal of the clock, effect drive control data, and power supply voltage in the first connector. The second board has the same left-right relationship when viewed facing the same direction, and the clock, effect drive control data, and power supply voltage connector terminals of the second connector are connected from the respective connector terminal sides to the respective connector terminals. The left-right relationship is the same as that of the first connector when viewed in the lead-out direction of the pattern wiring connected to the connector terminals.
In addition, the second board has a second effect driving means by a chip component for inputting a clock and effect driving control data via pattern wiring from the second connector, wherein the second board includes: The second effect drive means and the second connector are arranged on the same surface of the substrate, and the pattern wiring of the input terminals of the clock, effect drive control data, and power supply voltage in the second effect drive means. The left-right relationship when the chip side is viewed from the side may be the same as that of the first effect driving means.
A third board provided with a third connector for inputting a clock for the third performance driving means, control data for driving performance, and power supply voltage is provided, and the clock and the control data for driving performance at the third connector are provided. The left-right relationship of each connector terminal for the power supply voltage may be the same as that of the first connector when viewed from the connector terminal side toward the lead-out direction of the pattern wiring connected to each connector terminal.
Further, the chip component may be a substantially rectangular chip having terminals formed on four sides.
Also, the first substrate may be a two-layer wiring substrate with a front surface and a rear surface of the substrate.

According to the gaming machine of the present invention, highly interesting effects are realized with an efficient configuration.

1 is a front perspective view showing the appearance of a gaming machine according to an embodiment of the present invention; FIG. It is a figure which shows the structure of the game board of the gaming machine of embodiment. It is a block diagram showing the control configuration of the gaming machine of the embodiment. FIG. 11 is an explanatory diagram of an example of a pre-reading advance notice effect according to the embodiment; 1 is a perspective view of a state in which a door of a game machine of an embodiment is opened; FIG. It is a perspective view of a state in which the inner frame of the gaming machine of the embodiment is opened. It is an explanatory view of the substrate arrangement on the back side of the game board of the embodiment. It is explanatory drawing of board|substrate arrangement|positioning of the door of the gaming machine of embodiment, and an inner frame. It is explanatory drawing of the board|substrate arrangement|positioning of the inner frame of the gaming machine of embodiment. FIG. 4 is an explanatory diagram of the arrangement of various devices; FIG. 3 is a block diagram of a connection configuration of substrates; 3 is an explanatory diagram of power system inputs and outputs of the power board 300. FIG. 4 is a circuit diagram of an inner frame LED relay board 400. FIG. 4 is a circuit diagram of an inner frame LED relay board 400. FIG. 5 is a circuit diagram of a front frame LED connection board 500. FIG. 5 is a circuit diagram of a front frame LED connection board 500. FIG. 5 is a circuit diagram of a front frame LED connection board 500. FIG. 5 is a circuit diagram of a front frame LED connection board 500. FIG. 5 is a circuit diagram of a front frame LED connection board 500. FIG. 5 is a circuit diagram of a front frame LED connection board 500. FIG. 4 is a block diagram showing the flow of signals in the front frame LED connection board 500. FIG. 4 is a block diagram showing the flow of signals in the front frame LED connection board 500. FIG. 5 is a circuit diagram of a relay board 550; FIG. 6 is a circuit diagram of the upper right LED board 600 of the side unit. FIG. 6 is a circuit diagram of the upper right LED board 600 of the side unit. FIG. 6 is a circuit diagram of the upper right LED board 600 of the side unit. FIG. 6 is a circuit diagram of the upper right LED board 600 of the side unit. FIG. 6 is a circuit diagram of the upper right LED board 600 of the side unit. FIG. 6 is a circuit diagram of the upper right LED board 600 of the side unit. FIG. It is a circuit diagram of the lower right LED board 620 of the side unit. It is a circuit diagram of the lower right LED board 620 of the side unit. 6 is a circuit diagram of a side unit upper LED board 630. FIG. 6 is a circuit diagram of a button LED connection board 640. FIG. 6 is a circuit diagram of button LED board 660. FIG. 6 is a circuit diagram of button LED board 660. FIG. 7 is a circuit diagram of an LED connection board 700. FIG. 7 is a circuit diagram of an LED connection board 700. FIG. 7 is a circuit diagram of an LED connection board 700. FIG. 7 is a circuit diagram of an LED connection board 700. FIG. 7 is a circuit diagram of an LED connection board 700. FIG. 7 is a circuit diagram of an LED connection board 700. FIG. is a circuit diagram of the backside left relay board 720 of FIG. 7 is a circuit diagram of a decoration substrate 740; FIG. 7 is a circuit diagram of a relay board 760; FIG. 7 is a circuit diagram of an LED board 780. FIG. 7 is a circuit diagram of an LED board 790. FIG. FIG. 11 is a circuit diagram of a backside lower relay board 800; 8 is a circuit diagram of a decorative substrate 820; FIG. FIG. 4 is a block diagram of another connection configuration of the substrate; 15 is a circuit diagram of an LED connection board 1500; FIG. 15 is a circuit diagram of an LED connection board 1500; FIG. 15 is a circuit diagram of an LED connection board 1500; FIG. 15 is a circuit diagram of an LED connection board 1500; FIG. 15 is a circuit diagram of an LED connection board 1500; FIG. 15 is a circuit diagram of an LED connection board 1500; FIG. 15 is a circuit diagram of an LED connection board 1500; FIG. 15 is a circuit diagram of an LED connection board 1500; FIG. 16 is a circuit diagram of an LED board 1600; FIG. FIG. 10 is an explanatory diagram of the configuration A1-1; FIG. 7 is an explanatory diagram of a pattern of a surface layer of an LED substrate 780; FIG. 7 is an explanatory diagram of a pattern of a back layer of an LED substrate 780; FIG. 4 is an explanatory diagram of terminals of an LED driver; FIG. 7 is an explanatory diagram of a pattern of a surface layer of an LED substrate 790; FIG. 7 is an explanatory diagram of a pattern of a back surface layer of an LED substrate 790; FIG. 10 is an explanatory diagram of configuration A1-2; FIG. 6 is an explanatory diagram of a pattern of a surface layer of a side unit LED substrate 630. FIG. FIG. 6 is an explanatory diagram of a pattern of a back surface layer of a side unit LED substrate 630. FIG. FIG. 11 is an explanatory diagram of configuration A2-1; FIG. 11 is an explanatory diagram of configuration A2-2; FIG. 13 is an explanatory diagram of the configuration A3-1; FIG. 4 is an explanatory diagram of an example of arrangement of surface layers of an LED connection substrate 1500; FIG. 15 is an explanatory diagram of an example of arrangement of the back layer of the LED connection substrate 1500; FIG. 6 is an explanatory diagram of an example of arrangement of the surface layer of the upper right LED board 600 of the side unit; FIG. 10 is an explanatory diagram of an example arrangement of the back layer of the upper right LED board 600 of the side unit; FIG. 15 is an explanatory diagram of another arrangement example of the surface layer of the LED connection substrate 1500; FIG. 11 is an explanatory diagram of a configuration A3-2; FIG. 13 is an explanatory diagram of the configuration A4-1; FIG. 4 is an explanatory diagram of a pattern of a surface layer of an LED substrate 1600; FIG. 4 is an explanatory diagram of the pattern of the back layer of the LED substrate 1600; FIG. 4 is an explanatory diagram of terminals of an LED driver 1601; FIG. 11 is an explanatory diagram of configuration A5; It is a circuit diagram of LED connection board 1500A. FIG. 11 is an explanatory diagram of configuration A6; It is a circuit diagram of LED board 790A. FIG. 11 is an explanatory diagram of configuration A7-1; FIG. 11 is an explanatory diagram of configuration A7-2; FIG. 11 is an explanatory diagram of a configuration A7-3; FIG. 11 is an explanatory diagram of configurations A8-1 and A8-2; FIG. 11 is an explanatory diagram of configurations A8-1 and A8-2; FIG. 11 is an explanatory diagram of configuration A9-1; FIG. 11 is an explanatory diagram of configuration A9-2; FIG. 11 is an explanatory diagram of a configuration A9-3; FIG. 4 is an explanatory diagram of slave address setting; FIG. 4 is an explanatory diagram of wiring for setting a slave address;

Embodiments according to the present invention will be described below in the following order with reference to the accompanying drawings.
<1. Game Machine Structure>
<2. Game Machine Control Configuration>
[2.1 Main control board]
[2.2 Production control board]
<3. Overview of operation>
[3.1 Game state]
[3.2 Symbol variation display game]
[3.3 Per hit]
[3.4 About production]
<4. Opening/Closing Structure and Substrate Arrangement>
<5. Board Connection Configuration>
[5.1 Connection state of each board]
[5.2 Inner frame LED relay board 400]
[5.3 Front frame LED connection board 500]
[5.4 Relay board 550]
[5.5 Side Unit Upper Right LED Board 600]
[5.6 Side unit lower right LED board 620]
[5.7 LED board 630 on the side unit]
[5.8 Button LED connection board 640]
[5.9 Button LED board 660]
[5.10 LED connection board 700]
[5.11 Board Back Left Relay Board 720]
[5.12 Decorative substrate 740]
[5.13 Relay board 760]
[5.14 LED board 780]
[5.15 LED board 790]
[5.16 Board Back Bottom Relay Board 800]
[5.17 Decorative substrate 820]
<6. Other Examples of Board Connection Configuration>
[6.1 Connection state of each board]
[6.2 LED connection board 1500]
[6.3 LED board 1600]
<7. Description of Noteworthy Configuration>
[7.1 Relationship between connector terminals and terminals of effect driving means]
[7.2 Slave address]
[7.3 Others]

<1. Game Machine Structure>

The structure of a pachinko game machine 1 as an embodiment according to the present invention will be described with reference to FIGS. 1 and 2. FIG. FIG. 1 is a front perspective view showing the appearance of the pachinko game machine 1, and FIG. 2 is a front view of the game board 3 of the pachinko game machine 1.
The pachinko game machine 1 has a frame member, a door member provided to be openable and closable with respect to the frame member, and a replacement member attached to the frame member so as to be replaceable.
The pachinko game machine 1 described below has an inner frame 2 as a structure corresponding to a frame member, a door 6 as a structure corresponding to a door member, and a game board 3 as a structure corresponding to a replacement member.

The pachinko game machine 1 shown in FIG. A game board 3 (see FIG. 2) is mounted in an attached game board storage frame (not shown), and a game area 3a formed on the surface of the game board 3 faces the opening of the inner frame 2. have. Since the game board 3 can be exchangeably attached to and detached from the inner frame 2, it can be called a replacement member.
A door 6 supporting transparent glass is provided on the front side of the game area 3a. Also, on the back side of the game board 3, various control boards (see FIG. 3) for controlling game operations are arranged.

On the front side of the door 6 (on the player's side), a side unit 10 is formed as a decoration unit surrounding all or part of the game board 3, for example.
The side unit 10 itself has a decorative shape that matches the theme of the game machine 1, and may also be provided with performance members such as LEDs and accessories inside, and has a performance effect that conveys the atmosphere of the game to the player. demonstrate. The side unit 10 is a unit attached to the door 6 so as to be replaceable.

A key cylinder (not shown) for unlocking the door is provided on the front side of the door 6. When a key is inserted into this key cylinder and operated to one side, the locked state of the door 6 with respect to the inner frame 2 is released. The door 6 can be opened forward by pressing it, and by operating it to the other side, the locked state of the inner frame 2 with respect to the outer frame 4 is released and the inner frame 2 can be opened forward.

Under the door 6, a front operation panel 7 is pivotally supported on the inner frame 2 by a hinge (not shown) so that it can be opened and closed.
An upper tray unit 8 is provided on the front operation panel 7, and the upper tray unit 8 is formed with an upper tray 9 for storing discharged game balls.

The upper receiving tray unit 8 also has a ball ejection button 14 for ejecting the game balls stored in the upper receiving tray 9 to the lower side of the gaming machine 1, and a game ball dispensing device (not shown) for dispensing game balls. A ball lending button 11 for making a request and a card return button 12 for requesting the return of the valuable value medium inserted in the game ball lending device are provided.
Also, the upper tray unit 8 is provided with a performance button 13 (operating means) configured to be operable by the player. The effect button 13 can be operated (input can be accepted) when the built-in lamp (button LED 75) is lit during a predetermined input reception period, and a predetermined operation (pressing, repeated hitting, long pressing, etc.) is performed during the lighting of the built-in lamp. By doing so, it is possible to bring about changes in the production.
The upper tray unit 8 also has a cross key 15a for users such as players and hall staff to select various items and give directions, and a determination button 15b for instructing determination of selection items. An operator is provided.

A firing operation handle 15 for operating a firing device 32 (see FIG. 3) is provided on the right end side of the front operation panel 7 .

Speakers 46 are provided on both sides of the upper part of the inner frame 2 and on the upper side of the shooting operation handle 15 to produce a sound effect (sound effect). Only the two speakers 46 on the top of the inner frame 2 are shown in FIG.
With a plurality of speakers 46, it is possible to perform so-called stereo sound reproduction and sound reproduction of a larger number of channels for sounds related to performance.

In addition, a plurality of decorative lamps 45 (for example, full-color LEDs for light production: see FIG. 3) are provided at appropriate locations on the door 6 to produce a light production effect. A plurality of full-color LEDs (light effect LEDs) and the like as the decorative lamps 45 are provided around the pachinko game machine 1, for example, around the door 6 and inside the side unit 10. FIG.

The configuration of the game board 3 will be described with reference to FIG.
The game board 3 shown in the figure is provided with a ball guiding rail 5 that guides the shot game balls in an annular shape as a board surface partitioning member. The four corners are non-game areas.

Approximately in the center of the game area 3a, for example, in three (left, middle, right) display areas (symbol variation display areas), a plurality of types of decorative patterns (for example, numbers, characters, symbols, etc.) are independently displayed. A liquid crystal display (LCD) 36 capable of variable display operation (variable display and stop display) of a left pattern (corresponding to the left display area), a middle pattern (corresponding to the middle display area), and a right pattern (corresponding to the right display area) is provided. is provided.
Under the control of the effect control board 30, which will be described later, the liquid crystal display device 36 displays various effects in the form of images in addition to the variable display operation of decorative symbols.

In the game area 3a, a center decoration 48 is provided so as to surround the display surface of the liquid crystal display device 36 in a long way. The center decoration 48 is provided along the front side of the game board 3 to protect the display surface of the liquid crystal display device 36 from surrounding game balls, and to control the flow of the game ball depending on the strength or stroke length of the game ball's launch. It works as flow path distribution means that enables distribution of the path to the left and right.
In this embodiment, the center decoration 48 is arranged substantially in the center of the game area 3a so that the flow paths for game balls are formed on both upper sides (left and right sides) of the game area 3a due to the presence of the center decoration 48. ing. The game balls hit by the shooting device 32 on the upper side of the game area 3a are distributed to the left and right on the upper side of the armor frame portion 48b, and are divided into the left flowing path 3b on the left side of the center decoration 48 and the right flowing path 3c on the right side. flow something.

In addition, the non-game area at the bottom of the game board 3 serves as various function display units, and includes a special symbol display device 38a (first special symbol display means) and a special symbol display device 38b (second special symbol display means) by a dot indicator. display means) are provided.
Various function display units including the special symbol display devices 38a and 38b are shown enlarged in FIG.

In the special symbol display devices 38a and 38b, a special symbol variable display game is executed by a variable display operation of the "special symbol" represented by the dot indicator. In the liquid crystal display device 36, in time synchronization with the variable display of the special patterns by the special pattern display devices 38a and 38b, the decorative patterns by images are variably displayed, and decorated with various advance notice effects (effect images). A symbol variation display game is executed (details of these symbol variation display games will be described later).

Also, in the various function display units, a composite display device (holding composite display LED display device) 38c composed of dot displays like the special symbol display devices 38a and 38b is arranged. Composite is called 5 special patterns 1, 2, display of the number of operation pending balls of normal patterns, state notification during variable time reduction function (during time saving) and during high probability state (during high probability). This is because it is a holding/time-saving/high-precision composite display device (hereinafter simply referred to as "composite display device") having a display function.

In addition, the various function display units are provided with a compound display device 38d, which is also made up of a dot display.
In this composite display device 38d, the number of rounds indicating the specified number of rounds (maximum number of rounds) related to the big hit is displayed by combining the ON/OFF states of the four LEDs. For example, a specified number of rounds (maximum number of rounds) relating to a big hit is notified by a combination of lighting/lighting-out states of four LEDs.
Further, in the combined display device 38d, a normal symbol variation display game is executed by a normal symbol variation display operation represented by one LED as the normal symbol display.
Further, in the composite display device 38d, right-handed display is performed by three LEDs.

Under the center decoration 48 in FIG. 2, a starting port 34 (first special symbol starting port: first starting means) is provided inside. Inside the starting hole 34, a detection sensor 34a (starting hole sensor 34a, see FIG. 3) for detecting passage of a game ball is formed.
In addition, the right flow path 3c is provided with a starting port 35 (second special symbol starting port: second starting means) that performs opening and closing operation, and a detection sensor 35a (starting A mouth sensor 35a: see FIG. 3) is formed.

The starting port 34, which is the first special symbol starting port, is the first special symbol in the special symbol display device 38a (hereinafter, the first special symbol is referred to as "special symbol 1", and in some cases "special symbol 1"). (abbreviated for short)), and is configured as a fixed winning rate type winning device that does not have starting opening/closing means (means for opening or enlarging the starting opening). In this embodiment, due to the action of the game ball fall direction changing member (for example, game nail, windmill 44, center decoration 48, etc.) in the game area 3a, the game ball that has flowed down the left flow path 3b to the starting port 34 is a configuration in which it is easy to enter (win a prize), whereas it is difficult or impossible to enter a game ball that has flowed down the right flow path 3c.

The starting port 35 starts the variable display operation of the second special symbol (hereinafter, the second special symbol is referred to as "special symbol 2", and in some cases is abbreviated as "special symbol 2") in the special symbol display device 38b. It is a winning opening according to conditions, and the winning area of the starting opening 35 is configured to be openable and closable between an open state in which winning is possible and a closed state in which winning is impossible.

The starting port 35 is a prize winning port related to the starting condition of the variable display operation of the special symbol 2 in the special symbol display device 38b, and is configured as a variable starting port whose opening and closing is controlled by the normal electric accessory 41.
The ordinary electric accessary 41 is controlled to an open state in which entry of a game ball into the starting port 35 is possible and a closed state in which entry of a game ball into the starting port 35 is difficult or impossible.

Two general winning holes 43 are provided in the left and right lower portions of the game area 3a, and a general winning hole sensor 43a for detecting passage of a game ball is formed inside each of them.
In addition, a movable accessory (not shown) that exerts a visual performance effect is arranged in the area of the game board at a position that does not interfere with the flow of the game ball.

In addition, diagonally above the normal electric accessory 41, that is, above the middle part of the right flow path 3c, there is a normal symbol start port 37 (third start means) consisting of a passage gate (specific passage area) through which game balls can pass. ) is provided. The normal symbol starting port 37 is a prize winning port related to the variable display operation of the normal symbols of the composite display device 38d, and the normal symbol starting port sensor 37a (see FIG. 3) for detecting the passing game ball is installed therein. formed. In addition, in this embodiment, the normal symbol starting port 37 is formed only on the right flow path 3c side, and is not formed on the left flow path 3b side. However, the present invention is not limited to this, and may be formed only in the left flow path 3b or may be formed in both flow paths.

A special variable winning device 52 (special electric accessory) configured to be able to open or expand the big winning opening 50 by an open door 52b is provided in the middle of the path from the normal symbol start opening 37 in the right flow path 3c. A big winning hole sensor 52a (see FIG. 3) for detecting a game ball entering the big winning hole 50 is formed inside.
A guide part 55 and a windmill 53 are provided around the big winning hole 50 to bring the falling game balls toward the big winning hole 50 .

The process of entering the game ball into the big winning hole 50 is as follows.
A game ball that has passed through the floating area between the upper surface of the center decoration 48 and the ball guide rail 5 and has passed through the right flow path 3c is guided toward the big winning opening 50 by the guide part 55. - 特許庁If the large winning opening 50 is open (large winning opening open state), the game ball is led into the large winning opening 50.例文帳に追加

In addition, in the gaming machine 1 of the present embodiment, when the player aims at the launch position on the side of the special variable winning device 52 (when aiming so that the game ball passes through the right flow path 3c), the starting port 34 A game ball is difficult or not guided to the side. Therefore, if the "large winning opening closed state", it is difficult or impossible to win a prize to the starting opening 34.
In addition, the starting port 35 operates in a more advantageous opening/closing pattern than in the normal state when it enters a game state accompanied by a state with an electric sapo, which will be described later.

In the case of the present embodiment, the manner in which the player should hit to obtain an advantageous situation changes according to the game state. Specifically, if the game state is accompanied by the "state without electric sapo", which will be described later, it is advantageous to hit "left", aiming for the game ball to pass through the left flow path 3b. If it is a game state accompanied by "with state", "right hitting" aiming to make the game ball pass through the right flow path 3c is advantageous.

In the gaming machine 1 of the present embodiment, when there is a winning in a winning opening other than the normal symbol start opening 37 among various winning openings provided in the game area 3a, a promise is made for each winning opening. The number of prize balls per winning ball (for example, 3 starting holes 34 or 35, 13 large winning holes 50, and 10 general winning holes 43) is determined by the game ball payout device 19 (see FIG. 3). It is designed to be disbursed from The game balls that have not won the winning openings are ejected from the game area 3a through the out opening 49. FIG.

Here, "winning" means that the winning opening does not have a structure in which the game ball is taken in, or the winning opening is not a structure in which the game ball is taken in, but is a winning opening made up of a pass-through gate (for example, the normal symbol start opening 37). If it is, it means that the game ball passes through the gate, and in fact, when the game ball is detected by each winning detection switch formed for each winning hole, "winning" occurs in that winning hole treated as if A game ball related to this winning is also called a "winning ball". If a game ball enters the winning hole, it will be detected by the winning detection switch. Irrespective of this, there are cases where the term "winning" includes the case where a game ball enters the winning opening.

<2. Game Machine Control Configuration>

A configuration (control configuration) for realizing game operation control of the gaming machine 1 will be described with reference to the block diagram of FIG.
The gaming machine 1 of the present embodiment includes a main control board (main control means) 20 that controls overall game operations (game operation control), and a production control command received from the main control board 20 to produce production means. A production control board 30 (production control means) that controls the execution control (appearance control) of the production by, a payout control board (payout control means) 29 that controls the payout of prize balls, and an external power supply (not shown) ) to generate and supply necessary power to the gaming machine 1 (power supply control means (not shown)).
Note that the power supply route to each part is omitted in FIG.

[2.1 Main control board]
The main control board 20 is equipped with a microprocessor with a built-in CPU (Central Processing Unit) 20a (main control CPU), and in addition to a control program describing game operation control procedures, various data necessary for game operation control are stored. A ROM (Read Only Memory) 20b (main control ROM) for storing data and a RAM (Random Access Memory) 20c (main control RAM) functioning as a work area and buffer memory are installed, and the microcomputer is configured as a whole. .

Although not shown, the main control board 20 includes a CTC (Counter Timer Circuit) for realizing periodic interrupts, a constant cycle pulse output generation function (bit rate generator), a time measurement function, and a main control circuit. An interrupt controller circuit that performs an interrupt permission/interrupt prohibition function such as a timer interrupt that gives an interrupt signal to the CPU 20a, and an interrupt controller circuit that detects when the power is turned on or off, when the power is turned off, or when the power is abnormal, and outputs a system reset signal for main control. A reset circuit that can reset the CPU 20a, a watchdog timer (WDT) circuit that monitors abnormal operation of the control program, and a prohibition of traveling outside the designated area that monitors whether the program is being executed correctly within a preset address range. (IAT) circuit, and a counter circuit for generating random numbers within a certain range in terms of hardware.

The counter circuit includes a random number generating circuit for generating random numbers and a sampling circuit for sampling random numbers from the random number generating circuit at predetermined timings, and functions as a 16-bit counter as a whole. By sending instructions to the sampling circuit according to the processing state, the main control CPU 20a uses the numerical value indicated by the random number generation circuit as the internal lottery random number (random number for judging a big hit (random number size: 65536)). The random number is obtained and used for the jackpot lottery. The internal lottery random number is obtained by adding a soft random number generated by appropriate software processing and a hard random number, in order to prevent cheating such as hitting a winning game.

The main control board 20 includes a starting hole sensor 34a for detecting winning (entering a ball) to the starting hole 34, a starting hole sensor 35a for detecting winning to the starting hole 35, and a normal symbol starting hole 37 for detecting passage. A normal symbol starting opening sensor 37a, a large winning opening sensor 52a for detecting winning to the big winning opening 50, a general winning opening sensor 43a for detecting winning to the general winning opening 43, and an out opening 49 are discharged. An OUT monitoring switch 49a for detecting a game ball (out ball) is connected, and the main control board 20 can receive detection signals output from these. The main control board 20 can grasp which winning opening the game ball has entered based on the detection signal from each sensor.

The main control board 20 also has a normal electric accessory solenoid 41c for controlling the opening and closing of the movable wing pieces of the starter opening 35, and a large winning opening solenoid 52c for controlling the opening and closing of the opening door 52b of the large winning opening 50. are connected, and the main control board 20 can transmit control signals for controlling them.

Further, a special symbol display device 38a and a special symbol display device 38b are connected to the main control board 20, and the main control board 20 can transmit a control signal for controlling the display of the special symbols 1 and 2. . Furthermore, the main control board 20 is connected to a composite display device 38c, and is capable of transmitting control signals for controlling the display of the pending number and the status display.

A composite display device 38d is connected to the main control board 20, and the main control board 20 outputs a control signal for controlling the normal symbol display, right-handed display, and round display displayed on the composite display device 38d. can be sent.

Further, the main control board 20 is connected to an external common terminal board 21 for frame, and the main control board 20 is connected to the hall computer HC provided outside the game machine via the external common terminal board 21 for frame. It is possible to transmit game information (for example, big hit information, prize ball information, symbol variation execution information, etc.).
The hall computer HC is an information processing device (computer device) for monitoring game information from the main control board 20 and managing the operational status of the pachinko hall gaming machines in a comprehensive manner.

Furthermore, a payout control board (payout control unit) 29 is connected to the main control board 20, and when it is necessary to pay out prize balls, a control command related to payout (number of prize balls A payout control command that specifies ) can be transmitted.

The payout control board 29 is connected with a launch control board (launch control section) 28 that controls the launcher 32 and a game ball payout device (game ball payout means) 19 that pays out game balls. The main roles of this payout control board 29 are reception of payout control commands from the main control board 20, control of prize ball payout of the game ball payout device 19 based on the payout control commands, transmission of status signals to the main control board 20, and the like. is.

The game ball payout device 19 is provided with a supply shortage detection sensor 19a for detecting a shortage of supply of game balls and a ball counting sensor 19b for detecting game balls (prize balls) to be paid out. can receive each detection signal. The game ball payout device 19 is provided with a payout motor 19c for driving a ball payout mechanism (not shown) for putting out game balls. of control signals can be transmitted.

Further, the payout control board 29 is provided with a full detection sensor 60 (in this embodiment, a detection sensor for detecting the state of game balls stored in the upper tray 9) that detects when the upper tray 9 is full of game balls. , a front door open sensor 61 (for example, a detection sensor for detecting the open state of the door 6 or the inner frame 2) is connected.

The payout control board 29 can transmit various status signals to the main control board 20 based on detection signals from the full detection sensor 60, the front door open sensor 61, the supply shortage detection sensor 19a, and the ball counting sensor 19b. It has become. This state signal includes a ball clogged signal indicating a full state, a door open signal indicating that at least the inner frame 2 is open, a resupply out signal indicating insufficient supply of game balls from the game ball payout device 19, and prize balls. A count error signal indicating an insufficient payout of balls or an abnormality in the ball counting sensor 19b, and a payout completion signal indicating completion of the payout operation are included, and various status signals can be transmitted. Based on these status signals, the main control board 20 determines whether the inner frame 2 is open (door open error), whether the dispensing operation of the game ball dispensing device 19 is normal (replenishment shortage error), and whether the upper tray 9 is open. Monitor the full state (ball clogging error), etc.

Furthermore, a firing control board 28 is connected to the payout control board 29, and a permission signal for permitting firing can be transmitted to the firing control board 28. FIG. The firing control board 28 controls energization of a firing solenoid (not shown) provided in the firing device 32 based on the output of the permission signal from the dispensing control board 29, and operates the firing operation handle 15. It realizes the shooting operation of the game ball by. Specifically, it is detected that a firing permission signal is output from the payout control board 29 (firing permission signal ON state) and that the player is touching the handle by a touch sensor provided on the firing operation handle 15. On the condition that the shooting stop switch (not shown) provided on the shooting operation handle 15 is not operated, the game ball shooting operation is permitted. Therefore, when the shooting permission signal is not output (shooting permission signal OFF state), even if the shooting operation handle 15 is operated, the shooting operation is not executed and the game ball is not shot. In addition, the strength of launching the game ball can be changed according to the operation amount of the shooting operation handle 15. - 特許庁
In addition, when the payout control board 29 detects the ball jam error, it transmits a ball jam signal to the main control board 20 and stops outputting the firing permission signal to the firing control board 28 (fire permission signal OFF). Until the full state of is eliminated, the control is performed to stop the launching operation.
Also, the payout control board 29 outputs a launch permission signal to the launch control board 28 on condition that the main control board 20 instructs launch permission.

A RAM clear switch 98 is connected to the main control board 20 so that detection signals from these switches can be received.

The RAM clear switch 98 is, for example, a push button type switch for inputting an instruction to initialize a predetermined area of the main control RAM 20c.

The RAM clear switch 98 is turned ON/OFF according to the operation of a RAM clear button which is operable when the inner frame 2 is open.
The RAM clear switch 98 is provided at an appropriate location inside the gaming machine 1 . For example, it is arranged on the main control board 20 .

A performance indicator 97 is also connected to the main control board 20 .
The performance indicator 97 is configured with, for example, a 7-segment indicator and functions as display means capable of displaying performance information (described later). The performance indicator 97 is mounted, for example, on the main control board 20 at an easily visible position.

(About performance display)
The main control board 20 can transmit a control signal for displaying predetermined performance information on the performance indicator 97 .
The performance information is information that pachinko halls and related government agencies want to confirm, and typical examples thereof include information on the presence or absence of fraudulent prize balls such as excess prize balls for the gaming machine 1 and information on the original performance of the gaming machine 1. is. Therefore, the performance information itself is information that is not directly related to the progress of the game itself when the player is enjoying the game, unlike the advance notice effect or the like.

For this reason, the performance indicator 97 is inside the game machine 1, for example, on the main control board 20, the payout control board 29, the launch control board 28, the relay board, the effect control board 30, and the board case (a protective cover that protects the board). ), etc., are provided at positions where display information can be visually recognized when the inner frame 2 is in an open state.

Here, the following information can be specifically adopted as the performance information.

(1) The total number of payout balls paid out due to winning during a specific state (total number of prize balls during a specific state: α) is The information (specific ratio information) based on the value (α/β) divided by the number of pieces: β can be adopted as the performance information.
The above-mentioned "total number of payouts" is the total value of the game balls (prize balls) paid out when entering the winning opening (starting opening 34, starting opening 35, general winning opening 43, big winning opening 50). . In the case of the present embodiment, there are three starting holes 34 or starting holes 35, thirteen big winning holes 50, and ten general winning holes 43. FIG.
Further, which state to adopt as the specific state can be appropriately determined according to the state under which performance information is desired to be grasped. In the case of this embodiment, any state can be employed among the normal state, latent probability state, time saving state, probability variable state, and jackpot game. Also, multiple types of states may be measured. For example, a normal state and a variable probability state, and all game states except during a winning game, etc., and the types to be measured can be determined as appropriate.
Also, as the period of the specific state, the period of either the low probability state or the high probability state of the jackpot lottery probability may be adopted.
Also, the total number of payouts excluding one or a plurality of specific winning holes from the measurement target may be the total number of payouts (total number of payouts excluding specific winning holes). For example, the total number of payouts may be determined by excluding the large winning openings 50 from the measurement targets among the winning openings.

(2) In addition, only one of the total number of payouts, the total number of payouts excluding a specific winning hole, or the total number of out-balls may be measured, and the measurement result may be used as the performance information.

In this embodiment, the total number of balls paid out during the normal state (normal number of balls paid out) and the total number of out balls during the normal state (normal number of out balls) are measured in real time. The value obtained by multiplying the value divided by 100 (normal payout count/normal out count x 100) is displayed as performance information (hereinafter referred to as “normal ratio information”). In addition, the display value at this time shall be the value rounded off to the first decimal place.
Therefore, each data of the normal payout number, the normal out number, and the normal ratio information are stored in the corresponding areas of the main control RAM 20c (specified total prize ball number storage area, specified out number storage area, specific ratio information storage area). are stored (memorized) in each. However, when the total number of out-balls reaches a predetermined specified number (for example, 60,000), the measurement is stopped once, instead of simply measuring permanently and displaying the performance information. This prescribed number is not the total number of out balls in the normal state, but the total number of out balls during all game states (including during winning games) (hereinafter referred to as "the number of out balls in all states"). This all-state-out number is also measured in real time and stored in the corresponding area (all-state-out number storage area) of the main control RAM 20c. Hereinafter, for convenience of explanation, the specified total number of winning balls storage area, specified out number storage area, specified ratio information storage area, and all state out number storage area are abbreviated as "measurement information storage area".

Then, the normal time ratio information at the end point is stored in a predetermined area (performance display storage area) of the main control RAM 20c (this normal time ratio information is stored), and then the measurement information storage area (normal payout number, normal time After clearing the number of out balls and the number of all out balls), measurement is started again (measurement of the number of normal payouts, the normal number of out balls, the normal ratio information, and the number of out balls in all states is started). The performance indicator 97 displays the previous normal time ratio information (measurement history information) and the normal time ratio information currently being measured. It should be noted that not only the information of the previous time but also the history of the time before last or the time before that (three times before) may be displayed.

(Production control command)
The main control board 20 can transmit various effect control commands including information on special symbol variation display games, information on errors, etc. to the effect control board 30 according to the processing state. However, in order to prevent dishonesty such as gratuitous acts, the main control board 20 only transmits signals to the effect control board 30, and a one-way communication configuration in which signals from the effect control board 30 cannot be received. It's becoming

Here, the effect control command defines the function by a 2-byte configuration consisting of a 1-byte length mode (MODE) and a 1-byte length event (EVENT). Bit7 is ON, and Bit7 of EVENT is OFF. When transmitting these information as valid, a strobe signal is output corresponding to each of the mode (MODE) and the event (EVENT). That is, when there is a command to be transmitted, the main control CPU 20a sets and outputs mode (MODE) information for transmitting the command to the effect control board 30, and after a predetermined time has elapsed from this setting, the first strobe signal is sent. Further, event (EVENT) information is set and output after a predetermined time has passed since the transmission of this strobe signal, and the second strobe signal is transmitted after a predetermined time has passed since this setting. The strobe signal is controlled to be active by the main control CPU 20a for a predetermined period during which the effect control CPU 30a can reliably receive commands.

[2.2 Production control board]
The performance control board 30 is equipped with a microprocessor containing a performance control CPU 30a, and a performance control ROM 30b storing performance data required for performance control processing, and a performance control RAM 30c functioning as a work area and a buffer memory. It is composed mainly of a computer, and is also provided with a sound control section (sound source IC), RTC (Real Time Clock) function section, counter circuit, interrupt controller circuit, reset circuit, WDT circuit, etc., and controls the overall performance operation.

The production control CPU 30a performs arithmetic processing for various production operations and controls each production means based on the production control program and the production control command received from the main control unit 20. FIG. In the case of the pachinko game machine 1 of this embodiment, the rendering means includes the liquid crystal display device 36 (main liquid crystal display device 36M, sub liquid crystal display device 36S), optical display device 45a, sound generator 46a, and a movable Become a body role.

The effect control ROM 30b stores a control program for the effect operation by the effect control CPU 30a and various data necessary for control of the effect operation.
The effect control RAM 30c is used as a work area used by the effect control CPU 30a for various arithmetic processing, a table data area, a buffer area for various input/output data and processing data, and the like.
Although the effect control board 30 has, for example, a structure in which a one-chip microcomputer and its peripheral circuits are mounted, various structures of the effect control board 30 are conceivable. For example, in addition to the microcomputer, an interface circuit with each part, a random number generation circuit that generates random numbers for lottery for production, CTC for various time counts, a watchdog timer (WDT) circuit, an interrupt signal to the production control CPU 30a may also include an interrupt controller circuit or the like that provides

The main roles of this production control board 30 are reception of production control commands from the main control unit 20, selection and determination of production based on the production control commands, display control of the liquid crystal display device 36 (supply of display data), and sound generator 46a. , light emission control of the optical display device 45a (LED), operation control of the movable body role object (drive control of the movable body role object motor 80c), and the like.

Since the effect control board 30 also has a function as a control device for the liquid crystal display device 36, the effect control board 30 also functions as a so-called VDP (Video Display Processor), an image ROM, and a VRAM (Video RAM). The provided effect control CPU 30a also functions as a liquid crystal control section.
VDP refers to a function of controlling overall video output processing such as image expansion processing and image drawing.
The image ROM refers to a memory in which image data (effect image data) on which the VDP performs image expansion processing is stored.
VRAM is an image memory area for temporarily storing image data developed by VDP.

The effect control board 30 generates various image data based on commands from the main control unit 20 and outputs the data to the main liquid crystal display device 36M and the sub liquid crystal display device 36S. As a result, various effect images are displayed on the main liquid crystal display device 36M and the sub liquid crystal display device 36S.
Here, the "liquid crystal display device 36" shown in FIG. 2 is the "main liquid crystal display device 36M". The illustration of the sub-liquid crystal display device 36S is omitted in FIG.

In addition, the production control board 30 has a sound control unit (for example, the sound controller 230 in FIG. 4) for the sound generator 46a including a plurality of speakers 46, and the sound signal output by the sound control unit is amplified by the amplifier unit 46d. and supplied to the speaker 46 . Although the sound controller 230 as the sound control section is described as being built in the effect control board 30, the sound control part may use a sound source IC separate from the effect control board 30. FIG.
In addition, the production control board 30 includes a lamp driver section 45d that functions as an optical display control section for an optical display device 45a that includes a decorative lamp 45 and various LEDs, and a movable body accessory motor that operates a movable body (not shown). A motor driver section 80d (motor drive circuit) that functions as a drive control section for 80c is connected. The performance control board 30 instructs the lamp driver section 45d and the motor driver section 80d to control the light display operation by the light display device 45a and the operation of the movable body accessory motor 80c.

The effect control board 30 is also connected with an origin switch 81 and a position detection sensor 82 for monitoring the motion of the movable accessory.
The origin switch 81 is composed of, for example, a photointerrupter or the like, and detects whether or not the movable accessory motor 80c is at the origin position. The origin position is, for example, a position where the movable body does not normally appear on the board surface of FIG. The effect control board 30 can determine whether or not the movable body accessory motor 80c is at the origin position based on the detection information of the origin switch 81. FIG.
In addition, the effect control board 30 controls the action mode while monitoring the current action position (for example, the amount of movement from the origin position) of the movable body role based on the detection information from the position detection sensor 82 . Furthermore, the effect control board 30 monitors malfunctions in the motion of the movable body role based on the detection information from the position detection sensor 82, and detects any malfunctions as errors.

In addition, the production control board 30 is connected to the production button 13, the cross key 15a, and the determination button 15b shown as the operation unit 17 in the figure, that is, the operation detection switch of the production button 13, the cross key 15a, and the determination button 15b. The production control board 30 can receive operation detection signals from the production button 13, the cross key 15a, and the decision button 15b.

Furthermore, the effect control board 30 is provided with a handle sensor 83 (touch sensor) for detecting whether or not the shooting operation handle 15 shown in FIG. 1 is touched by a user such as a player. The performance control board 30 can determine whether or not the shooting operation handle 15 is touched by the user based on the information detected by the handle sensor 83 .

Based on the performance control command sent from the main control unit 20, the performance control board 30 selects (determines) a performance pattern by lottery or uniquely from a plurality of types of performance patterns prepared in advance, and selects (determines) the required performance pattern. To display a desired performance by controlling various performance means at timing. As a result, the display of the effect image by the liquid crystal display device 36 corresponding to the effect pattern, the reproduction of the sound from the speaker 46, the lighting and blinking driving of the decorative lamp 45 and the LED are realized, and various effect patterns (decorative pattern fluctuation display operation, A "drawing scenario" in a broad sense is realized by the time-series development of advance notice effects, etc.

Here, for the production control command, the production control board 30 (production control CPU 30a) generates an interrupt process based on the input of the above-described strobe signal transmitted by the main control unit 20 (main control CPU 20a), and receives and analyzes it. conduct. Specifically, the effect control CPU 30a executes a control program for command reception interrupt processing based on the input of the strobe signal described above, and acquires the effect control command in the interrupt processing realized thereby, do the analysis.
At this time, if an interrupt occurs based on the input of the strobe signal, the effect control CPU 30a, even during execution of interrupt processing based on other interrupts (timer interrupt processing that is periodically executed), The command reception interrupt processing is performed by interrupting the processing concerned, and the command reception interrupt processing is preferentially performed even if other interrupts occur at the same time.

<3. Overview of operation>
Next, the outline of the game operation of the gaming machine 1 realized by the control configuration (FIG. 3) as described above will be described.

[3.1 Game state]
The game machine 1 is configured to be able to set a plurality of types of game states in addition to the jackpot game which is a special game state. In order to facilitate understanding of this embodiment, first, various game states will be described.

In the game machine 1, the game progresses in one of the game states in which either the low-probability state or the high-probability state and the non-time-saving state or the time-saving state are combined.

The low-probability state is a state in which the probability of winning the big-hit lottery is relatively low, and the high-probability state is a state in which the probability of winning the big-hit lottery is relatively high.
The non-time-saving state is a state in which it is relatively difficult for a game ball to enter the starting port 35, and the time-saving state is a state in which it is relatively easy for a game ball to enter the starting port 35. - 特許庁For example, the opening time of the starting port 35 is set longer in the time-saving state than in the non-time-saving state when winning the lottery per normal figure. However, if it is easier for a game ball to enter the starting port 35 in the time-saving state than in the non-time-saving state, the probability of winning the lottery per normal figure is higher in the time-saving state than in the non-time-saving state. Alternatively, the fluctuation time of normal symbols may be shortened.

In this embodiment, the "normal state" refers to a low-probability state and a non-time-saving state, and corresponds to the initial state.

[3.2 Symbol variation display game]
A symbol variation display game will be described.

(Special symbol variation display game)
In the pachinko gaming machine 1 of the present embodiment, a random number A “big hit lottery” will be held by lottery. Based on the result of the lottery, the main control board 20 causes the special symbol display devices 38a and 38b to variably display the special symbol 1 and the special symbol 2 to start the special symbol variation display game, and after the lapse of a predetermined time, displays the result as a special symbol. Derivation display is performed on the symbol display device, thereby ending the special symbol variation display game.

Here, in the present embodiment, the big-hit lottery based on the winning to the starting port 34 and the big-hitting lottery based on the winning to the starting port 35 are performed separately and independently. Therefore, the big-hit lottery result for the starting port 34 is derived from the special symbol display device 38a side, and the big-hit lottery result for the starting port 35 is derived from the special symbol display device 38b side. Specifically, on the side of the special symbol display device 38a, on the condition that the game ball enters the starting port 34, the special symbol 1 is variably displayed and the first special symbol variation display game is started. On the side of the special symbol display device 38b, on the condition that the game ball enters the starting port 35, the special symbol 2 is variably displayed and the second special symbol variability display game is started. . Then, when the special symbol variation display game on the special symbol display device 38a or the special symbol display device 38b is started, after a predetermined variation display time elapses, if the big win lottery result is a "big win", a predetermined "big win". In other cases, the special symbol during variable display is stopped and displayed in a predetermined "lost" mode, thereby deriving the game result (big hit lottery result).

In this specification, for convenience of explanation, the first special symbol variation display game on the side of the special symbol display device 38a is referred to as "special symbol variation display game 1", and the second special symbol on the side of the special symbol display device 38b. The variable display game is called "special symbol variable display game 2". In addition, unless particularly necessary, "special symbol 1" and "special symbol 2" are simply referred to as "special symbol" (sometimes abbreviated as "special symbol"), and "special symbol variation display game 1" and ""Special symbol variation display game 2" is simply referred to as "special symbol variation display game".

(Decorative pattern variation display game)
Further, when the above-mentioned special symbol variation display game is started, along with this, the decorative symbol variation display game is started by variably displaying decorative symbols (dramatic game symbols) on the main liquid crystal display device 36M. Various productions are developed along with. When the special symbol variation display game ends, the decorative symbol variation display game also ends, the special symbol display device displays a predetermined special symbol indicating the jackpot lottery result, and the main liquid crystal display device 36M reflects the jackpot lottery result. The decorative pattern is derived and displayed. In other words, the result of the special symbol variation display game is reflected and displayed by the decorative symbol variation display game including the decorative symbol variation display operation.

Therefore, for example, when the result of the special symbol variation display game is "big win" (when the big win lottery result is "big win"), the decorative symbol variation display game develops an effect reflecting the result. Then, in the special symbol display device, when the special symbol is stopped and displayed in a display mode indicating a big hit (for example, the display state of "7" in the 7 segment), the main liquid crystal display device 36M displays "left", "middle", " In each of the "right" display areas, the decorative pattern reflects the "big hit" (for example, in each of the "left", "middle" and "right" display areas, the three decorative patterns are "7", "7", " 7” display state).

When the "big hit" is achieved, specifically, the special symbol variation display game ends, and the decorative symbol variation display game ends accordingly, and as a result, the "big win" symbol mode is derived and displayed. After that, the large winning opening solenoid 52c of the special variable winning device 52 is actuated to open and close the opening door 52b in a predetermined pattern. A special game state (jackpot game) occurs. In this jackpot game, the open door 52b is operated until the opening time of the jackpot opens for a predetermined time (maximum opening time: for example, 29.8 seconds) or until the number of game balls that win the jackpot (big prize jack) 50) (maximum number of winning balls: maximum number of winning balls allowed for a winning opening whose entrance is opened or enlarged by one actuation of the accessory: e.g. 9) until the winning area is opened or expanded, and if any of these conditions are met, the big winning opening is closed. round) repeated.

When the big win game is started, an opening performance for notifying the start of the big win is first performed, and after the opening performance is completed, the round game is performed a plurality of times with a predetermined number of rounds as an upper limit. After the end of the specified number of rounds, an ending effect is performed to notify that the big win is over, thereby ending the big win game.

Regarding the information necessary for executing the decorative symbol variation display game, first, the main control board 20 is based on the fact that the game ball enters (wins) the starting port 34 or the starting port 35. On the condition that the game ball is detected by the mouth sensor 34a or the starting mouth sensor 35a and the starting condition (starting condition regarding special symbols) is established, a lottery is performed to determine whether it is a "big hit" or "lost". (Lottery by type of winner)' and 'Pattern lottery (lottery of winning type (winning type) lottery)' that draws the type of jackpot if it is a "big hit" and the type of loss if it is a "losing". Perform a jackpot lottery (if there is only one type of loss, the lottery may be omitted because there is no need to perform a type lottery for the loss), and based on the lottery result information, the variation pattern of the special symbol and the winning type Accordingly, a special symbol to be finally stopped and displayed (hereinafter referred to as "special stop symbol") is determined.

Then, the main control board 20, as an effect control command specifying the processing state, at least the special symbol variation pattern information (for example, information about the big hit lottery result and the special symbol variation time, etc.) "variation pattern specification command" including. It is transmitted to the performance control board 30 side. As a result, the basic information required for the decorative symbol variation display game is sent to the effect control board 30 . In the present embodiment, in order to increase the variation of effects, a "decorative design designation command" including special stop design information (symbol lottery result information (information on winning type)) is also transmitted to the effect control board 30. It's like

The above-mentioned special symbol variation pattern information can include information designating whether or not a specific advance notice effect (for example, "ready-to-win effect" or "pseudo-continuous effect", which will be described later) will occur. More specifically, the variation patterns of the special symbols are roughly classified into a "hit variation pattern" for winning and a "losing variation pattern" for losing, depending on the result of the jackpot lottery. For these variation patterns, for example, 'reach variation pattern' that specifies the occurrence of reach production described later, 'normal variation pattern' that does not specify the occurrence of reach production, pseudo-continuous production and reach production (overlapping occurrence) A plurality of types of variation patterns are included, such as 'pseudo-continuous reach fluctuation pattern' to be specified, 'pseudo-continuous normal fluctuation pattern' that specifies the occurrence of pseudo-continuous production and does not specify the occurrence of reach production. In order to secure the performance time of the ready-to-win effect and the pseudo-continuous effect, the variation pattern that designates the ready-to-win effect and the pseudo-continuous effect is usually set to have a longer variation time than the normal variation pattern.

The effect control board 30 is based on the information included in the effect control command (here, the variation pattern designation command and the decorative design designation command) sent from the main control board 20, during the decorative design variation display game chronologically. Decide the production content to be developed (production scenario such as advance notice production) and the decorative pattern to be finally displayed stopped (decorative stop pattern), and display the decorative pattern by fluctuating according to the time schedule based on the special pattern fluctuation pattern. A pattern variation display game is executed. As a result, the decorative symbols are variably displayed by the main liquid crystal display device 36M in synchronization with the variable display of the special symbols by the special symbol display devices 38a and 38b, and the period of the special symbol variable display game and the decorative symbol variable display game. The middle period has substantially the same time width. In addition, the effect control board 30 controls the main liquid crystal display device 36M, the optical display device 45a, or the sound generator 46a so as to correspond to the effect scenario, and develops various effects in the decorative symbol variation display game. As a result, image reproduction (image effect), sound effect reproduction (sound effect), and lighting and blinking driving of the decoration lamp 45 and LED (light effect) are realized on the main liquid crystal display device 36M.

As described above, the special symbol variation display game and the decorative symbol variation display game have an inseparable relationship, and the display results of the special symbol variation display game are reflected in the decoration symbol variation display game. , These two symbol variation display games may be regarded as equivalent symbol games. In this specification, the above-described two symbol variation display games may be simply referred to as "symbol variation display games" unless otherwise specified.

(Normal pattern fluctuation display game)
In addition, in the gaming machine 1, based on the fact that the game ball passes through the normal symbol starting port 37 (winning a prize), the main control board 20 performs an "auxiliary winning lottery" based on a random number lottery. Based on the result of the lottery, the normal symbols represented by the LEDs are variably displayed on the composite display device 38d to start the normal symbol variation display game, and after a certain period of time has elapsed, the results are displayed in combination of lighting and non-lighting of the LEDs. It is designed to stop display. For example, when the result of the normal symbol variation display game is "assist hit", the display unit of the normal symbol of the composite display device 38d is in a specific lighting state (for example, all the two LEDs 39 are in a lighting state, or "○" and "X", the LED on the "O" side is lit).

When this "auxiliary hit" occurs, the normal electric accessory solenoid 41c (see FIG. 3) operates, thereby opening the movable wing and opening or expanding the starting port 35, making it easier for game balls to flow in. It becomes a state (starting opening open state), and an auxiliary game state (hereinafter referred to as "general electric open game") that is more advantageous to the player than the normal game state is generated. In this general electric open game, by the movable wing pieces, until the opening time of the starting port 35 passes a predetermined time (for example, 0.2 seconds), or the number of game balls that win the starting port 35 is a predetermined number (for example, 4) , the winning area is opened or expanded, and when any one of these conditions is met, the starting port 35 is closed.

(About hold)
Here, in this embodiment, during the special/decorative pattern variation display game, during the normal pattern variation display game, during the jackpot game, or during the general electric open game, etc., the starting port 34, the starting port 35, or the normal symbol starting port 37 is won. occurs, that is, there is a detection signal input from the start sensor 34a, the start sensor 35a, or the normal symbol start sensor 37a, and the corresponding start condition (symbol game start condition) is established, this is displayed in a variable manner. As the data relating to the right to start the game, except for the data relating to the variable display, the data is reserved and stored up to the maximum number of reserved memories (for example, a maximum of 4), which is a predetermined upper limit. The reserved data that is not used for the symbol variation display operation or the game ball related to the reserved data is also referred to as "operational reserved ball". In order to make clear to the player the number of activated balls to be held, a dedicated holding display (not shown) provided at an appropriate place in the gaming machine 1 or the liquid crystal display device 36 (main liquid crystal display device 36M or sub liquid crystal display device) is displayed. 36S) light up a hold indicator provided as an icon image in the screen.

In addition, in this embodiment, up to four operation reserve balls relating to special design 1, special design 2, and normal design are reserved and stored in the corresponding storage area of the main control RAM 20c, and reserved as the number of determinations of special design or normal design variation. do. In addition, the maximum memory number (maximum reservation memory number) of each operation reservation ball number regarding the special symbol 1, the special symbol 2, and the normal symbol is not particularly limited. Also, all or part of the maximum reserved memory number of each symbol may be different, and the number can be appropriately determined according to the game characteristics.

[3.3 Per hit]
Next, the “hit” in the game machine 1 will be explained.
In the gaming machine 1 of the present embodiment, a big win lottery (hit lottery) is performed for a plurality of types of wins. In the case of this example, the types of hits include, for example, "normal 4R", "normal 6R", "variable probability 6R", and "variable probability 10R".
Note that the notation of "R" means the prescribed number of rounds (maximum number of rounds).

The jackpot type is a hit that triggers the operation of the condition device. Here, the "conditional device" is a device whose operation is a necessary condition for the operation of the accessory continuous operation device for performing a round game, and a combination of specific special symbols is displayed, or a game ball is displayed. It means something that operates when passing through a specific area in the big winning opening.

The variable probability state ends the high probability state and shifts to the low probability state when the special symbol variation display game is executed a predetermined number of times (for example, 70 times: the prescribed ST number) without winning the jackpot type. , It is a so-called "number-of-times-cutting variable machine (ST machine)", and when the prescribed number of STs is completed, the game is shifted to the normal state from the next game. However, it may be a "general probability changer" that continues until the next big hit is won.

The number of executions of the special symbol variation display game may be the total number of executions of the special symbol variation display game 1 and the special symbol variation display game 2 (the total number of variations of the special symbol 1 and the special symbol 2), It may be the number of executions of either one (for example, the number of executions of the special symbol variation display game 2). Also, the number of times of the time-saving state is not limited to 60 times or 100 times, and can be determined as appropriate according to the playability. Also, there is no particular limitation on the type of hit to be provided, and it can be determined as appropriate.

Here, in this example, a plurality of types are provided for "losing" as well as the jackpot types. Specifically, there are three kinds of loss types: "loss 1", "loss 2", and "loss 3".
As described above, when the result of the win-lose lottery is "lost", the lottery for the type of loosing is performed in the symbol lottery.

[3.4 About production]
(Direction mode)
Next, the production mode (production state) will be described. The gaming machine 1 of the present embodiment is provided with a plurality of types of performance modes for producing performances related to game states, and is configured to be able to move between the performance modes. Specifically, there are provided a normal production mode, a time saving production mode, a latent probability production mode, and a probability variable production mode corresponding to each of the normal state, the time saving state, the latent probability state, and the probability variable state. In each production mode, the background display as the background of the variable display screen of decorative patterns is displayed with different background production, so that the player can grasp what kind of game state he is currently staying in. It has become.

The production control board 30 (production control CPU 30a) has a functional section (production state transition control means) that controls transition between a plurality of types of production modes. The production control board 30 (production control CPU 30a) includes specific production control commands sent from the main control board 20 (main control CPU 20a), specifically, game state information managed on the main control board 20 side. Based on the performance control command, the current game state is grasped in a form that maintains consistency with the game state managed by the main control board 20 side, and the shift control between plural kinds of performance modes is possible. As the specific effect control command as described above, for example, there are a variation pattern designation command, a decorative design designation command, a game state designation command sent when a change occurs in the game state, and the like.

(Notice production)
Next, the advance notice effect will be described. The production control board 30 is based on the content of the production control command from the main control board 20, specifically, at least the variation pattern information included in the variation pattern designation command, variously related to the current production mode and the jackpot lottery result. It is configured to be able to control the appearance of such a "notice effect". Such a notice effect is used as a "promotion effect" to suggest (notice) the degree of expectation of whether or not the winning type has been won (hereinafter referred to as "expectation to win"), and to arouse the player's expectation of winning. work. Typical advance notice effects include "ready effect", "pseudo-continuous effect", and "pre-reading effect". The effect control board 30 functions as a notice effect control means capable of controlling execution (appearance) of these effects.

"Reach production" refers to a production mode with a reach state (variation display mode with a reach state: reach fluctuation pattern), specifically, to derive and display the final game result via the reach state Say the production mode. The ready-to-win effects include multiple types of ready-to-win effects associated with winning expectations. For example, in some cases, the degree of winning expectation is relatively higher than when the normal reach effect appears. Such reach performance is called 'super reach performance'. Many of these "super reach" have relatively longer presentation time (fluctuation time) than normal reach in order to arouse expectation of winning. In addition, normal reach and super reach include multiple types of reach effects. In this example, the super reach includes a plurality of types of reach effects such as super reach 1, 2, 3, and 4, and the winning expectation of these super reach 1 to 4 is "super reach 1 < super reach 2 < super Reach 3 < Super Reach 4” relationship.

"Pseudo-continuous effect" refers to a mode of production accompanied by a pseudo-continuous change display state (pseudo-continuous change) of decorative patterns. It refers to a variable display mode in which a part or all of the symbols are once temporarily stopped, and the display operation is repeated once or more than once, such as executing the re-variable display operation of the decorative symbols from the temporarily stopped state. In this respect, it is different from the later-described "pre-reading forewarning effect (continuous forewarning effect)" that is developed over a plurality of symbol variation display games. Such a "pseudo-run" basically has a rate of occurrence (appearance rate) that increases the expectation of winning as the number of pseudo-fluctuations increases. It is made easy to select an effect for arousing expectations such as reach.

"Pre-reading notice effect" (hereinafter sometimes abbreviated as "pre-reading notice" or "pre-reading effect") is based on the result of pre-reading judgment, before the fluctuation display of the pattern to be judged is performed, It means an effect that notifies the possibility of being controlled in an advantageous state. The term "advantageous state" means a state that is advantageous to the player.
Specifically, the look-ahead effect of this example is mainly for pending display of the operation pending balls (undigested operation pending balls) that have not yet been subjected to the execution of the symbol variation display game (the special symbol variation display operation). Before the operation reserve ball is offered to the symbol variation display game, it is performed in a performance mode that can notify the winning expectation in advance by using the aspect and the background effect of the symbol variation display game to be executed first. . In addition, in the pattern variation display game, in addition to the above-mentioned "reach effect", various effects such as so-called "SU (step-up) notice effect", "timer notice effect", "resurrection effect", and "premier notice effect" are available. It occurs, and it is designed to excite the game content.

Here, with reference to FIG. 4, the "holding change notice effect" as an example of the look-ahead notice effect will be described.
In the case of the gaming machine 1 of the present embodiment, a display area for displaying a decorative symbol variation display game (decorative symbol variation display effect or advance notice effect is displayed) is provided in the upper display area within the screen of the main liquid crystal display device 36M. display area) is provided, and in the lower display area in the screen, a reservation display area 76 (reservation display part a1 to d1) that displays the number of operation reservation balls on the special symbol 1 side and a special A reservation display area 77 (reservation display portions a2 to d2) for displaying the number of operation reservation balls on the symbol 2 side is provided. As for the presence or absence of the operation pending ball, that effect is reported by a predetermined pending display mode. In FIG. 5, the presence or absence of the operation retention ball is lit (with operation retention ball: “○ (white circle)” in the illustration), or in the off state (no operation retention ball: dashed circle in the illustration). It shows an example in which information about the number of balls in operation is notified.

The display (suspension display) regarding the presence or absence of the operation reserve ball is sequentially displayed in the order of occurrence (the order of winning). It is displayed as the first (that is, the oldest) active holding ball on the time axis among the holding balls. Further, on the left side of the holding display areas 76 and 77, there is provided a changing display area 78 for showing the active holding ball currently being used in the special symbol changing display game. In the case of this embodiment, the changing display area 78 is configured so that an image in which the icon of the game pending K which is currently being played is placed on the icon of the strike seat J appears. That is, when the variable display of the special symbol 1 or the special symbol 2 is started, the oldest pending a1 or a2 icon (icon image) displayed in the pending display areas 76 and 77 is the pending K during game execution. As an icon, it moves onto the icon of the striker J in the changing display area 78, and this state is maintained for a predetermined display time.

When an operation pending ball occurs, from the main control board 20, the pre-reading judgment information related to the jackpot lottery result and the number of operating pending balls at the time of the pre-reading judgment (the number of existing operating pending balls including the currently generated operating pending ball) A "suspended addition command" specifying and is transmitted to the effect control board 30 (see steps S1309 to S1312 in FIG. 28).
In the case of this embodiment, the pending addition command is composed of 2 bytes, and the pending addition command can specify the upper byte side data that can specify the number of operation pending balls at the time of prefetching determination, and the prefetching determination information. It consists of lower byte side data.

Here, as can be understood from the above description, in the present embodiment, based on the occurrence of a winning prize at the starting port 34 or the starting port 35 and a new retained ball, as a prefetch determination for the retained ball , a jackpot lottery for the symbol variation display game related to the reserved ball is carried out. As will be described later, the main control board 20 reserves and stores information representing the result of the big hit lottery performed as such prefetch determination in the corresponding storage area of the main control RAM 20c.
The information of the jackpot lottery result obtained at the time of the prefetch determination is used to select (lottery) the pattern variation pattern in the pattern variation display game, and can be rephrased as "variation pattern selection information". Therefore, it can be said that the main control board 20 carries out a pre-reading determination, and reserves and stores the "variation pattern selection information" obtained as a result in a predetermined area of the main control RAM 20c.

When the effect control board 30 receives the pending addition command transmitted by the main control board 20, based on the prefetch determination information included therein, as part of the display control processing related to the pending display, "prefetching preview effect" is performed. Effect control processing related to is performed. Concretely, a "pre-reading notice lottery" is carried out to determine whether or not the pre-reading notice effect can be executed.

Here, the look-ahead determination information is, specifically, the result of the big win lottery (big win lottery result at the start of variation) executed when the operation reserve ball is offered to the symbol variation display game in the main control board 20, This is the game information obtained by pre-reading and judging the fluctuation pattern at the time of fluctuation start. That is, this information includes at least the information (prefetching winning/losing information) that prefetches the winning/losing lottery result at the start of the fluctuation, and the information that prefetches the pattern lottery result (prefetching pattern information) and the fluctuation at the start of the fluctuation. Information (prefetch variation pattern information) obtained by prefetch determination of the pattern can be included. What kind of information is included in the pending addition command to be sent to the effect control board 30 can be appropriately determined according to the content to be notified by the pre-reading notice.
In this example, it is assumed that the pending addition command includes prefetch hit/loss information, prefetch pattern information, and prefetch variation pattern information.

It should be noted that the "look-ahead fluctuation pattern" obtained by the look-ahead judgment when the operation reserve ball is generated is not necessarily the "variation pattern at the start of fluctuation" obtained when the operation reserve ball is actually used for the fluctuation display operation. no. For example, representatively explaining the case where the fluctuation pattern at the start of fluctuation is a fluctuation pattern that specifies "super reach 1", in this case, the content specified by the look-ahead fluctuation pattern is called "super reach 1" It is possible to specify that it is not the type of reach production itself, but the "super reach type" that is the gist of it.

In the case of this embodiment, when the pre-reading notice lottery is won, among the holding icons of the holding display portions a1 to d1 and a2 to d2, the holding icon targeted for the pre-reading notice is, for example, a normal holding display. (Normal pending display mode) can change from white (normal pending display mode) to pending display (special pending display mode) with blue, green, red, and danger patterns (or special colors and patterns such as rainbow colors) for advance notice display (special pending display mode) System" pre-reading notice effect (also referred to as "holding change notice") is performed.
FIG. 5 shows an example in which the operation holding ball of the hatched holding display portion b1 has changed to a special holding display. Here, the display of blue, green, red, and danger pattern of the pending icon means that the expectation of winning is high in this order, and especially the display of the pending icon with the danger pattern has an extremely high expectation of winning the jackpot. It is supposed to be a premium pending icon that will be displayed.

(Direction means)
Various effects in the game machine 1 are produced by effect means provided in the game machine 1 . The directing means may be stimulus transmission means capable of exhibiting directing effects by appealing to human perception such as visual, auditory, and tactile sensations. light effect means), sound generator such as speaker 46 (sound generator 46a: sound effect means), effect display device (display means) such as main liquid crystal display device 36M and sub liquid crystal display device 36S, contact with operator's body Typical examples include a pressure device that transmits pressure, a wind pressure device that applies wind pressure to the player's body, and a movable body accessory that exerts a visual performance effect by its operation. Here, the effect display device is a display device that appeals to the sense of sight like the image display device, but differs from the image display device in that it also includes devices that do not rely on images (for example, a 7-segment display device). When it is called an image display device, it mainly refers to a type that produces effects by image display, and devices that produce effects by means other than images, such as 7-segment displays, are included in the concept of the above-mentioned effect display device.

<4. Opening/Closing Structure and Substrate Arrangement>

The configuration of FIG. 3 described above is actually realized via a plurality of substrates. Some of the boards mounted on the game machine 1 will be extracted and their arrangement will be described below. Also, the opening/closing structure of the gaming machine 1 will be explained for the mounting position of the board.

FIG. 5 shows a state in which the door 6 is opened.
By opening the door 6, the inner frame 2 and the game board 3 attached to the inner frame 2 are directly exposed.
The substrate arranged on the door 6 and the substrate arranged on the inner frame 2 are wired and connected by a harness as a transmission line H8.

The gaming machine 1 is also configured so that the inner frame 2 can be opened with respect to the outer frame 4 .
FIG. 6 shows a state in which the inner frame 2 is opened. By opening the inner frame 2, the game board 3 attached to the inner frame 2 is also released from the outer frame 4.例文帳に追加FIG. 6 shows a state in which the back cover 18 attached to the back side of the game board 3 is visible. Although the game board 3 is not shown in FIG. 6, the back side of the game board 3 is exposed when the back cover 18 is removed (opened). Actually, the back side of the game board 3 can be visually recognized in the state of FIG. 6 because the back cover 18 is transparent or translucent.
In addition, the game board 3 can be further removed from the inner frame 2 .

Thus, the gaming machine 1 can be roughly divided into an outer frame 4, an inner frame 2 attached to the outer frame 4, a game board 3 attached to the inner frame 2, and a It consists of a door 6 located. Various substrates are attached to any of the game board 3, the inner frame 2, and the door 6.

FIG. 7 shows the positions of some of the boards attached to the game board 3. As shown in FIG. Note that FIG. 7 shows a board mounted on the back side of the game area 3a when the game board 3 is viewed from the back side. Therefore, the right side of the drawing is the left side when the game board 3 is viewed from the front side. In the drawing, the outline of the frame of the game board 3 is indicated by a dashed line for the reference of the position.

As shown in the figure, on the back side of the game board 3, the effect control board 30 is arranged slightly above the center, and the main control board 20 is arranged below it. A liquid crystal control board 901 is arranged so as to overlap with the performance control board 30, and a ROM board 902 and a liquid crystal interface board 903 are arranged in the vicinity thereof.

An LED connection board 700 is arranged on the left side of the back surface of the game board 3, and a power supply module board 904 is arranged near the top thereof.
An upper connection board 905 is arranged above the game board 3 .

In the vicinity of the main control board 20, a relay board 760, a decoration board 740, a board back left relay board 720, a game board connection board 906, a board back bottom relay board 800, and a frame LED relay board 840 are arranged.

Further, there are LED boards 780 and 790 and a decorative board 820 as boards mounted on movable accessories (not shown) mounted on the game board.

FIG. 8 shows the positions of some of the substrates attached to the door 6 as seen from the front side of the game machine 1. FIG. As a configuration inside the gaming machine 1, the door 6, the effect button 13, the firing operation handle 15, and the upper speaker 46 are indicated by a dashed line for the purpose of positioning.

A relay board 550 is provided above the door 6 .
Similarly, a side unit upper LED board 630 is provided above the door 6, a side unit upper right LED board 600 is provided on the upper right of the door 6, and a side unit lower right LED board 620 is provided below. The side unit upper right LED board 600, the side unit lower right LED board 620, and the side unit upper LED board 630 are mounted inside the side unit 10 (see FIG. 1). By being mounted, the position state shown in FIG. 8 is obtained.

A frame left LED board 907 is arranged on the upper left side of the door 6, and a frame lower left LED board 908 is arranged below it.
A front frame LED connection board 500 is arranged below the door 6 .
A button LED connection board 640 is arranged at the lower right, and a button LED board 660 is arranged inside the production button 13 .

Next, the positions of the substrates attached to the inner frame 2 will be described. FIG. 9 is a diagram of the gaming machine 1 as seen from the back. The rear side of the gaming machine 1 is mostly protected by a transparent or translucent rear cover 18.例文帳に追加
A power supply board 300 and a payout control board 29 are arranged in the front-rear direction under the back side.
In addition, the inner frame LED relay board 400 is attached to the lower right side as viewed from the back side.

FIG. 10 shows the arrangement positions of various devices arranged on the door 6 and the game board 3 . The contours of the game board 3 and the door 6 are indicated by dashed lines to indicate the position of each device.

10, devices provided in the side unit 10 of the door 6 include a side unit device 101, a side unit lower right movable object position detection switch 102, a side unit lower right movable object motor 103, and a side unit upper right movable object motor 104. , the upper right movable solenoid 105 of the side unit, the blower 106, and the photocouplers PC1F, PC2F, and PC3F are arranged at the illustrated positions. Photocouplers PC1F, PC2F, and PC3F are attached to the lower right LED board 620 of the side unit.

In FIG. 10, the devices attached to the game board 3 include a lower back movable object upper position detection switch 120, a lower back movable object right position detection switch 121, a distribution position detection switch 122, a lower front movable object position detection switch 123, a lower Front movable object motor 124, bottom back movable object left position detection switch 125, bottom back movable object left motor 126, bottom back movable object bottom right position detection switch 127, bottom back movable object bottom left position detection switch 128, top movable object left Motor 129, upper movable object left position detection switch 130, left movable object motor 131, upper movable object position detection switch 132, upper movable object right motor 133, left movable object position detection switch 134, lower back movable object right motor 135, They are arranged at the positions shown in the figure.

It should be noted that the boards shown in FIGS. 7, 8, and 9 are only part of the boards provided in the gaming machine 1. FIG. In particular, it illustrates the main substrates to be covered in the following description.
Also, the devices shown in FIG. 10 are only part of the devices provided in the gaming machine 1 .

<5. Board Connection Configuration>
[5.1 Connection state of each board]

The connection configuration of each substrate arranged as described above will be described, and the supply path of the power supply voltage will be referred to.

FIG. 11 shows an example of substrates arranged on the game board 3, the inner frame 2, and the door 6, respectively.
In this case, the boards mounted on the game board 3 include the main control board 20, the effect control board 30, the frame LED relay board 840, the LED connection board 700, the board back left relay board 720, the decoration board 740, the relay board 760, and the LED A substrate 780, an LED substrate 790, a backside lower relay substrate 800, and a decoration substrate 820 are shown.
As the boards mounted on the inner frame 2, the power supply board 300, the payout control board 29, and the inner frame LED relay board 400 are shown.
Boards mounted on the door 6 include a front frame LED connection board 500, a relay board 550, a side unit upper right LED board 600, a side unit lower right LED board 620, a side unit upper LED board 630, a button LED connection board 640, and buttons. An LED substrate 660 is shown.

Each of these boards is a part of the boards mounted on the game machine 1, and the boards mounted on the game board 3, the inner frame 2, and the door 6 include various boards other than those shown in the drawings. This FIG. 11 shows a connection system of substrates extracted for use in explaining the technology as an embodiment of the present invention, and does not show all substrates.

The power supply substrate 300 is a substrate that supplies a DC voltage as an operating power supply to each part based on an AC input power supply.
The main control board 20, the performance control board 30, and the payout control board 29 are as explained in FIG.

The front frame LED connection board 500 is a board for supplying operation control signals and power supply voltages to performance means such as LEDs provided on the door 6, motors of movable bodies, solenoids, and blowers.

A side unit upper right LED board 600, a side unit lower right LED board 620, and a side unit upper LED board 630 are boards arranged in the side unit 10, and constitute a drive control system for the mode of LEDs and movable body parts. These boards also constitute a detection system that transmits detection signals from motor position sensors, touch sensors, and other various sensors to the effect control board 30 .
As described above, the side unit 10 is attached to the door 6 as one of the decorative units, and the side unit 10 can be attached to and detached from the door 6 for replacement. The side unit upper right LED board 600 , the side unit lower right LED board 620 , and the side unit upper LED board 630 are attached and detached together with the side unit 10 .
When the side unit 10 is mounted and the relay board 550 and the transmission line H10 of the upper right LED board 600 of the side unit are connected, the electrical configuration shown in FIG. 11 is obtained.

The button LED board 660 constitutes the LED in the production button 13 and its light emission driving system, and also constitutes a circuit for transferring detection signals of various detection sensors.
The button LED connection board 640 relays control signals and power supply voltage to the button LED board 660, and transfers detection signals of various sensors.

The inner frame LED relay board 400 performs necessary signal processing while relaying between the frame LED relay board 840 connected to the effect control board 30 and the front frame LED connection board 500, and also generates and supplies power supply voltage. .
The frame LED relay board 840 relays the signal path between the inner frame LED relay board 400 and the effect control board 30 .

The LED boards 780 and 790 are mounted with LEDs in the game board 3 and drive the light emission. The relay board 760 relays the light emission driving signal of the LED. These LED boards 780, 790 and relay board 760 are attached to the movable accessory.
Decoration board 740 provides relay and drive for other LED boards.
The board rear left relay board 720 performs relay.
The decorative substrate 820 carries LEDs.
The board rear bottom relay board 800 performs relay.
LED connection board 700, based on the control signal from the effect control board 30, performs various necessary signal processing for the light emission drive of the effect means such as LEDs and motors.

These substrates are electrically connected by a transmission line H using harnesses and cables. "Transmission line H" is a generic term for the illustrated transmission lines H1, H2, . . . H31.
In each transmission line H, individual wiring paths for transmitting signals, power supply voltages, etc. are also simply referred to as "lines."
A transmission line H refers to a set of one or more lines.
The transmission line H includes various forms such as a flexible harness, a flexible substrate, and a wire harness. The transmission line H may be formed by integrating a plurality of lines, or may be formed by binding individual lines with a binder, tape, or the like.
Further, when the connectors are directly connected to each other, the terminals of the respective connectors become the transmission line H. In other words, the "transmission line H" includes a case where a wire material such as a harness does not exist.
That is, the transmission line H does not refer to a specific type or shape, but broadly refers to those forming electrical wiring between substrates or the like.

The power board 300 and the payout control board 29 are connected by a transmission line H1.
Also, the power supply board 300 and the inner frame LED relay board 400 are connected by a transmission line H3.
These transmission lines H1 and H3 are formed by harnesses or the like arranged within the inner frame 2. As shown in FIG.

The power board 300 and the performance control board 30 are connected by a transmission line H2.
The payout control board 29 and the main control board 20 are connected by a transmission line H4.
The inner frame LED relay board 400 and the frame LED relay board 840 are connected by a transmission line H7.
These transmission lines H2, H4, and H7 are made up of harnesses or the like connecting between the inner frame 2 and the game board 3. As shown in FIG.

The main control board 20 and the performance control board 30 are connected by a transmission line H5.
The effect control board 30 and the frame LED relay board 840 are connected by a transmission line H6.
The effect control board 30 and the LED connection board 700 are connected by a transmission line H20.
The LED connection board 700 and the backside left relay board 720 are connected by a transmission line H21.
The backside left relay board 720 and the decoration board 740 are connected by a transmission line H22.
The decoration board 740 and the relay board 760 are connected by a transmission line H23. It is conceivable that the transmission line H23 is a flexible cable for connection with the relay board 760 attached to the movable object.
The relay board 760 and the LED board 780 are connected by a transmission line H24.
The LED substrate 780 and the LED substrate 790 are connected by a transmission line H25.
The LED connection board 700 and the underboard relay board 800 are connected by a transmission line H30.
The underside relay board 800 and the decoration board 820 are connected by a transmission line H31.
These transmission lines H 5 , H 6 , H 20 , H 21 , H 22 , H 23 , H 24 , H 25 , H 30 and H 31 are harnesses arranged within the game board 3 .

The inner frame LED relay board 400 and the front frame LED connection board 500 are connected by a transmission line H8.
The transmission line H8 is formed by a harness or the like that connects across the inner frame 2 and the door 6. As shown in FIG.

The front frame LED connection board 500 and the relay board 550 are connected by a transmission line H9.
The relay board 550 and the side unit upper right LED board 600 are connected by a transmission line H10.
The side unit upper right LED board 600 and the side unit lower right LED board 620 are connected by a transmission line H11.
The side unit upper right LED board 600 and the side unit upper LED board 630 are connected by a transmission line H12.
The front frame LED connection board 500 and the button LED connection board 640 are connected by a transmission line H15.
The button LED connection board 640 and the button LED board 660 are connected by a transmission line H16.
These transmission lines H 9 , H 10 , H 11 , H 12 , H 15 and H 16 are harnesses or the like arranged inside the door 6 .

The power supply substrate 300 supplies a power supply voltage to each part through transmission lines H1, H2, and H3.
FIG. 12 shows the power supply input/output of the power supply substrate 300. As shown in FIG.
The power board 300 is mounted with connectors CN1A to CN7A.
Transmission line ends of transmission lines H40, H41, and H42 (not shown in FIG. 11) are connected to the connectors CN5A, CN6A, and CN7A.

In the following description, the connectors CN1A to CN7A and the connectors shown in other drawings are collectively referred to as "connector CN".
In this specification, "connector CN" refers to a connector terminal component provided on the board. A terminal portion formed at the end of the transmission line H for connector connection is called a "transmission line end".
The "connector CN" is connected to the "transmission line end". Alternatively, the "connector CN" may be directly connected to another connector CN having a corresponding shape.

AC 24V power from the power plug 301 of the gaming machine 1 is supplied to the three-terminal connector CN5A through the transmission line H40 (AC-IN (A), AC-IN (B)).
Also, an FG (frame ground) path (FG) is formed through the ground terminal 302, the transmission line H40, and the connector CN5A. The ground terminal 302 is connected to the outside of the game machine main body, for example.

A transmission line H41 is connected to the two-terminal connector CN6A to form an FG path (FG-1) via ground terminals 303 and 304. FIG. The ground terminals 303 and 304 are connected to, for example, the main body of the gaming machine.
A transmission line H42 is connected to the two-terminal connector CN7A to form an FG path (FG-2) through ground terminals 305 and 306. FIG. The ground terminals 305 and 306 are connected to, for example, the main body of the gaming machine.

A transmission line H1-1 is connected to the 14-terminal connector CN1A. A transmission line H1-1 is connected to the connector CN4A having three terminals. The transmission lines H1-1 and H1-2 as these two harnesses are shown as the transmission line H1 in FIG. 11 described above.
35V DC voltage (DC35VA), 12V DC voltage (DC12VA), and 5V DC voltage (DC5VA) are supplied to payout control board 29 by transmission line H1-1, and a ground path (GND) is formed.
Two systems of 24V DC voltage (DC24VA, DC24VB) are supplied to the payout control board 29 through the transmission line H1-2, and an FG path (FG) is formed.

35V DC voltage (DC35VA), 12V DC voltage (DC12VA), and 5V DC voltage (DC5VA) are supplied to the main control board 20 via the payout control board 29, and a ground path (GND) is formed. .

A transmission line H2 is connected to the 20-terminal connector CN2A.
5V DC voltage (DC5VB), 12V DC voltage (DC12VB), and 35V DC voltage (DC35VB) are supplied to the effect control board 30 by the transmission line H2, and a ground path (GND) is formed.

Based on the power supply by the transmission line H2, the effect control board 30 to the LED connection board 700, 5V DC voltage (DC5VB), 12V DC voltage (DC12VB), 35V DC voltage (DC35VB) is supplied, the LED connection board 700 and each downstream circuit board (the backside left relay board 720, the backside lower relay board 800, etc.).
On the other hand, the frame LED relay board 840 is a board having a simple relay wiring and does not require a power supply voltage, and the power supply voltage is not supplied from the effect control board 30 .

For the sake of explanation, the terms "upstream" and "downstream" are used, but with regard to data and control signals, the main control board 20 is the most upstream, followed by the effect control board 30, and from the effect control board 30 to the actual components such as LEDs and motors. "Downstream" toward the production device of
Regarding the power supply voltage, the power supply board 300 is the most upstream, and it is assumed to be "downstream" toward the actual production device.

A transmission line H3 is connected to the six-terminal connector CN3A.
A 12V DC voltage (DC12VB) is supplied to the inner frame LED relay board 400 through the transmission line H3, and a ground path (GND) is formed.
In other words, the inner frame LED relay board 400 is a board controlled from the effect control board 30, but is configured to receive the power supply voltage directly from the power board 300.
Each board (front frame LED connection board 500 and the like) provided on the door 6 downstream from the inner frame LED relay board 400 receives supply of power supply voltage from the inner frame LED relay board 400 .

[5.2 Inner frame LED relay board 400]

The circuit configuration of some of the substrates shown in FIG. 11 will be described below. First, the inner frame LED relay board 400 will be described with reference to FIGS. 13 and 14. FIG.
13 and 14 separately show the circuit configuration provided on the inner frame LED relay board 400. FIG.

Connectors CN1B, CN2B, and CN3B shown in FIG. 13 and connector CN4B shown in FIG. 14 are mounted on the inner frame LED relay board 400 .

The transmission line end of the transmission line H7 connecting between the frame LED relay board 840 and the connector CN1B is connected.
Although the details of the frame LED relay board 840 are omitted, it is a board having a simple relay wiring as described above. Therefore, the connector CN1B substantially forms wiring between the effect control board 30 via the transmission line H7, the frame LED relay board 840, and the transmission line H6.

This connector CN1B has 28 terminals from the first pin to the 28th pin as indicated by the numbers "1" to "28".
For convenience of explanation, the term "pin" of the connector CN does not refer only to pin-shaped male terminals, but includes both male terminals and female terminals. It is used to include terminals and the like.

The first, third, fifth, seventh, eighth, seventeenth and eighteenth pins are ground terminals. The second pin is assigned to the clock signal S_IN_CLK, the fourth pin to the load signal S_IN_LOAD, and the sixth pin to the serial data signal S_IN_DATA.

9th pin is clear signal CLR_L, 10th pin is clear signal CLR_M, 11th pin is clock signal CLK_L, 12th pin is clock signal CLK_M, 13th pin is data signal DATA_L, 14th pin is data signal DATA_M, 15th pin is A pin is assigned as an enable signal ENABLE_L, and a 16th pin is assigned as an enable signal ENABLE_M terminal.
The 19th to 28th pins are assigned to +terminals and -terminals of the upper right speaker, the middle right speaker, the lower right speaker, the upper left speaker, the middle left speaker, and the lower speaker as the speaker 46, respectively.

Here, the serial data signal S_IN_DATA is serial data received from the front frame LED connection board 500 and transmitted from the inner frame LED relay board 400 to the effect control board 30 .
The clock signal S_IN_CLK and the load signal S_IN_LOAD are supplied from the effect control board 30 to the inner frame LED relay board 400 and further sent to the front frame LED connection board 500 . These are used for serial data transmission operation from the front frame LED connection board 500 on the downstream side.

Clear signals CLR_L, CLR_M, clock signals CLK_L, CLK_M, data signals DATA_L, DATA_M, enable signals ENABLE_L, ENABLE_M are signals supplied from the effect control board 30 and used for drive control of the effect devices.
For example, the data signals DATA_L and DATA_M are light emission drive signals and motor drive signals that indicate the gradation of the LED, and the clear signals CLR_L and CLR_M, etc., the clock signals CLK_L, CLK_M, etc., and the enable signals ENABLE_L, ENABLE_M, etc. This is a signal for controlling the operation of the motor driver.
Note that the suffix "_L" of the clock signals CLK_L, CLK_M, etc. indicates that they are signals mainly used for LED operation control, and "_M" indicates that they are signals mainly used for motor operation control.

The connector CN2B is connected to the transmission line end of the transmission line H8 connecting to the front frame LED connection board 500 .
This connector CN2B has 30 terminals from the 1st pin to the 30th pin as indicated by the numbers "1" to "30".

The 1st pin and the 3rd pin are terminals for a 5V DC voltage (DC5VB).
Four pins from the 27th pin to the 30th pin are terminals for a 12V DC voltage (DC12VB).
The fifth, seventh, eighth, seventeenth and eighteenth pins are ground terminals.
Conductor points P1 and P2 on the housing of connector CN2B are grounded. This is due to the mounting strength of the connector. The conductor points P1 and P2 are not connected to the ground terminal inside the connector.
In all other illustrated connectors CN, the conductor points P1 and P2 on the housing are not connected to the ground terminal inside the connector.

The second pin is assigned to the clock signal S_IN_CLK, the fourth pin to the load signal S_IN_LOAD, and the sixth pin to the serial data signal S_IN_DATA.
9th pin is clear signal CLR_L, 10th pin is clear signal CLR_M, 11th pin is clock signal CLK_L, 12th pin is clock signal CLK_M, 13th pin is data signal DATA_L, 14th pin is data signal DATA_M, 15th pin is The pin is assigned as a general-purpose output port, and the 16th pin is assigned as each terminal of an enable signal ENABLE_M.
The 19th pin to the 26th pin are assigned to the + terminal and - terminal of the upper right speaker, the middle right speaker, the lower right speaker, the upper left speaker, and the middle left speaker as the speaker 46, respectively, as shown in the figure.

A connector CN3B is a connector for connection with a lower speaker, which is one of the speakers 46 (not shown in FIG. 11). The first and second pins numbered "1" and "2" of the connector CN3B are assigned to the + and - terminals of the lower speaker, and are connected to the 27th and 28th pins of the connector CN1B.

The connector CN4B in FIG. 14 is connected to the transmission line end of the transmission line H3 connecting to the power supply board 300, and is connected to the connector CN3A of the power supply board 300 shown in FIG.
This connector CN4B has six terminals from the first pin to the sixth pin as indicated by the numbers "1" to "6", which are assigned in the same manner as the connector CN3A of the power supply board 300. FIG. That is, the first pin, the second pin, and the third pin are terminals to which a 12 V DC voltage (12 VA DC) is supplied from the power supply board 300 . The fourth, fifth and sixth pins are ground terminals.

In this case, the inner frame LED relay board 400 is configured to input the 12V DC voltage (DC12VA) from the first pin, the second pin, and the third pin to the voltage regulator 401 via the fuse F1B. A 5V DC voltage (DC5VB) is obtained as an output. Capacitors C3B, C4B, C5B, and C6B are connected in parallel between the input terminal side of the voltage regulator 401 and the ground. A capacitor C7B and a resistor R24B are connected in parallel between the output terminal side of the voltage regulator 401 and the ground.
That is, a 5V generator 410 is formed to generate a 5V DC voltage (DC5VB) from a 12V DC voltage (DC12VA).

From the first and third pins of the connector CN2B in FIG. 13, the 5V DC voltage (DC5VB) generated by the inner frame LED relay board 400 is supplied to the downstream board.
The 12V DC voltage (DC12VB) supplied to the downstream board via the 27th to 30th pins of the connector CN2B is supplied via the 1st, 2nd and 3rd pins of the connector CN4B in FIG. This is the voltage supplied from the power supply board 300 .

As shown in FIG. 13, buffer circuits 402 and 403 formed of ICs are arranged on the inner frame LED relay board 400 .
As the buffer circuits 402 and 403, an IC is used that functions as an inverter when the CONT terminal of the first pin is at L level and as a buffer when at H level. It works as a buffer.
As an operating power supply, a 5V DC voltage (DC5VB) is applied to the VCC terminal of the 20th pin.

The buffer circuits 402 and 403 are Schmitt trigger buffers containing CMOS8 circuits, buffering the signals input from the second pin (A1 terminal) to the ninth pin (A8 terminal), that is, signal compensation (deteriorated H/ L signal waveform recovery), and output from the 18th pin (Y1 terminal) to the 11th pin (Y8 terminal), respectively.
That is, the signal input to the A1 terminal is buffered and output from the Y1 terminal, the signal input to the A2 terminal is buffered and output from the Y2 terminal, . . . the signal input to the A8 terminal is buffered. and output from the Y8 terminal.
Note that buffer processing is signal compensation processing such as signal amplification and waveform shaping, and since it mainly deals with pulse signals as digital data, waveform shaping has a great significance. These processes are hereinafter referred to as "buffer processing" or "signal compensation".

The buffer circuit 402 performs signal compensation for the clock signal S_IN_CLK, the load signal S_IN_LOAD, and the serial data signal S_IN_DATA.
A clock signal S_IN_CLK from the second pin of the connector CN1B is input to the A3 terminal of the buffer circuit 402, output from the Y3 terminal and supplied to the second pin of the connector CN2B.
A load signal S_IN_LOAD from the fourth pin of the connector CN1B is input to the A1 terminal of the buffer circuit 402, output from the Y1 terminal, and supplied to the fourth pin of the connector CN2B.
The serial data signal S_IN_DATA input to the 6th pin of the connector CN2B from the downstream side is input to the A5 terminal of the buffer circuit 402, output from the Y5 terminal, and supplied to the 6th pin of the connector CN1B.

Further, the buffer circuit 402 includes the 3rd pin (A2 terminal), the 5th pin (A4 terminal), the 7th pin (A6 terminal), the 8th pin (A7 terminal), the 9th pin (A8 terminal), the 10th pin ( GND terminal) and the 19th pin (G terminal) are grounded. The 11th pin (Y8 terminal), 12th pin (Y7 terminal), 13th pin (Y6 terminal), 15th pin (Y4 terminal), and 17th pin (Y2 terminal) are open.

The buffer circuit 403 performs signal compensation for the clear signals CLR_L, CLR_M, the clock signals CLK_L, CLK_M, the data signal DATA_L, the data signal DATA_M, the enable signal ENABLE_L for the 15th pin, and the enable signal ENABLE_M for the 16th pin.
These signals input from the 9th to 16th pins of the connector CN1B are input to any one of the A1 to A8 terminals of the buffer circuit 402, output from the Y1 to Y8 terminals, and sent to the connector CN2B. It is supplied to the 9th to 16th pins.
The buffer circuit 403 has the 10th pin (GND terminal) and the 19th pin (G terminal) connected to the ground.

As described above, the inner frame LED relay board 400 has the following configuration.
- The clock signal S_IN_CLK and the load signal S_IN_LOAD supplied from the effect control board 30 (frame LED relay board 840) to the connector CN1B are signal-compensated by the buffer circuit 402 and transmitted to the downstream side by the connector CN2B.
The serial data signal S_IN_DATA supplied from the downstream front frame LED connection board 500 to the connector CN2B is signal-compensated by the buffer circuit 402 and transmitted to the upstream side by the connector CN1B.
・Clear signals CLR_L, CLR_M, clock signals CLK_L, CLK_M, data signals DATA_L, DATA_M, enable signals ENABLE_L, ENABLE_M supplied to the connector CN1B from the effect control board 30 (frame LED relay board 840) are signal-compensated by the buffer circuit 403. and transmitted downstream through the connector CN2B.

・Relay the audio signal to the speaker and directly send it to the substrate or speaker unit on the downstream side.
· Power supply voltage is not supplied from the connector CN1B (transmission line H7) connected to the effect control board 30 side (frame LED relay board 840).
12V DC voltage (DC12V) is received from the power supply board 300 through the connector CN4B, and is supplied to the downstream side via the fuse F1B as 12V DC voltage (DC12VB).
12V DC voltage (DC12V) is used to generate a 5V DC voltage (DC5VB) used in the inner frame LED relay board 400 and the downstream side, which is used as the operating power source for 403 of the buffer circuit 402 and supplied to the downstream side.

In the inner frame LED relay board 400, resistors R1B to R26B, chip resistors RA1B and RA2B, and capacitors C1B to C17B are connected to required locations as shown in FIGS. 13 and 14 in addition to the above. .
For example, for clock signal S_IN_CLK, load signal S_IN_LOAD, clear signals CLR_L, CLR_M, clock signals CLK_L, CLK_M, data signals DATA_L, DATA_M, enable signals ENABLE_L, ENABLE_M, resistors R25B, R26B, R8B, R9B, R10B, R11B, R12B, R13B, R14B, and R15B are inserted as damping resistors. Resistors R3B and R2B and chip resistors RA1B and RA2B are inserted as damping resistors on the output side (connector CN2B side).
In this case, if LA is the wiring distance between the connector and the damping resistor, and LB is the wiring distance between the damping resistor and the buffer circuits 402 and 403,
LA < LB
relationship. That is, the damping resistors are arranged closer to the connector (CN1B or CN2B) than the buffer circuits 402 and 403. This improves the signal noise reduction performance.

[5.3 Front frame LED connection board 500]

The front frame LED connection board 500 will be described with reference to FIGS. 15, 16, 17, 18, 19 and 20. FIG. These figures show separately the circuit configuration provided on the front frame LED connection board 500 .

15, connectors CN1C and CN4C in FIG. 16, connector CN3C in FIG. 17, connectors CN7C and CN9C in FIG. 18, and connector CN10C in FIG. is installed.

The connector CN2C in FIG. 15 is connected to the transmission line end of the transmission line H8 that connects with the connector CN2B of the inner frame LED relay board 400 in FIG.
Therefore, this connector CN2C has 30 terminals from the 1st pin to the 30th pin as indicated by the numbers "1" to "30", and the terminal assignments are the same as those of the connector CN2B. Conductor points P1 and P2 on the housing of connector CN2C are also connected to ground. This is due to the mounting strength of the connector, and the conductor points P1 and P2 are not connected to the ground terminal inside the connector.
Although not mentioned again, conductor points P1 and P2 in housings of connectors CN1C, CN3C, CN4C, CN7C, CN8C, CN9C, and CN10C, which will be described later, are also grounded for mounting strength.

A connector CN5C is a connector for connection with a middle right speaker, which is one of the speakers 46 . The 1st and 2nd pins numbered "1" and "2" of the connector CN3B are assigned to the +terminal and -terminal of the right middle speaker, and are connected to the 20th and 22nd pins of the connector CN2C. .

A connector CN6C is a connector for connection with a left middle speaker, which is one of the speakers 46 . The 1st and 2nd pins numbered "1" and "2" of this connector CN6B are assigned to the +terminal and -terminal of the left middle speaker, and are connected to the 24th and 26th pins of the connector CN2C. .

A connector CN8C is a connector for connection with an upper right speaker and an upper left speaker, which are one of the speakers 46 . The first and second pins numbered "1" and "2" of the connector CN6B are assigned to the + and - terminals of the upper right speaker, and are connected to the 19th and 21st pins of the connector CN2C. The third and fourth pins numbered "3" and "4" are assigned to the +terminal and -terminal of the upper left speaker, and are connected to the 23rd and 25th pins of the connector CN2C.

A connector CN1C in FIG. 16 is a connector that is connected to an LED board (not shown in FIG. 11).
The connector CN4C is also connected to the LED board inside the handle (not shown).

The connector CN1C has 13 terminals from the 1st pin to the 13th pin as indicated by the numbers "1" to "13".
The 1st and 6th pins are ground terminals, the 2nd pin is a clock signal CLK terminal, the 3rd pin is a 5V DC voltage (DC5V) terminal, the 4th pin is a data signal DATA terminal, and the 5th pin is a reset signal RESET. , and the seventh pin is a terminal for a 12V DC voltage (DC12V).

The eighth to thirteenth pins are R, G, and B LED light emission drive currents (17-R6, 17- G6, 17-B6, 17-R7, 17-G7, 17B-7) input terminals.
This LED light emission drive current (17-R6, 17-G6, 17-B6, 17-R7, 17-G7, 17B-7) is passed directly from the 2nd pin to the 7th pin of the connector CN4C to another is supplied to the LED substrate in the handle on the downstream side of the .

That is, on the downstream side of the front frame LED connection board 500, an LED board (not shown) and an in-handle LED board are connected by connectors CN1C and CN4C, and an LED driver is mounted on the LED board. The LED driver operates using a clock signal CLK from the connector CN1C, a 5V DC voltage (DC5V), a data signal DATA, a reset signal RESET terminal, and a 12V DC voltage (DC12V) to drive the LEDs on the LED board. At the same time, LED emission drive currents (17-R6, 17-G6, 17-B6, 17-R7, 17-G7, 17B-7) for the LEDs of the LED board in the handle are also generated. The LED emission drive currents (17-R6, 17-G6, 17-B6, 17-R7, 17-G7, 17B-7) are relayed through the front frame LED connection board 500 and supplied to the LEDs of the LED board in the steering wheel. will be

It should be noted that each of the 2nd to 7th pins of the connector CN4C has is connected to Zener diodes D8C to D15C as a protection circuit.
A 12V DC voltage (DC12VB) is applied to the first pin of the connector CN4C, and power supply voltage is supplied to the LED board side in the handle (not shown).

Such a configuration is used so that two LED boards are connected downstream of the front frame LED connection board 500 and only one of them is provided with an LED driver.
That is, the front frame LED connection board 500 outputs a clock signal CLK, a 5V DC voltage (DC5V), a data signal DATA, a reset signal RESET, and a 12V DC voltage (DC12V) for the operation of the LED driver. Then, the LED light emission drive current from the LED driver is returned, relayed, and sent to the other LED substrate.

In this case, one LED driver is sufficient for driving the two downstream LED substrates. In particular, when light emission is controlled by a common LED drive control signal, it is sufficient to transmit the LED drive control signal only to one of the LED boards, which facilitates simplification of the wiring configuration. In other words, the clock signal CLK, the 5V DC voltage (DC5V), the data signal DATA, the reset signal RESET, and the 12V DC voltage (DC12V) need not be sent to both LED boards.
In addition, by relaying the LED light emission drive current (17-R6, 17-G6, 17-B6, 17-R7, 17-G7, 17B-7), a harness that transmits these between the two downstream LED boards becomes unnecessary.

The connector CN3C in FIG. 17 is connected to the transmission line end of the transmission line H9 connecting to the relay board 550 on the downstream side.
This connector CN3C has a 22-terminal configuration from the 1st pin to the 22nd pin as indicated by the numbers "1" to "22".

Five pins of the 1st pin, the 3rd pin, the 11th pin, the 13th pin, and the 18th pin are ground terminals.
The second pin is a terminal for a 5V DC voltage (DC5VB).
Three pins of the 5th pin, the 7th pin, and the 9th pin are terminals of a 12V DC voltage (DC12VB).

The 4th pin is assigned as the terminal for the serial data signal S_IN_DATAx, the 6th pin as the terminal for the load signal S_IN_LOAD, and the 8th pin as the terminal for the clock signal S_IN_CLK.

The 10th pin is the enable signal ENABLE_L, the 12th pin is the clear signal CLR_P, the 14th pin is the reset signal RESET_P, the 15th pin is the clock signal CLK_M, the 16th pin is the data signal DATA_P, the 17th pin is the reset signal RESET_M, and the 19th pin. A pin is assigned as a data signal DATA_M, a 20th pin is assigned as a drive general signal 1, a 21st pin is assigned as an enable signal ENABLE_M, and a 22nd pin is assigned as a drive general signal 2.

The connector CN7C in FIG. 18 is connected to a board (not shown) for detecting the cross key 15a, enter key 15b, volume button (not shown), light amount button and the like. This connector CN7C has a 9-terminal configuration of 1st to 9th pins indicated by "1" to "9". Sense signals SENS0 to SENS7, which are detection signals of operations of 15a and the like, are input.
The sense signals SENS0 to SENS7 of the 2nd to 9th pins are pulled up by a 5V DC voltage (DC5VB) via chip resistors RA3C and RA4C.

The connector CN9C is connected to a touch sensor (not shown) provided on the firing operation handle 15. As shown in FIG. This connector CN9C has a two-terminal configuration indicated by "1" and "2", the first pin receives the sense signal SENS14 from the touch sensor, and the second pin serves as a ground terminal.
The sense signal SENS14 is pulled up by a 5V DC voltage (DC5VB) via a resistor R26C.

The connector CN10C in FIG. 20 is connected to the transmission line end of the transmission line H15 connecting to the button LED connection board 640 in FIG.
This connector CN10C has 20 terminals from the 1st pin to the 20th pin marked with "1" to "20".

Five pins, 2nd pin, 4th pin, 12th pin, 13th pin, and 19th pin, are ground terminals.
The eighth pin is a terminal for a 5V DC voltage (DC5VB).
The sixth pin is a terminal for a 12V DC voltage (DC12VB).
The fifth pin and the seventh pin are terminals for a 12V motor drive voltage (MOT12V).

The 1st pin is the motor drive signal MOTφ/2, the 3rd pin is the motor drive signal MOTφ/1, the 9th pin is the motor drive signal MOTφ2, the 10th pin is the motor drive signal DCMOT3, and the 11th pin is the motor drive signal MOTφ1. Assigned as a terminal.

The 14th pin is assigned as the terminal for the clear signal CLR_L, the 16th pin as the terminal for the clock signal CLK_L, and the 18th pin as the terminal for the data signal DATA_L.
The 15th pin, 17th pin, and 20th pin are terminals to which sense signals SENS8, SENS9, and SENS11, which are detection signals from the downstream side, are input.
The sense signals SENS8, SENS9 and SENS11 are pulled up by a 5V DC voltage (DC5VB) via a chip resistor RA5C.

The power supply voltage in the front frame LED connection board 500 will be described.
On the front frame LED connection substrate 500, buffer circuits 501, 502, 503, 507 and 508, which are Schmitt trigger buffers containing eight circuits similar to the buffer circuit 402 described above with reference to FIG. Certain buffer circuits 504, 512, 513 are mounted.
A 5V DC voltage (DC5VB) supplied from the first pin of the connector CN2C is used as the power supply voltage for these.

As ICs, the parallel/serial (hereinafter referred to as "P/S") conversion circuits 505 and 506 shown in FIG. 18 are mounted. ) is used.

As an IC, the S/P conversion circuit 509 (LED driver) of FIG. 19 is mounted, and as the power supply voltage for this, the 12V DC voltage (DC12VB) supplied from the 27th to 30th pins of the connector CN2C is used. be done.

Motor drivers 510 and 511 shown in FIG. 19 are mounted as ICs, and these use a 12V motor drive voltage (MOT12V) and a 12V DC voltage (DC12VS) as power supply voltages.
A 12V motor drive voltage (MOT12V) is used as a power supply voltage for motor driving, and a 12V DC voltage (DC12VS) is used as a power supply voltage for motor drivers such as motor drivers 510 and 511 .

The 12V motor drive voltage (MOT12V) is separate from the 12V DC voltage (DC12VB). As shown in FIG. 15, a capacitor C11 is inserted between the 27th to 30th pins of the connector CN2C and the ground, and the anode side of a Schottky barrier diode D18C is connected to the positive side of the capacitor C11. there is A resistor R27C, capacitors C12C and C13C, and a chip varistor 515 are connected in parallel between the cathode side of the Schottky barrier diode D18C and the ground. This configuration isolates the 12V motor drive voltage (MOT12V) as an overvoltage protected power supply voltage.
That is, a power separation/protection circuit 520 is formed to separate the 12V motor drive voltage (MOT12V) from the 12V DC voltage (DC12VA).

The 12V DC voltage (DC12VS) is separated from the 12V DC voltage (DC12VB) by using the power separation/protection circuit 521 shown in FIG.

The flow of various signals in the front frame LED connection board 500 will be described below.
Clear signals CLR_L, CLR_M, clock signals CLK_L, CLK_M, data signals DATA_L, DATA_M, general-purpose output port signals (general-purpose signal HANYOU), and enable signal ENABLE_M are transmitted from the inner frame LED relay board 400 to the connector CN2C in FIG. It's coming.
These signals are input to terminals A1 to A8 of the buffer circuit 501 and signal-compensated.
Clear signals CLR_L and CLR_M supplied from the inner frame LED relay board 400 are shown as reset signals RESET_L and RESET_M in the front frame LED connection board 500 .

The clock signal CLK_L, the data signal DATA_L, and the reset signal RESET_L are signal-compensated by the buffer circuit 501 and then supplied to the buffer circuit 504 of FIG. 16 via the chip resistor RA1C. After being buffered, it is output from the connector CN1C to an LED board (not shown).

These clock signal CLK_L, general-purpose signal HANYOU, data signal DATA_L, and reset signal RESET_L signal-compensated by the buffer circuit 501 shown in FIG. supplied to The signal-compensated outputs of Y5, Y6, Y7 and Y8 terminals of the buffer circuit 502 are relayed from connector CN3C as clock signal CLK_P, enable signal ENABLE_L (from general-purpose signal HANYOU), data signal DATA_P, and reset signal RESET_P. Output to substrate 550 .

That is, signals for LED control and the like output from the upstream inner frame LED relay board 400 are signal-compensated by the buffer circuits 501 and 502 and transmitted to the downstream side after the relay board 550 .

The clock signal CLK_P is a constant voltage/protection circuit with a Zener diode D5C and a resistor R19C, the enable signal ENABLE_L is a constant voltage/protection circuit with a Zener diode D4C and a resistor R15C, and the data signal DATA_P is a constant voltage/protection circuit with a Zener diode D6C and a resistor R20C. The protection circuit and the reset signal RESET_P are output from the connector CN3C via a constant voltage/protection circuit consisting of a Zener diode D7C and a resistor R21C.

The clock signal CLK_L, the data signal DATA_L, and the reset signal RESET_L signal-compensated by the buffer circuit 501 in FIG. 15 are supplied to the buffer circuit 512 in FIG. After being amplified, they are output as a clock signal CLK_L, a data signal DATA_L, and a clear signal CLR_L (reset signal RESET_L) to the button LED connection board 640 from the connector CN10C.

Therefore, the signal for LED control output from the upstream inner frame LED relay board 400 is compensated by the buffer circuits 501 and 512 and transmitted to the downstream side after the button LED connection board 640. Become.

The clock signal CLK_L, data signal DATA_L, and general-purpose signal HANYOU_L signal-compensated by the buffer circuit 501 in FIG. 15 are supplied to the serial/parallel (S/P) conversion circuit 509 in FIG. This S/P conversion circuit 509 is configured using a chip as an LED driver. An LED driver is a device that outputs a light emission driving current according to a clock signal CLK_L and a data signal DATA_L. In this case, it is mainly used for serial/parallel conversion for motor driving. That is, the LED driver chip is used as part of the motor driving means.

The S/P conversion circuit 509 configured by the LED driver chip has output terminals LEDR1, LEDG1, LEDB1, . , in this case, seven output terminals LEDR1, LEDG1, LEDB1, LEDR2, LEDG2, LEDB2, and LEDR3 are used. The other output terminal is connected to ground as shown.
And the outputs of output terminals LEDR1, LEDG1, LEDB1, LEDR2, LEDG2, LEDB2, and LEDR3 (currents 23-R1, 23-G1, 23-B1, 23-R2, 23-G2, 23-B2, 23-R3) are After being buffered by the buffer circuit 508 , it is supplied to the input terminals IN 1 , IN 2 , IN 3 and IN 4 of the motor driver 510 and the input terminals IN 1 , IN 3 and IN 4 of the motor driver 511 .

In addition, output terminals LEDR1, LEDG1, LEDB1, LEDR2, LEDG2, LEDB2, and LEDR3 are designed to flow currents 23-R1, 23-G1, 23-B1, 23-R2, 23-G2, 23-B2, and 23-R3. are connected to a 5V DC voltage (DC5VB) through chip resistors RA6C and RA7C.

Motor driver 510 outputs motor drive signals MOT1-1, MOT1-/1, MOT1-2 and MOT1-/2 from output terminals OUT1, OUT2, OUT3 and OUT4 based on the signals of input terminals IN1, IN2, IN3 and IN4. Output.
The motor driver 511 outputs motor drive signals MOT3-1, MOT3-3 and MOT3-4 from output terminals OUT1, OUT3 and OUT4 based on signals of input terminals IN1, IN3 and IN4.

Motor drive signals MOT1-1, MOT1-/1, MOT1-2, MOT1-/2, MOT3-1 are supplied to connector CN10 of FIG. It is output to the button LED connection board 640 as MOTφ/2 and DCMOT3.
The motor drive signals MOT3-3 and MOT3-4 are supplied to the connector CN3C of FIG.

In the front frame LED connection board 500, the circuit system described above uses the clock signal CLK_L-, the data signal DATA_L-, and the general-purpose signal HANYOU_L- to generate motor drive signals for the downstream button LED connection board 640 and subsequent ones.

The clock signal CLK_M, data signal DATA_M, enable signal ENABLE_M, and clear signal CLR_M (reset signal RESET_M) input from the connector CN2C in FIG. are supplied to the A1 terminal, A3 terminal, A5 terminal and A7 terminal of the buffer circuit 503 of FIG. The signal-compensated outputs of Y1 terminal, Y3 terminal, Y5 terminal, and Y7 terminal of buffer circuit 503 are output from connector CN3C to relay board 550 as clock signal CLK_M, data signal DATA_M, enable signal ENABLE_M, and reset signal RESET_M. .

Therefore, signals for motor control from the inner frame LED relay board 400 upstream are compensated by the buffer circuits 501 and 503 and transmitted to the downstream side after the relay board 550 .

The clock signal CLK_M is a constant voltage/protection circuit with a Zener diode D12C and a resistor R22C, the enable signal ENABLE_M is a constant voltage/protection circuit with a Zener diode D16C and a resistor R24C, and the data signal DATA_M is a constant voltage/protection circuit with a Zener diode D14C and a resistor R23C. The protection circuit and the reset signal RESET_M are output from the connector CN3C through a constant voltage/protection circuit consisting of a Zener diode D17C and a resistor R25C.

A clock signal S_IN_CLK and a load signal S_IN_LOAD input from the connector CN2C in FIG. 15 are supplied to terminals A3 and A2 of the buffer circuit 502 in FIG. The signal-compensated outputs from the Y3 and Y2 terminals of the buffer circuit 502 are output from the connector CN3C to the relay board 550 as the clock signal S_IN_CLK and the load signal S_IN_LOAD.
Therefore, signals for serial data transmission are compensated by the buffer circuits 501 and 502 and transmitted to the downstream side after the relay board 550 .

The clock signal S_IN_CLK is output from the connector CN3C via a constant voltage/protection circuit consisting of a Zener diode D3C and a resistor R11C, and the load signal S_IN_LOAD is output via a constant voltage/protection circuit consisting of a Zener diode D2C and a resistor R9C.

A serial data signal S_IN_DATAx input from the connector CN3C of FIG. The signal-compensated output from the Y1 terminal of the buffer circuit 502 is input to the SI terminal (serial input terminal) of the P/S conversion circuit 505 in FIG.

A P/S conversion circuit 505 and a P/S conversion circuit 506 in the figure are CMOS 8-bit shift registers, have 8-bit parallel input/output, serial input, and serial output, and perform parallel-to-serial conversion of data. .
When P/S CONT pin = L, 8 pins from Q/D1 pin to Q/D8 pin become parallel output, and SI pin data is stored in each register at the rising edge of CK pin input waveform and Q/D1 pin ~ Output to Q/D8 pin. By setting the CLR/LOAD terminal to L, each register is reset asynchronously with the input of the CK terminal.
When P/S CONT terminal = H, 8 terminals from Q/D1 terminal to Q/D8 terminal become parallel input, and when CLR/LOAD terminal = L, Q/D1 terminal to Q/D8 terminal input asynchronously with CK terminal input. Data is stored in each register.

In the case of this example, the P/S conversion circuits 505 and 506 are applied with a 5V DC voltage (DC5VB) to the P/S CONT terminal so that the P/S CONT terminal is set to H, and the Q/D1 terminal to Q Eight terminals of the /D8 terminal are used for parallel input.
A clock signal S_IN_CLK and a load signal S_IN_LOAD input from the connector CN2C of FIG. That is, the clock signal S_IN_CLK is input to the CK terminal, and the load signal S_IN_LOAD is input to the CLR/LOAD terminal.

At the Q/D1 terminal to Q/D8 terminal, which are parallel input terminals of the P/S conversion circuit 505, the sense signal SENS8 is applied to the Q/D1 terminal, the sense signal SENS9 is applied to the Q/D2 terminal, and the sense signal SENS11 is applied to the Q/D4 terminal. , the sense signal SENS14 is input to the Q/D7 terminals.
The Q/D3, Q/D5, Q/D6 and Q/D8 terminals are grounded. That is, each input becomes "0" (L level).
The sense signals SENS8, SENS9, and SENS11 are input from the downstream button LED connection board 640 to the connector CN10C of FIG. It is the detection signal of the sensor.
A sense signal SENS14 is a detection signal of the touch sensor input from the connector CN9C of FIG.

The P/S conversion circuit 505 collectively converts the serial data signal S_IN_DATAx and the sense signals SENS8, SENS9, SENS11, and SENS14 input as described above into serial data, and outputs the serial data signal SDT1 from the Q8C terminal. This serial data signal SDT 1 is input to the SI terminal of the P/S conversion circuit 506 .

At the Q/D1 to Q/D8 terminals, which are parallel input terminals of the P/S conversion circuit 506, the sense signal SENS0 is applied to the Q/D1 terminal, the sense signal SENS1 is applied to the Q/D2 terminal, and the sense signal SENS2 is applied to the Q/D3 terminal. , the Q/D4 terminal receives the sense signal SENS3, the Q/D5 terminal receives the sense signal SENS4, the Q/D6 terminal receives the sense signal SENS5, the Q/D7 terminal receives the sense signal SENS6, and the Q/D8 terminal receives the sense signal SENS7.
These sense signals SENS0 to SENS7 are detection signals of the cross key 15a and the like input to the connector CN7C in FIG.
The sense signals SENS0 to SENS7 from the connector CN7C are signal-compensated by the buffer circuit 507 and input to the above terminals of the P/S conversion circuit 506. FIG.

As described above, the P/S conversion circuit 506 collectively converts the serial data signal SDT1 from the P/S conversion circuit 505 input to the SI terminal and the sense signals SENS0 to SENS7 into serial data, and outputs Q8 as the serial data signal SDT2. output from the terminal. This serial data signal SDT2 is input to the buffer circuit 513 via a filter comprising a resistor R35C and a capacitor C27C, and buffered. This output is transmitted upstream from the connector CN2C in FIG. 15 as the serial data signal S_IN_DATA from the front frame LED connection board 500 .

As described above, the front frame LED connection board 500 has the following configuration.
FIG. 21 shows clock signals CLK_L, CLK_M, clear signals CLR_L, CLR_M (reset signals RESET_L, RESET_M), data signals DATA_L, DATA_M, general-purpose signals HANYOU, and enable signals supplied from the upstream inner frame LED relay board 400 to the connector CN2C. The flow about ENABLE_M was summarized.

・Clock signal CLK_L, clear signal CLR_L (reset signal RESET_L), data signal DATA_L, and general-purpose signal HANYOU are output as clock signal CLK_P, reset signal RESET_P, data signal DATA_P, and enable signal ENABLE_L by connector CN3C via buffer circuits 501 and 502. sent downstream.
The clock signal CLK_L, clear signal CLR_L (reset signal RESET_L), and data signal DATA_L are transmitted downstream via the buffer circuit 504 from the connector CN1C as the clock signal CLK, reset signal RESET, and data signal DATA.
The clock signal CLK_L, clear signal CLR_L (reset signal RESET_L), and data signal DATA_L are transmitted downstream from the connector CN10C via the buffer circuit 512 as the clock signal CLK_L, clear signal CLR_L, and data signal DATA_L.
The clock signal CLK_L, the data signal DATA_L, and the general-purpose signal HANYOU are supplied to the S/P conversion circuit 509 and used to generate the motor drive current.

・The clock signal CLK_M, clear signal CLR_M (reset signal RESET_M), data signal DATA_M, and enable signal ENABLE_M are output as clock signal CLK_M, reset signal RESET_M, data signal DATA_M, and enable signal ENABLE_M by connector CN3C via buffer circuits 501 and 503. sent downstream.

・Motor drive signals MOTφ1, MOTφ/1, MOTφ2, MOTφ/2, and DCMOT3 are generated by the S/P conversion circuit 509, the buffer circuit 508, and the motor drivers 510 and 511, which are configured as motor drive means. sent to.

FIG. 22 summarizes the flow of the serial data signal S_IN_DATA, clock signal S_IN_CLK, load signal S_IN_LOAD, and sense signals SENS0 to SENS7, SENS8, SENS9, SENS11, and SENS14.

- The clock signal S_IN_CLK and the load signal S_IN_LOAD are transmitted downstream from the connector CN3C via the buffer circuit 502 .
- The clock signal S_IN_CLK and the load signal S_IN_LOAD are supplied to the P/S conversion circuits 505 and 506 via the buffer circuit 513 and used for parallel/serial conversion processing.

・The serial data signal S_IN_DATAx input to the connector CN3C from the downstream side is input to the P/S conversion circuit 505 via the buffer circuit 502, and the P/S conversion circuit 505 collects the sense signals SENS8, SENS9, SENS11, and SENS14. is converted to serial data and input to the P/S conversion circuit 506 as a serial data signal SDT1. Also, the sense signals SENS0 to SENS7 input to the connector CN7C from the downstream side are input to the P/S conversion circuit 506 via the buffer circuit 507. FIG. In the P/S conversion circuit 506, the serial data signal SDT1 from the P/S conversion circuit 505 and the sense signals SENS0 to SENS7 are combined into serial data, and the serial data signal SDT2 is output. This serial data signal SDT2 is transmitted as the serial data signal S_IN_DATA from the front frame LED connection board 500 to the upstream side from the connector CN2C via the buffer circuit 513 .

Further, the front frame LED connection board 500 has the following configuration.
・Relay the audio signal to the speaker and send it to the speaker unit.
・Receives 12V DC voltage (DC12VB) and 5V DC voltage (DC5VB) through connector CN2C and uses it as an operating power supply.
- The 12V motor drive voltage (MOT12V) and the 12V DC voltage (DC12VS) used to generate the motor drive signal are separated from the 12V DC voltage (DC12VB). 12V DC voltage (DC12VB) for LED and LED driver, 12V motor drive voltage (MOT12V) for motor drive, and 12V DC voltage (DC12VS) for motor driver. prevent
・12V DC voltage (DC12VB) and 5V DC voltage (DC5VB) are supplied to the downstream side as the operating power supply voltage.

15 to 20, the front frame LED connection board 500 includes resistors R1C, R2C . . . , chip resistors RA1C, RA2C . , C2C . . . , diodes (including Zener diodes and Schottky barrier diodes) D1C, D2C .
As a damping resistor for signal lines such as clear signals CLR_L, CLR_M, clock signals CLK_L, CLK_M, data signals DATA_L, DATA_M, general-purpose output port signals (general-purpose signal HANYOU), enable signal ENABLE_M, etc., a resistor is provided on the connector CN2C side of FIG. R8C, R10C, R12C, R13C, R14C, R16C, R17C and R18C are inserted, and chip resistors RA1C and RA2C are inserted. That is, the waveform is shaped by inserting damping resistors in the vicinity of the connector CN2C and before the signal branch.
Further, taps TP1C to TP14C are provided as shown in the figure and used for connection to required locations.
Although not shown in the drawings, a capacitor for reducing power supply noise or the like is appropriately arranged between the DC 5V or DC 12V power supply line and the ground.

[5.4 Relay board 550]

FIG. 23 shows the structure of the relay board 550. As shown in FIG. Connectors CN1D and CN2D are mounted on the relay board 550 .

The connector CN1D is connected to the transmission line end of the transmission line H9 connecting to the connector CN3C of the front frame LED connection board 500 in FIG.
Therefore, this connector CN1D has 22 terminals from the 1st pin to the 22nd pin as indicated by the numbers "1" to "22", and the terminal assignments are the same as those of the connector CN3C. Conductor points P1 and P2 on the housing of connector CN1D are also grounded for mounting strength.

The connector CN2D is connected to the transmission line end of the transmission line H10 connecting with the upper right LED board 600 of the side unit on the downstream side.
This connector CN2D has 20 terminals from the 1st pin to the 20th pin as indicated by the numbers "1" to "20".

Four pins of the 3rd pin, the 9th pin, the 11th pin, and the 16th pin are ground terminals.
The first pin is a terminal for a 5V DC voltage (DC5VB).
Two pins of the fifth pin and the seventh pin are terminals of a 12V DC voltage (DC12VB).

The second pin is assigned to the serial data signal S_IN_DATAx, the fourth pin to the load signal S_IN_LOAD, and the sixth pin to the clock signal S_IN_CLK.

The 8th pin is the enable signal ENABLE_L, the 10th pin is the clock signal CLK_P, the 12th pin is the reset signal RESET_P, the 13th pin is the clock signal CLK_M, the 14th pin is the data signal DATA_P, the 15th pin is the reset signal RESET_M, and the 17th pin is The pin is assigned as a data signal DATA_M, the 18th pin is assigned as a drive general signal 1, the 19th pin is assigned as an enable signal ENABLE_M, and the 20th pin is assigned as a drive general signal 2.

In this relay board 550, the 12V DC voltage (DC12VB) assigned to the 5th, 7th and 9th pins of the connector CN1D is applied to the 5th and 7th pins of the connector CN2D. , and forwarded to the downstream side.
In the connector CN1D, five terminals of the 1st pin, the 3rd pin, the 11th pin, the 13th pin, and the 18th pin are used as ground terminals. It has four terminals of the 16th pin.
This reduces the number of terminals of the connector CN2D on the downstream side.
Also, the connector CN1D and the connector CN2D are assumed to be of different types. The connector CN2D has a higher rated current per pin, so the number of power terminals and ground terminals of the connector CN2D can be reduced.
Further, the connector CN2D is easier to insert and remove than the connector CN1D, has thicker terminals, and has a larger housing.

[5.5 Side Unit Upper Right LED Board 600]

24, 25, 26, 27, 28 and 29, the side unit upper right LED board 600 will be described. These figures show separately the circuit configuration provided on the upper right LED board 600 of the side unit.

24, CN7E in FIG. 25, connectors CN2E and CN3E in FIG. 26, and connectors CN4E, CN5E and CN6E in FIG. 28 are mounted as connectors on the upper right LED board 600 of the side unit.

The connector CN1E in FIG. 24 is connected to the transmission line end of the transmission line H10 that connects with the connector CN2D of the relay board 550 in FIG.
Therefore, this connector CN1E has 20 terminals from the 1st pin to the 20th pin as indicated by the numbers "1" to "20", and the terminal assignments are the same as those of the connector CN2D.

The connector CN7E in FIG. 25 is connected to the sensor in the side unit device 101 shown in FIG. 10, and the sense signal SENS2X is input to the third pin. This sensor 101S is a sensor that detects a player's operation of the side unit device 101, for example. The sense signal SENS2X of the sensor 101S is pulled up by a 5V DC voltage (DC5V) via a resistor R64E.
A 12V DC voltage (DC12VB), which is the power supply voltage of the sensor 101S side of the side unit device 101, is applied to the first pin. The second pin serves as a ground terminal.

The connector CN2E in FIG. 26 is a six-terminal configuration connector to which the transmission line end of the transmission line H12 connecting with the LED board 630 on the side unit on the downstream side is connected.
The first to sixth pins of this connector CN2E are assigned as a ground terminal, a clock signal CLK terminal, a data signal DATA terminal, a reset signal RESET terminal, a ground terminal, and a 12V DC voltage (DC12VB) terminal. .

The connector CN3E is connected to the transmission line end of the transmission line H11 that connects with the lower right LED board 620 of the side unit on the downstream side.
This connector CN3E has 16 terminals from the 1st pin to the 16th pin as indicated by the numbers "1" to "16".

The first pin is a terminal for a 5V DC voltage (DC5VB).
The eighth pin and the thirteenth pin are ground terminals.
The 15th pin is a terminal for a 12V motor drive voltage (MOT12V). A Zener diode D11E is connected between the 15th pin and the ground as a protection circuit.

2nd pin is clock signal CLK, 3rd pin is sense signal SENS1X, 4th pin is data signal DATA, 5th pin is sense signal SENS_A, 6th pin is reset signal RESET, 7th pin is sense signal SENS_B, 9th pin is A pin is assigned as each terminal of the sense signal SENS_C.
As shown in FIG. 25, the sense signal SENS1X is pulled up by a 5V DC voltage (DC5V) via a resistor R13E.
The sense signal SENS_A, the sense signal SENS_B, and the sense signal SENS_C are also pulled up by a 5V DC voltage (DC5V) through resistors R29E, R27E, and R21E, respectively.

The connector CN3E in FIG. 26 has a motor drive signal MOT1-/2 for the 10th pin, a motor drive signal MOT1-/1 for the 12th pin, a motor drive signal MOT1-2 for the 14th pin, and a motor drive signal MOT1-2 for the 16th pin. Assigned as each terminal of MOT1-1.
Zener diodes D10E, D12E, D13E and D14E are connected as protective circuits between the tenth, twelfth, fourteenth and sixteenth pins and the ground, respectively.

The connector CN4E in FIG. 28 is connected to the side unit upper right movable object motor 104 (see FIG. 10). The connector CN4E has a first pin for a 12V motor drive voltage (MOT12V) terminal and a second pin for a vibration control signal L_VIB.

The connector CN5E is connected to the side unit upper right movable solenoid 105 (see FIG. 10). The connector CN5E has a first pin for a 12V motor drive voltage (MOT12V) terminal and a second pin for a solenoid control signal L_SOL_01.

Connector CN6E is connected to blower 106 (see FIG. 10) on the side unit. The connector CN6E has a first pin for a 12V motor drive voltage (MOT12V) terminal and a second pin for a blower control signal L_BRO.

The conductor points P1 and P2 on the housings of the connectors CN2E, CN3E, CN4E, CN5E, CN6E and CN7E are grounded for mounting strength.

The power supply voltage at the upper right LED board 600 of the side unit will be described.
Buffer circuit 601 in FIG. 25, buffer circuit 604 in FIG. 26, and buffer circuit 607 in FIG. 28 are mounted as ICs on the upper right LED board 600 of the side unit. These are 8-circuit Schmitt trigger buffers similar to the buffer circuit 402 previously described in FIG.
A 5V DC voltage (DC5V) is used as the power supply voltage for these. The 5V DC voltage (DC5V) is the positive side voltage of the capacitor C1E via the fuse F1E with respect to the 5V DC voltage (DC5VB) supplied from the first pin of the connector CN1E in FIG.

As ICs, the P/S conversion circuits 602 and 603 of FIG. 25 are mounted, and the power supply voltage for these is also a 5 V DC voltage (DC 5 V). P/S conversion circuits 602 and 603 are ICs similar to P/S conversion circuit 505 in FIG.

As ICs, an LED driver 605 in FIG. 27 and an S/P conversion circuit (LED driver) 606 in FIG. 28 are mounted. A direct current voltage (DC12VB) is used.
In this case, the 12V DC voltage (DC12VB) is taken out from the 5th and 7th pins of the connector CN1E in FIG. 24 as the voltage on the positive electrode side of the capacitor C2E via the fuse F2E.

Motor drivers 608 and 609 in FIG. 28 are mounted as ICs, and these use a 12V motor drive voltage (MOT12V) and a 12V DC voltage (DC12VS) as power supply voltages.

The 12V motor drive voltage (MOT12V) is separate from the 12V DC voltage (DC12VB).
As shown in FIG. 29, the anode side of the Schottky barrier diode D8E is connected to the 12V DC voltage (DC12VB) line. A resistor R23E, capacitors C10E and C11E, and a chip varistor 611 are connected in parallel between the cathode side of the Schottky barrier diode D8E and the ground. This configuration isolates the 12V motor drive voltage (MOT12V) as an overvoltage protected power supply voltage.
The 12V DC voltage (DC12VS) is separated from the 12V DC voltage (DC12VB) using a circuit consisting of a diode D7E, a resistor R17E, and a capacitor C8E, as shown in the figure.

The flow of various signals in the upper right LED board 600 of the side unit will be described below.
A load signal S_IN_LOAD, a clock signal S_IN_CLK, an enable signal ENABLE_L (reset signal RESET_M), a clock signal CLK_P, a reset signal RESET_P, and a data signal DATA_P are input to the connector CN1E of FIG. 25 through resistors R66E, R9E, R11E, and R12E for signal compensation.
24, resistor R3E and Zener diode D2E, resistor R6E and Zener diode D3E, resistor R66E and Zener diode D15E, resistor R9E and Zener diode D6E, resistor R11E and Zener diode D5E. , a resistor R12E and a Zener diode D15E.

The clock signal CLK_P, the data signal DATA_P, and the reset signal RESET_P are signal-compensated by the buffer circuit 601, output as the clock signal CLK_A, the data signal DATA_A, and the reset signal RESET_A, and input to the buffer circuit 604 in FIG. In this case, the clock signal CLK_A is input to terminals A1 and A5, the data signal DATA_A is input to terminals A2 and A6, and the reset signal RESET_A is input to terminals A3 and A7.
The buffered signals output from terminals Y1, Y2, and Y3 are output as clock signal CLK, data signal DATA, and reset signal RESET from connector CN2E via damping resistors R18E, R19E, and R20E.
The buffered signals output from terminals Y5, Y6, and Y7 are output as clock signal CLK, data signal DATA, and reset signal RESET from connector CN3E via damping resistors R24E, R25E, and R26E.

That is, the clock signal CLK_A, the data signal DATA_A, and the reset signal RESET_A shown in FIG. 26 are each branched into two systems before being input to the buffer circuit 604, and buffered respectively. After that, they are output as a clock signal CLK, a data signal DATA, and a reset signal RESET from connectors CN2E and CN3E to separate boards. Therefore, the buffer circuit 604 performs buffer processing while branching to two systems, and appropriate buffer processing can be performed after each branch.
The clock signal CLK, data signal DATA, and reset signal RESET output from the connectors CN2E and CN3E are originally the clock signal CLK_P, the data signal DATA_P, and the reset signal RESET_P input from the connector CN1E in FIG. . After being buffered by the buffer circuit 601 in FIG. 25 as described above, these signals are output as the clock signal CLK_A, the data signal DATA_A, and the reset signal RESET_A, and branched into two systems at the stage of the buffer circuit 604 in FIG. . In other words, buffer processing is performed before branching, so that attenuation in the transmission line up to that point is compensated for and branched. Stable signal supply is realized when a common signal is distributed to two boards.

The clock signal CLK_A, data signal DATA_A, and reset signal RESET_A output from the buffer circuit 601 in FIG. 25 are also supplied to the LED driver 605 in FIG.
The LED driver 605 outputs a light emission drive current according to the clock signal CLK_A, data signal DATA_A, and reset signal RESET_A.
The LED driver 605 has output terminals LEDR1, LEDG1, LEDB1, . 14 terminals of LEDB1, LEDR2, LEDG2, LEDB2, LEDR3, LEDG3, LEDB3, LEDR4, LEDG4, LEDB4, LEDR5 and LEDG5 are used. The other output terminal is connected to ground as shown.

The output terminals LEDR1, LEDG1, LEDB1, LEDR2, LEDG2, LEDB2, LEDR3, LEDG3, LEDB3, LEDR4, LEDG4, LEDB4, LEDR5, and LEDG5 are connected to 14 LED circuits formed as the light emitting section 612, respectively. The light emission drive current (25-R1, 25-G1, 25-B1...25-R5, 25-G5, 25-B5) is applied.
The LED circuit of each system of the light emitting unit 612 is composed of two or three LEDs (LED1, LED2, . . . ) connected in series and resistor elements, as shown in the drawing. The LED circuits of each system are arranged in parallel, and a 12V DC voltage (DC12VB) is applied to each anode side.

In this configuration, the clock signal CLK_P, the data signal DATA_P, and the reset signal RESET_P input from the connector CN1E of FIG. 24 are buffered by the buffer circuit 601 of FIG. 25 and branched. The buffered clock signal CLK_A, data signal DATA_A, and reset signal RESET_A are supplied to the LED driver 605 of FIG. 27 as one branch. The other branched signal is supplied to the buffer circuit 604 of FIG. 26, further branched, and transmitted to the downstream board from the connectors CN2E and CN3E after buffer processing.
In this case, the signal for light emission drive control is buffered by the buffer circuit 601 and then branched for transmission to the LED driver and the downstream board. is becoming

Also, the clock signal CLK_A, the data signal DATA_A, and the reset signal RESET_M output from the buffer circuit 601 in FIG. 25 are supplied to the S/P conversion circuit 606 in FIG.
This S/P conversion circuit 606 is configured using a chip as an LED driver. An LED driver is a device that outputs a light emission driving current according to a clock signal CLK_L and a data signal DATA_L. In this case, it is mainly used for serial/parallel conversion for motor driving. That is, the LED driver chip is used as part of the motor driving means.

The S/P conversion circuit 606 configured by the LED driver chip is a device that outputs a light emission drive current according to the clock signal CLK_A, the data signal DATA_A, and the reset signal RESET_M. It functions as a serial/parallel conversion circuit. The S/P conversion circuit 606 has output terminals LEDR1, LEDG1, LEDB1, . , LEDB1, LEDR2, LEDG2, LEDB2, LEDR3, and LEDG3. The other output terminal is connected to ground as shown.
And the outputs of output terminals LEDG1, LEDB1, LEDR2, LEDG2, LEDB2, LEDR3, LEDG3 (current 30-G1, 30-B1, 30-R2, 30-G2, 30-B2, 30-R3, 30-G3) are After being buffered by the buffer circuit 607 , they are supplied to the input terminals IN 2 , IN 3 and IN 4 of the motor driver 608 and the input terminals IN 1 , IN 2 , IN 3 and IN 4 of the motor driver 609 .

The output terminals LEDG1, LEDB1, LEDR2, LEDG2, LEDB2, LEDR3, and LEDG3 are connected to a 5V DC voltage (DC5V) through resistors R60E, R61E, R62E, R56E, R57E, R58E, and R59E. This is because currents 30-G1, 30-B1, 30-R2, 30-G2, 30-B2, 30-R3, and 30-G3 are caused to flow using a 5V DC voltage (DC5V) as a power source.

A motor driver 608 outputs a blower control signal L_BRO, a solenoid control signal L_SOL01, and a vibration control signal L_VIB from output terminals OUT2, OUT3, and OUT4 based on signals from input terminals IN2, IN3, and IN4. These blower control signal L_BRO, solenoid control signal L_SOL01, and vibration control signal L_VIB are supplied to connectors CN6E, CN5E, and CN4E, respectively.

Motor driver 609 outputs motor drive signals MOT1-1, MOT1-2, MOT1-/1 and MOT1-/2 from output terminals OUT1, OUT2, OUT3 and OUT4 based on the signals of input terminals IN1, IN2, IN3 and IN4. Output. These motor drive signals MOT1-1, MOT1-2, MOT1-/1, MOT1-/2 are supplied to connector CN3E in FIG.
Therefore, the circuit from the LED driver 605 to the motor driver 609 forms a circuit system in the side unit upper right LED board 600 that generates a motor drive signal for the side unit lower right LED board 620 on the downstream side.

The load signal S_IN_LOAD and the clock signal S_IN_CLK input from the connector CN1E in FIG. 24 are signal-compensated in the buffer circuit 601 in FIG. It is input to the CLR/LOAD pin and CK pin, and controls parallel/serial conversion processing.
In the P/S conversion circuits 602 and 603, the P/S CONT terminal is set to H by applying a 5V DC voltage (DC5V) to the P/S CONT terminal, and the 8 terminals from Q/D1 terminal to Q/D8 terminal A terminal is a parallel input.

At the Q/D1 terminal to Q/D8 terminal, which are parallel input terminals of the P/S conversion circuit 603, the sense signal SENS_C is applied to the Q/D1 terminal, the sense signal SENS_B is applied to the Q/D2 terminal, and the sense signal SENS_A is applied to the Q/D4 terminal. , the sense signal SENS1X is input to the Q/D4 terminal, and the sense signal SENS2X is input to the Q/D5 terminal.
The Q/D6, Q/D7 and Q/D8 terminals are grounded.
Sense signals SENS_A, SENS_B, SENS_C, and SENS1X are input from connector CN3E. Sense signal SENS2X is input from connector CN7E.

The P/S conversion circuit 603 collectively converts the sense signals SENS_A, SENS_B, SENS_C, SENS1X, and SENS2X input as described above into serial data (serial data signal SDT3) and outputs the serial data from the Q8C terminal. This serial data signal SDT3 is input to the SI terminal of the P/S conversion circuit 602 .

In the Q/D1 terminal to Q/D8 terminal, which are parallel input terminals of the P/S conversion circuit 602, a 5V DC voltage (DC5V) is applied to the Q/D1 terminal, Q/D2 terminal, and Q/D8 terminal. is connected to ground.
The P/S conversion circuit 602 combines the serial data signal SDT3 from the P/S conversion circuit 603 input to the SI terminal and the logic (H/L) of the Q/D1 to Q/D8 terminals into serial data (serial data). It is converted into a data signal SDT4) and output from the Q8 terminal. This serial data signal SDT4 is input to the buffer circuit 601 and buffered. This output is transmitted upstream from connector CN1E via damping resistor R1E in FIG. 24 as serial data signal S_IN_DATAx from upper right LED board 600 of the side unit.

As described above, the side unit upper right LED board 600 has the following configuration.
- An enable signal ENABLE_L (reset signal RESET_M), a clock signal CLK_P, a reset signal RESET_P, and a data signal DATA_P are input, and the buffer circuit 601 performs buffer processing on these. The buffered signal is used for LED light emission, used for generating a motor drive signal, or transferred to the downstream side.

- The clock signal S_IN_CLK and the load signal S_IN_LOAD are supplied to the P/S conversion circuits 602 and 603 via the buffer circuit 601 and used for parallel/serial conversion processing.
・The various sense signals SENS_A, SENS_B, SENS_C, SENS1X, and SENS2X are collectively converted into serial data to generate the serial data signal S_IN_DATAx. This serial data signal S_IN_DATAx is transmitted upstream. As described above, this serial data signal S_IN_DATAx is converted into serial data together with the sense signals SENS8, SENS9, SENS11, and SENS1 in the front frame LED connection board 500, and converted to the serial data signal S_IN_DATA so that the inner frame LED relay board 400 can It will be transmitted to the production control board 30 via.

・Receives 12V DC voltage (DC12VB) and 5V DC voltage (DC5VB) through connector CN1E and uses it as an operating power supply.
- The 12V motor drive voltage (MOT12V) and the 12V DC voltage (DC12VS) used to generate the motor drive signal are separated from the 12V DC voltage (DC12VB).
・12V DC voltage (DC12VB) and 5V DC voltage (DC5VB) are supplied to the downstream side as the operating power supply voltage.

24 to 29, resistors R1E, R2E . . . , capacitors C1E, C2E . ) are connected to electronic elements such as D1E, D2E, and so on.
Also, as shown in the figure, taps TP1E, TP2E, .
Although not shown in the drawings, a capacitor for reducing power supply noise or the like is appropriately arranged between the DC 5V or DC 12V power supply line and the ground.

[5.6 Side unit lower right LED board 620]

The side unit lower right LED board 620 will be described with reference to FIGS. 30 and 31. FIG. These figures show separately the circuit configuration provided on the lower right LED board 620 of the side unit.

As connectors, connectors CN1F, CN3F, and CN4F in FIG. 30 and connector CN2F in FIG. 31 are mounted on the lower right LED board 620 of the side unit.

The connector CN3F in FIG. 30 is connected to the transmission line end of the transmission line H11 that connects with the connector CN3E of the upper right LED board 600 of the side unit in FIG.
Therefore, this connector CN3F has 16 terminals from the 1st pin to the 16th pin as indicated by the numbers "1" to "16", and the terminal assignments are the same as those of the connector CN3E.

The connector CN1F is connected to the side unit lower right movable object motor 103 shown in FIG.
A 12V motor drive voltage (MOT12V) is applied to the third and fourth pins. Motor drive signals MOT1-/2, MOT1-/1, MOT1-2 and MOT1-1 input from the connector CN3F are output from the first, second, fifth and sixth pins.

The connector CN4F is connected to the side unit lower right movable object position detection switch 102 shown in FIG.
The first pin is a 12V DC voltage (DC12VB), and the second pin is a ground terminal. A third pin serves as an input terminal for the sense signal SENS1X from the connected position detection switch.

The connector CN2F in FIG. 31 is connected to an LED board (not shown) arranged on the side unit 10. As shown in FIG. The first pin is a terminal for a 12V DC voltage (DC12VB). The 2nd to 5th pins are terminals for light emission driving signals.

The conductor points P1 and P2 in the housings of the connectors CN1F, CN2F, CN3F and CN4F are grounded for mounting strength.

The power supply voltage at the lower right LED board 620 of the side unit will be described.
Photocouplers PC1F, PC2F, and PC3F are mounted on the lower right LED board 620 of the side unit.
A 5V DC voltage (DC5V) is used as the power supply voltage for these. A 5V DC voltage (DC5V) is supplied from the first pin of connector CN3F.

The LED driver 621 of FIG. 31 is mounted as an IC on the lower right LED board 620 of the side unit, and the 12V DC voltage (DC12VB) supplied from the 11th pin of the connector CN1E is used as the power supply voltage for this. .
Also, the 12V motor drive voltage (MOT12V) output from the connector CN1F in FIG. 30 is supplied from the 15th pin of the connector CN3F.

The flow of various signals in the side unit lower right LED board 620 will be described.
A clock signal CLK, a data signal DATA, and a reset signal RESET are input to the connector CN3F from the upper right LED board 600 of the side unit, and these signals are supplied to the LED driver 621 in FIG.
The LED driver 621 outputs a light emission drive current according to the clock signal CLK, data signal DATA, and reset signal RESET.

The LED driver 621 has output terminals LEDR1, LEDG1, LEDB1, . 12 terminals LEDB1, LEDR2, LEDG2, LEDB2, LEDR3, LEDG3, LEDB3, LEDR4, LEDG4, and LEDB4 are used to drive LED light emission. Also, an LED board (not shown) connected to the connector CN2F is driven to emit light using four output terminals LEDR7, LEDG7, LEDB7, and LEDR8. The other output terminal is connected to ground as shown.

The output terminals LEDR1, LEDG1, LEDB1, LEDR2, LEDG2, LEDB2, LEDR3, LEDG3, LEDB3, LEDR4, LEDG4, and LEDB4 are connected to the 12 LED circuits formed as the light emitting unit 622, respectively, and the light emission drive current ( 27-R1, 27-G1, 27-B1 ... 27-R4, 27-G4, 27-B4).
Each system of the LED circuit of the light emitting unit 622 is composed of one or three LEDs connected in series and a resistance element, as shown. The LED circuits of each system are arranged in parallel, and a 12V DC voltage (DC12VB) is applied to each anode side.
The output terminals LEDR7, LEDG7, LEDB7, and LEDR8 are connected to four systems of the light emission driving section 623. FIG. The light emission driving section 623 outputs four systems of light emission drive currents (27-R7, 27-G7, 27-B7 . . . 27-R8) from the connector CN2F.

Sense signals SENS_A, SENS_B, and SENS_C are obtained by photocouplers PC1F, PC2F, and PC3F in FIG. These are transmitted to the side unit upper right LED board 600 from the connector CN3F.
A sense signal SENS1X obtained from the connector CN4F is also transmitted to the upper right LED board 600 of the side unit from the connector CN3F.
These sense signals SENS_A, SENS_B, SENS_C, and SENS1X are serialized as described above.

In the side unit lower right LED board 620, as shown in FIGS. 30 and 31, electronic elements such as resistors R1F, R2F, . is connected.
Also, as shown in the figure, taps TP1F, TP2F, .

[5.7 LED board 630 on the side unit]

The side unit upper LED board 630 will be described with reference to FIG.
A connector CN1T is mounted on the LED board 630 on the side unit.
The connector CN1T is connected to the transmission line end of the transmission line H12 connecting to the connector CN2E of the upper right LED board 600 of the side unit in FIG.

Therefore, this connector CN1T has a six-terminal configuration from the first pin to the sixth pin as indicated by the numbers "1" to "6", and the terminal assignments are the same as those of the connector CN2E.
The conductor points P1 and P2 on the housing of the connector CN1T are grounded for mounting strength.

An LED driver 631 is mounted as an IC on the side unit LED board 630, and a 12V DC voltage (DC12VB) supplied from the 6th pin of the connector CN1T is used as the power supply voltage for this.

The flow of various signals will be described.
A clock signal CLK, a data signal DATA, and a reset signal RESET are input to the connector CN1T from the upper right LED board 600 of the side unit, and these signals are supplied to the LED driver 631 .
The LED driver 631 outputs a light emission drive current according to the clock signal CLK, data signal DATA, and reset signal RESET.

The LED driver 631 has output terminals LEDR1, LEDG1, LEDB1, . Nine terminals of LEDB1, LEDR2, LEDG2, LEDB2, LEDR3, LEDG3, and LEDB3 are used to drive LED light emission. The other output terminal is connected to ground as shown.

The output terminals LEDR1, LEDG1, LEDB1, LEDR2, LEDG2, LEDB2, LEDR3, LEDG3, and LEDB3 are connected to the nine LED circuits formed as the light emitting section 632, respectively, and the light emission driving currents (27-R1, 27- G1, 27-B1 ... 27-R3, 27-G3, 27-B3) flow.
Each system of the LED circuit of the light emitting unit 632 is composed of two LEDs connected in series and a resistance element, as shown in the drawing. The LED circuits of each system are arranged in parallel, and a 12V DC voltage (DC12VB) is applied to each anode side.

In the side unit LED board 630, as shown in FIG. 32, electronic elements such as resistors R1T, R2T, . . . , capacitors C1T, C2T, . .
Also, as shown in the figure, taps TP1T, TP2T, .

[5.8 Button LED connection board 640]

The button LED connection board 640 will be explained using FIG.
Connectors CN1G, CN2G, CN3G, CN4G, CN5G, CN6G, and CN8G are mounted on the button LED connection board 640 as connectors.

The connector CN1G is connected to the transmission line end of the transmission line H15 connecting to the connector CN10C of the front frame LED connection board 500 in FIG.
Therefore, this connector CN1E has 20 terminals from the 1st pin to the 20th pin as indicated by the numbers "1" to "20", and the terminal assignments are the same as those of the connector CN10C.

Connector CN2G is connected to the transmission line end of transmission line H16 connecting button LED board 660 shown in FIG.
A 12V DC voltage (DC12VB), which is the power supply voltage of the button LED board 660, is applied to the third pin and the seventh pin. The first pin and the sixth pin are ground terminals.
A second pin, a fourth pin, and a fifth pin are terminals for a clock signal CLK, a data signal DATA, and a reset signal RESET, respectively.

Connector CN3G is connected to a motor (not shown).
The motor drive signals MOTφ1, MOTφ/1, MOTφ2 and MOTφ/2 input from the connector CN1G are output from the 6th, 2nd, 5th and 1st pins of the connector CN3G.
Also, the 12V motor drive voltage (MOT12V) input from the connector CN1G is applied to the third and fourth pins as the illustrated 12V motor drive voltage (MOT12VA).

The connector CN4G is connected to a vibration device (not shown). A 12 V motor drive voltage (MOT12VA) is applied to the first pin as a power supply voltage for the vibrating device, and a motor drive signal DCMOT3 input from the connector CN1G is output to the second pin as a drive signal for the vibrating device. A DC motor is used for the vibration device.

The connector CN5G is connected to a push button sensor inside the effect button 13.
The first pin is a 12V DC voltage (DC12VB), and the second pin is a ground terminal. A third pin serves as an input terminal for the sense signal SENS8 from the connected push button sensor.

Connector CN6G is connected to a rotation origin sensor.
The first pin is a 12V DC voltage (DC12VB), and the third pin is a ground terminal. The second pin serves as an input terminal for the sense signal SENS9 from the connected rotation origin sensor.

A connector CN8G is connected to a rotating effect light sensor.
The first pin is a 12V DC voltage (DC12VB), and the third pin is a ground terminal. The second pin serves as an input terminal for the sense signal SENS11 from the connected rotation effect light sensor.

The conductor points P1 and P2 on the housings of the connectors CN1G, CN2G, CN3G, CN4G, CN5G, CN6G and CN8G are grounded for mounting strength.

A buffer circuit 641 is mounted on the button LED connection board 640 . A 5V DC voltage (DC5V) is used as the power supply voltage for this. A 5V DC voltage (DC5V) is supplied from pin 8 of connector CN1G.

The flow of various signals in the button LED connection board 640 will be described.
The clock signal CLK_L, clear signal CLR_L, and data signal DATA_L supplied from the upstream front frame LED connection board 500 to the connector CN1G are input to the buffer circuit 641 via the chip resistor RA1G and buffered. Then, it is sent to the connector CN2G via the chip resistor RA2G and sent to the button LED board 660 downstream.
A capacitor C1G is inserted between the 5V DC voltage (DC5V) of the buffer circuit 641 and the ground.

Although not shown, in the button LED connection board 640, a capacitor for reducing power supply noise and the like is appropriately arranged between the DC 5V or DC 12V power supply line and the ground.

[5.9 Button LED board 660]

The button LED board 660 will be described with reference to FIGS. 34 and 35. FIG. These figures show separately the circuit configuration provided on the button LED board 660 .

The connector CN1H of FIG. 34 is mounted on the button LED board 660. FIG.
The connector CN1H is connected to the transmission line end of the transmission line H16 connecting to the connector CN2G of the button LED connection board 640 in FIG.
Therefore, this connector CN1H has seven terminals from the first pin to the seventh pin as indicated by the numbers "1" to "7", and the terminal assignments are the same as those of the connector CN2G.
Also, the conductor points P1 and P2 on the housing of the connector CN1H are grounded for mounting strength.

A 12V DC voltage (DC12VB) is supplied to the button LED board 660 as a power supply voltage input to the connector CN1H.
The LED driver 661 of FIG. 34 and the LED driver 663 of FIG. 35 are mounted as ICs on the button LED board 660, and a 12V DC voltage (DC12VB) is used as the power supply voltage for these.
A 12V DC voltage (DC12VB) is also used as the power supply voltage for the light emitting units 664 and 662 .

The flow of various signals in the button LED board 660 will be described.
A clock signal CLK, a data signal DATA, and a reset signal RESET are input to the connector CN1H from the upper right LED board 600 of the side unit, and these signals are supplied to the LED driver 661 via the chip resistor RA1H in FIG.
The LED driver 661 outputs a light emission drive current according to the clock signal CLK, data signal DATA, and reset signal RESET.

The LED driver 661 uses output terminals LEDR1, LEDG1, LEDB1, .
That is, the output terminals LEDR1, LEDG1, LEDB1, . -B1・・・19-R8, 19-G8, 19-B8) flow.
The LED circuit of each system of the light emitting unit 662 is composed of two or three LEDs connected in series and a resistance element, as shown in the drawing. The LED circuits of each system are arranged in parallel, and a 12V DC voltage (DC12VB) is applied to each anode side.

The clock signal CLK, data signal DATA, and reset signal RESET are also supplied to the LED driver 663 in FIG.
The LED driver 663 performs LED light emission drive of six systems using three terminals each of output terminals LEDR1, LEDG1, LEDB1, .
That is, the output terminals LEDR1, LEDG1, LEDB1, . -B1・・・20-R6, 20-G6, 20-B6) flow.
The LED circuit of each system of the light emitting unit 664 is composed of two or three LEDs connected in series and a resistance element, as shown. A Zener diode is connected in parallel with each LED. The LED circuits of each system are arranged in parallel, and a 12V DC voltage (DC12VB) is applied to each anode side.

In the side unit lower right LED board 620, resistors R1H, R2H . . . , capacitors C1H, C2H . Electronic elements such as D1H, D2H, etc. (including diodes) are connected.
Also, as shown in the figure, taps TP1H, TP2H, .

[5.10 LED connection board 700]

Next, the board arranged on the game board 3 side will be explained.
First, the LED connection substrate 700 will be described with reference to FIGS. 36, 37, 38, 39, 40 and 41. FIG. These figures show the circuit configuration provided on the LED connection substrate 700 separately.
The LED connection board 700 is a board connected to the effect control board 30 in the game board 3, as shown in FIG.

36, connectors CN5J and CN6J in FIG. 37, connectors CN2J, CN3J, CN4J and CN12J in FIG. 38, connector CN10J in FIG. 39, connectors CN7C and CN11J in FIG. 41 connectors CN8J and CN9J are mounted.

The connector CN1J in FIG. 36 is connected to the transmission line end of the transmission line H20 that connects with the effect control board 30 as shown in FIG.
This connector CN1J has 40 terminals from the 1st pin to the 40th pin as indicated by the numbers "1" to "40".

1st pin, 2nd pin, 8th pin, 9th pin, 10th pin, 16th pin, 18th pin, 19th pin, 20th pin, 22nd pin, 29th pin, 31st pin of connector CN1J , 32nd, 33rd, 34th, 39th and 40th pins are grounded.
The 4th pin and the 6th pin are terminals for a 5V DC voltage (DC5VB).
The 12th pin, the 14th pin, the 24th pin, the 26th pin, the 28th pin, and the 30th pin are terminals for a 12V DC voltage (DC12VB).
The 11th, 17th, 35th and 37th pins are unused.

The third pin is assigned to the clock signal P_S_IN_CLK, the fifth pin to the serial data signal P_S_IN_DATA, and the seventh pin to the load signal P_S_IN_LOAD.
The serial data signal P_S_IN_DATA is serial data transmitted from the LED connection board 700 to the effect control board 30, and the clock signal P_S_IN_CLK and the load signal P_S_IN_LOAD are supplied from the effect control board 30 for transmitting the serial data signal P_S_IN_DATA. is a signal.

The 13th pin is assigned as a terminal for the clock signal P_S_OUT_CLK, and the 15th pin is assigned as a terminal for the serial data signal P_S_OUT_DATA.
The serial data signal P_S_OUT_DATA is serial data transmitted from the performance control board 30 together with the clock signal P_S_OUT_CLK.

The 21st pin is the clear signal M_S_CLR (reset signal RESET_M), the 23rd pin is the clock signal M_S_OUT_CLK (clock signal CLK_M), the 25th pin is the serial data signal M_S_OUT_DATA (serial data signal DATA_M), and the 27th pin is the enable signal M_S_ENABLEP (latch signal LATCH_M).
The serial data signal M_S_OUT_DATA is serial data transmitted from the performance control board 30 together with the clock signal M_S_OUT_CLK.

Conductor points P1 and P2 on the housing of connector CN1J and connectors CN2J, CN4J, CN5J, CN6J, CN7J, CN8J, CN9J, CN10J, CN11J, and CN12J, which will be described later, are grounded for mounting strength.

A connector CN5J in FIG. 37 is connected to a motor of a movable object (not shown). A 18V DC voltage (MOT18VA), which is the power supply voltage of the motor, is applied to the third pin and the fourth pin.
The 1st pin is assigned to the motor drive signal MOT6-/2, the 2nd pin to the motor drive signal MOT6-/1, the 5th pin to the motor drive signal MOT6-2, and the 6th pin to the motor drive signal MOT6-1. It is

The connector CN6J in FIG. 37 is also connected to a motor of another movable object (not shown). A 18V DC voltage (MOT18VA), which is the power supply voltage of the motor, is applied to the third pin and the fourth pin.
The 1st pin is assigned to the motor drive signal MOT7-/2, the 2nd pin to the motor drive signal MOT7-/1, the 5th pin to the motor drive signal MOT7-2, and the 6th pin to the motor drive signal MOT7-1. It is

The connector CN2J in FIG. 38 is connected to the position detection switch of the character. A 12V DC voltage (DC12VB) is applied to the first pin as a power supply voltage on the side of the position detection switch. Let the 3rd pin be a ground terminal.
The second pin of the connector CN2J receives, for example, the sense signal SENSv0, which is the detection signal of the bottom-rear movable object right position detection switch 121 (see FIG. 10). The sense signal SENSv0 is pulled up by a 5V DC voltage (DC5V) via a resistor R5J.

The connector CN4J is also connected to the position detection switch of the accessory, the first pin is a 12V DC voltage (DC12VB) terminal serving as the power supply voltage of the position detection switch, and the third pin is a ground terminal.
For example, the sense signal SENSv1, which is the detection signal of the bottom-rear movable object left position detection switch 125 (see FIG. 10), is input to the second pin of the connector CN4J. The sense signal SENSv1 is pulled up by a 5V DC voltage (DC5V) via a resistor R29J.

The connector CN12J is also connected to the position detection switch of the accessory, the first pin is a terminal for a 12V DC voltage (DC12VB) which is the power supply voltage of the position detection switch, and the third pin is a ground terminal.
For example, the sense signal SENSv9, which is the detection signal of the bottom-rear movable object top position detection switch 120 (see FIG. 10), is input to the second pin of the connector CN12J. The sense signal SENSv9 is pulled up by a 5V DC voltage (DC5V) via a resistor R31J.

Connector CN3J is connected to power supply module board 904 in FIG. 18V DC voltage Vout for 1st pin, 2nd pin and 4th pin, 35V DC voltage (DC35V) for 7th pin, 9th pin and 10th pin, 5th pin, 6th pin and 8th pin for ground Used as each terminal.

The connector CN10J in FIG. 39 is connected to a relay board (not shown). As indicated by the numbers "1" to "32", it has a 32-terminal configuration from the 1st pin to the 32nd pin. The 2nd pin is a terminal to which a 5V DC voltage (DC5V) is applied via a fuse F9J, and the 3rd, 4th and 5th pins are terminals to which a 12V motor driving voltage (MOT12V) is applied.
The 9th, 13th, 17th, 21st, 25th, 27th, 29th, 30th, 31st and 32nd pins are grounded.

The 7th pin is assigned to the motor drive signal MOT1-/2, the 8th pin to the motor drive signal MOT1-/1, the 10th pin to the motor drive signal MOT1-2, and the 12th pin to the motor drive signal MOT1-1. It is
The 14th pin is assigned to the motor drive signal MOT2-/2, the 16th pin to the motor drive signal MOT2-/1, the 18th pin to the motor drive signal MOT2-2, and the 20th pin to the motor drive signal MOT2-1. It is
The 22nd pin is assigned as the motor drive signal MOT3-/2, the 24th pin is assigned as the motor drive signal MOT3-/1, the 26th pin is assigned as the motor drive signal MOT3-2, and the 28th pin is assigned as the motor drive signal MOT3-1. It is

The seventh pin is the terminal for the clock signal CLK_B, and the eleventh pin is the terminal for the data signal DATA_B. The 15th pin is a terminal for the sense signal SENSv2, the 19th pin is a terminal for the sense signal SENSv3, and the 23rd pin is a terminal for the sense signal SENSv4.
The sense signal SENSv2 is, for example, the detection signal of the upper movable object position detection switch 132 in FIG. is a signal.

A connector CN7J in FIG. 40 is connected to an LED board (not shown). The first pin is a terminal for a 12V DC voltage (DC12VB). The fifth and sixth pins are terminals for the 18V LED driving voltage (LED18V). The 4th, 7th and 8th pins are connected to ground.
The second pin is the terminal for the clock signal CLK_E, and the third pin is the terminal for the data signal DATA_E.

The connector CN11J is connected to the transmission line end of the transmission line H30 that connects to the underboard relay board 800 shown in FIG. It has 16 terminals from the first pin to the 16th pin as indicated by the numbers "1" to "16".

The 4th and 6th pins are terminals to which a 12V DC voltage (DC12VB) is applied through a fuse F10J, and the 7th and 9th pins are terminals to which a 12V motor drive voltage (MOT12V) is applied through a fuse F11J. is.
The 1st, 15th and 16th pins are connected to the ground.

The 3rd pin is for the motor drive signal MOT4-/2, the 5th pin is for the motor drive signal MOT4-/1, the 11th pin is for the motor drive signal MOT4-2, and the 13th pin is for the motor drive signal MOT4-1. be.
The 14th pin is used as a terminal for the sense signal SENSv7. The sense signal SENSv7 is, for example, the detection signal of the lower front movable object position detection switch 123 in FIG.
The second pin, eighth pin, tenth pin, and twelfth pin are terminals for outputting the light emission drive currents 13-B7, 13-R8, 13-G8, and 13-B8 to the underboard relay board 800 side.

A connector CN9J in FIG. 41 is connected to an LED board (not shown). The first pin is a terminal for a 12V DC voltage (DC12VB). The tenth pin is a terminal for a 5V DC voltage (DC5V). The 4th pin and the 9th pin are connected to the ground.
The second pin is the terminal for the clock signal CLK_D, and the third pin is the terminal for the data signal DATA_D.

The 8th, 7th, 6th and 5th pins are terminals for light emission drive currents 13-B7, 13-R8, 13-G8 and 13-B8. The light emission drive currents 13-B7, 13-R8, 13-G8, and 13-B8 are supplied by LED drivers mounted on an LED board (not shown). The clock signal CLK_D and the data signal DATA_D from the second pin and the third pin of the connector CN9J are supplied to an LED driver mounted on the LED board (not shown), and based on this, the LED driver generates light emission drive currents 13-B7, 13-R8, 13-G8, 13-B8 are swept away. The light emission drive currents 13-B7, 13-R8, 13-G8, and 13-B8 are sent from the connector CN11J in FIG. ), causing them to emit light.

The 11th pin of the connector CN9J is used as a terminal for the sense signal SENSv8. The sense signal SENSv8 is, for example, the detection signal of the distribution position detection switch 122 in FIG.

The connector CN8J in FIG. 41 is connected to the transmission line end of the transmission line H21 connecting to the backside left relay board 720 shown in FIG. It has a 24-terminal configuration from the first pin to the 24th pin as indicated by the numbers "1" to "24".

1st to 4th pins are terminals to which 18V motor drive voltage (MOT18VB) is applied through fuse F12J, and 5th and 9th pins are terminals to which 12V DC voltage (DC12VB) is applied through fuse F7J. , the 11th pin is a terminal to which a 5V DC voltage (DC5VB) is applied through a fuse F8J.
The 7th, 13th, 14th, 19th and 20th pins are grounded.

The 15th pin is the terminal for the clock signal CLK_C, and the 17th pin is the terminal for the data signal DATA_C.
6th and 8th pins are motor drive signal MOT5-/2, 10th and 12th pins are motor drive signal MOT5-/1, 16th and 18th pins are motor drive signal MOT5-2, 22nd and 24th pins are the terminals of the motor drive signal MOT5-1. In this case, the motor to be driven is a high-torque motor and is driven by a motor drive voltage of 18V (MOT18VB). Since the power consumption is large, the motor drive signals MOT5-/2, MOT5-/1, MOT5-2 and MOT5-1 each use two pins/lines.
The 21st pin is a terminal for the sense signal SENSv6, and the 23rd pin is a terminal for the sense signal SENSv5. The sense signal SENSv6 is, for example, the detection signal of the lower-back movable object lower-left position detection switch 128 in FIG.

The power supply voltage in this LED connection board 700 will be described.
The LED connection board 700 includes, as ICs, the buffer circuits 703 and 704 of FIG. A circuit 705 and buffer circuits 707 and 708 of FIG. 41 are mounted.
As the power supply voltage for these, as shown in FIG. 36, a 5V DC voltage (DC5V) based on the 5V DC voltage (DC5VB) from the connector CN1J is used.

As ICs, the P/S conversion circuits 701 and 702 of FIG. 36 are mounted, and a 5V DC voltage (DC5V) is used as the power supply voltage for these. A 5V DC voltage (DC5VB) is taken out from the positive side of the capacitor C4J from the connector CN1J via the fuse F1J. The P/S conversion circuits 701 and 702 are ICs similar to the P/S conversion circuit 505 in FIG.

The 12V DC voltage (DC12VB) output downstream from connectors CN2J, CN4J, CN7J, CN8J, CN10J, CN11J, and CN12J is taken out from the positive side of capacitor C5J via fuse F2J from connector CN1J.

Motor drivers 710 to 713 shown in FIG. 37 are mounted as ICs on the LED connection board 700, and 12V motor drive voltage (MOT12V) and 12V DC voltage (DC12VS) are used as power supply voltages for these.
Furthermore, motor drivers 714, 715, and 716 are mounted, and 18V motor drive voltage (MOT18VA) and 12V DC voltage (DC12VS) are used as power supply voltages for these.

The 12V motor drive voltage (MOT12V) is separated from the 12V DC voltage (DC12VB) by power isolation/protection circuit 719 .
As shown in FIG. 36, the anode side of the Schottky barrier diode D5J is connected to the 12th, 14th, 24th, 26th, 28th and 30th pins of the connector CN1J. . A resistor R6J, capacitors C14J and C15J, and a chip varistor 709 are connected in parallel between the cathode side of the Schottky barrier diode D5J and the ground. Due to the configuration of this power supply separation/protection circuit 719, the 12V motor drive voltage (MOT12V) is separated as the overvoltage protected power supply voltage.

The 12V DC voltage (DC12VS) is separated from the 12V DC voltage (DC12VB) using the circuit of diode D1J, resistor R1J and capacitor C3J shown in FIG.

The 18V motor drive voltage (MOT18VA), 18V motor drive voltage (MOT18VB), and 18V LED drive voltage (LED18V) are separated from the 18V DC voltage Vout input from connector CN3J as also shown in FIG.
The anode side of the Schottky barrier diode D7J is connected via the fuse F3J to the first, second and fourth pins to which the 18V DC voltage Vout is applied. A resistor R7J and capacitors C17J and C18J are connected in parallel between the cathode side of the Schottky barrier diode D7J and the ground. This configuration extracts the 18V motor drive voltage (MOT18VA).
Similarly, the anode side of a Schottky barrier diode D9J is connected via a fuse F4J to the first, second and fourth pins to which the 18V DC voltage Vout is applied. A resistor R8J and capacitors C20J and C21J are connected in parallel between the cathode side of the Schottky barrier diode D9J and the ground. This arrangement extracts the 18V motor drive voltage (MOT18VB).
Similarly, the anode side of a Schottky barrier diode D11J is connected via a fuse F5J to the first, second and fourth pins to which the 18V DC voltage Vout is applied. A resistor R9J and capacitors C23J and C24J are connected in parallel between the cathode side of the Schottky barrier diode D11J and the ground. This configuration yields an 18V LED drive voltage (LED18V).

The flow of various signals in the LED connection board 700 will be described below.
A clock signal P_S_OUT_CLK and a serial data signal P_S_OUT_DATA are transmitted from the production control board 30 to the connector CN1J of FIG. These are signals used for downstream operation control of the LED connection board 700 .

The clock signal P_S_OUT_CLK and the serial data signal P_S_OUT_DATA are input to terminals A5 and A7 of the buffer circuit 703 and signal-compensated as indicated by the clock signal CLK_P and the serial data signal DATA_P in FIG.
Then, the signals are output from terminals Y5 and Y7 of the buffer circuit 703, and input to the buffer circuit 706 in FIG. Then, they are transmitted downstream from the connector CN7J as shown as a clock signal CLK_E and a serial data signal DATA_E.

The clock signal CLK_A and the serial data signal DATA_A output from the Y5 terminal and Y7 terminal of the buffer circuit 703 are also input to the buffer circuit 705 in FIG. It is sent downstream as DATA_B.
Further, the clock signal CLK_A and the serial data signal DATA_A are also input to the buffer circuit 707 in FIG. 41, buffered, and transmitted downstream from the connector CN9J as the clock signal CLK_D and the serial data signal DATA_D.
Further, the clock signal CLK_A and the serial data signal DATA_A are also input to the buffer circuit 708 in FIG. 41, buffered, and transmitted from the connector CN8J as the clock signal CLK_C and the serial data signal DATA_C to the backside left relay board 720 on the downstream side. be done.

From the production control board 30, the connector CN1J in FIG. ) is sent.
These are used for control for motor drive.
These signals are input to terminals A7, A1, A3, and A5 of the buffer circuit 704 for signal compensation. Then, they are input to the motor drivers 710 to 716 of FIG. 37 through the chip resistor RA4J.
That is, in each of the motor drivers 710 to 716, the reset signal RESET_M is input to the RESET terminal, the latch signal LATCH_M is input to the LATCH terminal, the clock signal CLK_M is input to the SCLK terminal, and the serial data signal DATA_M is input to the SDIN terminal.

The motor drivers 710 to 713 generate 12V motor drive signals according to these inputs.
That is, the motor driver 710 generates motor drive signals MOT1-/2, MOT1-/1, MOT1-2, MOT1-1 that are output from the connector CN10J.
The motor driver 711 generates motor drive signals MOT2-/2, MOT2-/1, MOT2-2, MOT2-1 output from the connector CN10J.
The motor driver 712 generates motor drive signals MOT3-/1, MOT3-2, MOT3-1 output from the connector CN10J.
The motor driver 713 generates motor drive signals MOT4-/2, MOT4-/1, MOT4-2, and MOT4-1 that are output from the connector CN11J.

Also, the motor drivers 714 to 716 similarly generate 18V motor drive signals according to the inputs of the reset signal RESET_M, the latch signal LATCH_M, the clock signal CLK_M, and the serial data signal DATA_M.
That is, the motor driver 714 generates motor drive signals MOT5-/2, MOT5-/1, MOT5-2, and MOT5-1 output from the connector CN8J.
The motor driver 715 generates motor drive signals MOT6-/2, MOT6-/1, MOT6-2 and MOT6-1 output from the connector CN5J.
The motor driver 716 generates motor drive signals MOT7-/2, MOT7-/1, MOT7-2 and MOT7-1 output from the connector CN6J.

A clock signal P_S_IN_CLK and a load signal P_S_IN_LOAD are transmitted from the performance control board 30 to the connector CN1J of FIG.
A clock signal P_S_IN_CLK and a load signal P_S_IN_LOAD are input to terminals A3 and A2 of the buffer circuit 703 for signal compensation. Then, the signals are input from the Y3 terminal and Y2 terminal of the buffer circuit 703 to the CK terminal and CLR/LOAD terminal of the P/S conversion circuits 701 and 702 via the chip resistor RA1J.
In the P/S conversion circuits 701 and 702, a 5V DC voltage (DC5V) is applied to the P/S CONT terminals so that the P/S CONT terminals are set to H, and the Q/D1 to Q/D8 terminals 8 terminals are used as parallel inputs. The P/S conversion circuits 701 and 702 perform parallel-serial conversion according to the clock signal P_S_IN_CLK and the load signal P_S_IN_LOAD.

A Q/D1 terminal of the P/S conversion circuit 701 receives the sense signal SENSv8 from the connector CN9J in FIG. As shown in FIG. 36, this sense signal SENSv8 is pulled up by a 5V DC voltage (DC5V) via a resistor R23J.
Sense signal SENSv9 from connector CN12J in FIG.
The inputs to the Q/D3 to Q/D7 terminals are ground level "0" (L level), and the Q/D8 terminal is set to the 5V level "1" (H level).
The P/S conversion circuit 702 converts the above parallel input into serial data (serial data signal SDT5) and outputs it from the Q8C terminal. This serial data signal SDT 5 is input to the SI terminal of the P/S conversion circuit 702 .

Sense signals SENSv0 to SENSv7 are input to eight terminals Q/D1 to Q/D8 of the P/S conversion circuit 702 . Sense signal SENSv0 is input from connector CN2J. Sense signal SENSv1 is input from connector CN4J. Sense signals SENSv2 to SENSv4 are input from connector CN10J. Sense signals SENSv5 and SENSv6 are input from connector CN8J. Sense signals SENSv5 and SENSv7 are input from connector CN11J.
The sense signals SENSv2 to SENSv7 are pulled up by a 5V DC voltage (DC5V) through resistors R24J, R2J and chip resistor RA3J, respectively.

As described above, the P/S conversion circuit 702 collectively converts the serial data signal SDT5 from the P/S conversion circuit 701 input to the SI terminal and the sense signals SENSv0 to SENSv7 into serial data (serial data signal SDT6). Output from Q8C pin. This serial data signal SDT6 is input to the A1 terminal of the buffer circuit 703 and buffered. And Y1 output is supplied to the 3rd pin of connector CN1J via chip resistance RA1J, and is transmitted to the upstream production control board 30 as a serial data signal P_S_IN_DATA from the LED connection board 700 concerned.

As described above, the LED connection board 700 has the following configuration.
・The sense signals SENSv0 to SENSv9 input from the downstream side are converted into serial data, and transmitted as serial data signals P_S_IN_DATA from the connector CN1J to the upstream side via the buffer circuit 703.
- The clock signal P_S_OUT_CLK and the serial data signal P_S_OUT_DATA transmitted from the performance control board 30 are transferred to the downstream side via the buffer circuit 703 and the buffer circuit (one of 705, 706, 707, 708).

・Clear signal M_S_CLR (reset signal RESET_M), clock signal M_S_OUT_CLK (clock signal CLK_M), serial data signal M_S_OUT_DATA (serial data signal DATA_M), and enable signal M_S_ENABLEP (latch signal LATCH_M) sent from the effect control board 30 are buffered. Motor drivers 710 to 716 are supplied via circuit 704, and motor drive signals (MOT1-/2, MOT1-/1, MOT1-2, MOT1-1...MOT7-/2, MOT7-/1, MOT7- 2, MOT7-1) is generated and sent to the downstream side (motor).

・Receives 12V DC voltage (DC12VB) and 5V DC voltage (DC5VB) through connector CN1J and uses it as an operating power supply.
・The 18V DC voltage Vout is received by the connector CN3J and used as an 18V operating power source (high brightness LED and high torque motor operating power source).
・12V DC voltage (DC12VB), 5V DC voltage (DC5V), 12V motor drive voltage (MOT12V), 18V motor drive voltage (MOT18V), and 18V LED drive voltage (LED18V) are supplied downstream as operating power supply voltages.

In the LED connection board 700, resistors R1J, R2J . . . , chip resistors RA1J, RA2J . , diodes (including Zener diodes and Schottky barrier diodes) D1J, D2J, and other electronic elements are connected.
Also, as shown in the figure, taps TP1J, TP2J, .
Although not shown in the drawings, a capacitor for reducing power supply noise or the like is appropriately arranged between the DC 5V or DC 12V power supply line and the ground.

[5.11 Board Back Left Relay Board 720]

FIG. 42 shows the configuration of the board rear left relay board 720 . Connectors CN1K and CN2K are mounted on the backside left relay board 720 .

The connector CN1K is connected to the transmission line end of the transmission line H21 connecting to the connector CN8J of the LED connection board 700 in FIG.
Therefore, this connector CN1K has 24 terminals from the 1st pin to the 24th pin as indicated by the numbers "1" to "24", and the terminal assignments are the same as those of the connector CN8J.

The connector CN2K is connected to the transmission line end of the transmission line H22 that connects with the decorative substrate 740 on the downstream side.
This connector CN1B has a 22-terminal configuration from the 1st pin to the 22nd pin as indicated by the numbers "1" to "22".

The 4th pin, the 7th pin, and the 10th pin are ground terminals.
The sixth pin is a terminal for a 5V DC voltage (DC5V).
The eighth and ninth pins are terminals for a 12V DC voltage (DC12VB).
The 11th, 12th, 13th and 14th pins are terminals for an 18V motor drive voltage (MOT18VB).

The fifth pin is the terminal for the clock signal CLK_C, and the third pin is the terminal for the data signal DATA_C.
15th and 16th pins are motor drive signals MOT5-/2, 17th and 18th pins are motor drive signals MOT5-/1, 19th and 20th pins are motor drive signals MOT5-2, 21st and 22nd pins are the terminals of the motor drive signal MOT5-1.
The second pin is the terminal for the sense signal SENSv6, and the first pin is the terminal for the sense signal SENSv5.

Conductor points P1 and P2 on the housings of the connectors CN1K and CN2K are grounded for mounting strength.

In this panel rear left relay board 720, the ground terminals of the 7th, 13th, 14th, 19th and 20th pins of the connector CN1K are connected to the 4th, 7th and 10th pins of the connector CN2K side. As 3 terminals of pins, the connector is converted from 24 terminals to 22 terminals. This reduces the number of terminals of the connector CN2D on the downstream side.

[5.12 Decorative substrate 740]

The decoration substrate 740 will be explained using FIG.
The decoration board 740 is mounted with connectors CN1L, CN2L, CN3L, CN4L, CN5L, and CN6L.

The connector CN1L is connected to the transmission line end of the transmission line H22 connecting to the connector CN2K of the backside left relay board 720 in FIG.
Therefore, this connector CN1L has 22 terminals from the first pin to the 22nd pin as indicated by the numbers "1" to "22", and the terminal assignments are the same as those of the connector CN2K.
The conductor points P1 and P2 on the housings of the connectors CN1K to CN6K are grounded for mounting strength.

The connector CN2L is connected to a position detection switch of a movable object (not shown).
The first pin is a 12V DC voltage (DC12VB), and the third pin is a ground terminal. A second pin serves as an input terminal for the sense signal SENSv5 from the connected position detection switch.

The connector CN3L is connected to another position detection switch of the movable object (not shown).
The first pin is a 12V DC voltage (DC12VB), and the third pin is a ground terminal. A second pin serves as an input terminal for the sense signal SENSv6 from the connected position detection switch.

The connector CN4L is connected to the transmission line end of the transmission line H23 connecting to the relay board 760 shown in FIG. As indicated by the numbers "1" to "14", it has a 14-terminal configuration from the 1st pin to the 14th pin.

The 1st, 2nd and 3rd pins are terminals to which a 12V DC voltage (DC12VB) is applied, and the 12th, 13th and 14th pins are terminals to which a 5V DC voltage (DC5V) is applied.
The 4th, 5th, 7th, 8th, 10th and 11th pins are grounded.
The sixth pin is the terminal for the clock signal CLK_C, and the ninth pin is the terminal for the data signal DATA_C.
A flexible cable (for example, a flexible flat cable) is connected to the connector CN4L as the transmission line H23. Since the flexible cable has a small rated current, the number of power supply terminals and ground terminals is made larger than those of the connector CN1L.

The connector CN5L is connected to a motor of a movable object (not shown).
The third and fourth pins are terminals to which a 18V motor drive voltage (MOT18V) is applied.
The first pin is for the motor drive signal MOT5-/2, the second pin is for the motor drive signal MOT5-/1, the fifth pin is for the motor drive signal MOT5-2, and the sixth pin is for the motor drive signal MOT5-1. be.

The connector CN6L is connected to a movable LED board (not shown).
A first pin and a second pin are terminals to which a 12V DC voltage (DC12VB) is applied.
The 3rd pin to the 24th pin are light emission drive current terminals for 22 systems of light emission drive currents 09-R1, 09-G1, 09-B1, . . . 09-R8, and 09-G8.

A buffer circuit 741, which is a triple buffer gate, is mounted on the decorative substrate 740. FIG. A 5V DC voltage (DC5V) is used as the power supply voltage for this. A 5V DC voltage (DC5V) is supplied from the 6th pin of connector CN1L.

Also, an LED driver 742 is mounted, and a 12V DC voltage (DC12VB) is used as the power supply voltage for this. A 12V DC voltage (DC12VB) is supplied from the eighth and ninth pins of the connector CN1L.

The 18V motor drive voltage (MOT18V) supplied downstream from the connector CN5L is obtained from the 11th to 14th pins of the connector CN1L.

The flow of various signals in the decoration board 740 will be described.
A clock signal CLK_C and a data signal DATA_C supplied to the connector CN1L from the upstream backside left relay board 720 are input to the buffer circuit 741 and buffered. Then, it is sent to the connector CN4L and sent to the downstream relay board 760 .

The clock signal CLK_C and data signal DATA_C are also supplied to the LED driver 742 .
The LED driver 742 uses output terminals LEDR1, LEDG1, LEDB1, .
These output terminals LEDR1, LEDG1, LEDB1 ... LEDR7, LEDG7, LEDR8, LEDG8 are connected to the 3rd to 24th pins of the connector CN6L, and are connected to the 22 LED circuits on the movable LED board (not shown). 09-R1, 09-G1, 09-B1, . . . 09-R6, 09-G6, 09-B6).

As described above, the decoration substrate 740 has the following configuration.
- Transfer the clock signal CLK_C and data signal DATA_C transmitted from the upstream side to the downstream side via the buffer circuit 703 .
- The clock signal CLK and data signal DATA are also used by the LED driver 742 . The LED driver 742 drives the light emitting portions of the other LED boards to emit light.

・Receives 12V DC voltage (DC12VB) and 5V DC voltage (DC5V) through connector CN1L and uses it as an operating power supply.
・12V DC voltage (DC12VB) and 18V motor drive voltage (MOT18VB) are supplied to the downstream side as the operating power supply voltage.

In the decoration board 740, electronic elements such as resistors R1L, R2L, . . . , capacitors C1L, C2L, .
Also, taps TP1L and TP2L are provided as shown in the figure and used for connection to required locations.

[5.13 Relay board 760]

FIG. 44 shows the configuration of the relay board 760. As shown in FIG. Connectors CN1M, CN2M, and CN3M are mounted on the relay board 760 .

The connector CN1M is connected to the transmission line end of the transmission line H23 connecting to the connector CN4L of the decoration board 740 in FIG.
Therefore, this connector CN1M has 14 terminals from the 1st pin to the 14th pin as indicated by the numbers "1" to "14", and the terminal assignments are the same as those of the connector CN4L.

The connector CN2M is connected with an LED board (not shown).
The fourth and sixth pins are ground terminals.
The fifth pin is a terminal for a 5V DC voltage (DC5V).
The first pin is a terminal for a 12V DC voltage (DC12VB).
The second pin is the terminal for the clock signal CLK, and the third pin is the terminal for the data signal DATA.

The connector CN3M is connected to the transmission line end of the transmission line H24 connecting to the LED substrate 780 on the downstream side.
This connector CN1B has six terminals from the first pin to the sixth pin as indicated by the numbers "1" to "6".
The fourth and sixth pins are ground terminals.
The fifth pin is a terminal for a 5V DC voltage (DC5V).
The first pin is a terminal for a 12V DC voltage (DC12VB).
The second pin is the terminal for the clock signal CLK, and the third pin is the terminal for the data signal DATA.

The conductor points P1 and P2 in the housings of the connectors CN1M, CN2M and CN3M are grounded for mounting strength.

This relay board 760 is mounted with a buffer circuit 761, which is a Schmitt trigger buffer containing eight CMOS circuits, similar to the buffer circuit 402 of FIG. A 5V DC voltage (DC5V) is used as the power supply voltage for this. A 5V DC voltage (DC5V) is supplied from the 12th, 13th and 14th pins of the connector CN1M.

A clock signal CLK_C and a data signal DATA_C supplied from the upstream decoration board 740 to the connector CN1M are input to terminals A1 and A2 of the buffer circuit 761 and signal-compensated. Then, they are output from terminals Y1 and Y2, and transmitted downstream as a clock signal CLK and a data signal DATA through a connector CN2M.
The clock signal CLK_C and the data signal DATA_C are also input to terminals A5 and A6 of the buffer circuit 761 and are signal-compensated. Then, they are output from terminals Y5 and Y6, and transmitted to the downstream LED substrate 780 as a clock signal CLK and a data signal DATA through the connector CN3M.

Therefore, the decoration board 740 buffers the clock signal CLK_C and the data signal DATA_C and then transmits them to the two downstream LED boards (the LED board 780 and the LED board not shown).

[5.14 LED board 780]

FIG. 45 shows the configuration of the LED board 780 . Connectors CN1N and CN2N are mounted on the LED board 780 .

The connector CN1N is connected to the transmission line end of the transmission line H24 connecting to the connector CN3M of the relay board 760 in FIG.
Therefore, this connector CN1N has a six-terminal configuration from the first pin to the sixth pin as indicated by the numbers "1" to "6", and the terminal assignments are the same as those of the connector CN3M.

Connector CN2N is connected to LED board 790 .
The first pin is a terminal for a 12V DC voltage (DC12VB).
A fourth pin serves as a ground terminal.
The second pin is the terminal for the clock signal CLK, and the third pin is the terminal for the data signal DATA.

Conductor points P1 and P2 on the housings of the connectors CN1N and CN2N are grounded for mounting strength.

A buffer circuit 781 that is a triple buffer gate is mounted on the LED substrate 780 . A 5V DC voltage (DC5V) is used as the power supply voltage for this. A 5V DC voltage (DC5V) is supplied from the fifth pin of connector CN1N.

Also, an LED driver 782 is mounted, and a 12V DC voltage (DC12VB) is used as the power supply voltage for this. A 12V DC voltage (DC12VB) is supplied from the first pin of connector CN1N.

The flow of various signals in the LED board 780 will be described.
A clock signal CLK and a data signal DATA supplied from the upstream relay board 760 to the connector CN1N are input to the buffer circuit 781 and buffered. Then, it is sent to the connector CN2N and sent to the LED board 790 downstream.

The clock signal CLK and data signal DATA are also supplied to the LED driver 782 .
The LED driver 782 performs LED light emission drive of 22 systems using output terminals LEDR1, LEDG1, LEDB1, .
These output terminals LEDR1, LEDG1, LEDB1, . 03-B1 ... 03-G7, 03-B7, 03-R8) flow.
The LED circuit of each system of the light emitting unit 783 is composed of two or three LEDs (LED1, LED2, . . . ) connected in series and resistor elements, as shown in the drawing. The LED circuits of each system are arranged in parallel, and a 12V DC voltage (DC12VB) is applied to each anode side.

As described above, the LED board 780 has the following configuration.
• Transfer the clock signal CLK and data signal DATA sent from the upstream side to the downstream side via the buffer circuit 781 .
The clock signal CLK and data signal DATA are also used by the LED driver 782 to drive the light emitting section 783 to emit light.

・Receives 12V DC voltage (DC12VB) and 5V DC voltage (DC5V) through connector CN1N and uses it as an operating power supply.
・12V DC voltage (DC12VB) is supplied to the downstream side as the operating power supply voltage.

In the LED board 780, electronic elements such as resistors R1N, R2N, . . . , capacitors C1N, C2N, .
Also, taps TP1N and TP2N are provided as shown in the figure and used for connection to required locations.

[5.15 LED board 790]

The structure of the LED board 790 is shown in FIG. A connector CN1X is mounted on the LED board 790 .

The connector CN1X is connected to the transmission line end of the transmission line H25 connecting to the connector CN2N of the LED board 780 in FIG.
Therefore, this connector CN1X has a four-terminal configuration from the first pin to the fourth pin as indicated by the numbers "1" to "4", and the terminal assignments are the same as those of the connector CN2N.

The conductor points P1 and P2 on the housing of the connector CN1X are grounded for mounting strength.

An LED driver 791 is mounted on the LED board 790 . A 12V DC voltage (DC12VB) is used as a power supply voltage for the LED driver 791 . A 12V DC voltage (DC12VB) is supplied from the first pin of connector CN1X.

The flow of various signals in the LED board 790 will be described.
A clock signal CLK and a data signal DATA supplied from the upstream LED board 780 to the connector CN1X are supplied to the LED driver 791 .
The LED driver 791 performs LED light emission drive of 16 systems using output terminals LEDR1, LEDG1, LEDB1, .
These output terminals LEDR1, LEDG1, LEDB1, . 02-B1 ... 02-G5, 02-B5, 02-R6) flow.
The LED circuit of each system of the light emitting unit 792 is composed of two or three LEDs (LED1, LED2, . . . ) connected in series and resistor elements, as shown in the drawing. The LED circuits of each system are arranged in parallel, and a 12V DC voltage (DC12VB) is applied to each anode side.

The above LED board 790 has the following configuration.
The LED driver 791 uses the clock signal CLK and the data signal DATA sent from the upstream to drive the light emitting unit 792 to emit light.

・Receives 12V DC voltage (DC12VB) through connector CN1X and uses it as an operating power supply.

In the LED board 790, electronic elements such as resistors R1X, R2X . . . , capacitors C1X, C2X . Also, taps TP1X and TP2X are provided as shown in the figure and used for connection to required locations.

An LED driver 791 and a light emitting section 792 are mounted on the LED board 790, but no buffer circuit is mounted. Therefore, only the 12V DC voltage (DC12VB) is supplied from the connector CN2N of the LED board 780 to the connector CN1X of the LED board 790, and the 5V DC voltage (DC5V) is not supplied. That is, the 5V DC voltage (DC5V) is based on the 5V DC voltage (DC5VB) from the effect control board 30 (see the 4th and 6th pins of the connector CN1J in FIG. 36), the LED board provided with the buffer circuit It is configured to supply up to 780.

[5.16 Board Back Bottom Relay Board 800]

FIG. 47 shows the configuration of the board rear lower relay board 800 . Connectors CN1Q, CN2Q, CN3Q, and CN4Q are mounted on the board rear lower relay board 800 .

The connector CN1Q is connected to the transmission line end of the transmission line H30 connecting to the connector CN11J of the LED connection board 700 in FIG.
Therefore, this connector CN1Q has 16 terminals from the 1st pin to the 16th pin as indicated by the numbers "1" to "16", and the terminal assignments are the same as those of the connector CN11J.

Connector CN2Q is connected to the moveable motor.
The third and fourth pins are terminals to which a 12V motor driving voltage (MOT12V) is applied.
The first pin is for the motor drive signal MOT4-/2, the second pin is for the motor drive signal MOT4-/1, the fifth pin is for the motor drive signal MOT4-2, and the sixth pin is for the motor drive signal MOT4-1. be.

The connector CN3Q is connected to the transmission line end of the transmission line H31 connecting to the decorative substrate 820 on the downstream side.
This connector CN3Q has 10 terminals from the 1st pin to the 10th pin as indicated by the numbers "1" to "10".
The 1st to 6th pins are terminals for a 12V DC voltage (DC12VB).
The 7th pin, 8th pin, 9th pin, and 10th pin are terminals for light emission drive currents 13-B7, 13-R8, 13-G8, and 13-B8.
A flexible cable (for example, a flexible flat cable) is connected to this connector CN3Q as the transmission line H31, and the rated current is small. For example, the number of terminals (6) for 12V DC voltage (DC12VB) on connector CN3Q is greater than the number of terminals (2) for 12V DC voltage (DC12VB) on connector CN1Q.

Connector CN4Q is connected to a position detection switch.
The first pin is a 12V DC voltage (DC12VB), and the second pin is a ground terminal. A third pin serves as an input terminal for the sense signal SENSv7 from the connected position detection switch.

The conductor points P1 and P2 on the housings of the connectors CN1Q, CN2Q, CN3Q and CN4Q are grounded for mounting strength.

In this board rear lower relay board 800, signals and voltages supplied from the connector CN1Q are distributed downstream by the connectors CN2Q, CN3Q, and CN4Q.
In the connector CN1Q, 12V DC voltage (DC12VB) is input through two terminals of the 4th pin and the 6th pin, but in the connector CN3Q, 12V DC voltage (DC12VB) is input downstream through the 6 terminals of the 1st pin to the 6th pin. sending. As a result, the number of downstream terminals (the total number of terminals of connectors CN2Q, CN3Q, and CN4Q) is greater than the number of upstream terminals (the number of terminals of connector CN1Q).

[5.17 Decorative substrate 820]

The decorative substrate 820 will be explained using FIG.
A connector CN1S is mounted on the decorative substrate 820. As shown in FIG.
The connector CN1S is connected to the transmission line end of the transmission line H31 connecting to the connector CN3Q of the backside lower relay board 800 of FIG.
Therefore, this connector CN1S has ten terminals from the 1st pin to the 10th pin as indicated by the numbers "1" to "10", and the terminal assignments are the same as those of the connector CN3Q.

A decoration substrate 820 is provided with a light-emitting portion 821 having four LED circuits, which are driven to emit light by light-emitting drive currents 13-B7, 13-R8, 13-G8, and 13-B8 through connectors CN1S, respectively. A 12V DC voltage (DC12VB) supplied via a connector CN1S is applied to the anode side of the LED of the light emitting portion 821 .
This decorative substrate 820 is arranged in a movable body (not shown) and is used as a substrate for LED light emission of the movable body portion.

Here, the light emitting portion 821 has nine LED chips as indicated by LED1, LED2, . . . LED9 surrounded by broken lines. As can be seen from the figure, each LED chip is a full-color LED chip that emits R, G, and B light. Note that "GA", "RA", and "BA" in the figure respectively mean the anode of the green LED, the anode of the red LED, and the anode of the blue LED in the full-color LED chip.

The decoration board 820 is designed to emit light in two colors, red and green, in terms of presentation specifications. In this case, full-color LED chips are used instead of monochromatic red and green LED chips. As shown in the figure, the series circuit of blue LEDs not used in the full-color LED chip has both the anode side and the cathode side connected to a 12V DC voltage (DC12VB) line so that no light emission drive current flows. For example, in a series circuit of LED1, LED2, and LED3, three blue LEDs are connected in series, and the anode side and cathode side of the series circuit are connected to a 12V DC voltage (DC12VB) line.

In the case of this configuration, cost reduction can be realized by arranging one full-color LED chip instead of using two single-color LED chips for red and green.
Also, if a light emission drive current terminal is connected to each of the R, G, and B terminals of the full-color LED chip, the number of terminals (number of pins) of the connector CN1S increases, and the light emission drive current used in the LED driver increases. terminals are also increased. Therefore, as described above, no emission drive current is supplied to unused blue LEDs. This simplifies the configuration of the connector, the configuration of the LED driver, and the wiring, resulting in cost reduction.

Also, if the terminal (BA) of an unused color is left unconnected, there is a possibility of unintended light emission due to noise, etc. prevent

Note that unused terminals (anode/cathode of blue LED) in the full-color LED chip may be left unconnected.
Also, if there is a ground on the substrate, the ground may be connected to both ends of the unused terminals of the full-color LED chip.

48, resistors R1S, R3S, and R5S are connected to the green LED system of the full-color LED chip, and resistors R2S, R4S, and R6S are connected to the red LED system. Since no current flows through the terminal (BA) of the blue LED in , no resistor is connected to the blue LED system. This also facilitates circuit simplification and cost reduction.

<6. Other Examples of Board Connection Configuration>
[6.1 Connection state of each board]

FIG. 49 shows an example that replaces the connection configuration shown in FIG.
In FIG. 49, the same blocks as in FIG. 11 are denoted by the same reference numerals, and description thereof is omitted. The example of FIG. 49 is an example in which an LED connection board 1500 is used instead of the LED connection board 700 on the game board 3 side of FIG.

The LED connection board 1500 is connected downstream of the effect control board 30 by a transmission line H50. Then, the LED connection board 1500 performs various necessary signal processing for light emission driving of the effect means such as LEDs and motors in the game board 3 based on the control signal from the effect control board 30 .

FIG. 49 illustrates an LED board 1600 downstream of the LED connection board 1500 . The LED board 1600 may be connected from the LED connection board 1500 via a relay board (not shown) or another LED board, or may be directly connected to the LED connection board 1500 . In this FIG. 49, the LED board 1600 is one of a plurality of boards connected to the downstream side of the LED connection board 1500 as an example.
49, downstream of the LED connection board 1500, each board from the board back left relay board 720 to the LED board 790 shown in FIG. may be connected in parallel with the LED substrate 1600 .

[6.2 LED connection board 1500]
The LED connection board 1500 will be described with reference to FIGS. 50, 51, 52, 53, 54, 55, 56 and 57. FIG. These figures show the circuit configuration provided on the LED connection board 1500 separately.

50, connectors CN4V to CN8V in FIG. 51, connectors CN9V to CN16V in FIG. 52 or 53, connectors CN17V to CN20V in FIG. 54, connectors CN17V to CN20V in FIG. CN21V to CN25V and connectors CN26V to CN28V of FIG. 56 are mounted.

The connector CN1V in FIG. 50 is connected to the transmission line end of the transmission line H50 connecting to the effect control board 30 as shown in FIG.
This connector CN1V has 40 terminals from the 1st pin to the 40th pin as indicated by the numbers "1" to "40".

1st pin, 2nd pin, 8th pin, 9th pin, 10th pin, 16th pin, 18th pin, 19th pin, 20th pin, 22nd pin, 29th pin, 32nd pin of connector CN1V , 33rd, 34th, 39th and 40th pins are grounded.
The 4th pin and the 6th pin are terminals for a 5V DC voltage (DC5VB).
The 12th pin, the 14th pin, the 24th pin, the 26th pin, the 28th pin, and the 30th pin are terminals for a 12V DC voltage (DC12VB).
The 36th pin and the 38th pin are terminals for a 35V DC voltage (DC35V).
The 17th pin is unused.

The 3rd pin is the clock signal LSI_SCK for the LSI as the motor driver control unit 1530 in FIG. 55, the 5th pin is the SPI bus slave selection signal LSI_SS for the LSI, the 7th pin is the serial data signal LSI_MOSI for the LSI, and the 11th pin. is assigned as a terminal for a hardware reset signal LSI_RESET for the LSI, and the 35th pin is assigned as a terminal for a serial data signal LSI_MISO output from the LSI.
The clock signal LSI_SCK and the serial data signal LSI_MOSI are signals transmitted from the performance control board 30 for motor drive control.
The serial data signal LSI_MISO is serial data transmitted from this LED connection board 1500 to the upstream effect control board 30 .

The 13th pin is assigned as a terminal for the clock signal CLK_P, and the 15th pin is assigned as a terminal for the serial data signal DATA_P.
The 31st pin is assigned as a terminal for the load signal S_IN_LOAD. A load signal S_IN_LOAD is a signal used for P/S conversion.

The clock signal CLK_P and the serial data signal DATA_P are branched into the following four systems by the buffer circuit 1502 after passing through the buffer circuit 1501 .
Clock signal CLK_A, serial data signal DATA_A
Clock signal CLK_B, serial data signal DATA_B
Clock signal CLK_C, serial data signal DATA_C
Clock signal CLK_D, serial data signal DATA_D

The clock signal CLK_A and the serial data signal DATA_A are supplied to the LED drivers 1510 and 1511 of FIG. 52 as signals for effect control.
The clock signal CLK_B and the serial data signal DATA_B are supplied to the LED drivers 1520, 1521 and 1522 of FIGS. 53 and 54 as signals for effect control.

The clock signal CLK_C and the serial data signal DATA_C are signals for effect control to be transmitted to the effect driving means on the downstream board, and are transmitted from the connector CN2V of FIG. 50 to the downstream board.
The clock signal CLK_D and the serial data signal DATA_D are signals for effect control to be transmitted to the effect driving means on the downstream board, and are transmitted from the connector CN3V to the downstream board.

The 21st pin of the connector CN1V in FIG. 50 is assigned to the reset signal RESET_M, the 23rd pin to the clock signal CLK_M/S, the 25th pin to the serial data signal DATA_M, and the 27th pin to the latch signal LATCH_M.
A reset signal RESET_M, a clock signal CLK_M/S, a serial data signal DATA_M, and a latch signal LATCH_M are signals used in the motor driver 1505 in FIG. Note that the motor driver 1505 is supplied with the clock signal CLK_M/S as the clock signal CLK_M via the buffer circuit 1503 in FIG.

The 37th pin of connector CN1V is assigned as a terminal for serial data signal S_IN_DATA.
The serial data signal S_IN_DATA is serial data transmitted from this LED connection board 1500 to the effect control board 30 . The clock signal CLK_M/S is supplied to the P/S conversion circuit 1504 as the clock signal S_IN_CLK via the buffer circuit 1503 for outputting the serial data signal S_IN_DATA.

The conductor points P1 and P2 on the housings of the connector CN1V and each of the other connectors CN2V to CN28V are grounded for mounting strength.

A connector CN2V in FIG. 50 is a connector connected to a downstream board.
The 4th, 6th and 8th pins of the connector CN2V are grounded.
The first pin is a terminal for a 12V DC voltage (DC12VB).
The second pin is a terminal for a 5V DC voltage (DC5VB).
A third pin serves as a terminal for the clock signal CLK (CLK_C).
A fifth pin serves as a terminal for the serial data signal DATA (DATA_C).
A seventh pin is a terminal to which a sense signal +P0x from the downstream side is input.
The ninth, tenth, eleventh and twelfth pins are terminals for motor drive signals MOTxA+, MOTxB-, MOTxA- and MOTxB+.

The connector CN3V is also a connector connected to the downstream board, and has terminals for a 12V DC voltage (DC12VB), serial data signal DATA (DATA_D), clock signal CLK (CLK_D), and ground.

A connector CN4V in FIG. 51 is connected to a motor of a movable object (not shown). A 12V DC voltage (MOT12V), which is the power supply voltage of the motor, is applied to the third pin. Terminals for motor drive signals MOT1-/2, MOT1-/1, MOT1-/2, and MOT1-1 are provided.
Connectors CN6V, CN7V, and CN8V are connectors to which sense signals SENS0, SENS1, and SENS2 are input from various sensors, respectively.

Connectors CN9V to CN16V in FIG. 52 or 53 are connectors connected to downstream LED boards (not shown). Each of these is provided with a terminal for outputting a light emission driving current to the corresponding LED substrate.
Connectors CN17V to CN20V in FIG. 54 are also connectors connected to downstream LED boards (not shown). Each of these is provided with a terminal for outputting a light emission driving current to the corresponding LED substrate.

Connectors CN21V to CN25V in FIG. 57 are connectors to which sense signals +P0y, +P0z, +P0u, +P1z, and +P1u are input from various sensors.
Connectors CN26V to CN28V in FIG. 56 are connectors connected to respective downstream motors (not shown).
The connector CN26V is provided with terminals for motor drive signals MOTuA+, MOTuB-, MOTuA- and MOTuB+.
The connector CN27V is provided with terminals for motor drive signals MOTZB+, MOTZA-, MOTZB- and MOTZA+.
The connector CN28V is provided with terminals for motor drive signals MOTyB+, MOTyA-, MOTyB- and MOTyA+.

The power supply voltage in this LED connection board 1500 will be described.
Buffer circuits 1501, 1502, 1503 of FIG. 50 and a buffer circuit 1540 of FIG. 57, which are 8-circuit Schmitt trigger buffers similar to the buffer circuit 402 described above with reference to FIG. be done. Also, the P/S conversion circuit 1504 of FIG. 50 is mounted.
A 5V DC voltage (DC5V) based on the 5V DC voltage (DC5VB) from the connector CN1V is used as the power supply voltage for these.
A 5V DC voltage (DC5VB) is taken out from the positive side of capacitor C3V from connector CN1V via fuse F1J. Note that the P/S conversion circuit 1504 is an IC similar to the P/S conversion circuit 505 in FIG.

51 is mounted as an IC on the LED connection board 1500, and a 12V motor drive voltage (MOT12V) and a 12V DC voltage (DC12VS) are used as power supply voltages for this.

The 12V motor drive voltage (MOT12V) and the 12V DC voltage (DC12VS) are separated from the 12V DC voltage (DC12VB) by the power separation/protection circuits 1551 and 1552 shown in FIG.

55 is mounted as an IC on the LED connection board 1500, and a 5V motor driving voltage (5V DC) is used as the power supply voltage for this.

55 and motor drivers 1533, 1534, and 1535 of FIG. 56 are mounted on the LED connection board 1500 as stepping motor drivers. 35V motor drive voltage (MOT35Vx) (MOT35Vy) (MOT35Vz) (MOT35Vu), 5V DC voltage (DC5V), voltage VCCx, voltage VCCy, voltage VCCz, and voltage VCCu are used as power supply voltages for these.

The 35V motor drive voltages (MOT35Vx) (MOT35Vy) (MOT35Vz) (MOT35Vu) are separated from the 35V DC voltage (DC35V) by the power separation/protection circuit 1553 shown in FIG.
The voltage VCCx, the voltage VCCy, the voltage VCCz, and the voltage VCCu are voltages obtained from the 34th terminals (internal regulator monitor terminals) of the motor drivers 1532, 1533, 1534, and 1535, respectively.

LED drivers 1510, 1511, 1520, 1521, and 1522 shown in FIGS. 52, 53, and 54 are mounted as ICs on the LED connection substrate 1500, and a 12 V DC voltage (DC 12 VB) is used as the power supply voltage for these. I am using

The flow of various signals in the LED connection board 1500 will be described below.
A clock signal LSI_SCK, a serial data signal LSI_MOSI, a slave selection signal LSI_SS, and a hardware reset signal LSI_RESET are transmitted from the production control board 30 to the connector CN1V of FIG. 50 for motor drive control. .

Each of these signals is signal-compensated by the buffer circuit 1501 and then supplied to the motor driver control section 1530 of FIG. 55 via the chip resistor RA1V or RA2V.
A motor driver control unit 1530 controls motor drivers 1532, 1533, 1534, and 1535 based on a clock signal LSI_SCK and a serial data signal LSI_MOSI.

Specifically, motor driver control section 1530 outputs X-axis output pulses OUTx, DIRx, and P3x to motor driver 1532 . The motor driver 1532 accordingly generates motor drive signals MOTxA+, MOTxB-, MOTxA- and MOTxB+ and supplies them to the connector CN2V in FIG.

The motor driver control section 1530 also outputs Y-axis output pulses OUTy, DIRy, and P3y to the motor driver 1533 in FIG.
The connections between FIGS. 55 and 56 are indicated by "c2", "c3" and "c4".
The motor driver 1533 generates motor drive signals MOTyB+, MOTyA-, MOTyB-, MOTyA+ according to the Y-axis output pulses OUTy, DIRy, P3y, and supplies them to the connector CN28V.
Motor driver control section 1530 also outputs Z-axis output pulses OUTz, DIRz, and P3z to motor driver 1534 . The motor driver 1534 accordingly generates motor drive signals MOTZB+, MOTZA-, MOTZB-, MOTZA+ and supplies them to the connector CN27V.
The motor driver control section 1530 also outputs U-axis output pulses OUTu, DIRu and P3u to the motor driver 1535 . The motor driver 1534 accordingly generates motor drive signals MOTuA+, MOTuB-, MOTuA-, MOTuB+ and supplies them to the connector CN26V.

Connectors CN26V, CN27V, and CN28V are connected to movable motors (not shown).
The connector CN2V in FIG. 50 is connected to the downstream substrate, and the motor drive signals MOTxA+, MOTxB-, MOTxA-, MOTxB+ from the motor driver 1532 are supplied to the movable motor (not shown) via the downstream substrate.
Therefore, the motor driver control section 1530 of FIG. 55 has a function of driving those movable motors based on the clock signal LSI_SCK and the serial data signal LSI_MOSI.

The motor driver control unit 1530 receives sense signals +P0x, +P0y, +P0z, +P0u, +P1z, and +P1u from various sensors input from the connector CN2V in FIG. 50 and the connectors CN21V to CN25V in FIG. It is input through buffer circuit 1540 . The sense signals +P0x, +P0y, +P0z, +P0u, +P1z, +P1u are signals for detecting the position of each movable body.
Note that the connection between FIG. 55 and FIG. 57 is indicated by "c1".
The motor driver control unit 1530 serializes these sense signals +P0x, +P0y, +P0z, +P0u, +P1z, +P1u and outputs them as serial data signal LSI_MISO. That is, the motor driver control section 1530 also functions as a P/S conversion circuit.
The serial data signal LSI_MISO obtained by the motor driver control section 1530 is signal-compensated by the buffer circuit 1501 of FIG. 50 and supplied to the connector CN1V.

Sense signals SENS0, SENS1 and SENS2 are input from connectors CN6V, CN7V and CN8V in FIG. These sense signals SENS0, SENS1 and SENS2 are also signals for detecting the position of each movable body. A signal from a motion sensor that detects the action of the player or a proximity sensor that detects a game ball may be used.
The input sense signals SENS0, SENS1, SENS2 are input to the P/S conversion circuit 1504 in FIG. 50 and converted to a serial data signal S_IN_DATA.
This serial data signal S_IN_DATA is signal-compensated by the buffer circuit 1503 and supplied to the connector CN1V.
These serial data signal LSI_MISO and serial data signal S_IN_DATA are transmitted to the effect control board 30 as signals obtained by serializing the detection signals of various sensors.

A clock signal CLK_P and a serial data signal DATA_P input from the connector CN1V are signal-compensated in the buffer circuit 1501 and then supplied to the buffer circuit 1502 via the chip resistor RA2V. As described above, the clock signal CLK_P and the serial data signal DATA_P are signal-compensated by the buffer circuit 1502 and branched into four systems, two of which are the clock signal CLK_C, the serial data signal DATA_C, and the clock signal CLK_D. The serial data signal DATA_D is transmitted to downstream boards from connectors CN2V and CN3V, respectively.

Clock signal CLK_A and serial data signal DATA_A from buffer circuit 1502 are supplied to LED drivers 1510 and 1511 in FIG.

Based on a clock signal CLK_A and a serial data signal DATA_A, the LED driver 1511 emits light from 20 LEDs using output terminals LEDR1, LEDG1, LEDB1, LEDR6, LEDG6, LEDB6 and output terminals LEDR8, LEDG8 for light emission drive currents. drive.

Among these output terminals, the output terminals LEDR1, LEDG1, LEDB1 ... LEDR3, LEDG3, LEDB3 are connected to the 2nd to 10th pins of the connector CN10V, and are connected to the 9 LED circuits on the LED board (not shown). 08-R1, 08-G1, 08-B1, . . . 08-R3, 08-G3, 08-B3).
The output terminals LEDR4, LEDG4, LEDB4 . 08-R4, 08-G4, 08-B4 ... 08-R6, 08-G6, 08-B6) are configured to flow.

The first pins of the connectors CN10V and CN14V are pins for supplying a 5V DC voltage (5V DC) to the downstream LED substrate.

Based on the clock signal CLK_A and the serial data signal DATA_A, the LED driver 1510 performs LED light emission drive of 21 systems using output terminals LEDR1, LEDG1, LEDB1, .

Among these output terminals, the output terminals LEDR1, LEDG1, LEDB1 ... LEDR4, LEDG4, LEDB4 are connected to the 2nd to 13th pins of the connector CN9V, and are connected to the 12 LED circuits on the LED board (not shown). 07-R1, 07-G1, 07-B1, . . . 07-R4, 07-G4, 07-B4).
Output terminals LEDR5, LEDG5, LEDB5, . Output terminals LEDR8 and LEDG8 of the LED driver 1511 are connected to the 11th and 12th pins. As a result, light emission drive currents (07-R5, 07-G5, 07-B5, 07-R7, 07-G7, 07-B7, and 08-R8) are applied to 11 LED circuits on an LED board (not shown). , 08-G8).
The first pins of the connectors CN9V and CN13V are pins for supplying a 12V DC voltage (DC12VB) to the downstream LED substrate.

The clock signal CLK_B and serial data signal DATA_B from the buffer circuit 1502 in FIG. 50 are supplied to the LED drivers 1520, 1521 and 1522 in FIGS.

Based on the clock signal CLK_B and the serial data signal DATA_B, the LED driver 1520 performs 24-system LED light emission drive using output terminals LEDR1, LEDG1, LEDB1, .

Among these output terminals, the output terminals LEDR1, LEDG1, LEDB1 ... LEDR5, LEDG5, LEDB5 are connected to any of the 2nd to 16th pins of the connector CN12V, and are connected to 15 LEDs on an LED board (not shown). A light emission drive current (09-R1 . . . 09-B5) is passed through the circuit.
The output terminals LEDR6, LEDG6, LEDB6...LEDR8, LEDG8, and LEDB8 are connected to the 2nd to 10th pins of the connector CN16V, and the light emission drive current ( 09-R6, 09-G6, 09-B6 ... 09-R8, 09-G8, 09-B8) are configured to flow.

The first pins of the connectors CN12V and CN16V are pins for supplying a 12V DC voltage (DC12VB) to the downstream LED substrate. A fuse F6V is connected to the first pin of the connector CN16V.

Based on the clock signal CLK_B and the serial data signal DATA_B, the LED driver 1521 performs 24-system LED light emission drive using output terminals LEDR1, LEDG1, LEDB1, .

Among these output terminals, the output terminals LEDR1, LEDG1, LEDB1, . A light emission drive current (10-R1 . . . 10-B5) is passed through the circuit.
The output terminals LEDR6, LEDG6, LEDB6, . 10-R6, 10-G6, 10-B6 ... 10-R8, 10-G8, 10-B8) are configured to flow.

The first pins of the connectors CN11V and CN15V are pins for supplying a 12V DC voltage (DC12VB) to the downstream LED substrate. A fuse F5V is connected to the first pin of the connector CN15V.

The LED driver 1522 of FIG. 54 drives 17 systems of LED light emission using output terminals LEDR1, . conduct.

The output terminals LEDR1...LEDR4 are connected to the 2nd to 11th pins of the connector CN17V, and the light emission drive current (11-R1...11-R4 ) is flowed.
The output terminals LEDR5, LEDG5, and LEDB5 are connected to the 2nd to 4th pins of the connector CN19V, and emit light emission drive currents (11-R5, 11-G5, 11-B5) is configured to flow.
The output terminals LEDR6, LEDG6, and LEDB6 are connected to the 2nd to 4th pins of the connector CN20V, and emit light emission drive currents (11-R6, 11-G6, 11-B6) is configured to flow.
The output terminal LEDR7 is connected to the second pin of the connector CN18V, and is configured to pass a light emission drive current (11-R7) to one system of LED circuits on an LED board (not shown).

The first pins of the connectors CN17V, CN18V, CN19V, and CN20V are pins for supplying a 12V DC voltage (DC12VB) to the downstream LED boards.

Reset signal RESET_M, clock signal CLK_M/S (clock signal CLK_M), serial data signal DATA_M, and latch signal LATCH_M input from connector CN1V in FIG. 51 to the motor driver 1505 of FIG.

The motor driver 1505 generates motor drive signals MOT1-/2, MOT1-/1, MOT1-/2, MOT1-1 based on the clock signal CLK_M and the serial data signal DATA_M, and supplies them to the connector CN4V. The connector CN4V is connected to a movable motor (not shown).
Therefore, the motor driver 1505 drives the movable motor based on the clock signal CLK_M and the serial data signal DATA_M.

As described above, the LED connection board 1500 has the following configuration.
Sense signals SENS0, SENS1, and SENS2 input from the downstream side are converted into serial data by the P/S conversion circuit 1504, and transmitted as serial data signals S_IN_DATA from the connector CN1V to the upstream side via the buffer circuit 1503.
The sense signals +P0x, +P0y, +P0z, +P0u, +P1z, and +P1u input from the downstream side are supplied to the motor driver control section 1530 via the buffer circuit 1540 and serialized. The serial data signal LSI_MISO is transmitted upstream from the connector CN1V via the buffer circuit 1501. FIG.

- The clock signal CLK_P (CLK_C, CLK_D) and the serial data signal DATA_P (DATA_C, DATA_D) transmitted from the production control board 30 are transferred downstream via the buffer circuits 1501 and 1502 .
・The clock signal CLK_P (CLK_A, CLK_B) and the serial data signal DATA_P (DATA_A, DATA_B) sent from the performance control board 30 are supplied to the LED drivers 1510, 1511, 1520, 1521, 1522 to drive the LED light emission. Execute.

· The clock signal LSI_SCK and the serial data signal LSI_MOSI transmitted from the performance control board 30 are supplied to the motor driver control section 1530 to execute motor driving. The drive system is a bipolar type.
- The clock signal CLK_M and the serial data signal DATA_M transmitted from the performance control board 30 are supplied to the motor driver 1505 to generate a motor drive signal and transmit it to the downstream motor/board. The drive system is a unipolar type.
Bipolar drive and unipolar drive are mixed in the motor drive system, but by adopting bipolar drive with high torque for large movable bodies and adopting low cost unipolar drive for small movable bodies, it is possible to find the appropriate We are trying to reduce driving force and cost.

・Receives 12V DC voltage (DC12VB), 5V DC voltage (DC5VB), and 35V DC voltage (DC35V) through connector CN1V, and uses it as an operating power supply.
・12V DC voltage (DC12VB) and 5V DC voltage (DC5V) are supplied to the downstream side as the operating power supply voltage.

In the LED connection board 1500, resistors R1V, R2V . . . , chip resistors RA1V, RA2V . . . , diodes (including Zener diodes and Schottky barrier diodes) D1V, D2V .. fuses F1V, F2V .. transistors (FET) Q1V, Q2V . be done. Also, as shown in the figure, taps TP1V, TP2V, .
Some of the capacitors C1V, C2V, .

By the way, instead of receiving the 5V DC voltage (DC5VB) from the substrate on the upstream side, for example, the 5V DC voltage (DC5VB) may be generated based on the 12V DC voltage (DC12VB).

[6.3 LED board 1600]

FIG. 58 shows the configuration of the LED board 1600 shown in FIG.
A connector CN1W is mounted on the LED board 1600 .

The connector CN1W is connected to a transmission line end of a transmission line that connects a connector on a board (not shown) downstream of the LED connection board 1500 described above.

This connector CN1W has 7 terminals from the 1st pin to the 7th pin as indicated by the numbers "1" to "7". A terminal, a ground terminal, a 5V DC voltage (DC5V) terminal, a serial data signal DATA terminal, a reset signal RESET terminal, and a 12V DC voltage (DC12VB) terminal.

The conductor points P1 and P2 on the housing of the connector CN1W are grounded for mounting strength.

An LED driver 1601 is mounted on the LED substrate 1600 . A 12V DC voltage (DC12VB) is used as a power supply voltage for the LED driver 1601 . A 12V DC voltage (DC12VB) is supplied from pin 7 of connector CN1W.

The flow of various signals in the LED board 1600 will be described.
A clock signal CLK, a data signal DATA, and a reset signal RESET supplied from the upstream board to the connector CN1W are supplied to the LED driver 1601 .
The LED driver 1601 uses output terminals LEDR1, LEDG1, LEDB1, .
These output terminals LEDR1, LEDG1, LEDB1, . B1・・・20-R5, 20-G5, 20-B5) flow.
Each LED circuit of each system of the light emitting unit 1602 is composed of a series connection of two LEDs (LED1, LED2, . . . ) and a resistive element, as shown. The LED circuits of each system are arranged in parallel, and a 12V DC voltage (DC12VB) is applied to each anode side.

As described above, the LED board 780 has the following configuration.
The LED driver 1601 drives the light emitting unit 1602 to emit light based on the clock signal CLK and data signal DATA sent from upstream.

・It receives 12V DC voltage (DC12VB) through the connector CN1W and uses it as an operating power supply.

In the LED board 1600, electronic elements such as resistors R1W, R2W, . . . , capacitors C1W, C2W, . Also, as shown in the figure, taps TP1W, TP2W, .

<7. Description of Noteworthy Configuration>
Among the configurations of the gaming machine 1 described so far, the configurations to be noted will be sequentially described below.

[7.1 Relationship between connector terminals and terminals of effect driving means]

First, the relationship between the connector terminals on various substrates and the terminals of the effect driving means will be described.
Note that the production drive means is a general term for circuit portions that drive production devices, such as light emission drive means and motor drive means. Specifically, it is a general term for an LED driver, a motor driver, a driver control section that controls them, and a circuit portion that functions as an S/P conversion circuit for motor drive control.
In particular, the "terminals" of the effect driving means are the terminals of chips mounted as chip parts (IC chips) that function as LED drivers, motor drivers, driver control units, S/P conversion circuits, and the like.

The gaming machine 1 of the embodiment has the following (configuration A1-1).
(Configuration A1-1)
The game machine 1 is
A first board provided with a first effect driving means by a chip component, a first connector for inputting a clock for the first effect driving means and control data for driving the effect,
A second board provided with a second effect driving means by chip parts, a second connector for inputting a clock for the second effect driving means and control data for driving effect,
with
In the first substrate,
The first effect driving means and the first connector are arranged on the same surface of the substrate,
the left-right relationship of the input terminals for the clock and the control data for driving effect in the first effect driving means when the chip side is viewed from the pattern wiring side;
a left-right relationship of each connector terminal for the clock and effect drive control data in the first connector when viewed from the connector terminal side toward the lead-out direction of the pattern wiring connected to each connector terminal;
are identical and
In the second substrate,
The second effect driving means and the second connector are arranged on the same surface of the substrate,
The left-right relationship of the connector terminals for the clock and effect drive control data in the second connector when viewed from the connector terminal side toward the lead-out direction of the pattern wiring connected to the connector terminals is the same as that of the second connector. 1 connector,
The left-right relationship of the input terminals for the clock and control data for driving effect in the second effect drive means is the same as in the first effect drive means when the chip side is viewed from the pattern wiring side.

FIG. 59 schematically shows the structure of the first substrate and the second substrate.
Various configurations are schematically shown below, but each figure mainly shows a connector and effect driving means in blocks, and also shows "clock CK", "data DT", and "pattern wiring PTH".
Specific examples of the clock CK and data DT will be described respectively, but these refer to the clock and control data for driving the effect supplied from the connector on the board to the effect driving means.
The same applies to each diagram schematically showing the configuration of (Configuration A1-2) to (Configuration A9-3) described later.

The pattern wiring PTH indicates a pattern wiring for supplying the clock CK and the data DT from the connector to the performance driving means.
Although there may be a case where a resistance element or the like is interposed between the connector and the performance driving means, such a case does not mean that the structure of the schematic diagram is not applicable. In other words, even if another element is interposed between the connector and the effect driving means, it is sufficient that the configuration shown in the figure is satisfied between the connector and the effect driving means. More precisely, in the element interposed between the connector and the effect drive means, unless the left-right relationship of the wiring of the clock CK and the data DT is reversed, it can be considered to correspond to the following configuration, ignoring them. It is.
Also, the IC chip as a buffer circuit connected to the signal path between the connector and the effect driving means can be considered as a part of the effect driving means, but there is also a way of thinking that it is excluded from the effect driving means in a narrower sense. Even if the buffer circuit is not included in the effect drive means, the buffer circuit is interposed between the connector and the effect drive means, as long as the structure does not invert the left-right relationship of the wiring of the clock CK and the data DT. can be considered to correspond to the following configuration, ignoring
The above should be considered in the same way for (configuration A1-2) to (configuration A9-3) described later.

As shown in FIG. 59, the first board is mounted with the first connector and the first effect driving means.
The first connector and the first effect driving means are arranged on the same plane on the first substrate. In the drawing, the blocks of the first connector and the first effect driving means are indicated by solid lines, which indicate that they are arranged on the plane shown.
In addition, "○" in the block that serves as a connector or effect driving means indicates a terminal.

The first connector inputs the clock CK and the control data for driving the effect (data DT) to the first effect driving means.
The clock CK and data DT are supplied to the first effect drive means through the pattern wiring PTH on the substrate. The connection is not limited to the pattern wiring PTH alone as described above, and there are cases where a resistance element or a chip intervenes. Also, some wiring may be formed on the other surface of the substrate through through holes as required. Although these matters are not mentioned repeatedly in each example, the same applies to the pattern wiring PTH in other configuration examples described later.

A second connector and a second effect driving means are mounted on the second board.
The second connector and the second effect driving means are arranged on the same plane on the second substrate.
The second connector inputs the clock CK and the control data for driving the effect (data DT) to the second effect driving means.
The clock CK and data DT are supplied to the second effect driving means through the pattern wiring PTH on the board.
The first effect driving means and the second effect driving means are shown by the same rectangles because the terminals of the clock CK and the data DT have the same left-right relationship.

In this case, attention is paid to the directions DIR1, DIR2, DIR3 and DIR4 indicated by arrows.
The directions DIR1 and DIR3 are directions from the respective connector terminals of the clock CK and the data DT toward the lead-out direction of the pattern wiring PTH connected to the respective connector terminals.
The directions DIR2 and DIR4 are directions from the pattern wiring PTH side of the input terminals of the clock CK and the data DT in the effect drive means to the chip (=the chip which is the effect drive means) side.

The left-right relationship between the clock CK terminal and the data DT terminal when viewed in the directions DIR1, DIR2, DIR3, and DIR4 is shown in the lower part of FIG.

What is the left-right relationship when viewed in directions DIR1 and DIR3?
"Right-to-left relation of each connector terminal of clock CK and data DT in a connector when viewed from the connector terminal side toward the derivation direction of the pattern wiring PTH connected to each connector terminal"
is.
In the example of FIG. 59, the clock CK terminal is on the left and the data DT terminal is on the right, as shown.

The left-right relationship when viewed in directions such as the directions DIR1 and DIR3 can also be expressed as in the following examples, and any one of them may be applicable.
"Right-to-left relation of each connector terminal of clock CK and data DT in the connector when the pattern wiring PTH side is viewed from the connector side"
"Right-to-left relationship of each connector terminal for clock CK and data DT in a connector when viewed in the direction of the connector side from which the pattern wiring PTH connected to each connector terminal is derived from each connector terminal side"

Also, what is the left-right relationship when viewed in the directions DIR2 and DIR4?
"Left-right relationship of each input terminal of the clock CK and the control data DT for driving effect in the effect driving means when the chip (= chip of the effect driving means) side is viewed from the pattern wiring PTH side"
is.
In the example of FIG. 59, the clock CK terminal is on the left and the data DT terminal is on the right, as shown.

The left-right relationship when viewed in directions such as the directions DIR2 and DIR4 can also be expressed as in the following examples, and any one of them will suffice.
"Right-to-left relation of the input terminals of the clock CK and the data DT in the performance driving means when viewed in a state facing the side of the chip on which the input terminals are located"
"Right-to-left relationship of the input terminals of the clock CK and the data DT in the effect driving means when the chip side is viewed along the introduction direction of the pattern wiring PTH connected to the input terminals"

In these directions, when the left-right relationship of the connector terminals and the left-right relationship of the terminals of the effect driving means are the same, it is assumed that the connector and the effect driving means are placed on the same surface on the board, and their corresponding terminals are connected to each other. are placed facing each other, and the terminals are wired with the shortest distance between them.

In the example of FIG. 59, the clock CK terminals and the data DT terminals have the same lateral relationship when viewed in the directions DIR1, DIR2, DIR3, and DIR4.

Note that the left-right relationship is the same, which means that the terminal for the clock CK may be the left and the terminal for the data DT may be the right, or the terminal for the clock CK may be the right and the data DT may be the left. good. This is the same for each configuration described later other than (configuration A1-1).

The configuration shown in FIG. 59 corresponds to the above (configuration A1-1).
The following (specific example 1) is assumed as an example corresponding to this (configuration A1-1).

(Specific example 1)
・First substrate: LED substrate 780 (see FIG. 45)
・Second substrate: LED substrate 790 (see FIG. 46)
・Clock (CK) for the first effect driving means: Clock signal CLK
Control data (DT) for effect driving for the first effect driving means: data signal DATA
・First effect driving means: LED driver 782
・Input terminal of the clock in the first effect driving means: No. 2 terminal (SCLK terminal)
・Input terminal for control data for driving effect in the first effect driving means: No. 3 terminal (SDATA terminal)
・First connector: connector CN1N
・Connector terminal for clock of first connector: 2nd pin ・Connector terminal for control data for driving effect of first connector: 3rd pin ・Second effect driving means: LED driver 791
・Clock (CK) for the second effect driving means: Clock signal CLK
Control data (DT) for effect drive for the second effect drive means: data signal DATA
・Input terminal of the clock in the second effect driving means: No. 2 terminal (SCLK terminal)
・Input terminal for control data for driving effect in the second effect driving means: No. 3 terminal (SDATA terminal)
・Second connector: connector CN1X
・Connector terminal for clock of the second connector: 2nd pin ・Connector terminal for control data for driving effect of the second connector: 3rd pin

60 and 61 show an LED substrate 780 corresponding to the first substrate in this (specific example 1).
FIG. 60 shows the conductor pattern on the surface layer of the LED substrate 780 having the circuit configuration described in FIG. 45, and FIG. 61 shows the conductor pattern on the back surface layer.
The back layer in FIG. 61 is shown as a perspective view as seen from the surface layer side in FIG. 60, and is shown in a left-right reversed state.
In FIGS. 60 and 61, identification numbers of components printed on the board are omitted. The part shown as "○○+XXΔΔ" actually displays the board management number.

The plurality of light emitting elements mounted on the LED substrate 780 are light emitting elements LED1 to LED12 as color LED chips and light emitting elements LED14 to LED22 as single color LED chips, as shown in the light emitting portion 783 of FIG.
"pLED1" to "pLED22" in FIG. 60 (surface layer) are positions (pads and lands as contacts, collectively referred to as pads hereinafter) where the light emitting elements LED1 to LED22 on the LED substrate 780 are arranged, respectively. is shown.
"p782" indicates the position (pad) where the LED driver 782 is arranged, and "pCN1N" and "pCN2N" indicate the positions (pads) where the connectors CN1N and CN2N are arranged. "p781" indicates the position (pad) where the buffer circuit 781 is arranged.

In the connector CN1N, the pad on the upper left side of the drawing is on the first pin side.
In the connector CN2N, the pad on the left side of the drawing is on the first pin side.

As shown in FIGS. 60 and 61, a ground pattern 784 as solid ground is formed on the surface layer and the back layer, and a pattern wiring for realizing the circuit configuration of FIG. 45 is formed.
A large number of small circular portions shown on the pattern represent through holes or vias. Through-hole vias with copper foil (interlayer wiring) are also included. These are also collectively referred to as "through holes" for explanation purposes.

A power supply pattern 785 for a 12V direct current voltage (DC12VB) is formed mainly on the back layer from the contact (pad) of the first pin of the connector CN1N through a through hole TH10 as shown in FIGS. there is
The power supply pattern 785 on the rear surface layer is connected to the SVCC terminal of the LED driver 782 via a through hole TH11. It is also connected to the VLED terminal of the LED driver 631 via the through hole TH12.

In the case of the LED substrate 780, a power supply pattern 786 is formed on the back layer from the contact (pad) of the fifth pin of the connector CN1N through the through hole TH15 in order to supply a 5V DC voltage (DC5V) to the buffer circuit 781. , and is connected to a buffer circuit 781 through a through hole TH16.

Here, for the connector CN1N, the first to sixth pins are shown enlarged in the lower left of FIG. As for the left-right relationship as viewed in the direction DIR1, the terminal (second pin) for the clock signal CLK is on the left, and the terminal (third pin) for the data signal DATA is on the right.

Also, the LED driver 782 arranged at "p782" is arranged with the directionality (orientation) shown in the enlarged upper left part of FIG.

A plan view of the LED driver 782 located at "p782" is shown in FIG. The LED driver 782 is a rectangular chip component.
In this example, the chip component is almost square, but of course it may be rectangular.
Also, the corners of the square chip housing are chamfered as shown in the figure, so strictly speaking, it is an octagon. want to be By "square" is meant an approximately square, ignoring minor features such as chamfers.

On the above premise, the chip as the LED driver 782 has four sides as a square. Let each side be side sd1, side sd2, side sd3, and side sd4. The sides sd1 and sd3 are opposite sides, and the sides sd2 and sd4 are opposite sides.
As the terminals of the LED driver 631 shown in FIG. 62, the 1st terminal (VREF) to the 12th terminal (A1) are provided on the side sd1, and the 13th terminal (A2) to the 24th terminal (LEDG3) are provided on the side sd2. 25th terminal (LEDB3) to 36th terminal (LEDR6) are provided on side sd3, and 37th terminal (LEDG6) to 48th terminal (SVCC) are provided on side sd4.

Terminal 1 (VREF) is a reference voltage output terminal of 5V.
A second terminal (SCLK) is an input terminal for the clock signal CLK.
A third terminal (SDATA) is an input terminal for the data signal DATA.
A fourth terminal (SDEN) is an enable signal input terminal.
No. 5 terminal (CTLSCT) is a serial bus communication setting terminal, and a reference voltage from No. 1 terminal, that is, H level is input to set a predetermined mode.
A sixth terminal (OUTSCT) is an LED drive current output method control terminal, and in this example, is set to L level by being grounded, and is set to a predetermined mode, for example, constant current output.
A seventh terminal (RESET) is an input terminal for a reset signal RESET.
The 8th terminal (RT1) is a resistance connection terminal for setting the reference current. A resistor R1T is connected in this example.
Terminals 9 and 31 (NC) are dummy terminals (no internal connection).
A tenth terminal (SGND) is a ground terminal.

Terminals 11 to 15 (A0 to A4) are address terminals for setting slave addresses. In this example, as shown in FIG. 75, A0, A1 and A2 are grounded and A3 and A4 are connected to the reference voltage of 5V, so that the slave address of the LED driver 631 is "00011".

Between the 16th terminal and the 45th terminal (excluding the 30th terminal and the 31st terminal), terminals for LED emission drive current (LEDR1 to LEDB8) and ground terminals (PGND1 to PGND4) are formed.

The 46th and 47th terminals are used as test terminals and are grounded.
As described above, the 48th terminal (SVCC) is the operating power supply terminal, and the 30th terminal (VLED) is the protection terminal for the LED drive output.

62 can also be used for the LED drivers mounted on other boards, such as the LED driver 631 on the side unit LED board and the LED driver 791 on the LED board 790 .

62 is applied to FIG. 60, the lateral relationship of the LED driver 782 as viewed in the direction DIR2 is such that the clock signal CLK terminal (2nd terminal (SCLK terminal)) is on the left and the data signal DATA is on the left. terminal (No. 2 terminal (SCLK terminal)) is on the right.

Between the connector CN1N and the LED driver 782, a clock pattern wiring 787 for the clock signal CLK and a signal pattern wiring 788 for the data signal DATA are formed.

Next, FIGS. 63 and 64 show an LED board 790 corresponding to the second board in the above (specific example 1). FIG. 63 shows the conductor pattern on the surface layer of the LED substrate 790 having the circuit configuration described in FIG. 46, and FIG. 64 shows the conductor pattern on the back surface layer.
The back layer in FIG. 64 is shown as a perspective view as seen from the surface layer side in FIG. 63, and is shown in a horizontally reversed state.
In FIGS. 63 and 64, identification numbers of components printed on the board are omitted. The part shown as "X○+○○○" actually displays the board management number.

The plurality of light emitting elements mounted on the LED board 790 are light emitting elements LED1 to LED9 as color LED chips and light emitting elements LED10 to LED17 as single color LED chips, as shown in the light emitting portion 792 in FIG.
“pLED1” to “pLED17” in FIG. 63 (surface layer) indicate the positions (pads) where the light emitting elements LED1 to LED17 on the LED substrate 790 are arranged, respectively. "p791" indicates the position (pad) where the LED driver 791 is arranged, and "pCN1X" indicates the position (pad) where the connector CN1X is arranged.

As shown in FIGS. 63 and 64, a ground pattern 794 as a solid ground is formed on the surface layer and the back layer, and pattern wiring and through holes for realizing the circuit configuration of FIG. 46 are also formed.

Here, for the connector CN1X, the first to fourth pins are shown enlarged on the right side of FIG. As for the left-right relationship when viewed in the direction DIR3, the terminal (second pin) for the clock signal CLK is on the left, and the terminal (third pin) for the data signal DATA is on the right.

Also, the LED driver 791 arranged at "p791" is arranged with the directionality (orientation) shown in the enlarged upper right portion of FIG. The terminal arrangement of the LED driver 791 is shown in FIG.
Therefore, if the terminal arrangement of FIG. 62 is applied to FIG. 63, the horizontal relationship of the LED driver 791 viewed in the direction DIR4 is such that the clock signal CLK terminal (2nd terminal (SCLK terminal)) is on the left and the data signal DATA is on the left. terminal (3rd terminal (SDATA terminal)) is on the right.

Between the connector CN1X and the LED driver 791, a clock pattern wiring 795 for the clock signal CLK and a signal pattern wiring 796 for the data signal DATA are formed.

Looking at the LED boards 780 and 790 as described above, they have the following configuration.
- In the LED board 780, the connector CN1N and the LED driver 782 are arranged on the same surface of the board.
・In the LED board 790, the connector CN1X and the LED driver 791 are arranged on the same surface of the board.
The left-right relationship between the terminals for the clock signal CLK and the terminals for the data signal DATA when viewed in the directions DIR1, DIR2, DIR3, and DIR4 is the same.

Therefore, it corresponds to the configuration of FIG.
The configuration of FIG. 59 provides the following effects.
The wiring of the clock CK between the first connector and the first performance driving means and the wiring of the control data DT for driving performance are extended from the connector in the same direction and are continued to the performance driving means without crossing each other. This makes it possible to improve wiring efficiency and shorten the wiring length on the first substrate. This is advantageous when wiring that does not pass through other layers is desired.
Specifically, as shown in FIG. 60, the clock pattern wiring 787 and the signal pattern wiring 788 are formed without intersecting with each other, and the efficiency of the wiring and the shortening of the wiring length are realized.

Also, the wiring for the clock CK and the wiring for the data DT from the first connector can be led out in the same direction (from the same side of the connector housing). This means that one of the wiring for the clock CK and the wiring for the data DT is not a wiring for adjusting the left-right relationship by going around from the opposite side. This eliminates the need for wiring that runs in the opposite direction from such a connector. It is effective in increasing the efficiency of wiring and shortening the wiring length.

In addition, since there is no need for unnecessary wiring, the wiring length can be shortened, and noise can be reduced. By reducing the noise mixture, the effect operation can be stabilized.
In particular, the clock CK and the data DT are signals that directly control the generation of the effect drive signal by the effect drive means at each time point. Therefore, at least for this set of clock CK and data DT, the efficiency of the wiring is improved and the noise mixture is reduced, so that the effect of improving the stability of the performance operation (LED light emission and movement of movable objects by the motor) is improved. is obtained.
In some cases, other signal wiring such as a reset signal may be provided between the connector and the effect driving means, but the clock CK and data DT are always signals that directly affect the effect operation and have an average frequency. is the highest signal in terms of Making the wirings of the clock CK and the data DT in such a relationship that they do not cross each other at least and improving the wiring efficiency are effective in reducing the influence of noise and stabilizing the performance operation.
The advantage of efficient wiring for this set of clock CK and data DT is the same for (configuration A1-2) to (configuration A9-3) described later.

The above effects can also be obtained with the second substrate.
By adopting the same lateral relationship of the terminals on the second board as on the first board, wiring from the connector to the driver can be made more efficient with a plurality of boards.
Specifically, as shown in FIG. 60, clock pattern wiring 787 and signal pattern wiring 788 are formed without crossing, and as shown in FIG. 63, clock pattern wiring 795 and signal pattern wiring 796 are formed without crossing. is formed in
As a result, it is possible to improve the wiring efficiency of a plurality of boards in the game machine 1, reduce the noise mixture, and improve the design efficiency, thereby promoting stable performance operations.

Further, since the left-right relationship of the pins assigned to the clock CK and the data DT of the connector is common among a plurality of substrates as the first substrate and the second substrate, it is easy to draw circuit diagrams and facilitate wiring design. This improves design efficiency and is useful for new game machine development.

Further, in the case of (specific example 1), by adopting the configuration of FIG. 59 between the substrates that are continuously connected as the LED substrates 780 and 790, each of the above effects can be exhibited more easily. It is also suitable for circuit design and maintenance because the substrates that are connected to each other can be shared.

The gaming machine 1 of the embodiment has the following (configuration A1-2) in addition to (configuration A1-1).
(Configuration A1-2)
The game machine 1 is
A third board provided with a third connector for inputting a clock for the third effect drive means and control data for effect drive,
The left-right relationship of the connector terminals for the clock and effect drive control data in the third connector when viewed from the connector terminal side toward the lead-out direction of the pattern wiring connected to the connector terminals is the same as the third connector. 1 connector.

FIG. 65 schematically shows the first substrate, the second substrate, and the third substrate in this (configuration A1-2). The first and second substrates are the same as in FIG. 59, and the third substrate is added in FIG.

A third connector is mounted on the third board.
A pattern wiring PTH for the clock CK and data DT is derived from the third connector.

In this figure, the third effect driving means is not shown on the third board, but it is one of the following.
・The third effect drive means is mounted on the third board on the same surface as the third connector. ・The third effect drive means is mounted on the third board on a different surface from the third connector. 3 effect driving means is mounted on another board downstream from the third board

A direction DIR5 is a direction in which the pattern wiring PTH connected to the connector terminals of the clock CK and the data DT is led out from the connector terminals of the clock CK and the data DT. In this example, the terminal for the clock CK is on the left and the terminal for the data DT is on the right.

The left-right relationship between the clock CK terminal and the data DT terminal when viewed in the directions DIR1, DIR2, DIR3, DIR4, and DIR5 is shown in the lower part of FIG. All relationships are the same.

As an example corresponding to (configuration A1-2) as shown in FIG. 65, the above (specific example 1) is assumed for the first substrate and the second substrate, and the following (specific example 2) is assumed for the third substrate. be done.

(Specific example 2)
・Third board: side unit upper LED board 630 (see FIG. 32)
・Clock (CK) for the third effect driving means: Clock signal CLK
Control data (DT) for effect drive for the third effect drive means: data signal DATA
・Third connector: connector CN1T
・Connector terminal for clock of the third connector: 2nd pin ・Connector terminal for control data for effect drive of the 3rd connector: 3rd pin

66 and 67 show a side unit LED board 630 corresponding to the third board in this (specific example 2).
FIG. 66 shows the conductor pattern on the surface layer of the LED board 630 on the side unit, and FIG. 67 shows the conductor pattern on the back layer.

The back surface layer of FIG. 67 is shown as a perspective view seen from the surface layer side of FIG. 66, and the conductor pattern and board control number are shown in a state in which the back surface of the board is left-right reversed from the state in which the back surface of the board is normally visually recognized. . In FIGS. 66 and 67, identification numbers of parts printed on the board are omitted. The part shown as "○○+×××Δ" actually displays the board management number.

In the surface layer of FIG. 66 and the back layer of FIG. 67, a ground pattern 633 as solid ground and a pattern wiring for realizing the circuit configuration of FIG. 32 are formed.
“pLED1” to “pLED10” in FIG. 66 (surface layer) indicate the positions (pads) where the light emitting elements LED1 to LED10 in FIG. 32 are arranged, respectively.
"p631" in FIG. 67 (back layer) indicates the position (pad) where the LED driver 631 is arranged, and "pCN1T" indicates the position (pad) where the connector CN1T is arranged.

As for the pads for the connector CN1T, as shown enlarged in the upper part of the drawing, the first pin side is the right pad on the drawing, and the sixth pin side is the left pad.
Therefore, regarding the connector CN1T, the left-right relationship when viewed in the direction DIR5 is such that the terminal (second pin) for the clock signal CLK is on the left and the terminal (third pin) for the data signal DATA is on the right.

The LED driver 631 arranged at "p631" in FIG. 67 is the rectangular chip part described in FIG.

Looking at the side unit upper LED board 630 as described above, it has the following configuration.
· A connector CN1T for inputting a clock signal CLK and a data signal DATA to the third effect driving means (LED driver 631) is provided.
The left-right relationship between the terminals of the clock signal CLK and the data signal DATA when viewed in the direction DIR5 of the connector CN1T is the same as the left-right relationship when viewed in the direction DIR1 of the connector CN1N (first connector) of the LED board 780. are identical.

Therefore, the LED boards 780 and 790 and the side unit upper LED board 630 correspond to (configuration A1-2) in FIG.
Such (configuration A1-2) promotes commonality of connector terminal settings for each substrate, and promotes improvement in design efficiency.

Furthermore, in the board corresponding to the third board, the left-right relationship of each input terminal for the clock and the control data for driving the effect in the third effect driving means (for example, the LED driver 631) when viewed from the pattern wiring side to the chip side is It may be the same as the first effect driving means.

FIG. 67 shows an example in which the LED driver 631 as the third effect driving means is arranged at "p631", and each terminal of this LED driver 631 is shown enlarged in the upper part of the figure. The LED driver 631 is as shown in FIG. 62, but since FIG. 67 shows the rear layer seen through from the front layer side, the terminal arrangement is shown reversed from that in FIGS. In the case of the example of FIG. 67, when the chip side is viewed from the pattern wiring side, the lateral relationship between the terminal of the clock signal CLK and the terminal of the data signal DATA is different from that of the LED driver 782, which is the first effect driving means. It's reversed.

This is an undesirable example for improving wiring efficiency. That is, with the connector CN1T and the LED driver 782 arranged on the same plane, the left-right relationship between the terminal for the clock signal CLK and the terminal for the data signal DATA is reversed.
The figure shows a clock pattern wiring 635 for the clock signal CLK and a signal pattern wiring 636 for the data signal DATA. A part is formed on the surface layer side, thereby correcting the left-right relation with the back surface layer in FIG.

Therefore, in such a case, the LED driver 631 may be arranged on a different surface from the connector CN1T, that is, on the surface layer side. By forming the clock pattern wiring 635 and the signal pattern wiring 636 so as to reach the surface side through the through holes, the left-right relationship can be corrected, so that inefficient wiring can be prevented.
Alternatively, if the LED driver 631 is arranged on the same surface as the connector CN1T, it is also preferable to adopt another chip as the LED driver 631 in which the terminal for the clock signal CLK and the terminal for the data signal DATA are opposite in left-right relationship. is.
By adopting these configurations, it is possible to promote improvement in wiring efficiency in a plurality of substrates, reduction in noise mixture, and improvement in design efficiency. In other words, the effect of (configuration A1-1) can be made more pronounced.

The gaming machine 1 of the embodiment has the following (configuration A2-1).
(Configuration A2-1)
The game machine 1 is
a first substrate provided with first light emission driving means by a chip part, a first connector for inputting a clock and light emission driving control data for the first light emission driving means;
a second board provided with a second connector for inputting a clock and light emission drive control data for the second light emission drive means;
with
In the first substrate,
the first light emission driving means and the first connector are arranged on the same surface of the substrate,
a left-right relationship of the input terminals for the clock and light emission drive control data in the first light emission drive means when the chip side is viewed from the pattern wiring side;
a left-right relationship of each connector terminal for the clock and light emission drive control data in the first connector when viewed from the connector terminal side toward the derivation direction of the pattern wiring connected to each connector terminal;
are identical and
In the second substrate,
The left-right relationship of the connector terminals for the clock and light emission drive control data in the second connector when viewed from the connector terminal side toward the lead-out direction of the pattern wiring connected to the connector terminals is the same as that of the second connector. 1 connector.

FIG. 68 schematically shows the structure of the first substrate and the second substrate.
A first connector and a first light emission driving means are mounted on the first substrate.
The first connector and the first light emission driving means are arranged on the same plane on the first substrate (indicated by solid lines).

The first connector inputs a clock CK and light emission drive control data (data DT) for the first light emission driving means.
The clock CK and data DT are supplied to the first light emission driving means through the pattern wiring PTH on the substrate.

A second connector is mounted on the second board.
The figure does not show the second light emission driving means on the second substrate, but it is one of the following.
The second light emission driving means is mounted on the second substrate on the same surface as the second connector. The second light emission driving means is mounted on the second substrate on a different surface from the second connector. 2 light emission driving means are mounted on another substrate downstream of the second substrate

In this case, the directions DIR11 and DIR13 indicated by arrows are the same directions as the directions DIR1 and DIR3 described in the above (structure A1-1), from the respective connector terminals of the clock CK and the data DT to the respective connector terminals. This is the direction viewed from the lead-out direction of the pattern wiring PTH to be connected.
The direction DIR12 is the same direction as the above-described direction DIR2, and is the direction when the chip (=the chip that is the light emission driving means) side is viewed from the pattern wiring PTH side of each input terminal of the clock CK and the data DT in the light emission driving means. is the direction.

The left-right relationship between the clock CK terminal and the data DT terminal when viewed in directions DIR11, DIR12, and DIR13 is shown at the bottom of the figure.
In the example of FIG. 68, the terminal for clock CK is on the left and the terminal for data DT is on the right, and the left-right relationship is the same.

As an example corresponding to (configuration A2-1) in FIG. 68, the following (specific example 3) is assumed.

(Specific example 3)
・First substrate: LED substrate 780 (see FIG. 45)
・Second substrate: LED substrate 790 (see FIG. 46)
- Clock (CK) for the first light emission driving means: Clock signal CLK
Light emission drive control data (DT) for the first light emission drive means: data signal DATA
- First light emission driving means: LED driver 782
・Input terminal for clock in the first light emission driving means: No. 2 terminal (SCLK terminal)
・Input terminal for light emission drive control data in the first light emission drive means: No. 3 terminal (SDATA terminal)
・First connector: connector CN1N
・Connector terminal for clock of first connector: 2nd pin ・Connector terminal for light emission drive control data of first connector: 3rd pin ・Second connector: connector CN1X
・Clock (CK): Clock signal CLK
・Light emission drive control data (DT): data signal DATA
- Clock connector terminal of the second connector: 2nd pin - Connector terminal of light emission drive control data of the second connector: 3rd pin

The LED substrates 780 and 790 corresponding to the first substrate and the second substrate in this (Specific Example 3) are as described with reference to FIGS.
The directions DIR1, DIR2, and DIR3 shown in FIGS. 60 to 64 correspond to the directions DIR11, DIR12, and DIR13, respectively, in this case (structure A2-1).
Then, the LED boards 780 and 790 have the following configuration.

- In the LED board 780, the connector CN1N and the LED driver 782 are arranged on the same surface of the board.
The left-right relationship between the terminals for the clock signal CLK and the terminals for the data signal DATA when viewed in the directions DIR11, DIR12, and DIR13 is the same.

Therefore, it corresponds to the configuration of FIG.
The configuration of FIG. 68 provides the following effects.
Wiring for clock CK and wiring for light emission drive control data DT between the first connector and the first light emission driving means are extended in the same direction from the connector and are continuous to the light emission driving means without crossing each other. This makes it possible to improve the efficiency of wiring and shorten the wiring length on the first substrate.
Also, the wiring for the clock CK and the wiring for the data DT from the first connector can be led out in the same direction (from the same side of the connector housing). Therefore, it is effective in increasing the efficiency of wiring and shortening the wiring length.

Moreover, since wasteful wiring is not necessary due to these, it is also possible to reduce noise mixing. By reducing the noise mixture, the production operation can be stabilized.
The LEDs are arranged in various places in the gaming machine 1, and the number of substrates on which LED drivers, which serve as light emission driving means, are arranged is large. In particular, it is extremely suitable to adopt this technique for a substrate or the like that is arranged in a place with a lot of high-frequency noise.

Further, since the left-right relationship of the pins assigned to the clock CK and the data DT of the connector is common among a plurality of substrates as the first substrate and the second substrate, it is easy to draw circuit diagrams and facilitate wiring design. As a result, design efficiency is improved, which is useful for game machine development.

The gaming machine 1 of the embodiment has the following (configuration A2-2) in addition to (configuration A2-1).
(Structure A2-2)
The second board has second light emission driving means by a chip component for inputting a clock and light emission driving control data via pattern wiring from the second connector,
In the second substrate, the second light emission driving means and the second connector are arranged on the same surface of the substrate,
The left-right relationship of the input terminals for the clock and light emission drive control data in the second light emission drive means is the same as in the first light emission drive means when the chip side is viewed from the pattern wiring side.

FIG. 69 schematically shows the first substrate and the second substrate in this (structure A2-2). FIG. 69 is similar to FIG. 68 with respect to the first substrate, and differs in that the second substrate shows the second light emission driving means. In the second board, the clock CK and data DT are supplied from the second connector to the second light emission drive means through the pattern wiring PTH on the board.
In the configuration of FIG. 69, the second light emission driving means and the second connector are arranged on the same surface of the second substrate. Direction DIR14 is a direction defined in the same manner as direction DIR4 above.

As an example corresponding to (configuration A2-2) in FIG. 69, in addition to the above (specific example 3), the following (specific example 4) is assumed.

(Specific example 4)
・Second light emission driving means: LED driver 791
・Input terminal for the clock in the second light emission driving means: No. 2 terminal (SCLK terminal)
・Input terminal for effect drive control data in the second light emission drive means: No. 3 terminal (SDATA terminal)

The LED substrates 780 and 790 corresponding to the first substrate and the second substrate in (Specific Example 3) and (Specific Example 4) are as described with reference to FIGS. The direction DIR4 shown in FIG. 63 corresponds to DIR14 in FIG.
Accordingly, the LED board 790 corresponding to the second board has the following configuration.

・In the LED board 790, the connector CN1X and the LED driver 791 are arranged on the same surface of the board.
The lateral relationship between the terminal for the clock signal CLK and the terminal for the data signal DATA when viewed in the direction DIR14 is the same as when viewed in the direction DIR11.
Therefore, it corresponds to the configuration of FIG.

In this way, the second board adopts the same lateral relationship of terminals as that of the first board, and the wiring from the connector to the light emission driving means can be made efficient with a plurality of boards, thereby increasing the efficiency of the wiring within the gaming machine 1. It improves the wiring efficiency of multiple boards, reduces noise contamination, improves design efficiency, and promotes stable light-emitting performance operations.

The gaming machine 1 of the embodiment has the following (configuration A3-1).
(Structure A3-1)
The game machine 1 is
a first motor driving means by a chip part; a first board provided with a first connector for inputting a clock and motor driving control data for the first motor driving means;
a second board provided with a second connector for inputting a clock and motor drive control data for the second motor drive means;
with
In the first substrate,
the first motor driving means and the first connector are arranged on the same surface of the substrate,
a left-right relationship when the chip side is viewed from the pattern wiring side of each input terminal for the clock and motor drive control data in the first motor driving means;
a left-right relationship of the connector terminals for the clock and motor drive control data in the first connector when viewed from the connector terminal side toward the lead-out direction of the pattern wiring connected to the connector terminals;
are identical and
In the second substrate,
The left-right relationship of the connector terminals for the clock and motor drive control data in the second connector when viewed from the connector terminal side in the lead-out direction of the pattern wiring connected to the connector terminals is the same as that of the second connector. 1 connector.

FIG. 70 schematically shows the structure of the first substrate and the second substrate.
A first connector and a first motor driving means are mounted on the first board.
The first connector and the first motor driving means are arranged on the same plane on the first substrate (indicated by solid lines).

The first connector inputs a clock CK and motor drive control data (data DT) for the first motor drive means.
The clock CK and data DT are supplied to the first motor driving means through the pattern wiring PTH on the substrate.

A second connector is mounted on the second board.
Although the drawing does not show the second motor driving means on the second substrate, it is either one of the following.
The second motor driving means is mounted on the second substrate on the same surface as the second connector. The second motor driving means is mounted on the second substrate on a different surface from the second connector. 2 motor driving means are mounted on another board downstream from the second board

In this case, the directions DIR21 and DIR23 indicated by the arrows are the same as the directions DIR1 and DIR3 described above, and are directed from the respective connector terminals of the clock CK and the data DT to the lead-out direction of the pattern wiring PTH connected to the respective connector terminals. This is the direction I saw.
The direction DIR22 is the same as the above-described direction DIR2, when viewed from the pattern wiring PTH side of each input terminal of the clock CK and the data DT in the motor drive means to the chip (=the chip that is the motor drive means) side. be.

The left-right relationship between the clock CK terminal and the data DT terminal when viewed in the directions DIR21, DIR22, and DIR23 is shown at the bottom of the figure.
In the example of FIG. 70, the terminal for clock CK is on the left and the terminal for data DT is on the right, and the left-right relationship is the same.

As an example corresponding to (configuration A3-1) in FIG. 70, the following (specific example 5) is assumed.

(Specific example 5)
・First substrate: LED connection substrate 1500 (see FIGS. 50 to 57)
・Second board: side unit upper right LED board 600 (see FIGS. 24 to 29)
- Clock (CK) for the first motor driving means: clock signal LSI_SCK
・Motor drive control data (DT) for the first motor drive means: serial data signal LSI_MOSI
First motor driving means: motor driver control unit 1530 (Although the buffer circuit 1501 exists in the signal path, the left-right relationship is not inverted at the input and output of the buffer circuit 1501, so the buffer circuit 1501 can be ignored for the left-right relationship. ).
is considered as the first motor driving means. )
・Input terminal for clock in the first motor driving means: No. 5 terminal (SCK terminal)
・Input terminal for motor drive control data of the first motor drive means: No. 7 terminal (MOSI terminal)
・First connector: connector CN1V (see FIG. 50)
Clock connector terminal of first connector: 3rd pin Connector terminal of motor drive control data of first connector: 7th pin Second connector: connector CN1E (see FIG. 24)
・Clock (CK): Clock signal CLK_A (CLK_P)
・Motor drive control data (DT): Data signal DATA_A (DATA_P)
- Clock connector terminal of the second connector: 10th pin - Connector terminal of motor drive control data of the second connector: 14th pin

FIG. 71 and FIG. 72 show an example of arrangement of components in the LED connection board 1500 corresponding to the first board in this (Specific Example 5).
FIG. 71 schematically shows the arrangement of main electronic components on the surface layer of the LED connection board 1500 having the circuit configuration described in FIGS. 50 to 57, and FIG. 72 schematically shows the arrangement of the back layer. Note that the back layer in FIG. 72 is shown as a perspective view seen from the surface layer side in FIG. 71, and is shown in a left-right inverted state.

The connectors CN1V to CN28V in the LED connection board 1500 are all arranged on the surface layer in FIG. Positions where connectors CN1V to CN28V are arranged (positions where pads are formed: the same shall apply hereinafter) are indicated by "pCN1V" to "pCN28V".

Also, positions where buffer circuits 1501, 1502 and 1503 are arranged are indicated as "p1501", "p1502" and "p1503".
Also, the position where the motor driver control section 1530 corresponding to the chip of the first motor driving means is arranged is indicated as "p1530".
Also, the position where the P/S conversion circuit 1504 is arranged is indicated as "p1504".
Also, the position where the buffer circuit 1540 is arranged is indicated as "p1540".

In the back layer of FIG. 72, the positions where the motor drivers 1532, 1533, 1534 and 1535 are arranged are indicated as "p1532", "p1533", "p1534" and "p1535".
Also, the position where the motor driver 1505 is arranged is indicated as "p1505".
Also, the positions where the LED drivers 1510, 1511, 1520, 1521 and 1522 are arranged are shown as "p1510", "p1511", "p1520", "p1521" and "p1522".

FIG. 71 shows some of the terminal numbers of connector CN1V, motor driver control section 1530, buffer circuits 1501, 1502, 1503, P/S conversion circuit 1504, and buffer circuit 1540. FIG. These correspond to the terminal numbers shown in FIGS.
A connector CN1V (see position pCN1V) corresponding to the first connector has two rows of terminals, and the bottom right of the drawing is the first pin side.
In the motor driver control section 1530 (see position p1530) corresponding to the first motor driving means, the terminals on the lower side of the figure are the 1st to 12th terminals in order from the left.

FIG. 72 also shows some of the terminal numbers of the motor driver 1505 and LED drivers 1510, 1511, 1520, 1521, and 1522 (see positions p1510, p1511, p1520, p1521, and p1522). These also correspond to the terminal numbers shown in FIGS.

As shown in FIG. 71, between the connector CN1V and the motor driver control unit 1530, wiring via a buffer circuit 1501 (see position p1501) includes a clock pattern wiring 1561 for the clock signal CLK and a wiring for the data signal DATA. A signal pattern wiring 1562 is formed for this purpose. Note that the illustration of the chip resistor RA1V and the like on the wiring path is omitted.

Here, FIG. 71 shows the directions DIR21 and DIR22 shown in FIG.
Regarding directions DIR21 and DIR22 shown in FIG. It can be seen that the left-right relationship between clock CK and data DT in is the same as the left-right relationship in directions DIR21 and DIR22 shown in FIG.
A clock pattern wiring 1561 and a signal pattern wiring 1562 corresponding to the pattern wiring PTH in FIG. 70 are formed between the connector CN1V and the motor driver controller 1530 to transmit the clock signal LSI_SCK and the serial data signal LSI_MOSI.

Next, FIG. 73 and FIG. 74 show an example of component arrangement in the side unit upper right LED board 600 corresponding to the second board in the above (Specific Example 5).
FIG. 73 schematically shows the arrangement of main electronic components on the surface layer of the side unit upper right LED board 600 having the circuit configuration described in FIGS. 24 to 29, and FIG. 74 schematically shows the arrangement of the back layer. Note that the back layer in FIG. 74 is shown as a perspective view as seen from the surface layer side in FIG. 73, and is shown in a horizontally reversed state.

All of the connectors CN1E to CN7E on the upper right LED board 600 of the side unit are arranged on the back layer of FIG. Positions at which connectors CN1E to CN7E are arranged (positions at which pads are formed: the same shall apply hereinafter) are indicated by "pCN1E" to "pCN7E".

Also, in FIG. 73 or 74, the positions where the buffer circuits 601, 604 and 607 are arranged are indicated as "p601", "p604" and "p607".
Also, the positions where the P/S conversion circuits 602 and 603 are arranged are shown as "p602" and "p603".
Also, the position where the LED driver 605 is arranged is indicated as "p605".
Also, the position where the S/P conversion circuit 606 corresponding to the chip of the second motor driving means described later is arranged is indicated as "p606".
Also, the positions where the motor drivers 608 and 609 are arranged are shown as "p608" and "p609".

73 and 74 show part of the terminal numbers of the connector CN1E, the S/P conversion circuit 606 (see position p606), and the buffer circuit 601 (see position p601). These correspond to the terminal numbers shown in FIGS. 24-29.
A connector CN1E (see position pCN1E) corresponding to the second connector has two rows of terminals, and the top right of the drawing is the first pin side.
In the S/P conversion circuit 606, the terminals on the left side of the drawing are the 1st to 12th terminals from the bottom to the top.

Between the connector CN1E and the S/P conversion circuit 606, wiring via the buffer circuit 601 includes a clock pattern wiring 681 for the clock signal CLK_P (CLK_A) and a signal pattern wiring for the data signal DATA_P (DATA_A). 682 is formed. The resistors R9E, R12E and other elements on the wiring path are omitted from the drawing.

FIG. 74 shows the direction DIR23 shown in FIG. Regarding the direction DIR23 shown in FIG. 74, when the illustrated terminal numbers correspond to the terminal assignments of the connector CN1E in FIG. I know the same thing about relationships.

Therefore, the LED connection board 1500 and the side unit upper right LED board 600 mentioned in (Specific Example 5) correspond to the first board and the second board in (Configuration A3-1) of FIG.

The configuration of FIG. 70 provides the following effects.
The wiring for the clock CK and the wiring for the motor driving control data DT between the first connector and the first motor driving means can extend in the same direction from the connector and can be continuous to the motor driving means without crossing each other. This makes it possible to improve wiring efficiency and shorten the wiring length on the first substrate.
Also, the wiring for the clock CK and the wiring for the data DT from the first connector can be led out in the same direction (from the same side of the connector housing). Therefore, it is effective in increasing the efficiency of wiring and shortening the wiring length.

Moreover, since wasteful wiring is not necessary due to these, it is also possible to reduce noise mixing. By reducing the noise mixture, the production operation can be stabilized.
Since the motors that execute the motions of accessories and other objects require high operating accuracy, this technology is very likely to be adopted for the stability of the motor operation, especially on substrates that are placed in places with a lot of high-frequency noise. be suitable.

Further, since the left-right relationship of the pins assigned to the clock CK and the data DT of the connector is common among a plurality of substrates as the first substrate and the second substrate, it is easy to draw circuit diagrams and facilitate wiring design. This improves design efficiency and is useful for new game machine development.

The gaming machine 1 of the embodiment has the following (configuration A3-2) in addition to (configuration A3-1).
(Structure A3-2)
The second substrate has second motor driving means by chip parts for inputting a clock and motor driving control data via pattern wiring from the second connector,
wherein the second motor driving means and the second connector are arranged on the same surface of the second substrate,
The left-right relationship of the clock and motor drive control data input terminals in the second motor driving means is the same as in the first motor driving means when the chip side is viewed from the pattern wiring side.

FIG. 76 schematically shows the first substrate and the second substrate in this (structure A3-2).
FIG. 76 is similar to FIG. 70 with respect to the first board, except that the second board shows the second motor driving means. In the second board, the clock CK and data DT are supplied from the second connector to the second motor driving means by the pattern wiring PTH on the board.
In the configuration of FIG. 76, the second motor driving means is arranged on the same surface as the second connector on the second substrate. Direction DIR24 is a direction defined similarly to direction DIR4 above.

As an example corresponding to (configuration A3-2) in FIG. 76, in addition to the above (specific example 5), the following (specific example 6) is assumed.

(Specific example 6)
・Second motor driving means: S/P conversion circuit 606
・Input terminal for the clock in the second motor driving means: No. 2 terminal (SCLK terminal)
・Input terminal for control data for driving performance in the second motor driving means: No. 3 terminal (SDATA terminal)

The arrangement of components in the LED connection board 1500 corresponding to the first board and the second board in (Specific Example 5) and (Specific Example 6) and the side unit upper right LED board 600 is as described with reference to FIGS. be. The direction DIR24 shown in FIG. 74 corresponds to DIR24 in FIG. Accordingly, the side unit upper right LED board 600 corresponding to the second board has the following configuration.

- On the upper right LED board 600 of the side unit, the connector CN1E and the S/P conversion circuit 606 are arranged on the same surface of the board.
The lateral relationship between the terminals of the clock signal CLK_A and the terminals of the data signal DATA_A when viewed in the direction DIR24 is the same as in the direction DIR22. Between the connector CN1E and the S/P conversion circuit 606, pattern wiring for the clock signal CLK_A and the data signal DATA_A (clock pattern wiring 681 and signal pattern wiring 682) is formed as the pattern wiring PTH as shown in FIG. . Therefore, it corresponds to the configuration of FIG.

In this way, the second board adopts the same lateral relationship of terminals as that of the first board, and the wiring from the connector to the motor drive means can be made more efficient with a plurality of boards, thereby increasing the number of connections in the gaming machine 1. It is possible to improve the wiring efficiency of multiple boards, reduce the noise mixture, and improve the design efficiency, and promote stable production operations of movable objects such as accessories.

Note that FIG. 75 shows a different configuration example of the surface layer of the LED connection board 1500 .
FIG. 71 described above shows a wiring example in the case of a circuit configuration in which the connector CN1V and the motor driver control unit 1530 are connected via the buffer circuit 1501. FIG. is an example of wiring connected without the buffer circuit 1501 between.

In the example of FIG. 75, the orientation of the connector CN1V is different from that in FIG. 71, and the first pin is located on the upper left side of the figure.
In this case, a clock pattern wiring 1561 and a signal pattern wiring 1562 are formed as shown. Although directions DIR21 and DIR22 in this case are shown in FIG. 75, the left-right relationship is the same as in the examples of FIGS. 70 and 76 as well. In other words, such an example can be considered as the first substrate of (Configuration A3-1) or (Configuration A3-2).

Similarly, in FIG. 74, the dashed lines indicate the wiring between the connector CN1E and the S/P conversion circuit 606 without the buffer circuit 601 intervening. An example in which a signal pattern wiring 682' for (DATA_A) is formed is shown.
Such an example is also conceivable as the second substrate of (Configuration A3-2).

The gaming machine 1 of the embodiment has the following (configuration A4-1).
(Structure A4-1)
The game machine 1 is
A first board provided with a first effect driving means by a chip component, a first connector for inputting a clock for the first effect driving means and control data for driving the effect,
A second substrate provided with a second connector for inputting a first effect drive means by chip parts, a clock for the second effect drive means and control data for effect drive,
with
In the first substrate,
The first effect driving means and the first connector are arranged on the same surface of the substrate,
the left-right relationship of the input terminals for the clock and the control data for driving effect in the first effect driving means when the chip side is viewed from the pattern wiring side;
a left-right relationship of each connector terminal for the clock and effect drive control data in the first connector when viewed from the connector terminal side toward the lead-out direction of the pattern wiring connected to each connector terminal;
are identical and
In the second substrate,
The left-right relationship of the connector terminals for the clock and effect drive control data in the second connector when viewed from the connector terminal side toward the lead-out direction of the pattern wiring connected to the connector terminals is the same as that of the second connector. 1 connector,
The left-right relationship of the input terminals of the clock and the control data for driving the effect in the second effect driving means when the chip side is viewed from the pattern wiring side is opposite to that of the first effect driving means,
The second effect driving means and the second connector are arranged on different surfaces of the second substrate.

FIG. 77 schematically shows the structure of the first substrate and the second substrate.
A first connector and a first effect driving means are mounted on the first board.
The first connector and the first effect driving means are arranged on the same plane on the first substrate (in the figure, the blocks of the first connector and the first effect driving means are both indicated by solid lines).

The first connector inputs the clock CK and the control data for driving the effect (data DT) to the first effect driving means.
The clock CK and data DT are supplied to the first effect drive means through the pattern wiring PTH on the substrate.

A second connector and a second effect driving means are mounted on the second board.
The second connector and the second effect driving means are arranged on different surfaces on the second board. In the drawing, part of the second effect drive means and the pattern wiring PTH are indicated by broken lines, indicating that they are arranged on the back side of the second connector indicated by solid lines. Pattern wirings PTH are formed on both sides through through holes TH.
Also, the second effect drive means is shown as an octagon (rectangular shape with chamfers), but this is different from the first effect drive means shown as a rectangle, with the left and right terminals of the clock CK and data DT. This indicates that the chip has a different relationship.
Also, the characters "CK" and "DT" at the terminals of the second effect driving means are shown in a mirror-inverted state. This expresses a state in which "CK" and "DT" are normally seen when viewed from the back side. Although the letters "CK" and "DT" are not actually written on the chip, it is clear from the drawing that the second effect driving means is arranged on the back surface when viewed from the second connector. intended to express. In other words, when viewed from the plane of the drawing, the first effect drive means and the second effect drive means have the same left-right relationship of "CK" and "DT", but the arrangement faces are opposite, so as a chip " It expresses that the left-right relationship of CK and DT is reversed.

The second connector inputs the clock CK and the control data for driving the effect (data DT) to the second effect driving means. The clock CK and data DT are supplied to the second effect drive means through the pattern wiring PTH.

In this case, the left-right relationship of the clock CK and data DT terminals in directions DIR31, DIR32, DIR33, and DIR34 indicated by arrows is shown at the bottom of the drawing. Directions DIR31, DIR32, DIR33, and DIR34 are directions defined similarly to directions DIR1, DIR2, DIR3, and DIR4 above, respectively.
The direction DIR34 has the same definition as the direction DIR4, but in this case, since the second effect drive means is arranged on the back surface when viewed from the second connector, the board is turned upside down. You can think of it in terms of your line of sight (it is easier to think of it as the line of sight when looking through the printed page of this figure from the back). Therefore, the left-right relationship when viewed in the direction DIR 34 is such that the terminal for data DT is on the left and the terminal for clock CK is on the right, as shown in the lower right of the figure.
Such directionality of observation is because the left-right relationship referred to in the present invention should be considered based on the surface on which the pattern wiring PTH is formed.

In the case of FIG. 77, the left-right relationship when viewed in directions DIR31, DIR32, and DIR33 is the same, with the clock CK terminal on the left and the data DT terminal on the right, but the left-right relationship when viewed in the direction DIR34. is reversed.
In other words, the chip used as the second effect driving means has a configuration in which the left-right relationship of the respective terminals of the clock CK and the data DT is opposite to that of the chip of the first effect driving means.

As an example corresponding to (configuration A4-1) in FIG. 77, the following (specific example 7) is assumed.

(Specific example 7)
・First substrate: LED connection substrate 1500 (see FIGS. 50 to 57)
・Second substrate: LED substrate 1600 (see FIG. 58)
・Clock (CK) for the first effect driving means: clock signal LSI_SCK
・Effect drive control data (DT) for the first effect drive means: serial data signal LSI_MOSI
・First effect drive means: motor driver control unit 1530 (see FIG. 55)
・Input terminal of the clock in the first effect driving means: No. 5 terminal (SCK terminal)
・Input terminal for control data for driving effect in the first effect driving means: No. 7 terminal (MOSI terminal)
・First connector: connector CN1V
・Connector terminal for clock of the first connector: 3rd pin ・Connector terminal for control data for driving effect of the first connector: 7th pin ・Second effect driving means: LED driver 1601 (see FIG. 58)
・Clock (CK) for the second effect driving means: clock signal CLK
Control data (DT) for effect drive for the second effect drive means: data signal DATA
・Input terminal for the clock in the second effect driving means: No. 48 terminal (SCLK terminal)
・Input terminal for control data for driving effect of the second effect driving means: No. 47 terminal (SDATA terminal)
・Second connector: connector CN1W
・Connector terminal for clock of the second connector: 2nd pin ・Connector terminal for control data for driving effect of the second connector: 5th pin

In this (Specific Example 7), the component arrangement of the LED connection board 1500 corresponding to the first board is as described with reference to FIGS. 71 and 72 .
Regarding the LED substrate 1600 corresponding to the second substrate, FIG. 78 schematically shows the arrangement of main electronic components on the surface layer, and FIG. 79 schematically shows the arrangement on the back layer. Note that the back layer in FIG. 79 is shown as a perspective view as seen from the surface layer side in FIG. 78, and is shown in a horizontally reversed state.

The connector CN1W on the LED board 1600 is arranged at the position of "pCN1W" on the surface layer in FIG.
On the surface layer, LED1 to LED10 in the light emitting portion 1602 of FIG. 58 are also arranged at positions of "pLED1" to "pLED10".
In the back layer of FIG. The LED driver 1601 is arranged at the position of "p1601".

FIG. 78 shows part of the terminal numbers of the connector CN1W (see position pCN1W), and FIG. 79 shows part of the terminal numbers of the LED driver 1601 (see position p1601). These correspond to the terminal numbers shown in FIG.
Note that the LED driver 1601 has a terminal configuration as shown in FIG. 80A, for example. Although the details of the terminal configuration are omitted here, the 48th terminal is the SCLK terminal and the 47th terminal is the SDATA terminal.
Since FIG. 79 is a perspective view from the surface layer side, the terminal numbers shown in FIG. 79 correspond to the mirror-inverted state (state viewed from the bottom side of the chip) as shown in FIG. 80B.

Between the connector CN1W and the LED driver 1601, a clock pattern wiring 1611 for the clock signal CLK and a signal pattern wiring 1612 for the data signal DATA are formed. It is connected to the second and fifth pins of the connector CN1W through through holes TH11 and TH12 shown in FIGS. The illustration of resistors R1W and R2W (see FIG. 58) on the wiring path is omitted.

78 and 79 show the directions DIR33 and DIR34 shown in FIG. 77 with respect to the connector CN1W and the LED driver 1601. FIG.
Regarding the directions DIR33 and DIR34 shown in FIGS. 78 and 79, when the illustrated terminal numbers correspond to the terminal assignments of the connector CN1W and the terminal configuration of the LED driver 1601 in FIG. and data DT are the same as those in the directions DIR33 and DIR34 shown in FIG.
Between the connector CN1W and the LED driver 1601, a clock pattern wiring 1611 and a signal pattern wiring 1612 for the clock signal SLK and data signal DATA are formed corresponding to the pattern wiring PTH in FIG.

Therefore, the LED connection board 1500 and the LED board 1600 mentioned in (Specific Example 7) correspond to the first board and the second board in (Configuration A4-1) of FIG.

The configuration of FIG. 77 provides the following effects.
With respect to the first substrate, the same effects as those of (structure A1-1) described above (reduction of wiring length, improvement of wiring efficiency, reduction of noise mixture, improvement of design efficiency, etc.) can be obtained.
In addition, in the case of (configuration A4-1), it is suitable when using ICs having terminals with different lateral relationships as the first and second effect drive means.
In the LED driver 1601 mentioned as the second effect drive means, the left-right relationship of the terminals of the clock CK and the data DT is opposite to that of the connector CN1W. As a result, the effect of the second substrate mentioned in (Structure A1-1) described above cannot be obtained. In this case, the second effect driving means is arranged on a different surface from the second connector. By being on a different surface from the second connector, the left-right relationship occurring in the wiring from the second connector can be adapted to the second effect drive means at the stage of passing through the through hole TH. In other words, it is possible to form the pattern wiring PTH that copes with the difference in the left-right relationship without unnecessary wiring. In addition, even when different types of ICs are used as effect driving means on the first board and the second board, the pin arrangement on the connector side (left-right relationship of pins assigned to the clock CK and data DT) can be changed between the first board and the second board. You can enjoy the benefits that can be shared with

The gaming machine 1 of the embodiment has the following (configuration A5-1).
(Configuration A5-1)
The game machine 1 is
a first effect driving means by chip parts;
a second effect drive means by chip parts;
a connector for inputting a clock for the first effect drive means and the second effect drive means and control data for effect drive;
A first substrate provided with
In the first substrate,
the left-right relationship of the input terminals for the clock and the control data for driving effect in the first effect driving means when the chip side is viewed from the pattern wiring side;
the left-right relationship of each connector terminal for the clock and effect driving control data in the connector when viewed from the connector terminal side toward the lead-out direction of the pattern wiring connected to each connector terminal;
are identical and
a left-right relationship when the chip side is viewed from the pattern wiring side of each input terminal for the clock and the control data for driving the effect in the second effect driving means;
the left-right relationship of each connector terminal for the clock and effect driving control data in the connector when viewed from the connector terminal side toward the lead-out direction of the pattern wiring connected to each connector terminal;
is the opposite, and
The first effect driving means is arranged on the same plane as the connector,
The second effect driving means is arranged on a different plane from the connector.

FIG. 81 schematically shows the configuration of this first substrate.
A connector, a first performance driving means and a second performance driving means are mounted on the first board.
The connector and the first effect driving means are arranged on the same plane on the first substrate. In the figure, the blocks of the first connector and the first effect driving means are both indicated by solid lines.
The connector and the second effect driving means are arranged on different surfaces on the first substrate. In the drawing, part of the second effect driving means and the pattern wiring PTH are indicated by broken lines, indicating that they are arranged on the back side of the connector indicated by solid lines. The pattern wiring PTH is formed over both surfaces through the through holes TH.
In FIG. 81 as well, in the same sense as in FIG. 77, the second effect driving means is shown with a different shape (octagonal), and the characters "CK" and "DT" are mirror-reversed.

The connector inputs a clock CK and control data for driving effects (data DT) for the first and second effect driving means.
The clock CK and data DT are supplied to the first effect drive means through the pattern wiring PTH on the substrate.
The clock CK and data DT are also supplied to the second effect driving means through the pattern wiring PTH.

In this case, the left-right relationship of the terminals of the clock CK and the data DT in directions DIR51, DIR52, and DIR53 indicated by arrows is shown in the lower part of the drawing. The direction DIR51 is defined similarly to the direction DIR1 described above, and the directions DIR52 and DIR53 are defined similarly to the direction DIR2 described above.
It should be noted that the direction DIR53 is considered to be the line-of-sight direction when the substrate is turned upside down with respect to the direction DIR2. This is for the reason described in the description of the direction DIR34 in FIG.

In this case, the left-right relationship is the same when viewed in the directions DIR51 and DIR52, but the left-right relationship is reversed when viewed in the direction DIR53.
In other words, the second effect driving means has a configuration in which the left-right relationship of the terminals of the clock CK and the data DT is opposite to that of the chip of the first effect driving means.

The following (specific example 8) is assumed as an example corresponding to (configuration A5-1) as shown in FIG.

(Specific example 8)
・First substrate: LED connection substrate 1500 (see FIGS. 50 to 57)
・Clock (CK) for the first effect driving means: clock signal LSI_SCK
・Effect drive control data (DT) for the first effect drive means: serial data signal LSI_MOSI
・First effect drive means: motor driver control unit 1530 (see FIG. 55)
・Input terminal of the clock in the first effect driving means: No. 5 terminal (SCK terminal)
・Input terminal for control data for driving effect in the first effect driving means: No. 7 terminal (MOSI terminal)
・Connector: Connector CN1V
・Connector terminal for connector clock: 3rd pin (or 3rd pin and 13th pin)
・Connector terminal of connector effect drive control data: 7th pin (or 7th pin and 15th pin)
・Second effect driving means: LED drivers 1510, 1511, 1520, 1521, 1522 (see FIGS. 52, 53 and 54)
・Clock (CK) for the second effect drive means: clock signals CLK_A, CLK_B
・Effect drive control data (DT) for the second effect drive means: data signals DATA_A, DATA_B
・Input terminal for the clock in the second effect driving means: No. 48 terminal (SCLK terminal)
・Input terminal for control data for driving effect of the second effect driving means: No. 47 terminal (SDATA terminal)

In this (Specific Example 8), the arrangement of the surface layer and back layer of each component of the LED connection board 1500 corresponding to the first board is as described with reference to FIGS. That is, the connector CN1V and the motor driver control unit 1530 corresponding to the first effect driving means are arranged on the surface layer, and the LED drivers 1510, 1511, 1520, 1521, 1522 corresponding to the second effect driving means are arranged on the back layer. It is

The connections between the 3rd and 5th pins of the connector CN1V and the 5th (SCK) and 7th (MOSI) terminals of the motor driver control unit 1530 are as described in FIG. , DIR52 (the directions DIR51 and DIR52 correspond to the directions DIR21 and DIR22 in FIG. 71).

The LED driver 1521 will be described as an example of the second effect driving means. A direction DIR53 is shown for the arrangement of the LED drivers 1521 shown in FIG. Since FIG. 72 is a perspective view, considering the back layer up, clock CK and data DT as the 48th terminal (SCLK terminal) and 47th terminal (SDATA terminal) of the LED driver 1521 viewed in the direction DIR53. The left-right relationship of the terminals is as shown in FIG.

Therefore, in the LED connection board 1500, the connector CN1V, the motor driver control section 1530, the LED driver 1521, etc. correspond to the configuration shown in FIG.
In the case of this configuration, in addition to obtaining the same effects (reduction of wiring length, improvement of wiring efficiency, reduction of noise mixture) as (configuration A1-1) described above, the following effects are obtained.

That is, it is suitable for use as the first and second effect driving means when ICs having terminals of clock CK and data DT with different lateral relationships are used.
Although the left-right relationship of the terminals for the clock CK and the data DT is opposite to that of the connector, the second effect drive means is arranged on a different surface from the connector, so that the wiring from the connector passes through a through hole. You can adapt the left-right relationship with Therefore, wiring is not complicated.

As for (configuration A5-1), as in the LED connection board 1500 described above, separate clocks CK (3rd and 13th pins) and data DT (7th and 15th pins) are input to the connector. , are separately supplied to the first and second effect drive means, but one clock CK and data DT input to the connector are branched and supplied to the first and second effect drive means. A configuration is also envisioned. This will be described as the following (configuration A5-2).

The gaming machine 1 of the embodiment has the following (configuration A5-2) in addition to (configuration A5-1).
(Configuration A5-2)
The clock inputted to the connector is branched and supplied to the first effect driving means and the second effect driving means,
The effect driving control data inputted to the connector is branched and supplied to the first effect driving means and the second effect driving means.

FIG. 82 shows an example of a structure in which one clock CK and data DT are branched and supplied to the first and second effect driving means.
FIG. 82 shows an example in which the portion of FIG. 50 is partially modified from the LED connection board 1500 of FIGS. 51 to 57 can be considered the same.

82 is an example in which the clock signal LSI_SCK from the 3rd pin of the connector CN1V in FIG. 81 and the serial data signal LSI_MOSI from the 7th pin are branched by a buffer circuit 1501.
The clock signal LSI_SCK is input to the A1 terminal (2nd terminal) and A6 terminal (7th terminal) of the buffer circuit 1501, and is output as the clock signal LSI_SCK to the motor driver control section 1530 from the Y1 terminal (18th terminal). It is output as a clock signal CLK_P from the Y6 terminal (13th terminal). The clock signal CLK_P is supplied to the LED driver 1521 and the like via the buffer circuit 1502 as the clock signals CLK_A and CLK_B.
The serial data signal LSI_MOSI is input to the A4 terminal (5th terminal) and A7 terminal (8th terminal) of the buffer circuit 1501, and is output from the Y4 terminal (15th terminal) to the motor driver control section 1530 as the serial data signal LSI_MOSI. and output as a data signal DATA_P from the Y7 terminal (12th terminal). The data signal DATA_P is supplied to the LED driver 1521 and the like as data signals DATA_A and DATA_B via the buffer circuit 1502 .

That is, as shown in FIG. 81, the clock CK and the data DT are branched and supplied to the first effect driving means of the surface layer and the second effect driving means of the back layer, and the first and second effect driving means The left-right relationship of the clock CK and data DT terminals is reversed.
As a result, when the clock CK and the data DT of one system are branched and supplied to a plurality of effect drive means, the first and second effect drive means determine that the left-right relationship between the clock CK and the data DT is mutual. In the case of the opposite IC, there is an effect that the pattern wiring is not complicated.

Such a configuration can also be applied to a case in which an LED driver 605 and an S/P conversion circuit 606 are provided as effect drive means, such as the upper right LED board 600 of the side unit. The side unit upper right LED board 600 branches the clock signal CLK_P (CLK_A) and the data signal DATA_P (DATA_A) input to the connector CN1E and supplies them to the LED driver 605 and the S/P conversion circuit 606 . In this case, if the S/P conversion circuit 606 uses a chip in which the lateral relationship of the terminals of the clock signal CLK_A and the data signal DATA_A is opposite to that shown in FIG. to be placed. This can prevent the wiring from becoming complicated.

The gaming machine 1 of the embodiment has the following (configuration A6-1).
(Structure A6-1)
The game machine 1 is
A first effect driving means by a chip component, a first input connector for inputting a clock for the first effect driving means and control data for driving effect, and an output connector for outputting the clock and control data for driving effect are provided. a first substrate;
A second board provided with a second effect driving means by chip parts, a second input connector for inputting a clock for the second effect driving means and control data for driving effect,
with
the left-right relationship of the input terminals for the clock and the control data for driving effect in the first effect driving means when the chip side is viewed from the pattern wiring side;
a left-right relationship when the chip side is viewed from the pattern wiring side of each input terminal for the clock and the control data for driving the effect in the second effect driving means;
a left-right relationship of each connector terminal for the clock and effect drive control data in the first input connector when viewed from the connector terminal side toward the lead-out direction of the pattern wiring connected to each connector terminal;
a left-right relationship of each connector terminal for the clock and effect drive control data in the output connector when viewed from the pattern wiring side connected to each connector terminal toward the direction of each connector terminal;
are identical and
the output connector and the second input connector are connected by a cross cable;
The assignment of each terminal of the second input connector is set in the reverse order of the assignment of each terminal of the first input connector,
In the first substrate, the first effect driving means and the first input connector are arranged on the same surface of the substrate,
In the second substrate, the second effect driving means and the second input connector are arranged on different surfaces of the substrate.

FIG. 83 schematically shows the structure of the first substrate and the second substrate.
A first input connector, a first effect driving means and an output connector are mounted on the first substrate.
The first connector and the first effect driving means are arranged on the same plane on the first substrate (in the figure, the blocks of the first connector and the first effect driving means are both indicated by solid lines).

The first connector inputs the clock CK and the control data for driving the effect (data DT) to the first effect driving means.
The clock CK and data DT are supplied to the first effect drive means through the pattern wiring PTH on the substrate.

A second input connector and a second effect driving means are mounted on the second board.
The second input connector and the second effect driving means are arranged on different surfaces on the second board. In the drawing, part of the second effect drive means and the pattern wiring PTH are indicated by broken lines, indicating that they are arranged on the back side of the second connector indicated by solid lines. Pattern wirings PTH are formed on both sides through through holes TH.
In this case, the second effect drive means has the same horizontal relation of the terminals of the clock CK and the data DT as the first effect drive means, so it is indicated by the same rectangle as the first effect drive means. . In addition, since it is the back surface, the letters "CK" and "DT" are mirror-reversed.

A second input connector inputs a clock CK and control data for driving effect (data DT) to the second effect driving means. The clock CK and data DT are supplied to the second effect drive means through the pattern wiring PTH.

The second input connector is connected to the output connector of the first board with a cross cable 2000 .
In this case, it is assumed that the output connector has a four-terminal configuration of pins 1 to 4, and for example, "power supply voltage VC", "clock CK", "data DT" and "ground GND" are assigned in order from the first pin.
The second input connector also has a four-terminal configuration, but since it is connected by the cross cable 2000, it is assigned to "ground GND", "data DT", "clock CK", and "power supply voltage VC" in order from the first pin. will be

The left-right relationship of the clock CK and data DT terminals in directions DIR61, DIR62, DIR63, DIR64, and DIR65 indicated by arrows is shown at the bottom of the figure.
Directions DIR61 and DIR62 are defined in the same manner as directions DIR1 and DIR2 described above, respectively. Directions DIR64 and DIR65 are directions defined similarly to directions DIR3 and DIR4 above, respectively. The direction DIR65 is considered as a line-of-sight direction in the same state with respect to the direction DIR4 and the top and bottom of the chip as described in the explanation of the direction DIR34 in FIG.
A direction DIR63 is a direction facing each connector terminal from the pattern wiring side connected to each connector terminal of the output connector.

In this case, the left-right relationship between the clock CK and the data DT when viewed in the directions DIR61, DIR62, DIR63, and DIR65 is the same, but the left-right relationship when viewed in the direction DIR64 is reversed. This is because they are connected by the cross cable 2000 .

As an example corresponding to (structure A6-1) shown in FIG. 77, the following (specific example 9) is assumed.

(Specific example 9)
・First substrate: LED substrate 780 (see FIG. 45)
・Second substrate: LED substrate 790A (see FIG. 84)
・Clock (CK) for the first effect driving means: clock signal CLK
Control data (DT) for effect driving for the first effect driving means: data signal DATA
・First effect driving means: LED driver control unit 782
・Input terminal of the clock in the first effect driving means: No. 2 terminal (SCLK terminal)
・Input terminal for control data for driving effect in the first effect driving means: No. 3 terminal (SDATA terminal)
・First input connector: connector CN1N
・Connector terminal for clock of the first input connector: 2nd pin ・Connector terminal for control data for effect drive of the first input connector: 3rd pin ・Output connector: connector CN2N
Output connector clock connector terminal: 2nd pin Output connector control data connector terminal for effect drive: 3rd pin Second effect drive means: LED driver 791
・Clock (CK) for the second effect driving means: clock signal CLK
Control data (DT) for effect drive for the second effect drive means: data signal DATA
・Input terminal of the clock in the second effect driving means: No. 2 terminal (SCLK terminal)
・Input terminal for control data for driving effect in the second effect driving means: No. 3 terminal (SDATA terminal)
・Second input connector: connector CN1XA
・Connector terminal for clock of the second input connector: 3rd pin ・Connector terminal for control data for effect drive of the 2nd input connector: 2nd pin

In this (Specific Example 9), the circuit configuration of the LED board 780 corresponding to the first board is as described with reference to FIGS. are placed.

FIG. 84 shows the circuit configuration of the LED board 790A corresponding to the second board.
FIG. 84 has the same electrical connection configuration as the LED substrate 780 of FIG. In this case, since the cross cable 2000 is used for connection, the connector CN1XA shown in FIG. 84 has the terminal assignments of the first to fourth pins reversed from those of the connector CN1X shown in FIG. That is, from the first pin, the ground terminal, the terminal for the data signal DATA, the terminal for the clock signal CLK, and the terminal for the 12V DC voltage (DC12VB) are arranged in order.
Also, the LED driver 791 in FIG. 84 and the LED driver 791 in FIG. 46 are assumed to be the same IC.

Therefore, the left-right relationship between the terminal for the data signal DATA and the terminal for the clock signal CLK is reversed between when viewed in the direction DIR64 and when viewed in the direction DIR65, as shown in FIG.

Therefore, in the example of FIG. 84, the LED driver 791 is arranged on a different surface from the connector CN1XA. For example, if the connector CN1XA is on the surface layer, the LED driver 791 is arranged on the back layer. Of course, the opposite is also possible.

Since the left-right relationship between the data signal DATA terminal and the clock signal CLK terminal is reversed, a cross occurs in the wiring as shown by the dashed line CRS in FIG. 84 in the circuit diagram.
In this case, since the connector CN1XA and the LED driver 791 are on different surfaces, the left-right relationship of the wiring is adapted to the LED driver 791 at the stage of wiring via the through hole TH as shown in FIG.

According to (Configuration A6-1) as in (Specific Example 9), the following effects are obtained.
Since the first board and the second board are connected by the cross cable 2000, the pin assignment of the second input connector must be reversed. When ICs with the same left-right relationship are used on the first and second substrates, efficiency of wiring, shortening of wiring length, reduction of noise mixture, and ease of design can be realized on the first and second substrates. .
On the first board, the left-right relationship of the output connector is matched with that of the first input connector, so that the wiring to the output on the first board is not complicated.
In the second board, the left-right relationship of the terminals of the second input connector and the second effect driving means is reversed, but the second input connector and the second effect driving means are formed on different surfaces, and wiring is performed before and after the through hole. , the wiring does not become complicated.
In the gaming machine 1, for example, FFC (Flexible Flat Cable), which is a cross cable, is mainly used for wiring to the movable body. In many cases, the same IC is used as an LED driver or a motor driver for the board (second board) inside the movable body and the board (first board) on the upstream side thereof. This configuration is effective in such a case.
For example, the above configuration is useful when the LED board 780 and the LED board 790A are connected via the movable portion of the movable body accessory.

It is also conceivable that the second effect driving means on the second board side is an IC in which the left-right relationship of the clock CK and data DT terminals is opposite to that of the first input connector and the first effect driving means.
In such a case, it is preferable to arrange the second input connector and the second effect drive means on the same surface of the second board.
By doing so, when the connector CN1XA whose terminal assignment order is reversed by using the cross cable 2000 and the second effect driving means are viewed from the directions DIR64 and DIR65 of the terminals of the clock CK and data DT, The left-right relationship is the same.
Therefore, pattern wiring on the same surface can be prevented from being complicated.

The gaming machine 1 of the embodiment has the following (configuration A7-1).
(Structure A7-1)
The game machine 1 is
A first effect driving means by chip parts, a first board provided with a first connector for inputting a clock for the first effect driving means, control data for driving effect, and a power supply voltage;
a second board provided with a second connector for inputting a clock for the second effect driving means, control data for driving effect, and a power supply voltage;
with
In the first substrate,
The first effect driving means and the first connector are arranged on the same surface of the substrate,
a left-right relationship when the chip side is viewed from the pattern wiring side of each input terminal of the clock, the control data for driving the effect, and the power supply voltage in the first effect driving means;
The left-right relationship of the connector terminals of the clock, the performance driving control data, and the power supply voltage in the first connector when viewed from the connector terminal side toward the derivation direction of the pattern wiring connected to the connector terminals. ,
are identical and
In the second substrate,
The left-right relationship of the connector terminals of the clock, the performance driving control data, and the power supply voltage in the second connector when viewed from the connector terminal side toward the lead-out direction of the pattern wiring connected to the connector terminals is , is the same as the first connector.

FIG. 85 schematically shows the structure of the first substrate and the second substrate.
In addition, "power supply voltage VC" refers to the power supply voltage supplied to the performance driving means.

A first connector and a first effect driving means are mounted on the first board.
The first connector and the first effect driving means are arranged on the same plane on the first substrate.
A first connector inputs a power supply voltage VC, a clock CK, and control data (data DT) for driving effects to the first effect driving means.
The power supply voltage VC, the clock CK and the data DT are supplied to the first effect driving means through the pattern wiring PTH on the substrate.

A second connector is mounted on the second substrate.
The second connector inputs the power supply voltage VC, the clock CK and the control data for driving the effect (data DT) to the second effect driving means.
In the figure, the second effect driving means is not shown on the second board, but it is either one of the following.
・The second effect driving means is mounted on the second substrate on the same surface as the second connector. ・The second effect driving means is mounted on the second substrate on a different surface from the second connector. 2 effect driving means is mounted on another board downstream from the second board

In this case, directions DIR71, DIR72, and DIR73 indicated by arrows are directions defined similarly to the above-described directions DIR1, DIR2, and DIR3, respectively.
The left-right relationship of the power supply voltage VC terminal, the clock CK terminal, and the data DT terminal when viewed in the directions DIR71, DIR72, and DIR73 is shown in the lower part of FIG. In this example, the power supply voltage VC terminal, the clock CK terminal, and the data DT terminal are arranged in the same order from left to right in the figure.
As an example corresponding to (configuration A7-1) as shown in FIG. 85, the following (specific example 10) is assumed.

(Specific example 10)
・First substrate: LED substrate 780 (see FIG. 45)
・Second substrate: LED substrate 790 (see FIG. 46)
・Power supply voltage for the first effect drive means: 12V DC voltage (DC12VB)
・Clock (CK) for the first effect driving means: Clock signal CLK
Control data (DT) for effect driving for the first effect driving means: data signal DATA
・First effect driving means: LED driver 782
・Input terminal for power supply voltage in the first effect driving means: No. 48 terminal (SVCC terminal)
・Input terminal of the clock in the first effect driving means: No. 2 terminal (SCLK terminal)
・Input terminal for control data for driving effect in the first effect driving means: No. 3 terminal (SDATA terminal)
・First connector: connector CN1N
・Connector terminal for power supply voltage of the first connector: 1st pin ・Connector terminal for clock of the first connector: 2nd pin ・Connector terminal for effect driving control data of the 1st connector: 3rd pin, 2nd Connector: Connector CN1X
・Connector terminal for power supply voltage of the second connector: 1st pin ・Connector terminal for clock of the second connector: 2nd pin ・Connector terminal for effect driving control data of the 2nd connector: 3rd pin

The LED board 780 corresponding to the first board in this (specific example 10) has been described with reference to FIGS. Also, the LED board 790 corresponding to the second board has been described with reference to FIGS. The terminal configuration of the LED driver 782 has been described with reference to FIG.

In this specific example, the horizontal relationships corresponding to the directions DIR71, DIR72, and DIR73 are all as shown in FIG. In the LED driver 782, the 48th terminal (SVCC terminal) is on a different side of the chip from the 2nd terminal (SCLK terminal) and the 3rd terminal (SDATA terminal). becomes.

In this configuration, it is possible to obtain the same effects as (configuration A1-1) described above (reduction of wiring length, improvement of wiring efficiency, reduction of noise mixture), and in addition, these effects can be obtained from the power supply wiring. .

Also, the gaming machine 1 of the embodiment has the following (configuration A7-2) in addition to (configuration A7-1).
(Structure A7-2)
The second board has second effect driving means by chip parts for inputting a clock and effect driving control data via pattern wiring from the second connector,
In the second substrate, the second effect driving means and the second connector are arranged on the same surface of the substrate,
The left-right relationship of the input terminals of the clock, the control data for driving the effect, and the power supply voltage in the second effect driving means is the same as that of the first effect driving means when the chip side is viewed from the pattern wiring side.

FIG. 86 schematically shows the first substrate and the second substrate in this (structure A7-2).
FIG. 86 is similar to FIG. 85 with respect to the first board, and differs in that the second board shows the second effect driving means. In the second board, the power supply voltage VC, the clock CK and the data DT are supplied from the second connector to the second effect drive means through the pattern wiring PTH on the board.
In this second substrate, the second light emission driving means and the second connector are arranged on the same surface. Direction DIR74 is a direction defined similarly to direction DIR14 above.

As an example corresponding to (configuration A7-2) in FIG. 86, in addition to the above (specific example 10), the following (specific example 11) is assumed.

(Specific example 11)
・Second effect driving means: LED driver 791
・Input terminal for power supply voltage in the second effect driving means: No. 48 terminal (SVCC terminal)
・Input terminal of the clock in the second effect driving means: No. 2 terminal (SCLK terminal)
・Input terminal for control data for driving effect in the second effect driving means: No. 3 terminal (SDATA terminal)

Note that the terminal configuration of the LED driver 791 is as described in FIG.
Accordingly, the LED board 790 corresponding to the second board has the following configuration.
・In the LED board 790, the connector CN1X and the LED driver 791 are arranged on the same surface of the board.
The left-right relationship of the SVCC terminal to which the 12V DC voltage (DC12VB) is input, the clock signal CLK terminal, and the data signal DATA terminal is as indicated by direction DIR74 in FIG. Therefore, the horizontal relationship in the directions DIR71, DIR72, DIR73, and DIR74 of the power supply voltage VC terminal, the clock CK terminal, and the data DT terminal are all the same.

Therefore, the configurations of (Concrete Example 10) and (Concrete Example 11) correspond to (Configuration A7-2) in FIG.
In this way, the second board adopts the same lateral relationship of the terminals as the first board, and by using a plurality of boards, it is possible to improve the efficiency of the wiring from the connector to the effect driving means, including the power supply voltage wiring. It is possible to improve the wiring efficiency of a plurality of boards in the game machine 1, reduce the noise mixture, and improve the design efficiency, thereby promoting stable performance operations.

The gaming machine 1 of the embodiment has the following (configuration A7-3) in addition to (configuration A7-1) and (configuration A7-2).
(Structure A7-3)
The game machine 1 is
A third board provided with a third connector for inputting a clock for the third performance driving means, control data for driving performance, and a power supply voltage,
The left-right relationship of the connector terminals of the clock, the effect driving control data, and the power supply voltage in the third connector when viewed from the connector terminal side toward the lead-out direction of the pattern wiring connected to the connector terminals is , is the same as the first connector.

FIG. 87 schematically shows the first substrate, the second substrate, and the third substrate in this (structure A7-3). The first substrate and the second substrate are the same as in FIG. 86, and the third substrate is added in FIG.

A third connector is mounted on the third board.
A pattern wiring PTH for a power supply voltage VC, a clock CK, and data DT is derived from the third connector.
In this figure, the third effect driving means is not shown on the third board, but it is one of the following.
・The third effect drive means is mounted on the third board on the same surface as the third connector. ・The third effect drive means is mounted on the third board on a different surface from the third connector. 3 effect driving means is mounted on another board downstream from the third board

Direction DIR75 is a direction defined similarly to direction DIR5 above.
The left-right relationship of the power supply voltage VC terminal, clock CK terminal, and data DT terminal when viewed in the directions DIR71, DIR72, DIR73, DIR74, and DIR75 is shown in the lower part of FIG. It's becoming

As an example corresponding to (Configuration A7-3) as shown in FIG. Example 12) is assumed.

(Specific example 12)
- Third board: relay board 760 (see FIG. 44)
・Clock (CK) for the third effect driving means: clock signal CLK_C
Control data (DT) for effect drive for the third effect drive means: data signal DATA_C
- Third connector: connector CN1M
・Power supply voltage connector terminals of the third connector: 1st pin, 2nd pin, 3rd pin ・Clock connector terminals of the 3rd connector: 6th pin ・Control data connector for effect drive of the 3rd connector Terminal: 9th pin

Considering the third effect driving means in (Specific Example 12), for example, an LED driver of an LED board (not shown) connected to the connector CN2M in FIG. 44 is assumed.

According to such (configuration A7-3), it is possible to improve the wiring efficiency in a plurality of substrates, reduce the noise mixture, and further improve the design efficiency. That is, the effects of (configuration A7-1) and (configuration A7-2) can be made more pronounced.

The gaming machine 1 of the embodiment has the following (configuration A8-1).
(Configuration A8-1)
The game machine 1 is
a first effect driving means by chip parts;
a second effect drive means by chip parts;
a connector for inputting a first system clock and effect driving control data for said first effect driving means and for inputting a second system clock and effect driving control data for said second effect driving means;
A first substrate provided with
In the first board, the first effect drive means, the second effect drive means, and the connector are arranged on the same plane,
the left-right relationship of the input terminals for the clock and the control data for driving effect in the first effect driving means when the chip side is viewed from the pattern wiring side;
a left-right relationship of each connector terminal for the clock of the first system and the effect drive control data in the connector when viewed from the connector terminal side toward the derivation direction of the pattern wiring connected to the connector terminal;
are identical and
a left-right relationship when the chip side is viewed from the pattern wiring side of each input terminal for the clock and the control data for driving the effect in the second effect driving means;
a left-right relationship of each connector terminal for the clock of the second system and the effect drive control data in the connector when viewed from the connector terminal side toward the derivation direction of the pattern wiring connected to the connector terminal;
are the same.

Also, the gaming machine 1 of the embodiment may have the following (configuration A8-2) in addition to (configuration A8-1).
(Configuration A8-2)
In the connector,
the left-right relationship of each connector terminal for the clock of the first system and the effect drive control data when viewed from the connector terminal side toward the lead-out direction of the pattern wiring connected to each connector terminal;
the left-right relationship of each connector terminal for the clock of the second system and the effect drive control data when viewed from the connector terminal side toward the lead-out direction of the pattern wiring connected to each connector terminal;
are identical.

Alternatively, the gaming machine 1 of the embodiment may have the following (configuration A8-3) in addition to (configuration A8-1).
(Structure A8-3)
In the connector,
the left-right relationship of each connector terminal for the clock of the first system and the effect drive control data when viewed from the connector terminal side toward the lead-out direction of the pattern wiring connected to each connector terminal;
the left-right relationship of each connector terminal for the clock of the second system and the effect drive control data when viewed from the connector terminal side toward the lead-out direction of the pattern wiring connected to each connector terminal;
is the opposite.

88 and 89 schematically show the structure of the first substrate (structure A8-1).
FIG. 88 is an example corresponding to (Configuration A8-1) or (Configuration A8-2).
FIG. 88 is an example corresponding to (configuration A8-1) or (configuration A8-3).

First, in FIG. 88, a connector, a first effect driving means, and a second effect driving means are mounted on the first board. The connector, the first effect driving means and the second effect driving means are arranged on the same surface on the first board.
The connector inputs a clock CK and control data (data DT) for driving effects to the first effect driving means. The clock CK and data DT are supplied to the first effect driving means through the pattern wiring PTH1.
The connector separately inputs the clock CK and the control data for driving the effect (data DT) for the second effect driving means. The clock CK and data DT are supplied to the second effect driving means through the pattern wiring PTH2.
The first effect driving means and the second effect driving means are shown by the same rectangles because the terminals of the clock CK and the data DT have the same left-right relationship.

In this case, directions DIR81-1 and DIR81-2 indicated by arrows are defined in the same manner as the direction DIR1 described above, and DIR82 and DIR83 are directions defined in the same manner as the direction DIR2.
The left-right relationship between the clock CK terminal and the data DT terminal when viewed in directions DIR81-1, DIR81-2, DIR82, and DIR83 is shown in the lower part of FIG. In this example, the clock CK terminal is arranged on the left side of the drawing, and the data DT terminal is arranged on the right side, and the left-right relationship is the same.

That is, the left-right relationship is the same when viewed in the directions DIR81-1 and DIR82, and the left-right relationship is the same when viewed in the directions DIR81-2 and DIR83.
・Since the left-right relationship is the same when viewed in the directions DIR81-1 and DIR81-2, it also corresponds to the configuration A8-2.

Next, FIG. 89 will be described. FIG. 89 has the same configuration as FIG. 88 in that the connector, the first effect driving means and the second effect driving means are arranged on the same plane on the first substrate.
However, in FIG. 89, the horizontal relationship between the clock CK terminal and the data DT terminal when viewed in the directions DIR81-1 and DIR82 is such that the left side of the figure is the clock CK terminal and the right side is the data DT terminal. On the other hand, the horizontal relationship between the clock CK terminal and the data DT terminal when viewed in the directions DIR81-2 and DIR83 is such that the data DT terminal is on the left side of the figure and the clock CK terminal is on the right side. ing.
Since the first effect drive means and the second effect drive means have different lateral relationships between the terminals of the clock CK and the data DT, the first effect drive means is indicated by a rectangle and the second effect drive means by an octagon. there is

That is, the left-right relationship is the same when viewed in the directions DIR81-1 and DIR82, and the left-right relationship is the same when viewed in the directions DIR81-2 and DIR83, so it corresponds to the configuration A8-1. Since the left-right relationship is reversed when viewed with DIR81-2, this also corresponds to configuration A8-3.

Specific examples of the above FIGS. 88 and 89 will be given.
First, the following (Specific Example 13) is assumed as a specific example of (Configuration A8-1) or (Configuration A8-2) in FIG.

(Specific example 13)
・First substrate: LED connection substrate 1500 (see FIGS. 50 to 57)
・Clock (CK) for the first effect driving means: clock signal LSI_SCK
・Effect drive control data (DT) for the first effect drive means: serial data signal LSI_MOSI
・First effect drive means: motor driver control unit 1530 (see FIG. 55)
・Input terminal of the clock in the first effect driving means: No. 5 terminal (SCK terminal)
・Input terminal for control data for driving effect in the first effect driving means: No. 7 terminal (MOSI terminal)
・Connector: Connector CN1V
Connector terminal for clock in first system of connector: 3rd pin Connector terminal for control data for driving effect in first system of connector: 7th pin Second effect driving means: motor driver 1505 (see FIG. 50). However, unlike the example shown in FIG. 72, the arrangement is an example arranged on the surface layer.)
・Clock (CK) for the second effect driving means: clock signal CLK_M
Control data (DT) for effect drive for the second effect drive means: data signal DATA_M
・Input terminal for the clock in the second effect driving means: No. 13 terminal (SCLK terminal)
・Input terminal for control data for driving effect in the second effect driving means: No. 14 terminal (SDIN terminal)
・Connector terminal for the clock of the second system of the connector: 23rd pin ・Connector terminal for the control data for driving the effect of the second system of the connector: the 25th pin

71 and 72, the motor driver 1505 is arranged on the back surface layer in the layout examples of the LED connection substrate 1500 shown in FIGS. Assume that the connector CN1V, the motor driver control unit 1530, and the motor driver 1505 are all arranged on the surface layer.

The left-right relationship of the 3rd pin and the 7th pin, which are the connector terminals of the clock CK and data DT of the first system of the connector CN1V, viewed in the direction DIR 83-1, and the 5th terminal (SCK terminal) and 7th terminal of the motor driver control unit 1530. The left-right relation of the number terminal (MOSI terminal) viewed in the direction DIR82 is the same as the left-right relation viewed in the directions DIR21 and DIR22 described above in the explanation of (configuration A3-1).

The left-right relationship of the 23rd and 25th pins, which are the connector terminals for the clock CK and data DT, of the second system of the connector CN1V when viewed in the direction DIR83-2 is as follows. Become.
As shown in FIG. 51, the motor driver 1505 inputs the clock signal CLK_M to the 13th terminal (SCLK terminal) and the data signal DATA_M to the 14th terminal (SDIN terminal). , the terminal for clock CK is on the left and the terminal for data DT is on the right.

From the above, it is understood that the above (specific example 13) has the configuration shown in FIG.
In the case of this (structure A8-1), in addition to obtaining the same effects (reduction of wiring length, improvement of wiring efficiency, reduction of noise mixture) as the above-described (structure A1-1), the following effects are obtained.

First, since efficient wiring can be realized for the clock CK and the data DT of the first and second systems, the same effect as (structure A1-1) becomes remarkable.
Also, in the case of (Configuration A8-1), the connector has a state in which the pin arrangements of the clock CK and data DT of multiple systems match the respective drivers, so that crosses and detours can be prevented from occurring in each system. , the wiring from the connector to each performance driving means can be made efficient. This is also suitable for reducing noise contamination. Therefore, this configuration is effective for a substrate in which a plurality of effect driving means are arranged on the same surface as the connector.

Further, (structure A8-2) is suitable for a case where terminals of the clock CK and the data DT have the same left-right relationship as a plurality of effect driving means.
In addition, since the left-right relationship of the pin assignment is unified between the first system and the second system in the connector, there is an advantage that the design can be made more efficient.

Next, (Specific Example 14) will be given as a specific example of (Structure A8-1) or (Structure A8-3). In (Specific Example 14), the first board is the same LED connection board 1500, the connector is the connector CN1V, the motor driver control section 1530 is mentioned as the first effect driving means, and the first system is the above (Specific Example 13). ).

(Specific example 14)
・Second effect driving means: LED drivers 1510, 1511, 1520, 1521, 1522 (see FIGS. 52, 53, and 54. However, unlike the example in FIG. 72, they are arranged in the surface layer.)
・Clocks for the second effect drive means: clock signals CLK_A, CLK_B
・Effect drive control data for the second effect drive means: data signals DATA_A, DATA_B
・Input terminal for the clock in the second effect driving means: No. 48 terminal (SCLK terminal)
・Input terminal for control data for driving effect of the second effect driving means: No. 47 terminal (SDATA terminal)
・Connector: Connector CN1V (however, the pin assignment is different from that shown in Fig. 50)
・Connector terminal for the clock of the second system of the connector: 15th pin (an example different from that shown in FIG. 50)
・Connector terminal of the control data for driving the effect drive of the second system of the connector: 13th pin (example different from FIG. 50)

FIG. 50 shows an example in which the 13th pin of the connector CN1V is assigned to the clock signal CLK_P (=CLK_A) and the 15th pin is assigned to the data signal DATA_P (=CLK_B). This is an example of assignment. In other words, the 15th pin is assigned to the clock signal CLK_P (=CLK_A), and the 13th pin is assigned to the data signal DATA_P (=CLK_B).
In this case, when viewed from the direction DIR81-2 in FIG. 89, the connector terminal for the data DT is on the left and the connector terminal for the clock CK is on the right.

53 will be used as a representative example of the second effect driving means. As for the left-right relationship between the clock CK and data DT terminals as terminals (SDATA terminals), when viewed in the direction DIR83 of FIG. 89, the data DT terminal is on the left and the clock CK terminal is on the right. . Assume that such an LED driver 1521 is arranged on the same surface as the connector CN1V.

Then, (specific example 14) has the configuration shown in FIG.
In the case of this (configuration A8-3), in addition to the same effect as the above-described (configuration A8-1), a plurality of performance driving means having clock terminals and data terminals with opposite left-right relationships are arranged on the same surface. In such a case, the effect that pattern wiring can be made more efficient can be obtained by dealing with the problem on the connector side.

In (Specific Example 14), the first system is the drive system for the motor, and the second system is the drive system for the LED. In this way, (configuration A8-1), (configuration A8-2), and (configuration A8-3) are also suitable when motor presentation driving means and light emitting presentation driving means are arranged as a plurality of presentation driving means.
In particular, the motor effect drive means and the light effect drive means may have different systems for the clock CK and the data DT, thereby making it possible to further diversify the light effect and effects such as accessories. In such a case, when the left-right relationship of the terminals of the clock CK and the data DT is reversed between the IC of the motor effect driving means and the IC of the light emitting effect driving means arranged on the same surface, the first system on the connector side is used. As the assignment of the second system, by reversing the left-right relationship of the respective connector terminals of the clock CK and the data DT, it is possible to realize efficient wiring.

The gaming machine 1 of the embodiment has the following (configuration A9-1).
(Configuration A9-1)
The game machine 1 is
a first effect driving means by chip parts;
a second effect drive means by chip parts;
an input connector for inputting a first system clock and effect driving control data for the first effect driving means and for inputting a second system clock and effect driving control data for the second effect driving means;
A first substrate provided with
In the first substrate,
The first effect driving means is arranged on the same plane as the input connector,
The second effect driving means is arranged on a different plane from the input connector,
the left-right relationship of the input terminals for the clock and the control data for driving effect in the first effect driving means when the chip side is viewed from the pattern wiring side;
The left-right relationship of each connector terminal for the clock of the first system and the effect drive control data in the input connector when viewed from the connector terminal side toward the lead-out direction of the pattern wiring connected to each connector terminal. ,
The left-right relationship of each connector terminal for the clock of the second system and the effect drive control data in the input connector when viewed from the connector terminal side toward the lead-out direction of the pattern wiring connected to each connector terminal. ,
are identical and
A gaming machine in which the left-right relationship of the input terminals for the clock and the control data for driving the effect in the second effect drive means is opposite to that of the first effect drive means when the chip side is viewed from the pattern wiring side.

FIG. 90 schematically shows the configuration of this first substrate.
An input connector, first performance driving means and second performance driving means are mounted on the first substrate.
The input connector and the first effect drive means are arranged on the same plane on the first substrate (in the figure, the blocks of the first connector and the first effect drive means are both indicated by solid lines).
The input connector and the second effect driving means are arranged on different surfaces on the first substrate (in the figure, the second effect driving means is indicated by a broken line, and is arranged on the back side of the connector shown by a solid line). indicates that
Further, the second effect drive means is indicated by an octagon to indicate that it is a chip in which the terminals of the clock CK and the data DT are different from the first effect drive means indicated by rectangles. In addition, since it is the back surface, the characters "CK" and "DT" of the second effect driving means are mirror-reversed.

The input connector inputs the clock CK of the first system and the control data for driving the effect (data DT) to the first effect driving means. The clock CK and data DT of the first system are supplied to the first effect driving means through the pattern wiring PTH1 on the substrate.
Also, the input connector inputs the second system clock CK and the control data for driving the effect (data DT) to the second effect driving means. The clock CK and data DT of the second system are supplied to the second effect driving means through the pattern wiring PTH2 on the substrate. The pattern wiring PTH2 is formed over both surfaces through the through holes TH.

In this case, directions DIR91-1 and DIR91-2 indicated by arrows are defined in the same manner as the direction DIR1 described above, and DIR92 and DIR93 are defined in the same manner as the directions DIR52 and DIR53 described in FIG. direction.
The left-right relationship between the clock CK terminal and the data DT terminal when viewed in the directions DIR91-1, DIR91-2, DIR92, and DIR93 is shown at the bottom of FIG. In this example, when viewed in directions DIR91-1, DIR91-2, and DIR92, the clock CK terminals are arranged on the left side of the drawing, and the data DT terminals are arranged on the right side. On the other hand, when viewed from the DIR 93, the clock CK terminal is arranged on the right side of the figure, and the data DT terminal is arranged on the left side.

As an example corresponding to (configuration A9-1) shown in FIG. 90, the following (specific example 15) is assumed.

(Specific example 15)
・First substrate: LED connection substrate 1500 (see FIGS. 50 to 57)
・Clock (CK) for the first effect driving means: clock signal LSI_SCK
・Effect drive control data (DT) for the first effect drive means: serial data signal LSI_MOSI
・First effect drive means: motor driver control unit 1530 (see FIG. 55)
・Input terminal of the clock in the first effect driving means: No. 5 terminal (SCK terminal)
・Input terminal for control data for driving effect in the first effect driving means: No. 7 terminal (MOSI terminal)
・Input connector: Connector CN1V
・Connector terminal for the clock of the first system of the input connector: 3rd pin ・Connector terminal for control data for driving the effect of the first system of the input connector: 7th pin 1520, 1521, 1522 (see FIGS. 52, 53 and 54)
・Clock (CK) for the second effect drive means: clock signals CLK_A, CLK_B
・Effect drive control data (DT) for the second effect drive means: data signals DATA_A, DATA_B
・Input terminal for the clock in the second effect driving means: No. 48 terminal (SCLK terminal)
・Input terminal for control data for driving effect of the second effect driving means: No. 47 terminal (SDATA terminal)
・Connector terminal for the clock of the second system of the input connector: Pin 13 ・Connector terminal for the control data for driving the effect of the second system of the input connector: Pin 15

Since each of these components overlaps the description of (Specific Example 8) mentioned in (Configuration A5-1) above, repeated description will be avoided, but (Specific Example 15) is schematically shown in FIG. It corresponds to the configuration shown.
In the case of this configuration, in addition to obtaining the same effects (reduction of wiring length, improvement of wiring efficiency, reduction of noise mixture) as (configuration A1-1) described above, the following effects are obtained.

That is, in (Configuration A9-1), when a board has a plurality of pairs of clock CK and data DT in one input connector, and the left-right relationship of each terminal of the clock CK and data DT of the effect driving means is reversed, the connector Assignment of the terminals adopts a configuration that matches the first effect driving means that is on the same surface.

For example, when using old and new driver chips as multiple production driving means, by placing driver chips with opposite left-right relationships on the back side of the input connector, wiring crosses and detours in each system are prevented. Thus, wiring from the input connector to each performance driving means can be made efficient. It is also suitable for reducing noise contamination.
In addition, since the left-right relationship of the pin assignment is unified between the first system and the second system in the input connector, design efficiency can be improved.

Further, the gaming machine 1 of the embodiment has the following (configuration A9-2) in addition to (configuration A9-1).
(Configuration A9-2)
The first board has an output connector for outputting a clock and control data for driving performance,
In the first substrate,
the output connector is arranged on the same plane as the input connector;
a left-right relationship of each connector terminal for the clock and effect drive control data in the input connector when viewed from the connector terminal side toward the lead-out direction of the pattern wiring connected to each connector terminal;
a left-right relationship of each connector terminal for the clock and effect drive control data in the output connector when viewed from the pattern wiring side connected to each connector terminal toward the direction of each connector terminal;
are identical.

FIG. 91 schematically shows the first substrate in this (configuration A9-2). The configuration is the same as that of FIG. 90 except that it has an output connector.
The output connector in FIG. 91 is a connector for transmitting clock CK and data DT to downstream boards.
The direction DIR 94 is the direction when the direction of each connector terminal is viewed from the pattern wiring side connected to each connector terminal of the output connector. , and the data DT terminals are arranged on the right. That is, it is the same as the left-right relationship when viewed in directions DIR91-1, DIR91-2, and DIR92.

As a specific example, the following (Specific example 16) regarding the output connector may be added to the above (Specific example 15).

(Specific example 16)
・Output connector: Connector CN2V (see Fig. 50)
・Output connector clock connector terminal: 3rd pin ・Input connector connector terminal for effect drive control data: 5th pin

In the case of the connector CN2V, the horizontal relationship between the terminals of the clock signal CLK_C and the serial data signal DATA_C viewed from the direction DIR 94 is as shown in FIG.
Accordingly, the LED connection board 1500 having the configurations of (Specific Example 15) and (Specific Example 16) has the configuration of FIG.
According to such (configuration A9-2), it is possible to improve the efficiency of wiring including the wiring up to the output connector on the first board.

The gaming machine 1 of the embodiment has the following (configuration A9-3) in addition to (configuration A9-1) and (configuration A9-2).
(Configuration A9-3)
A second board provided with an input connector for inputting a clock for the third effect drive means and control data for effect drive,
The left-right relationship of each connector terminal for the clock and effect drive control data in the input connector of the second substrate when viewed from the connector terminal side toward the lead-out direction of the pattern wiring connected to each connector terminal is as follows: It is the same as each connector terminal of the clock of the first system in the input connector of the first board and the control data for effect driving.

FIG. 92 schematically shows the first substrate in this (configuration A9-3). Note that the configuration of the first substrate in FIG. 92 is the same as in FIG.

An input connector for inputting a clock CK and data DT to the third effect driving means is mounted on the second board. A pattern wiring PTH for the clock CK and data DT is derived from this input connector.

In this figure, the third effect drive means is not shown on the second board, but it is either one of the following.
・The third effect driving means is mounted on the second substrate on the same surface as the input connector ・The third effect driving means is mounted on the second substrate on a different surface from the input connector ・Third effect driving Means are mounted on another substrate downstream from the second substrate

A direction DIR95 is a direction of the input connector on the second substrate viewed from the connector terminal side of the clock CK and the data DT toward the lead-out direction of the pattern wiring PTH connected to each connector terminal. In this example, the terminal for the clock CK is on the left and the terminal for the data DT is on the right.

The horizontal relationship between the clock CK terminal and the data DT terminal when viewed in the directions DIR91-1, DIR91-2, DIR92, DIR93, DIR94, and DIR95 is shown at the bottom of the figure. The left-right relationship of the terminals of DT is the same except when viewed in the direction DIR93.

As an example corresponding to (configuration A9-3) as shown in FIG. Example 17) is assumed.

(Specific example 17)
・Second substrate: LED substrate 1600 (see FIG. 58)
・Input connector of the second substrate: connector CN1W
・Connector terminal for the clock in the input connector of the second substrate: 2nd pin ・Connector terminal for control data for effect drive in the input connector of the second substrate: 5th pin

In the case of the connector CN1W, the lateral relationship between the terminals of the clock signal CLK and the data signal DATA viewed from the direction DIR95 is as shown in FIG.
Accordingly, the game machine 1 having the LED connection board 1500 and the LED board 1600 having the configurations of (Specific Example 15), (Specific Example 16) and (Specific Example 17) has the configuration of FIG.
According to such (configuration A9-3), there is an advantage that the design can be made more efficient by sharing the assignment of the clock CK and the data DT of the input connector between the first board and the second board.

(Configuration A1-1) to (Configuration A9-3) have been described so far, and the following (Configuration A100) (Configuration A101) (Configuration A102) (Configuration A103) are applied to each of these configurations. can do.

(Configuration A100)
The chip parts in (configuration A1-1) to (configuration A9-3) above are surface-mounted chips.

In (Configuration A1-1) to (Configuration A9-3) described above, the first effect drive means, the second effect drive means, and the third effect drive means are mentioned as chip parts. The effect drive means includes light emission drive means and motor drive means.

That is, the chip parts are, for example, the LED drivers 782 and 791 in (Specific Example 1). The LED drivers 782 and 791 described in FIG. 62 are surface mount chips. It can be seen from the pad shapes of "p782" in FIG. 60 and "p791" in FIG. 63 that they are surface mount chips.

Motor driver control unit 1530, S/P conversion circuit 606, LED driver 1601, LED drivers 1510, 1511, 1520, 1521, 1522, motor driver 1505, etc. are also illustrated as the effect driving means. These are also surface mount chips.

Dip parts that are not surface-mounted, that is, chips that fix leads through holes (vias/through-holes) in the board are left-right reversed on the back side of the board so that the left-right relationship between the connector and the effect drive means terminals. However, surface-mounted chips cannot.
That is, when a surface-mounted chip is used as the performance driving means, if the left-right relationship between the clock CK and the data DT is reversed between the connector and the performance driving means, useless wiring paths increase and the wiring becomes complicated. end up
In view of this point, when surface-mounted chips are used as the first effect driving means and the second effect driving means, etc., the effects of (Configuration A1-1) to (Configuration A9-3) become remarkable. understood.

(Configuration A101)
The chip components in (configuration A1-1) to (configuration A9-3) are substantially rectangular chips having terminals on four sides.

Effect drive means (light emission drive means, The chip exemplified as the motor driving means) is a substantially rectangular chip having terminals formed on four sides.

For example, the LED drivers 782 and 791 are substantially rectangular chips having terminals formed on four sides as described in FIG. Also, the LED driver 1601 and the like are also substantially rectangular chips having terminals formed on four sides as described with reference to FIG.

In the case of a square chip with terminals formed on each of the four sides, even if the wiring is wrapped around, it is impossible or difficult to deal with the case where the left-right relationship of the terminals between the connector and the LED driver is reversed. . This is because wiring to other terminals will be obstructed if an attempt is made to reverse the left-right relationship by wrapping the wiring.
In other words, in the case of a chip having terminals formed on four sides, if one of the configurations (configuration A1-1) to (configuration A9-3) is adopted, the wiring is wrapped around and the left-right relationship is reversed. It is no longer necessary to deal with , and the effect of improving the wiring efficiency becomes remarkable.

(Configuration A102)
The first substrate, the second substrate, the third substrate, etc. in (Configuration A1-1) to (Configuration A9-3) described above are substrates with two-layer wiring on the front surface and the rear surface of the substrate.

For example, the LED connection board 1500 corresponding to the first board of (Configuration A4-1) is a two-layer wiring board with a front surface and a rear surface of the substrate as described with reference to FIGS. The LED board 1600, which corresponds to the second board, is also a two-layer wiring board consisting of the front surface and the back surface of the substrate, as described with reference to FIGS.

A substrate with two-layer wiring on the front and back surfaces is less expensive than a substrate with multilayer wiring provided with an inner layer. On the other hand, since there are only two layers for forming pattern wiring, more efficient pattern design is required. In such a case, the techniques of (configuration A1-1) to (configuration A9-3) are effective, and can promote cost reduction of the substrate.

(Configuration A103)
In the above (configuration A1-1) to (configuration A9-3), the clock CK and data DT from the connector pass through a buffer circuit that does not change the left-right relationship between the clock CK and data DT and the effect drive means (light emission drive means , motor driving means).
In this case, the buffer circuit is a chip component, and the fact that the left-right relationship is not changed means that
・The left-right relationship of the input terminals for the clock and control data for driving the effect in the buffer circuit when viewed from the pattern wiring side to the chip side,
The left-right relationship of each output terminal of the clock and effect drive control data in the buffer circuit when viewed in the derivation direction of the pattern wiring connected to each output terminal,
are the same.

For example, the buffer circuits 1501, 1502, 1503, etc. in FIG. 50 have such a configuration. Then, in configurations such as (configuration A3-1) (configuration A5-1), etc., in which the LED connection board 1500 is used as a specific example, the clock CK and the data DT are supplied to the effect driving means via the buffer circuit.

By doing so, signal compensation of the clock CK and the data DT is performed on the board, and stable signal transmission is realized on the board. It also improves noise immunity.
Since the left-right relationship is not changed between the input terminal and the output terminal of the buffer circuit, the effects of the configurations (configuration A1-1) to (configuration A9-3) can be obtained.

[7.2 Slave address]
In the gaming machine 1 of the embodiment, setting of a slave address for the effect driving means as a chip component mounted on the substrate will be described.

The gaming machine 1 of the embodiment has the following (configuration B1-1).
(Configuration B1-1)
The game machine 1 is
having a plurality of performance driving means of the same configuration by chip parts having a substantially square shape and having terminals formed on two or more sides;
The production driving means is
X terminals formed with consecutive terminal numbers from the first side to the second side, which are two consecutive sides, are used as address terminals for setting slave addresses,
(x1) address terminals are formed on the first side,
(x2) address terminals are formed on the second side,
(x1) + (x2) = X and (x1) < (x2),
All of the plurality of the effect driving means are at least one of (x2) address terminals on the second side, and a specific address terminal common to the plurality of the effect driving means is at least one. Set to L level. However, X, x1, and x2 are natural numbers.

It should be noted that a plurality of effect driving means having the same configuration may be interpreted in any of the following ways.
・Plural effect driving means by the same IC chip (IC chip of the same model number) ・Plural effect driving means by IC chips having the same number of terminals for setting slave addresses even if they are not all the same IC chip

From the point of view of the same configuration as above, for example, the gaming machine 1 may include effect drive means (for example, LED drivers) having “different configurations”. In such a case, the "different configuration" effect drive means is not included in "all of the plurality of effect drive means" in (configuration B1-1). In other words, (configuration B1-1) defines the configuration of a plurality of performance drive means having the same configuration.
Also, this "all" has the meaning of all of the performance driving means that are individually assigned slave addresses and are distinguished from each other. Therefore, it does not necessarily refer to all the effect driving means in the game machine 1. ``All of the plurality of effect drive means'' means a plurality of identically-configured means for receiving a effect control signal of one channel from at least one effect control means (for example, the effect control board 30) and driving the effect. It means that all of the performance driving means of
The above meanings of "same configuration" and "all" are the same for (configuration B2-1) and (configuration B3-1) described later.

Examples of slave address setting include LED drivers 1510, 1511, 1520, 1521, and 1522 (FIGS. 52, 53, and 54) of LED connection board 1500 and LED driver 1601 of LED board 1600 (FIG. 58).

The terminal arrangement of LED drivers 1510, 1511, 1520, 1521, 1522 and 1601 is as shown in FIG. 80A.
80A, the 1st terminal (SVCC) to the 12th terminal (A1) are provided on the side sd21, the 13th terminal (A2) to the 24th terminal (LEDR3) are provided on the side sd22, and The 25th terminal (LEDG3) to the 36th terminal (LEDG6) are provided, and the 37th terminal (LEDB6) to the 48th terminal (SCLK) are provided on the side sd24.

Terminal 1 (SVCC) is a power supply terminal.
A second terminal (VREF) is an output terminal for a 5V reference voltage.
A third terminal (CTLSCT) is a setting terminal for serial signal control.
A fourth terminal (CTLSCT) is a setting terminal for the LED output method.
A fifth terminal (RESET) is a reset signal input terminal.
The 6th terminal (Ilef_B), the 7th terminal (Ilef_G), and the 8th terminal (Ilef_R) are resistor connection terminals for setting the B, G, and R LED currents.
A ninth terminal (SGND) is a ground terminal.
The 10th terminal is used as a test terminal and is grounded.

Terminals 11 to 16 (A0 to A5) are address terminals for setting slave addresses. In this case, it is possible to set the slave address with 6 bits.

Between the 17th terminal and the 44th terminal (excluding the 34th terminal), terminals for LED emission driving current (LEDR1 to LEDB8) and ground terminals for LED output (PGND1 to PGND3) are formed.
A 34th terminal (LVCC) is a terminal for a protection circuit power source for LED output terminals.

A 45th terminal (SDO) is a dummy terminal.
A 46th terminal (SDEN) is an input terminal for an enable signal.
A 47th terminal (SDATA) is an input terminal for the data signal DATA.
A 48th terminal (SCLK) is an input terminal for the clock signal CLK.

Here, the slave addresses of the LED drivers 1510, 1511, 1520, 1521, 1522, and 1601 set by the 11th to 16th terminals (A0 to A5) are known from FIGS. so that:
The 11th terminal (A0) is the LSB (least significant bit), and the 16th terminal (A5) is the MSB (most significant bit). A bit corresponding to a terminal connected to the ground is set to "0", and a bit corresponding to a terminal connected to a VREF terminal (terminal 2) with a reference voltage of 5V is set to "1".

LED driver 1510: 000111 (see Figure 52)
LED driver 1511:001000 (see FIG. 52)
LED driver 1520:001001 (see FIG. 53)
LED driver 1521:001010 (see FIG. 53)
LED driver 1522:001011 (see FIG. 54)
LED driver 1601:001100 (see FIG. 58)

Although the above is an example, six of the LED drivers on the board arranged on the game board 3 side of FIG. 49 are shown here. There are also LED drivers mounted on substrates (not shown).
A plurality of LED drivers are also mounted on the board arranged on the door 6 side in FIG.

The effect control board 30 of FIG. 49 performs serial data transmission to the game board 3 side and the door 6 side using two channels as serial data output channels.
A clock and serial data, that is, the clock CK and data DT are transmitted from the performance control board 30 to the plurality of LED drivers on the game board 3 side through the transmission line H50. This serial data output channel to the game board 3 side is referred to as a first channel.
A plurality of LED drivers on the side of the door 6 are transmitted with a clock and serial data, that is, the above-mentioned clock CK and data DT from the performance control board 30 through the transmission line H6. This serial data output channel to the door 6 side is referred to as a second channel.

In the following description, it is assumed that the LED drivers of the first channel and the second channel use driver ICs (for example, the IC in FIG. 80A) in which slave addresses are set with 6 bits.

In the gaming machine 1 of the present embodiment, slave addresses are set as shown in FIG. 93 for a plurality of LED drivers.
In FIG. 93, the slave address is shown in decimal notation, hexadecimal notation, and 6-bit notation from bit (A5) to bit (A0).

In this example, "0" to "15" in decimal notation are slave addresses assigned to the LED driver of the first channel, and "16" to "31" are assigned to the LED driver of the second channel. "32" to "63" are unused.
Thereby, slave addresses can be assigned to 16 LED drivers in the first channel and the second channel, respectively.

In this way, all bits (A5) can be set to "0". In other words, the 16th terminal (A5) can be set to "0" for all LED drivers having the same configuration in the first channel and the second channel.

However, this does not mean that the slave address that can be set with 6 bits is simply used with 5 bits from bit (A4) to bit (A0).
If 5 bits are used, for example, all bits (A0) may be set to "0", or all bits (A1) may be set to "0". Similarly, bit (A2) or bit (A3) may be used. In other words, slave addresses can be set corresponding to the number of LED drivers without using any one of bits (A5) to (A0).

Under these circumstances (structure B1-1), when using the LED drivers with the terminal arrangement of FIG. Adopt a design policy of setting one of A2) to “0”. FIG. 93 is an example of selecting bit (A5).

Hereinafter, the LED drivers 1510, 1511, 1520, 1521, 1522, 1601 and other LED drivers (not shown) are referred to as "LED drivers 1510, etc.".
As shown in FIG. 80A, the LED driver 1510 and the like have six terminals (terminals 11 to 16 (terminal A0 ~A5 pins)) are used as address pins for setting the slave address.

Since side sd1 has terminals A0 and A1, and side sd2 has terminals A2 to A5, X, x1, and x2 in (Configuration B1-1) are X=6, x1=2, and x2=4. be.
At least one address terminal (for example, A5 terminal) common to all LED drivers 1510 and the like on side sd2 is set to L level.

The connection state of the address terminals of the LED drivers 1510, 1511, 1520, 1521, 1522 and 1601 is schematically shown in FIG.
A reference voltage from the VREF terminal is applied to the terminal of the bit set to H level (“1”) in the slave address.
A terminal of a bit set to L level (“0”) in the slave address is grounded.
FIG. 94 shows the connection state for realizing the slave address values described above. The pattern wiring on the back side of the mounting surface is shown.
For example, the ground is wired to the solid ground on the chip mounting surface of the LED driver 1510 or the like, and the wiring pattern varies depending on the shape of the solid ground, and each terminal is necessarily connected in a common pattern. It is not necessary, and it is sufficient if the pattern is formed with a short path to the solid ground.

An example of wiring for the reference voltage for setting the H level (“1”) of the slave address as indicated by the broken line in FIG. 94 is shown.
Although the LED drivers 782, 791, and 631 differ in the number of slave address terminals from the LED driver 1510 and the like, the reference voltage wiring shown by the dashed lines in FIG. 63 and 64, and the LED board 630 on the side unit in FIGS.
As shown in FIG. 62, these LED drivers 782, 791 and 631 have a VREF terminal as the 1st terminal and 11th to 15th terminals (A0 to A4 terminals) as address terminals for setting slave addresses.

In the case of the LED board 780, from the first terminal of the LED driver 782, the reference voltage wiring 789a (FIG. 60), the through hole TH50 (FIGS. 60 and 61), the reference voltage wiring 789b (FIG. 61), the through hole TH51 (FIGS. 60), and the H level (“1”) of the slave address is set in the reference voltage wiring 789a (FIG. 60).

In the case of the LED board 790, from terminal 1 of the LED driver 791, reference voltage wiring 799a (FIG. 63), through-hole TH60 (FIGS. 63 and 64), reference voltage wiring 799b (FIG. 64), through-hole TH61 (FIGS. 63), and the reference voltage wiring 799c (FIG. 63) sets the H level (“1”) of the slave address.

In the case of the LED board 630 on the side unit, from the first terminal of the LED driver 631, the reference voltage wiring 639a (FIG. 67), the through hole TH70 (FIGS. 67 and 66), the reference voltage wiring 639b (FIG. 66), the through hole TH71 ( 66 and 67) and the reference voltage wiring 639c (FIG. 67), the H level ("1") of the slave address is set.

Each of the LED drivers 1510 and the like in FIG. 94 also has a slave address set by pattern wiring on the chip mounting surface and its back surface, like the examples of the LED drivers 782, 791, and 631 described above.

In the example of FIG. 94, the A5 terminal is grounded.
Such a configuration is realized as follows.
First, where it is possible to set, for example, an address of X bits (or X×Y bits if one terminal can set Y bits) with X terminals, a slave address is set with (X−1) terminals. For this purpose, the total number of LED drivers 1510 and the like for all channels is desirably set to a number capable of setting slave addresses with (X-1) terminals.

However, setting the total number of LED drivers 1510 and the like to (X−1) or less may be considered as the total number in at least one serial data output channel.
The example of FIG. 93 is just an example in which the number of LED drivers 1510 and the like is 32 or less in total for the first channel and the second channel (that is, in all channels), but the present invention is not limited to this.
Since the first channel and the second channel are independent as serial data communication channels, there is no problem even if the same slave address exists between the first channel and the second channel. Therefore, in at least one channel, the number of terminals of the LED driver 1510 and the like should be (X-1) so that the slave address can be set.

Then, when setting the slave address with (X-1) terminals, on the second side (side sd2 in the above example) where the number of address terminals is larger, a specific terminal (for example, A5 terminal) is set to L level. set. This setting is commonly set for all LED drivers to which slave addresses are assigned within at least one serial data output channel. The example of FIG. 93 is an example in which all the LED drivers 1510 and the like are set in common over the first channel and the second channel.

By setting the slave address so that one common terminal is set to the L level on the side sd2 having the larger number of terminals in this way, it is possible to provide a margin for the wiring around the LED driver 1510 and the like. easier. This makes it possible to improve wiring efficiency and facilitate wiring design.
Although the wiring around each LED driver differs depending on the slave address value and the peripheral circuit, at least one side on the sd2 side where there are many address wirings is fixed to the L level to generate an LED driver that facilitates the wiring. You can increase your odds.

Note that the first side and the second side referred to in (Configuration B1-1) to (Configuration B3-3) described later are not limited to sides sd1 and sd2. It may be the sides sd2 and sd3, the sides sd3 and sd4, or the sides sd4 and sd1.
Also, the first side and the second side are not arranged in the order of the terminal numbers. In some cases, the first side corresponds to side sd2 and the second side corresponds to side sd1.
In (structure B1-1), the first side and the second side are continuous sides, and the side with the greater number of address terminals is the second side.
Also, the present invention is not limited to an IC chip having terminals on four sides.

For example, in the configuration of FIG. An example using a driver IC chip that is set by bits has been given.
Even when such a driver IC chip is used, the idea of (structure B1-1) can be realized by setting a terminal common to a plurality of LED drivers to L level.

By the way, in the LED driver 1510 and the like in the above example, it was said that all LED drivers adopt the design policy of setting one of the bits (A5) to (A2) to "0". Most preferably, bit (A5) is "0".
This is because the A5 terminal is the farthest from the VREF terminal and the corner of the A5 to A2 terminals, so when this terminal goes high, the wiring length of the reference voltage becomes the longest. . In order to shorten the wiring length of the reference voltage as much as possible, it is desirable to set the bit (A5) to "0" so that the A5 terminal is grounded regardless of the LED driver.

It should be noted that the plurality of effect driving means in the gaming machine 1 of the above (configuration B1-1) includes those based on chip parts mounted on the first board and those based on chip parts mounted on the second board. .

Among the LED drivers 1510 and the like mentioned above, the LED drivers 1510, 1511, 1520, 1521, and 1522 are chip parts mounted on the LED connection board 1500, and the LED driver 1601 is a chip part mounted on the LED board 1600. is. Therefore, the LED connection board 1500 and the LED board 1600 can be used as the first board and the second board.

In this way, one terminal on the second side of the effect driving means on a plurality of boards is commonly set to the L level, thereby promoting efficiency of wiring on the plurality of boards and facilitation of wiring design.

The gaming machine 1 of the embodiment has the following (configuration B2-1).
(Configuration B2-1)
The game machine 1 is
having a plurality of performance driving means of the same configuration by chip parts having a substantially square shape and having terminals formed on two or more sides;
The effect driving means includes an address terminal for setting a slave address, which is a plurality of terminals having consecutive terminal numbers extending from the first side to the second side, which are two consecutive sides, and an address terminal formed on the first side. and a set voltage terminal for setting to H level,
At least one of the address terminals on the second side of all of the plurality of the effect driving means and a specific address terminal common to the plurality of the effect driving means is set to L level.

It should be noted that the meanings of "same configuration" and "all" in this case are as described in the explanation of (configuration B1-1) above, and do not necessarily refer to all the effect drive means in the gaming machine 1. .

A specific example will be described with the LED driver 1510 and the like in FIG. 80A as well.
A set voltage terminal is a VREF terminal that is an output terminal for a 5V reference voltage.
Therefore, in this case, the first side is side sd1 and the second side is side sd2.
Then, according to the example of FIG. 93, the A5 terminal on side sd2 is set to L level.

By doing so, it is easy to facilitate the wiring from the VREF terminal to the side sd2. This is because there is no wiring up to at least the A5 terminal. Therefore, it is possible to improve wiring efficiency and facilitate wiring design.
In particular, by making it a terminal (bit) on the side sd2 side, wiring of the VREF terminal on the side sd2 side may become unnecessary depending on the assigned slave address value. Therefore, the number of substrates that can facilitate wiring for setting slave addresses can be increased in the gaming machine 1 as a whole.

The gaming machine 1 of the embodiment has the following (configuration B2-2) in addition to (configuration B2-1).
(Configuration B2-2)
The address terminal to be set to H level and the set voltage terminal are connected on the substrate via pattern wiring on a surface different from the mounting surface of the effect driving means,
The address terminal set to L level is connected to the ground of the mounting surface.

As described with reference to FIG. 94, the L level terminal is connected to the solid ground on the mounting surface of the chip such as the LED driver 1510, and the H level terminal is wired using the back surface of the chip mounting surface. By doing so, H-level wiring can be facilitated on a surface other than the chip mounting surface. In addition, by providing a margin in the wiring on the chip mounting surface, it is possible to improve the efficiency of the wiring and facilitate the design. In particular, it is suitable for a configuration in which the pattern wiring length to the ground on the mounting surface is short.

Also, the gaming machine 1 of the embodiment can have the following (configuration B2-3) in addition to (configuration B2-1).
(Configuration B2-3)
The address terminal to be set to H level and the set voltage terminal are connected on the substrate by pattern wiring on the mounting surface of the effect driving means,
The address terminal set to L level is connected to the ground on the surface different from the mounting surface.

Contrary to the above (structure B2-2), the L level terminal is connected to the solid ground on the back side of the mounting surface of the chip such as the LED driver 1510, and the H level terminal is connected to the chip mounting surface. This is an example of wiring using In FIG. 94, contrary to the above, the dashed lines can be considered as the wiring on the chip mounting surface, and the solid lines can be considered as the wiring on the back surface.

For example, when a solid ground is formed on a surface other than the chip mounting surface, such a configuration may be adopted, and the address terminal to be L level should be connected to the solid ground on a surface other than the chip mounting surface. Therefore, the wiring on the mounting surface can be made more efficient, and the design can be simplified.

The gaming machine 1 of the embodiment has the following (configuration B3-1).
(Configuration B3-1)
The game machine 1 is
having a plurality of performance driving means of the same configuration by chip parts having a substantially square shape and having terminals formed on two or more sides;
The production driving means is
A plurality of terminals formed with consecutive terminal numbers from the first side to the second side, which are two consecutive sides, are used as address terminals for setting slave addresses,
From the set voltage terminal for setting the address terminal to H level, follow the periphery of the chip and reach one of the address terminals on the first side by the shortest first distance, follow the periphery of the chip from the set voltage terminal, and follow the second distance. the shortest second distance to reach one of the address terminals on the side is longer,
All of the plurality of effect driving means are at least one address terminal of the second side, and a specific address terminal common to the plurality of effect driving means is set to L level. be.

It should be noted that the meanings of "same configuration" and "all" in this case are as described in the explanation of (configuration B1-1) above, and do not necessarily refer to all the effect drive means in the gaming machine 1. .

A specific example will be described with the LED driver 1510 and the like in FIG. 80A as well.
A set voltage terminal is a VREF terminal that is an output terminal for a 5V reference voltage.
Also, due to the distance from the VREF terminal, the first side is side sd1 and the second side is side sd2. The shortest first distance from the VREF terminal to one of the address terminals on the side sd1 along the periphery of the chip is the distance dst1 from the VREF terminal to the A0 terminal shown in FIG. This is because the shortest second distance reaching any address terminal on the side sd2 is the distance dst2 from the VREF terminal to the A2 terminal, where dst1<dst2.
The distance dst1 and the distance dst2 are schematically shown in FIG. It is something to think about.

As described above, in the LED driver 1510 and the like, the side sd2 is the second side in (configuration B3-1). Then, according to the example of FIG. 93, the terminal A5 on the side sd2 is set to L level.

By setting one of the address terminals on the side sd2 where the wiring is far from the terminal VREF to the L level in this way, the wiring between the terminal VREF terminal and the address terminal is facilitated, and wiring efficiency and wiring design are facilitated. can be realized.
In particular, by making it a terminal (bit) on the side sd2 side, wiring of the terminal VREF on the side sd2 side may become unnecessary depending on the assigned slave address value. Therefore, the number of substrates that can facilitate wiring for setting slave addresses can be increased in the gaming machine 1 as a whole.

Also, the gaming machine 1 of the embodiment may have the following (configuration B3-2) in addition to (configuration B3-1).
(Configuration B3-2)
The address terminal to be set to H level and the set voltage terminal are connected on the substrate via pattern wiring on a surface different from the mounting surface of the effect driving means,
The address terminal set to L level is connected to the ground of the mounting surface.

The gaming machine 1 of the embodiment can also have the following (configuration B3-3) in addition to (configuration B3-1).
(Configuration B3-3)
The address terminal to be set to H level and the set voltage terminal are connected on the substrate by pattern wiring on the mounting surface of the effect driving means,
The address terminal set to L level is connected to the ground on the surface different from the mounting surface.

These (configuration B3-2) (configuration B3-3) are the same as the above-described (configuration B2-2) (configuration B2-3), and the above-described effects can be obtained.

The gaming machine 1 of the embodiment has the following (configuration B4-1).
(Configuration B4-1)
The game machine 1 is
effect control means having a first channel and a second channel as serial data output channels for outputting serial data for effect operation control;
a plurality of first effect drive means for driving the effect means based on the serial data of the first channel;
a plurality of second effect drive means for driving the effect means based on the serial data of the second channel;
with
Each of the first effect driving means and the second effect driving means is composed of a chip part in which a slave address is set at X or more address terminals,
Each of the plurality of first effect driving means is set with a unique slave address with a value within a first numerical range of the address value range settable by the X address terminals,
Each of the plurality of second effect driving means uses a value within a second numerical range that does not overlap with the first numerical range among the address value ranges that can be set by the X address terminals. A unique slave address is set. However, X is a natural number.

(Concrete Example 18) corresponding to this configuration B4-1 is as follows.

(Specific example 18)
・Production control means: production control means 30 (see FIG. 49)
・A plurality of first effect drive means: each LED driver on the game board 3 side ・A plurality of second effect drive means: each LED driver on the door 6 side ・Chip parts: Driver IC chip of FIG. 80A ・First numerical value Within range: “0” to “15” (decimal) in FIG.
・Within the second numerical range: “16” to “31” (decimal) in FIG.

That is, the effect control board 30 transmits and outputs the clock CK and the data DT through a plurality of serial data output channels as described above. Parallel output from a plurality of channels such as the first channel and the second channel enables high-speed control of a large number of LED drivers 1510 and the like.

Since the LED driver corresponding to the first channel and the LED driver corresponding to the second channel are different serial data output channels, there is no problem even if the same slave address is used. Overlap is also avoided between the first and second channels.
By doing so, the same slave address setting can be used as it is even when the design is changed so as to be controlled by the common channel later. This is suitable for securing versatility in consideration of future design changes. For example, in the game machine 1, when the board on the side of the door 6 is used to develop another model, the efficiency of design is improved.

Further, the gaming machine 1 of the embodiment has the following (configuration B4-2) in addition to (configuration B4-1).
(Configuration B4-2)
The game machine 1 is
a frame member;
a door member that can be opened and closed with respect to the frame member;
a game board replaceably attached to the frame member;
has
The first channel is a channel for transmitting serial data to the first effect driving means arranged on a board attached to the game board,
The second channel is a channel for transmitting serial data to the second effect driving means arranged on a board attached to the door member or the frame member.

As explained so far, the first channel is a channel for transmitting serial data to the LED driver arranged on the board attached to the game board 3, and the second channel is a channel for transmitting serial data to the board attached to the door 6. This is the channel that transmits serial data to the arranged LED drivers.

By distributing the first channel and the second channel to the game board 3 side and the door 6 side in this manner, versatility can be enhanced. For example, even when the inner frame 2 and the door 6 are used and the game board 3 is replaced, the setting of the second channel can be used as it is because the slave addresses are not duplicated.

Note that the second channel is not limited to the LED driver of the door 6 . For example, in the case where the inner frame 2 is provided with an effect drive means such as an LED driver, the LED driver of the inner frame 2 may be handled by the second channel.

In addition to (configuration B4-1) or (configuration B4-2), the gaming machine 1 of the embodiment has the following (configuration B4-3).
(Configuration B4-3)
The game machine 1 is
Among the address value ranges that can be set by the X address terminals, address values equal to or greater than a predetermined value are not included in the first numerical range nor in the second numerical range, and are not used as slave addresses. be done.

In the example of FIG. 93, "32" to "63" in decimal notation are unused.
For example, a value whose most significant bit is "1" is not used. If it is 6 bits, the address value range is "100000" or more.
By doing so, it is possible to fix the terminal A5, which corresponds to the highest level among the six address terminals (A0) to (A5) of the LED driver 1510, etc., to the L level. Therefore, the wiring around the chip can be made efficient as described above.

[7.3 Others]
Although the embodiments have been described above, various combinations of the configuration examples from (configuration A1-1) to (configuration A103) and from (configuration B1-1) to (configuration B4-3) are possible. , can be combined arbitrarily to make the gaming machine 1 having the effects described in each configuration.
In addition, it is also possible to combine the configurations and operations described in the embodiments.
Moreover, the various illustrated specific examples are merely one aspect of realizing each configuration. Various specific examples that are not particularly specified are also conceivable.

In the configurations (configuration A1-1) to (configuration A9-3), (specific example 1) to (specific example 17) are shown, but specific examples other than these are also assumed in each configuration.
LED driver, motor driver, driver control unit for controlling these, S/P conversion circuit for motor drive control, etc. Board mounted with chips functioning as effect drive means, or connector CN mounted The substrate can adopt configurations from (configuration A1-1) to (configuration A9-3). For example, each of the substrates shown in FIGS. 11 and 49 can adopt a configuration corresponding to any of the first substrate, the second substrate, and the third substrate in (Configuration A1-1) to (Configuration A9-3). can.

Further, in the above (configuration B1-1) to (configuration B4-3), the LED driver 1510 and the like are taken as an example of the effect driving means, but these configurations can also be applied to motor drivers.

Moreover, although the embodiment has been described with a pachinko game machine, the present invention can also be applied to a reel-type game machine such as a so-called slot game machine.
The reel-type game machine also has a frame member, a door member provided to be openable and closable with respect to the frame member, and a replacement member attached to the frame member so as to be replaceable.
For example, a reel-type game machine has a frame housing as a structure corresponding to a frame member, a door as a structure corresponding to a door member, and a reel unit as a structure corresponding to a replacement member. For example, the frame housing constitutes the main body of the reel-type game machine, and the reel unit is attached to the frame housing directly or via sheet metal or the like by screwing or the like, so that it can be replaced. The door is attached to the frame housing so as to be openable and closable.
Also in such a reel-type game machine, the substrate configuration, circuit configuration, connector configuration, power supply configuration, slave address setting, etc. described in each configuration example can be employed.

1 Game machine 300 Power supply board 400 Inner frame LED relay board 500 Front frame LED connection board 550 Relay board 600 Side unit upper right LED board 620 Side unit lower right LED board 625 LED board 630 Side unit upper LED board 640 Button LED connection board 660 Button LED substrates 661, 663 700 LED connection substrate 720 Back left relay substrate 740 Decoration substrate 760 Relay substrate 790 LED substrate 800 Back bottom relay substrate 820 Decoration substrate 1500 LED connection substrate 1600 LED substrate

Claims (5)

A first effect driving means by chip parts, a first board provided with a first connector for inputting a clock for the first effect driving means, control data for driving effect, and a power supply voltage;
a second board provided with a second connector for inputting a clock for the second effect driving means, control data for driving effect, and a power supply voltage;
with
In the first substrate,
The first effect driving means and the first connector are arranged on the same surface of the substrate,
a left-right relationship when the chip side is viewed from the pattern wiring side of each input terminal of the clock, the control data for driving the effect, and the power supply voltage in the first effect driving means;
The left-right relationship of the connector terminals of the clock, the performance driving control data, and the power supply voltage in the first connector when viewed from the connector terminal side toward the derivation direction of the pattern wiring connected to the connector terminals. ,
are identical and
In the second substrate,
The left-right relationship of the connector terminals of the clock, the performance driving control data, and the power supply voltage in the second connector when viewed from the connector terminal side toward the lead-out direction of the pattern wiring connected to the connector terminals is , the same as the first connector. The second board has second effect driving means by chip parts for inputting a clock and effect driving control data via pattern wiring from the second connector,
In the second substrate, the second effect driving means and the second connector are arranged on the same surface of the substrate,
The left-right relationship of the input terminals of the clock, the control data for driving the effect, and the power supply voltage in the second effect driving means is the same as that of the first effect driving means when the chip side is viewed from the pattern wiring side. Item 1. The gaming machine according to Item 1. A third board provided with a third connector for inputting a clock for the third performance driving means, control data for driving performance, and a power supply voltage,
The left-right relationship of the connector terminals of the clock, the effect driving control data, and the power supply voltage in the third connector when viewed from the connector terminal side toward the lead-out direction of the pattern wiring connected to the connector terminals is , is the same as the first connector. 4. The gaming machine according to any one of claims 1 to 3, wherein the chip component is a substantially rectangular chip having terminals formed on four sides. The gaming machine according to any one of claims 1 to 4, wherein the first substrate is a two-layer wiring substrate with a substrate front surface and a substrate rear surface.

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