JP7392311B2 - Circuit devices, oscillators, electronic equipment, and mobile objects - Google Patents

Description

The present invention relates to a circuit device, an oscillator, an electronic device, and a moving body.

Oscillators that oscillate a resonator such as a crystal resonator to output a signal at a desired frequency are used in a wide range of fields such as electronic devices and systems. Such an oscillator includes an integrated circuit (IC) that integrates a vibrator, an oscillation circuit for causing the vibrator to oscillate, and a peripheral circuit for controlling the operation of the oscillation circuit. For example, in Patent Document 1, an oscillator having a temperature compensation function includes a vibrator, an oscillation circuit that oscillates the vibrator, a first compensation signal based on an n-th order temperature compensation function, and one or more An oscillator is disclosed, comprising: a peripheral circuit including a temperature compensation circuit that generates a second compensation signal that further compensates for the temperature characteristics that remain uncompensated by the first compensation signal based on the second-order temperature compensation function of the first compensation signal. ing.

Japanese Patent Application Publication No. 2018-137512

However, in the oscillator described in Patent Document 1, there is a concern that the clock signal used for the operation of the peripheral circuit becomes a noise source, and the startup of the oscillation circuit that oscillates the vibrator is inhibited. To address such concerns, for example, a configuration may be considered in which the oscillation circuit that oscillates the vibrator is started first, and then the peripheral circuits are started. However, when such a configuration is used, there is a problem that the startup of the oscillator as a whole is delayed.

One aspect of the circuit device according to the present invention is
a first oscillation circuit that generates a first oscillation signal by oscillating a vibrator;
a second oscillation circuit that generates a second oscillation signal;
digital circuit and
Equipped with
During at least part of the startup period from when the first oscillation circuit starts operating until it starts stable operation, the digital circuit operates based on the second oscillation signal, and the digital circuit operates based on the second oscillation signal. The frequency of is controlled to vary.

In one aspect of the circuit device,
In the startup period, the frequency of the second oscillation circuit may be controlled to vary randomly.

In one aspect of the circuit device,
After the activation period has elapsed, the digital circuit may operate based on the first oscillation signal.

In one aspect of the circuit device,
After the activation period has elapsed, the second oscillation circuit may stop outputting the second oscillation signal.

In one aspect of the circuit device,
The second oscillator circuit may include a CR oscillator or a ring oscillator.

In one aspect of the circuit device,
The second oscillation circuit is
a phase comparison circuit that compares the phase of the first oscillation signal and the phase of the second oscillation signal;
a voltage controlled oscillation circuit that outputs a third oscillation signal based on the output signal of the phase comparison circuit;
a frequency dividing circuit that divides the frequency of the third oscillation signal and outputs it as the second oscillation signal;
May include.

In one aspect of the circuit device,
The frequency of the second oscillation signal may be controlled to change by controlling the frequency of the third oscillation signal.

In one aspect of the circuit device,
The frequency of the second oscillation signal may be controlled to change by controlling the frequency division ratio of the frequency divider circuit.

In one aspect of the circuit device,
comprising a storage unit that stores operation setting information for controlling the operation of the first oscillation circuit;
The digital circuit may include a programmable logic controller that controls the operation of the first oscillation circuit based on the operation setting information.

One aspect of the oscillator according to the present invention includes one aspect of the circuit device, and
and the vibrator.

One aspect of an electronic device according to the present invention includes one aspect of the circuit device.

One aspect of the moving object according to the present invention includes one aspect of the circuit device.

Functional block diagram of an oscillator. A diagram showing the configuration of a ring oscillator. 5 is a timing chart for explaining the operation of the oscillator from when it starts operating until it shifts to stable operation. 7 is a timing chart for explaining the operation of the oscillator in the modified example of the first embodiment from when the oscillator starts its operation to a stable operation. The functional block diagram of the oscillator of the second embodiment. The functional block diagram of the oscillator of the third embodiment. The figure which shows an example of the structure of a voltage controlled oscillator. FIG. 2 is a functional block diagram showing an example of the configuration of an electronic device. FIG. 1 is a diagram showing an example of the appearance of a smartphone, which is an example of an electronic device. The figure which shows an example of a moving object.

Hereinafter, preferred embodiments of the present invention will be described using the drawings. The drawings used are for convenience of explanation. Note that the embodiments described below do not unduly limit the content of the present invention described in the claims. Furthermore, not all of the configurations described below are essential components of the present invention.

1. Oscillator 1.1 First embodiment [Functional configuration of oscillator]
FIG. 1 is a functional block diagram of an oscillator 1 of this embodiment. As shown in FIG. 1, oscillator 1 includes an integrated circuit element 10 and a vibrator 2. As shown in FIG.

As the vibrator 2, for example, a crystal vibrator, a SAW (Surface Acoustic Wave) resonant element, another piezoelectric vibrating element, a MEMS (Micro Electro Mechanical Systems) vibrator, etc. can be used. In this embodiment, the resonator 2 will be described as a crystal resonator.

The integrated circuit device 10 includes a first oscillation circuit 20, a second oscillation circuit 30, a voltage amplitude detection circuit 40, a control circuit 50, an output circuit 60, a voltage regulator 70, and a memory circuit 80. Note that the integrated circuit element 10 may have a configuration in which some of these elements are omitted or changed, or other elements are added. This integrated circuit element 10 is an example of a circuit device.

The voltage regulator 70 generates a predetermined voltage Vdd based on the power supply voltage supplied via the VDD terminal, with reference to the ground voltage supplied via the VSS terminal. The voltage Vdd generated by the voltage regulator 70 is used as a power supply voltage for each circuit block of the integrated circuit element 10.

The first oscillation circuit 20 is connected to one end of the vibrator 2 via the XG terminal, and is connected to the other end of the vibrator 2 via the XD terminal. Then, by supplying the voltage Vdd to the first oscillation circuit 20, the first oscillation circuit 20 amplifies the output signal of the vibrator 2 inputted via the XG terminal, and also transmits the amplified signal to the XD By feeding back to the vibrator 2 via the terminal, the vibrator 2 is caused to oscillate. The first oscillation circuit 20 then generates an oscillation signal Scry by amplifying the signal output from the oscillating vibrator 2, and outputs it to each of the control circuit 50 and the output circuit 60. That is, the first oscillation circuit 20 generates and outputs an oscillation signal Scry by causing the vibrator 2 to oscillate. This oscillation signal Scry is an example of the first oscillation signal.

Here, as the oscillation circuit constituted by the vibrator 2 and the first oscillation circuit 20, various types of oscillation circuits are used, such as a Pierce oscillation circuit, an inverter type oscillation circuit, a Colpitts oscillation circuit, and a Hartley oscillation circuit. Further, the first oscillation circuit 20 may output a signal with the frequency stability of the output signal as it is as the oscillation signal Scry without performing temperature compensation or temperature control on the output signal of the vibrator 2. A temperature compensation circuit for increasing frequency stability may be provided, and a signal obtained by subjecting the output signal of the vibrator 2 to temperature compensation in consideration of the ambient temperature may be output as the oscillation signal Scry. Furthermore, in order to achieve extremely high frequency stability, a configuration may be provided that includes a constant temperature bath for keeping the temperature of the vibrator 2 constant. That is, the oscillator 1 including the resonator 2 and the first oscillation circuit 20 may be a packaged crystal oscillator (SPXO) or a temperature compensated crystal oscillator (TCXO). It may also be a high-precision crystal oscillator (OCXO: Oven Controlled Crystal Oscillator).

The output circuit 60 receives an oscillation signal Scry output from the first oscillation circuit 20 and a control signal OUTctrl output from the control circuit 50 described later. Then, the output circuit 60 converts the oscillation signal Scry into a signal in an output format selected based on the control signal OUTctrl and outputs the signal.

The output circuit 60 includes an output frequency divider circuit 61 and an output buffer 62. The output frequency divider circuit 61 divides the frequency of the oscillation signal Scry output from the first oscillation circuit 20 by a frequency division ratio set by the control signal OUTctrl and outputs a signal to the output buffer 62. The output buffer 62 converts the signal output from the output frequency divider circuit 61 into a signal in the output format selected by the control signal OUTctrl based on the power supply voltage supplied via the VDDO terminal, and outputs the signal to the OUT terminal and OUTB. It is output to the outside of the integrated circuit element 10 via at least one of the terminals. For example, if a differential signal output format such as PECL (Positive Emitter Coupled Logic) output, LVDS (Low Voltage Differential Signaling) output, or HCSL (High-Speed Current Steering Logic) output is selected by the control signal OUTctrl, the output buffer 62 outputs the signal converted into the differential signal format via the OUT terminal and the OUTB terminal. Furthermore, when a single-end signal output format such as CMOS (Complementary Metal Oxide Semiconductor) output is selected as the output format by the control signal OUTctrl, the output buffer 62 converts the signal into a single-end signal via the OUT terminal or OUTB terminal. Outputs the signal. Note that the output buffer 62 may control whether to execute or stop outputting a signal according to the control signal OUTctrl.

The voltage amplitude detection circuit 40 detects the voltage amplitude of the oscillation signal Scry output by the first oscillation circuit 20, and outputs a detection signal Sdet according to the detected voltage amplitude. Note that the voltage amplitude detection circuit 40 in this embodiment outputs a high-level detection signal Sdet when the voltage amplitude of the oscillation signal Scry is equal to or greater than a predetermined value, and outputs a high-level detection signal Sdet when the voltage amplitude of the oscillation signal Scry is less than a predetermined value. The following description assumes that in some cases, a low-level detection signal Sdet is output. Here, the relationship between the voltage amplitude of the oscillation signal Scry and the logic level of the detection signal Sdet is not limited to the above-mentioned relationship. , a low level detection signal Sdet may be output, and when the voltage amplitude of the oscillation signal Scry is less than a predetermined value, a high level detection signal Sdet may be output. A signal including information based on the magnitude of the voltage amplitude of the signal Scry may be output.

The second oscillation circuit 30 starts operating upon being supplied with the voltage Vdd, and outputs an oscillation signal Sosc. Specifically, the second oscillation circuit 30 receives the frequency control signal Sfc from the control circuit 50 . The second oscillation circuit 30 generates an oscillation signal Sosc having a frequency based on the input frequency control signal Sfc, and outputs it to the control circuit 50. That is, the second oscillation circuit 30 outputs an oscillation signal Sosc whose frequency is controlled by the frequency control signal Sfc. This oscillation signal Sosc is an example of the second oscillation signal. Here, the second oscillation circuit 30 in this embodiment is configured to include a ring oscillator or a CR oscillator. Note that a specific configuration example of the second oscillation circuit 30 will be described later.

The control circuit 50 includes a multiplexer 51 and a PLC (Programmable Logic Controller) 52.

The multiplexer 51 receives an oscillation signal Scry and an oscillation signal Sosc. Then, the multiplexer 51 selects either the oscillation signal Scry or the oscillation signal Sosc and outputs it to the PLC 52 as the oscillation signal Sclk. Here, the multiplexer 51 in this embodiment selects the oscillation signal Scry as the oscillation signal Sclk when the detection signal Sdet output from the voltage amplitude detection circuit 40 is at a high level, and selects the oscillation signal Scry as the oscillation signal Sclk when the detection signal Sdet is at a low level. The signal Sosc is selected as the oscillation signal Sclk. Although not shown in FIG. 1, the oscillation signal Sclk is supplied to the control circuit 50 including the PLC 52. In other words, the control circuit 50 operates based on the oscillation signal Sclk.

The PLC 52 sequentially reads out the operation setting information stored in the storage circuit 80 based on the oscillation signal Sclk, and adjusts the integrated circuit element 10 including the first oscillation circuit 20 and the second oscillation circuit 30 based on the read operation setting information. Each circuit block included in the circuit is sequentially controlled. That is, the storage circuit 80 stores operation setting information for controlling the operations of the first oscillation circuit 20 and the second oscillation circuit 30, and the PLC 52 controls the operation of the first oscillation circuit 20 and the second oscillation circuit 30 based on the operation setting information. The operation of the second oscillation circuit 30 is controlled. Here, the control circuit 50 is an example of a digital circuit, the storage circuit 80 is an example of a storage section, and the PLC 52 included in the control circuit 50 is an example of a programmable logic controller.

Specifically, the PLC 52 operates based on the oscillation signal Sclk, and reads correction information for correcting the frequency of the oscillation signal Scry stored in the storage circuit 80. Then, the control circuit 50 generates an oscillation control signal Sadj based on the correction information read by the PLC 52 and outputs it to the first oscillation circuit 20. Further, the PLC 52 operates based on the oscillation signal Sclk, and reads frequency information for controlling the frequency of the second oscillation circuit 30 stored in the storage circuit 80. Then, the control circuit 50 generates a frequency control signal Sfc based on the frequency information read by the PLC 52 and outputs it to the second oscillation circuit 30. Further, the PLC 52 operates based on the oscillation signal Sclk, and reads frequency division information for defining the frequency division ratio of the output frequency division circuit 61 stored in the storage circuit 80. Then, the control circuit 50 generates a control signal OUTctrl based on the frequency division information read by the PLC 52 and outputs it to the output circuit 60.

Note that the storage circuit 80 stores, as operation setting information, correction information for correcting the frequency of the oscillation signal Scry, frequency information for controlling the frequency of the second oscillation circuit 30, and division of the output frequency dividing circuit 61. In addition to the frequency division information for specifying the frequency ratio, output signal information for specifying the format of the signal output to the outside of the integrated circuit element 10, judgment threshold information for specifying the judgment threshold in the voltage amplitude detection circuit 40, etc. A plurality of pieces of operation setting information for controlling the operation of the integrated circuit device 10 may be stored.

[Specific example of second oscillation circuit]
Here, an example of the configuration of the second oscillation circuit 30 for changing the frequency of the oscillation signal Sosc based on the frequency control signal Sfc will be described. In the following explanation, the frequency control signal Sfc will be explained as a signal including 3-bit frequency control data Sfc-1, Sfc-2, and Sfc-3.

FIG. 2 is a diagram showing a configuration of a ring oscillator 30a as an example of the second oscillator circuit 30. Ring oscillator 30a includes delay circuits 310, 320, 330 and an inverter 340. The output terminal of delay circuit 310 is electrically connected to the input terminal of delay circuit 320. The output terminal of delay circuit 320 is electrically connected to the input terminal of delay circuit 330. The output terminal of delay circuit 330 is electrically connected to the input terminal of delay circuit 310. That is, the delay circuit 310, the delay circuit 320, and the delay circuit 320 are electrically connected in series and in a ring shape. Furthermore, the output end of the delay circuit 330 is also electrically connected to the input end of the inverter 340. Then, an oscillation signal Sosc is output from the output end of the inverter 340.

Delay circuit 310 includes an inverter 311, an inverter 312 that requires a longer time for signal propagation than inverter 311, and a changeover switch 313. An output end of the inverter 311 is electrically connected to a first switching terminal of a changeover switch 313. An output end of the inverter 312 is electrically connected to a second switching terminal of the changeover switch 313. Further, the input end of the inverter 311 and the input end of the inverter 312 are electrically connected to each other at a connection point N1. In the delay circuit 310 configured as described above, the common terminal of the changeover switch 313 corresponds to the output terminal of the delay circuit 310 described above, and the connection point N1 corresponds to the input terminal of the delay circuit 310.

Furthermore, frequency control data Sfc-1 is input to the control end of the changeover switch 313.
The changeover switch 313 switches whether to electrically connect the common terminal and the first switching terminal or to electrically connect the common terminal and the second switching terminal, according to the frequency control data Sfc-1. That is, the changeover switch 313 inputs the signal output from the output end of the inverter 311 to the common terminal, or inputs the signal output from the output end of the inverter 312 to the common terminal, according to the frequency control data Sfc-1. or switch. This determines whether the signal input to the input terminal of the delay circuit 310 is propagated to the output terminal of the delay circuit 310 via the inverter 311, or via the inverter 312, which takes a longer time for signal propagation than the inverter 311. It is switched whether the signal is propagated to the output terminal of the delay circuit 310 or not. That is, the time required for signal propagation in delay circuit 310 is controlled by frequency control data Sfc-1.

Delay circuit 320 includes an inverter 321, an inverter 322 that requires a longer time for signal propagation than inverter 321, and a changeover switch 323. An output end of the inverter 321 is electrically connected to a first switching terminal of a changeover switch 323. An output end of the inverter 322 is electrically connected to a second switching terminal of the changeover switch 323. Further, the input end of the inverter 321 and the input end of the inverter 322 are electrically connected to each other at a connection point N2. In the delay circuit 320 configured as described above, the common terminal of the changeover switch 323 corresponds to the output terminal of the delay circuit 320 described above, and the connection point N2 corresponds to the input terminal of the delay circuit 320.

Furthermore, frequency control data Sfc-2 is input to the control end of the changeover switch 323. The changeover switch 323 switches whether to electrically connect the common terminal and the first switching terminal or to electrically connect the common terminal and the second switching terminal, according to the frequency control data Sfc-2. That is, the changeover switch 323 inputs the signal output from the output end of the inverter 321 to the common terminal, or inputs the signal output from the output end of the inverter 322 to the common terminal, according to the frequency control data Sfc-2. or switch. This determines whether the signal input to the input terminal of the delay circuit 320 is propagated to the output terminal of the delay circuit 320 via the inverter 321, or via the inverter 322, which takes a longer time for signal propagation than the inverter 321. It is switched whether the signal is transmitted to the output terminal of the delay circuit 320 or not. That is, the time required for signal propagation in the delay circuit 320 is controlled by the frequency control data Sfc-2.

Delay circuit 330 includes an inverter 331, an inverter 332 that requires a longer time for signal propagation than inverter 331, and a changeover switch 333. An output end of the inverter 331 is electrically connected to a first switching terminal of a changeover switch 333. An output end of the inverter 332 is electrically connected to a second switching terminal of a changeover switch 333. Further, the input end of the inverter 331 and the input end of the inverter 332 are electrically connected to each other at a connection point N3. In the delay circuit 330 configured as described above, the common terminal of the changeover switch 333 corresponds to the output terminal of the delay circuit 330 described above, and the connection point N3 corresponds to the input terminal of the delay circuit 330.

Furthermore, frequency control data Sfc-3 is input to the control end of the changeover switch 333. The changeover switch 333 switches whether to electrically connect the common terminal and the first switching terminal or to electrically connect the common terminal and the second switching terminal, according to the frequency control data Sfc-3. That is, the changeover switch 333 inputs the signal output from the output end of the inverter 331 to the common terminal, or inputs the signal output from the output end of the inverter 332 to the common terminal, according to the frequency control data Sfc-3. or switch. This determines whether the signal input to the input terminal of the delay circuit 330 is propagated to the output terminal of the delay circuit 330 via the inverter 331 or via the inverter 332, which takes a longer time for signal propagation than the inverter 331. It is switched whether the signal is transmitted to the output terminal of the delay circuit 330 or not. That is, the time required for signal propagation in the delay circuit 330 is controlled by the frequency control data Sfc-3.

In the ring oscillator 30a configured as described above, when a high level signal is input to the input terminal of the delay circuit 310, a low level signal is input to the input terminal of the delay circuit 320, and the input terminal of the delay circuit 330 receives a low level signal. A high level signal is input to the end. Then, the delay circuit 330 outputs a low level signal from its output terminal. The low level signal output from the delay circuit 330 is input to the input terminal of the delay circuit 310 and also to the input terminal of the inverter 340. That is, in the ring oscillator 30a, the logic level is inverted every time the signal propagates in the delay circuit 310, the delay circuit 320, and the delay circuit 330. A signal is input to the input end of inverter 340. Therefore, the frequency of the oscillation signal Sosc output from the output terminal of the inverter 340 depends on the time the signal propagates in the delay circuit 310, the time the signal propagates in the delay circuit 320, and the time the signal propagates in the delay circuit 330. defined by the total time of That is, by controlling the propagation time of the signal in each of the delay circuits 310, 320, and 330 using each of the frequency control data Sfc-1, Sfc-2, and Sfc-3, the signal is output from the ring oscillator 30a. The frequency of the oscillation signal Sosc is controlled to vary.

In addition, in the above description, the ring oscillator 30a was used as an example of the second oscillator circuit 30, but the second oscillator circuit 30 changes the frequency of the oscillation signal Sosc based on the frequency control signal Sfc. Any configuration that allows this may be used, for example, it may be a CR oscillator. In other words, the second oscillator circuit 30 may include a CR oscillator or a ring oscillator.

Here, when the second oscillator circuit 30 is configured with a CR oscillator, at least one of the resistance value of the resistance circuit and the capacitance value of the capacitor circuit included in the CR oscillator is changed based on the frequency control signal Sfc. By doing so, it becomes possible to change the frequency of the oscillation signal Sosc. Specifically, the resistance circuit included in the CR oscillator includes a plurality of resistance elements connected in series, and the number of resistance elements connected in series is switched based on the frequency control signal Sfc. It becomes possible to change the resistance value of the resistance circuit. Furthermore, the capacitor circuit included in the CR oscillator includes a variable capacitance element such as a varicap, and by controlling the voltage value applied to the variable capacitance element, it is possible to change the capacitance value of the capacitor circuit. . This makes it possible to realize a CR oscillator that can be controlled so that the frequency of the oscillation signal Sosc changes based on the frequency control signal Sfc.

[Oscillator operation]
The operation of the oscillator 1 configured as above at startup will be explained using FIG. 3. FIG. 3 is a timing chart for explaining the operation of the oscillator 1 from when it starts operating until it shifts to stable operation. FIG. 3 schematically shows an example of the signal waveform of the oscillation signal Scry as a waveform Wcry, an example of the oscillation frequency of the oscillation signal Scry as a frequency Fcry, and an example of the voltage amplitude of the oscillation signal Scry as an amplitude Vcry. It is schematically shown as . Similarly, FIG. 3 schematically shows an example of the signal waveform of the oscillation signal Sosc as a waveform Wosc, an example of the oscillation frequency of the oscillation signal Sosc as a frequency Fosc, and an example of the voltage amplitude of the oscillation signal Sosc. It is schematically shown as amplitude Vosc.

As shown in FIG. 3, at time t0, the power supply voltage is supplied through the VDD terminal of the integrated circuit element 10, and the ground voltage is supplied through the VSS terminal, so that the voltage regulator 70 generates the voltage Vdd. and outputs to each circuit block of the integrated circuit element 10. Then, by supplying the voltage Vdd to the first oscillation circuit 20 and the second oscillation circuit 30, the first oscillation circuit 20 and the second oscillation circuit 30 start operating. At this time, the amplitude Vcry of the oscillation signal Scry output by the first oscillation circuit 20 is smaller than the threshold value Vth. Therefore, the voltage amplitude detection circuit 40 outputs a low level detection signal Sdet to the control circuit 50. Thereby, the multiplexer 51 included in the control circuit 50 selects the oscillation signal Sosc output from the second oscillation circuit 30 as the oscillation signal Sclk. Therefore, the control circuit 50 starts operating based on the oscillation signal Sosc.

At time t1, the amplitude Vcry of the oscillation signal Scry becomes equal to or greater than the threshold value Vth. As a result, the logic level of the detection signal Sdet output by the voltage amplitude detection circuit 40 becomes high level. Then, at time t2 when a predetermined period has elapsed after the logic level of the detection signal Sdet becomes high level, the multiplexer 51 included in the control circuit 50 selects the oscillation signal Scry as the oscillation signal Sclk. As a result, the control circuit 50 and the PLC 52 included in the control circuit 50 start operating with the oscillation signal Scry as the oscillation signal Sclk.

More specific operations will be explained. At time t0, voltage Vdd is supplied to the first oscillation circuit 20. As a result, the first oscillation circuit 20 starts operating. Then, when the first oscillation circuit 20 starts operating, the vibrator 2 starts oscillating. As a result, the amplitude Vcry of the oscillation signal Scry output by the first oscillation circuit 20 gradually increases.

Further, at time t0, the voltage Vdd is also supplied to the second oscillation circuit 30. As a result, the second oscillation circuit 30 starts operating. Then, when the second oscillation circuit 30 starts operating, the second oscillation circuit 30 starts outputting the oscillation signal Sosc. At this time, since the amplitude Vcry of the oscillation signal Scry is less than the threshold value Vth, the voltage amplitude detection circuit 40 outputs a low-level detection signal Sdet to the control circuit 50. Therefore, the multiplexer 51 included in the control circuit 50 selects the oscillation signal Sosc as the oscillation signal Sclk and outputs it to the control circuit 50 including the PLC 52.

The control circuit 50 and the PLC 52 included in the control circuit 50 start sequence control based on the oscillation signal Sclk. By starting sequence control of the control circuit 50 and the PLC 52 included in the control circuit 50, frequency information that is the basis of the frequency control signal Sfc stored in the storage circuit 80 is read out. Then, the control circuit 50 outputs a frequency control signal Sfc based on the frequency information. Thereby, the frequency of the oscillation signal Sosc output by the second oscillation circuit 30 is controlled to change.

At time t1, the amplitude Vcry of the oscillation signal Scry output by the first oscillation circuit 20 becomes greater than or equal to a predetermined threshold Vth. As a result, the voltage amplitude detection circuit 40 generates a high-level detection signal Sdet and outputs it to the control circuit 50. Then, at time t2, the control circuit 50 controls the multiplexer 51 and outputs the oscillation signal Sosc as the oscillation signal Sclk to the control circuit 50 including the PLC 52.

That is, at time t1 when the amplitude Vcry of the oscillation signal Scry output by the first oscillation circuit 20 becomes equal to or higher than the predetermined threshold value Vth, or the control circuit 50 uses the oscillation signal Sosc as the oscillation signal Sclk to the control circuit 50 including the PLC 52. The time t2 at which the first oscillation circuit 20 starts outputting is an example of the timing at which the first oscillation circuit 20 starts stable operation. A period Δt2 from time t0 when the circuit 20 starts operating to time t2 corresponds to a startup period of the first oscillation circuit.

As described above, the control circuit 50 included in the integrated circuit element 10 controls the oscillation signal Sosc during at least part of the period Δt1 or the period Δt2 from when the first oscillation circuit 20 starts operating until it starts stable operation. operate based on In this case, the frequency of the oscillation signal Sosc output by the second oscillation circuit is controlled to vary by the frequency control signal Sfc.

Then, during the period Δt2, the control circuit 50 outputs the oscillation signal Scry as the oscillation signal Sclk to the control circuit 50 including the PLC 52. That is, after the period Δt2 has elapsed, the control circuit 50 operates based on the oscillation signal Scry.

Note that the voltage amplitude detection circuit 40 may be configured to change the logic level of the detection signal Sdet when a predetermined period of time after the voltage Vdd is supplied has elapsed. Here, the period after the voltage Vdd is supplied to the voltage amplitude detection circuit 40 until the logic level of the detection signal Sdet is changed is another example of the startup period. Note that the period from when the voltage Vdd is supplied to the voltage amplitude detection circuit 40 to when the logic level of the detection signal Sdet is changed is determined by measuring the start-up time of the first oscillation circuit 20 during the manufacture of the oscillator 1, for example. , activation period information based on the measurement results may be stored in the storage circuit 80.

[Effect]
As described above, in the oscillator 1 according to the present embodiment, in the integrated circuit element 10, the first oscillation circuit that outputs the oscillation signal Scry by oscillating the vibrator 2 starts operating at time t0 and then stably operates. During at least part of the startup period until the start, the control circuit 50 operates using an oscillation signal Sosc whose frequency is controlled to change. That is, during the startup period of the first oscillation circuit 20, the frequency of the oscillation signal Scry output by the first oscillation circuit 20 and the frequency of the oscillation signal Sosc for operating the control circuit 50 continue to have the same value. This reduces the risk of the frequency becoming too high. Therefore, the possibility that the frequency of the oscillation signal Sosc for operating the control circuit 50 will be in reverse phase with respect to the frequency of the oscillation signal Scry outputted by the first oscillation circuit 20 is also reduced. As a result, the possibility that the oscillation signal Sosc for operating the control circuit 50 will interfere with the activation of the first oscillation circuit 20 is reduced. Since the operation of the control circuit 50 can be started in parallel while reducing the possibility of inhibiting the activation of the first oscillation circuit 20, the possibility that the activation of the integrated circuit element 10 and the oscillator 1 will be delayed is reduced.

Furthermore, the control circuit 50 operates based on the oscillation signal Sosc during at least part of the startup period of the first oscillation circuit 20, so that the control circuit 50 is started after the first oscillation circuit 20 has transitioned to stable operation. It becomes possible to shorten the startup time of the integrated circuit element 10 and the oscillator 1 compared to the case where the integrated circuit element 10 and the oscillator 1 are activated.

[Modified example]
In the oscillator 1 of the first embodiment described above, the control circuit 50 may include a pseudo-random number generation circuit that generates a pseudo-random number signal. The control circuit 50 controls the frequency of the oscillation signal Sosc output from the second oscillation circuit 30 based on the pseudo-random number signal generated by the pseudo-random number generation circuit and the frequency information read by the PLC 52. The frequency control signal Sfc may be generated. That is, during at least part of the period Δt1 or period Δt2 from when the first oscillation circuit 20 starts operating until it starts stable operation, the frequency of the oscillation signal Sosc output from the second oscillation circuit 30 changes randomly. It may be controlled to do so.

In the oscillator 1 and the integrated circuit element 10 configured as described above, the frequency of the oscillation signal Sosc output from the second oscillation circuit 30 is controlled to vary randomly, so that the frequency of the oscillation signal Sosc output from the first oscillation circuit 20 is controlled to vary randomly. The possibility that the frequency of the oscillation signal Scry and the frequency of the oscillation signal Sosc continue to have the same value is further reduced. Therefore, the possibility that the frequency of the oscillation signal Sosc for operating the control circuit 50 will be in reverse phase with respect to the frequency of the oscillation signal Scry output by the first oscillation circuit 20 is further reduced. As a result, the possibility that the oscillation signal Sosc for operating the control circuit 50 will interfere with the activation of the first oscillation circuit 20 is further reduced. Therefore, the possibility that the integrated circuit element 10 and the oscillator 1 will start up late is further reduced.

Further, in the oscillator 1 of the first embodiment, the second oscillation circuit 30 may stop outputting the oscillation signal Sosc after the first oscillation circuit 20 starts stable operation. In other words, even if the second oscillation circuit 30 stops outputting the oscillation signal Sosc after the period Δt1 or Δt2 from when the first oscillation circuit 20 starts operating until it starts stable operation, the second oscillation circuit 30 stops outputting the oscillation signal Sosc. good.

FIG. 4 is a timing chart for explaining the operation of the oscillator 1 in a modification of the first embodiment to shift to stable operation. As shown in FIG. 4, at time t0, when voltage Vdd is supplied to the VDD terminal of integrated circuit element 10, first oscillation circuit 20 and second oscillation circuit 30 start operating. At this time, the multiplexer 51 included in the control circuit 50 selects the oscillation signal Sosc as the oscillation signal Sclk. Therefore, the control circuit 50 starts operating based on the oscillation signal Sosc.

At time t1, the amplitude Vcry of the oscillation signal Scry becomes equal to or greater than the threshold value Vth, so that the logic level of the detection signal Sdet output from the voltage amplitude detection circuit 40 becomes high level. Then, at time t2 when a predetermined period has elapsed after the logic level of the detection signal Sdet becomes high level, the multiplexer 51 included in the control circuit 50 selects the oscillation signal Scry as the oscillation signal Sclk. As a result, the control circuit 50 and the PLC 52 included in the control circuit 50 start operating with the oscillation signal Scry as the oscillation signal Sclk.

Then, the control circuit 50 causes the multiplexer 51 to select the oscillation signal Scry as the oscillation signal Sclk, and then outputs a stop signal (not shown) for stopping the operation of the second oscillation circuit 30. The second oscillation circuit 30 stops outputting the oscillation signal Sosc when the stop signal is input.

In the oscillator 1 configured as described above, after the control circuit 50 and the PLC 52 included in the control circuit 50 start operating with the oscillation signal Scry as the oscillation signal Sclk, the second oscillation circuit 30 starts the operation with the oscillation signal Sosc. By stopping the output, it is possible to reduce the power consumption of the oscillator 1 and the integrated circuit element 10 after the first oscillation circuit 20 reaches a stable operating state.

In the example shown in FIG. 4, the second oscillation circuit 30 stops outputting the oscillation signal Sosc at time t2 when the multiplexer 51 included in the control circuit 50 selects the oscillation signal Scry as the oscillation signal Sclk. However, the second oscillation circuit 30 may stop outputting the oscillation signal Sosc after a certain period of time has elapsed after time t2. This makes it possible to reduce the possibility that the oscillation signal Sclk will stop at the signal switching timing of the multiplexer 51.

1.2 Second Embodiment The configuration and operation of the oscillator 1 in the second embodiment will be described using FIG. 5. The oscillator 1 in the second embodiment differs from the oscillator 1 and the integrated circuit element 10 in the first embodiment in that the integrated circuit element 10 includes a PLL circuit 100. Note that in describing the configuration and operation of the oscillator 1 in the second embodiment, the same components as the oscillator 1 in the first embodiment are denoted by the same reference numerals, and the explanation thereof may be simplified or omitted.

FIG. 5 is a functional block diagram of the oscillator 1 of the second embodiment. As shown in FIG. 5, oscillator 1 includes an integrated circuit element 10 and a vibrator 2. As shown in FIG. As the vibrator 2, as in the first embodiment, a crystal vibrator, a SAW resonant element, other piezoelectric vibrating elements, a MEMS vibrator, or the like can be used.

The integrated circuit device 10 includes a first oscillation circuit 20, a second oscillation circuit 30, a voltage amplitude detection circuit 40, a control circuit 50, an output circuit 60, a voltage regulator 70, a memory circuit 80, and a PLL circuit 100. Note that the integrated circuit element 10 may have a configuration in which some of these elements are omitted or changed, or other elements are added.

The first oscillation circuit 20 is connected to one end of the vibrator 2 via the XG terminal and to the other end of the vibrator 2 via the XD terminal, as in the first embodiment. Then, by supplying the voltage Vdd to the first oscillation circuit 20, the first oscillation circuit 20 amplifies the output signal of the vibrator 2 inputted via the XG terminal, and also transmits the amplified signal to the XD terminal. By feeding back to the vibrator 2 via the oscillator 2, the vibrator 2 is caused to oscillate. The first oscillation circuit 20 then generates an oscillation signal Scry by amplifying the signal output from the oscillating vibrator 2, and outputs it to each of the control circuit 50 and the PLL circuit 100.

The PLL circuit 100 is phase-synchronized with the oscillation signal Scry output from the first oscillation circuit 20, and generates and outputs an oscillation signal obtained by multiplying and dividing the frequency of the oscillation signal Scry. Note that the multiplication number and frequency division ratio of the PLL circuit 100 are set by the control signal PLLctrl output from the control circuit 50.

The PLL circuit 100 includes a phase comparator 110, a charge pump 120, a low-pass filter 130, a voltage controlled oscillator 140, a first frequency divider circuit 150, and a second frequency divider circuit 160.

The phase comparator 110 compares the phase of the oscillation signal Scry with the phase of the oscillation signal output by the second frequency dividing circuit 160, and outputs the comparison result as a pulse voltage. Charge pump 120 converts the pulse voltage output by phase comparator 110 into a current. The low-pass filter 130 smoothes the current output from the charge pump 120 and converts it into a voltage. Voltage controlled oscillator 140 outputs an oscillation signal whose frequency changes depending on the output voltage of low-pass filter 130. The first frequency dividing circuit 150 outputs an oscillation signal obtained by dividing the oscillation signal output by the voltage controlled oscillator 140 by an integer frequency using a frequency division ratio set by the control signal PLLctrl. The second frequency dividing circuit 160 outputs an oscillation signal obtained by dividing the oscillation signal output by the voltage controlled oscillator 140 by an integer at a frequency division ratio set by the control signal PLLctrl.

Here, a control signal PLLctrl that sets the frequency division ratio of each of the first frequency dividing circuit 150 and the second frequency dividing circuit 160 is output from the control circuit 50. The PLC 52 included in the control circuit 50 operates based on the oscillation signal Sclk, and is configured to define the frequency division ratios of the first frequency division circuit 150 and the second frequency division circuit 160 stored in the storage circuit 80. Read PLL frequency division information. Then, the control circuit 50 generates a control signal PLLctrl based on the PLL frequency division information read by the PLC 52 and outputs it to the PLL circuit 100.

The output circuit 60 receives the oscillation signal Scry output from the first oscillation circuit 20, the oscillation signal output from the first frequency dividing circuit 150 of the PLL circuit 100, and the control signal OUTctrl. Then, the output circuit 60 selects one of the two types of oscillation signals input based on the control signal OUTctrl, and divides the oscillation signal at the division ratio set by the control signal OUTctrl. Generates a frequency oscillation signal. Thereafter, the output circuit 60 outputs the generated oscillation signal in the output format selected by the control signal OUTctrl.

As described above, the integrated circuit element 10 included in the oscillator 1 includes the PLL circuit 100, and the frequency of the oscillation signal Scry generated by the first oscillation circuit 20 oscillating the vibrator 2 is multiplied in the PLL circuit 100. Even in the case of the oscillator 1 that converts the divided oscillation signal into an oscillation signal and outputs the frequency-divided oscillation signal, the period Δt1 from when the first oscillation circuit 20 starts operating to when it starts stable operation is similar to the first embodiment. Alternatively, during the period Δt2, the control circuit 50 operates based on the oscillation signal Sosc output from the second oscillation circuit and whose frequency changes, so that the same effects as the oscillator 1 in the first embodiment can be obtained.

1.3 Third Embodiment The configuration and operation of the oscillator 1 in the third embodiment will be explained using FIGS. 6 and 7. In the oscillator 1 in the third embodiment, the PLL circuit 100 included in the integrated circuit element 10 has the same function as the second oscillation circuit 30 in the first embodiment and the second embodiment. This is different from the oscillator 1 in the second embodiment. Note that in explaining the configuration and operation of the oscillator 1 in the third embodiment, the same components as the oscillator 1 in the first and second embodiments are denoted by the same reference numerals, and the explanation thereof will be simplified or omitted. There are cases where

FIG. 6 is a functional block diagram of the oscillator 1 of the third embodiment. As shown in FIG. 6, oscillator 1 includes an integrated circuit element 10 and a vibrator 2. As the vibrator 2, as in the first embodiment and the second embodiment, a crystal vibrator, a SAW resonant element, other piezoelectric vibrating elements, a MEMS vibrator, or the like can be used.

The integrated circuit device 10 includes a first oscillation circuit 20, a voltage amplitude detection circuit 40, a control circuit 50, an output circuit 60, a voltage regulator 70, a memory circuit 80, and a PLL circuit 100. Note that the integrated circuit element 10 may have a configuration in which some of these elements are omitted or changed, or other elements are added.

Similar to the second embodiment, the PLL circuit 100 is phase-locked to the oscillation signal Scry output from the first oscillation circuit 20, and generates and outputs an oscillation signal obtained by multiplying and dividing the frequency of the oscillation signal Scry. . Note that the multiplication number and frequency division ratio of the PLL circuit 100 are set by the control signal PLLctrl output from the control circuit 50.

The PLL circuit 100 includes a phase comparator 110, a charge pump 120, a low-pass filter 130, a voltage controlled oscillator 140, a first frequency dividing circuit 150, and a second frequency dividing circuit 160, as in the second embodiment.

The phase comparator 110 compares the phase of the oscillation signal Scry with the phase of the oscillation signal output by the second frequency dividing circuit 160, and outputs the comparison result as a pulse voltage. Charge pump 120 converts the pulse voltage output by phase comparator 110 into a current. The low-pass filter 130 smoothes the current output from the charge pump 120 and converts it into a voltage. Voltage controlled oscillator 140 outputs an oscillation signal Svco with a frequency corresponding to the output voltage of low-pass filter 130. In other words, voltage controlled oscillator 140 outputs oscillation signal Svco based on the output signal of phase comparator 110. The first frequency dividing circuit 150 outputs an oscillation signal obtained by dividing the oscillation signal Svco by an integer frequency using a frequency division ratio set by the control signal PLLctrl. The second frequency dividing circuit 160 outputs an oscillation signal obtained by dividing the oscillation signal Svco by an integer at a frequency division ratio set by the control signal PLLctrl. The oscillation signal output by the second frequency dividing circuit 160 is input to the phase comparator 110, and is also input to the multiplexer 51 included in the control circuit 50 as the oscillation signal Sosc2.

Here, the phase comparator 110 is an example of a phase comparison circuit, the voltage controlled oscillator 140 is an example of a voltage controlled oscillation circuit, and the second frequency divider circuit 160 is an example of a frequency divider circuit. The PLL circuit 100 including the phase comparator 110, the voltage controlled oscillator 140, and the second frequency dividing circuit 160 is an example of the second oscillation circuit in the third embodiment. Further, the oscillation signal Svco output by the voltage controlled oscillator is an example of the third oscillation signal, and the oscillation signal Sosc2 output from the PLL circuit 100 to the control circuit 50 is an example of the second oscillation signal in the third embodiment. .

Here, an example of the configuration of the voltage controlled oscillator 140 will be described using FIG. 7. FIG. 7 is a diagram showing an example of the configuration of the voltage controlled oscillator 140. As shown in FIG. 7, voltage controlled oscillator 140 includes a current source 141, inductors 142 and 143, variable capacitance diodes 144 and 145 that are variable capacitance elements, and transistors 146 and 147 that are N-channel MOS transistors. Then, the voltage controlled oscillator 140 outputs the oscillation signal Svco generated by the oscillation stage constituted by the transistors 146 and 147, for example, as differential signals OUT+ and OUT-.

Here, in the voltage controlled oscillator 140, the frequency of the oscillation signal Svco is determined by the inductance values of the inductors 142 and 143 and the capacitance values of the variable capacitance diodes 144 and 145. That is, in the voltage controlled oscillator 140 shown in FIG. 7, the output voltage of the low-pass filter 130 is applied to the connection point N4 where the anode of the variable capacitance diode 144 and the anode of the variable capacitance diode 145 are electrically connected. The capacitance values of the variable capacitance diodes 144 and 145 change depending on the value of the applied voltage. This controls the frequency of the oscillation signal Svco output by the voltage controlled oscillator 140.

Returning to FIG. 6, the control circuit 50 includes a multiplexer 51 and a PLC 52, similar to the first embodiment and the second embodiment.

The oscillation signal Scry and the oscillation signal Sosc2 output from the PLL circuit 100 are input to the multiplexer 51. The multiplexer 51 selects either the oscillation signal Scry or the oscillation signal Sosc2 based on the logic level of the detection signal Sdet, and outputs it to the PLC 52 as the oscillation signal Sclk. Note that, similarly to the first embodiment and the second embodiment, when the detection signal Sdet output from the voltage amplitude detection circuit 40 is at a high level, the multiplexer 51 selects the oscillation signal Scry as the oscillation signal Sclk and performs the detection. When the signal Sdet is at a low level, the oscillation signal Sosc2 is selected as the oscillation signal Sclk.

The PLC 52 sequentially reads out the operation setting information stored in the storage circuit 80 based on the oscillation signal Sclk, and operates the first oscillation circuit 20, the second oscillation circuit 30, and the PLL circuit 100 based on the read operation setting information. Each circuit block included in the integrated circuit element 10 is sequentially controlled. Specifically, the PLC 52 reads frequency information for controlling the frequency of the voltage controlled oscillator 140 included in the PLL circuit 100 stored in the storage circuit 80 based on the oscillation signal Sclk. Then, the control circuit 50 generates a frequency control signal Sfc2 based on the frequency information read by the PLC 52 and outputs it to the voltage controlled oscillator 140. In addition to the above operations, the PLC circuit 52 also executes various processes described in the first embodiment and the second embodiment.

Here, the frequency control signal Sfc2 outputted by the control circuit 50 is a signal that controls the voltage value applied to the connection point N4 of the voltage controlled oscillator 140, and is, for example, an analog of the voltage value supplied to the connection point N4. Alternatively, it may be a digital signal for controlling the output of a power supply circuit (not shown) that generates the voltage value applied to the connection point N4 of the voltage controlled oscillator 140.

In the oscillator 1 according to the third embodiment configured as described above, the control circuit 50 performs voltage control during at least part of the startup period from when the first oscillation circuit 20 starts operating until it starts stable operation. A frequency control signal Sfc2 that changes the frequency of the oscillation signal Svco output from the oscillator 140 is generated and output. Therefore, the frequency of the oscillation signal Sosc2 output from the second frequency dividing circuit 160 also changes. At this time, the control circuit 50 selects the oscillation signal Sosc2 as the oscillation signal Sclk based on the detection signal Sdet. That is, the control circuit 50 operates based on the oscillation signal Sosc2. In other words, the frequency of the oscillation signal Svco is controlled during at least part of the startup period from when the first oscillation circuit 20 starts operating until it starts stable operation, so that the frequency of the oscillation signal Sosc2 is controlled to change.

Then, when it is determined based on the detection signal Sdet that the operation of the first oscillation circuit 20 has started stable operation, the control circuit 50 causes the multiplexer 51 to select the oscillation signal Scry as the oscillation signal Sclk. Thereby, the control circuit 50 operates based on the oscillation signal Scry. In this case, the control circuit 50 stops outputting the frequency control signal Sfc2 or sets it to a predetermined fixed value. Thereby, the frequency of the oscillation signal Svco output from the voltage controlled oscillator 140 is controlled according to the output voltage of the low-pass filter 130. Therefore, the PLL circuit 100 is phase-synchronized with the oscillation signal Scry output from the first oscillation circuit 20, and starts an operation of generating and outputting an oscillation signal obtained by multiplying and dividing the frequency of the oscillation signal Scry. In other words, after the first oscillation circuit 20 starts stable operation, the PLL circuit 100 starts operating.

Even in the oscillator 1 according to the third embodiment configured as described above, the control circuit 5 However, by operating with the oscillation signal Sosc2 whose frequency is controlled to change, it is possible to achieve the same effects as the oscillator 1 shown in the first embodiment and the second embodiment.

Here, in the oscillator 1 of the third embodiment described above, the frequency of the oscillation signal Svco is controlled by the frequency control signal Sfc2 outputted by the control circuit 50, so that the frequency of the oscillation signal Sosc2 is controlled to change. However, during at least part of the startup period from when the first oscillation circuit 20 starts operating until it starts stable operation, the frequency division ratio in the second frequency dividing circuit 160 is controlled by PLLctrl output from the control circuit 50. By controlling, the frequency of the oscillation signal Sosc2 may be changed. Even when the frequency division ratio in the second frequency divider circuit 160 is controlled, the control circuit 50 remains in control during at least part of the startup period from when the first oscillation circuit 20 starts operating until it starts stable operation. , the oscillator 1 can operate using the oscillation signal Sosc2 whose frequency is controlled to change, and the same effects as the oscillator 1 shown in the first embodiment and the second embodiment can be achieved. Note that a third frequency dividing circuit different from the second frequency dividing circuit 160 is further provided, and the frequency of the oscillation signal Sosc2 is changed by controlling the frequency division ratio in the third frequency dividing circuit using PLLctrl outputted by the control circuit 50. The configuration may be such that control is performed so as to.

2. Electronic Device FIG. 8 is a functional block diagram showing an example of the configuration of the electronic device of this embodiment. Moreover, FIG. 9 is a diagram showing an example of the appearance of a smartphone, which is an example of the electronic device of this embodiment.

The electronic device 500 of this embodiment includes an oscillator 510, a CPU (Central Processing Unit) 520, an operation section 530, a ROM (Read Only Memory) 540, a RAM (Random Access Memory) 550, a communication section 560, and a display section 570. It is configured. Note that the electronic device of this embodiment may have a configuration in which some of the components shown in FIG. 8 are omitted or changed, or other components are added.

Oscillator 510 includes an integrated circuit element 512 and a vibrator 513. The integrated circuit element 512 causes the vibrator 513 to oscillate to generate an oscillation signal. This oscillation signal is output from an external terminal of oscillator 510 to CPU 520.

The CPU 520 is a processing unit that performs various calculation processes and control processes using an oscillation signal input from the oscillator 510 as a clock signal according to a program stored in the ROM 540 or the like. Specifically, the CPU 520 performs various processes in response to operation signals from the operation unit 530, processes for controlling the communication unit 560 to perform data communication with an external device, and processes for displaying various information on the display unit 570. Performs processing such as transmitting display signals.

The operation unit 530 is an input device configured with operation keys, button switches, etc., and outputs an operation signal to the CPU 520 in accordance with a user's operation.

The ROM 540 is a storage unit that stores programs, data, etc. for the CPU 520 to perform various calculation processes and control processes.

The RAM 550 is a storage unit that is used as a work area for the CPU 520 and temporarily stores programs and data read out from the ROM 540, data input from the operation unit 530, calculation results executed by the CPU 520 according to various programs, etc. .

The communication unit 560 performs various controls for establishing data communication between the CPU 520 and an external device.

The display unit 570 is a display device configured with an LCD (Liquid Crystal Display) or the like, and displays various information based on display signals input from the CPU 520. The display section 570 may be provided with a touch panel that functions as the operation section 530.

By applying the oscillator 1 of each embodiment described above as the oscillator 510, it is possible to reduce the possibility that the integrated circuit element 512 and the oscillator 510 will start up late, and it is possible to realize a highly reliable electronic device. can.

Various electronic devices can be considered as such electronic device 500, such as personal computers such as mobile type, laptop type, and tablet type, mobile terminals such as smartphones and mobile phones, digital cameras, and inkjet printers such as inkjet printers. Storage area network equipment such as routers and switches, local area network equipment, mobile terminal base station equipment, televisions, video cameras, video recorders, car navigation equipment, real-time clock equipment, pagers, electronic notebooks, electronic dictionaries , calculators, electronic game devices, game controllers, word processors, workstations, video phones, security TV monitors, electronic binoculars, POS terminals, electronic thermometers, blood pressure monitors, blood sugar meters, electrocardiogram measuring devices, ultrasound diagnostic devices, electronic equipment Medical equipment such as endoscopes, fish finders, various measuring instruments, instruments for vehicles, aircraft, ships, etc., flight simulators, head-mounted displays, motion tracing, motion tracking, motion controllers, pedestrian autonomous navigation (PDR: Pedestrian Dead) Reckoning) equipment, etc.

An example of the electronic device 500 of this embodiment is a transmission device that uses the above-described oscillator 510 as a reference signal source and functions as, for example, a terminal base station device that communicates with a terminal by wire or wirelessly. By applying, for example, the oscillator 1 of each of the embodiments described above as the oscillator 510, an electronic device 500 that is desired to have high frequency accuracy, high performance, and high reliability, which can be used in a communication base station, etc., can be realized. It is also possible.

Further, as another example of the electronic device 500 of the present embodiment, the communication unit 560 receives an external clock signal, and the CPU 520 controls the frequency of the oscillator 510 based on the external clock signal and the output signal of the oscillator 510. The communication device may include a frequency control unit that performs the following. This communication device may be, for example, a backbone network device such as Stratum 3 or a communication device used in a femtocell.

3. Mobile Object FIG. 10 is a diagram showing an example of a mobile object according to the present embodiment. The moving body 400 shown in FIG. 10 includes an oscillator 410, controllers 420, 430, 440 that perform various controls such as an engine system, a brake system, and a keyless entry system, a battery 450, and a backup battery 460. Note that the moving body of this embodiment may have a configuration in which some of the components shown in FIG. 10 are omitted, or other components are added.

The oscillator 410 includes an integrated circuit element (not shown) and a vibrator, and the integrated circuit element causes the vibrator to oscillate to generate an oscillation signal. This oscillation signal is output from an external terminal of the oscillator 410 to the controllers 420, 430, and 440, and is used, for example, as a clock signal.

Battery 450 powers oscillator 410 and controllers 420, 430, 440. Backup battery 460 supplies power to oscillator 410 and controllers 420, 430, 440 when the output voltage of battery 450 drops below a threshold.

By applying, for example, the oscillator 1 of each of the embodiments described above as the oscillator 410, it is possible to reduce the possibility that the activation of the oscillator 410 will be delayed, and a highly reliable moving object can be realized.

Various types of moving objects can be considered as such a moving object 400, and examples thereof include automobiles such as electric vehicles, aircraft such as jet planes and helicopters, ships, rockets, artificial satellites, and the like.

Although the embodiments and modified examples have been described above, the present invention is not limited to these embodiments, and can be implemented in various forms without departing from the gist thereof. For example, it is also possible to combine the above embodiments as appropriate.

The present invention includes configurations that are substantially the same as those described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same objectives and effects). Further, the present invention includes a configuration in which non-essential parts of the configuration described in the embodiments are replaced. Further, the present invention includes a configuration that has the same effects or a configuration that can achieve the same purpose as the configuration described in the embodiment. Further, the present invention includes a configuration in which known technology is added to the configuration described in the embodiment.

DESCRIPTION OF SYMBOLS 1... Oscillator, 2... Vibrator, 10... Integrated circuit element, 20... First oscillation circuit, 30... Second oscillation circuit, 30a... Ring oscillator, 40... Voltage amplitude detection circuit, 50... Control circuit, 51... Multiplexer , 52... PLC circuit, 60... Output circuit, 61... Output frequency divider circuit, 62... Output buffer, 70... Voltage regulator, 80... Memory circuit, 100... PLL circuit, 110... Phase comparator, 120... Charge pump, 130 ...Low pass filter, 140...Voltage controlled oscillator, 141...Current source, 142,143...Inductor, 144,145...Variable capacitance diode, 146,147...Transistor, 150...First frequency divider circuit, 160...Second frequency divider circuit , 310... Delay circuit, 311, 312... Inverter, 313... Changeover switch, 320... Delay circuit, 321, 322... Inverter, 323... Changeover switch, 330... Delay circuit, 331, 332... Inverter, 333... Changeover switch, 340 ... Inverter, 400 ... Mobile object, 410 ... Oscillator, 420, 430, 440 ... Controller, 450 ... Battery, 460 ... Backup battery, 500 ... Electronic equipment, 510 ... Oscillator, 512 ... Integrated circuit element, 513 ... Vibrator, 520...CPU, 530...Operation unit, 540...ROM, 550...RAM, 560...Communication unit, 570...Display unit

Claims (14)

a first oscillation circuit that generates a first oscillation signal by oscillating a vibrator;
a second oscillation circuit that generates a second oscillation signal;
digital circuit and
Equipped with
During at least part of the startup period from when the first oscillation circuit starts operating until it starts stable operation, the digital circuit operates based on the second oscillation signal, and the digital circuit operates based on the second oscillation signal. The frequency of is controlled to vary ,
In the startup period, the frequency of the second oscillation circuit is controlled to vary randomly . The circuit device according to claim 1 , wherein the digital circuit operates based on the first oscillation signal after the activation period has elapsed. a first oscillation circuit that generates a first oscillation signal by oscillating a vibrator;
a second oscillation circuit that generates a second oscillation signal;
digital circuit and
Equipped with
During at least part of the startup period from when the first oscillation circuit starts operating until it starts stable operation, the digital circuit operates based on the second oscillation signal, and the digital circuit operates based on the second oscillation signal. The frequency of is controlled to vary,
After the activation period has elapsed, the digital circuit operates based on the first oscillation signal. 4. The circuit device according to claim 2, wherein the second oscillation circuit stops outputting the second oscillation signal after the activation period has elapsed. 5. The circuit device according to claim 1, wherein the second oscillator circuit includes a CR oscillator or a ring oscillator. The second oscillation circuit is
a phase comparison circuit that compares the phase of the first oscillation signal and the phase of the second oscillation signal;
a voltage controlled oscillation circuit that outputs a third oscillation signal based on the output signal of the phase comparison circuit;
a frequency dividing circuit that divides the frequency of the third oscillation signal and outputs it as the second oscillation signal;
The circuit device according to any one of claims 1 to 3, comprising: a first oscillation circuit that generates a first oscillation signal by oscillating a vibrator;
a second oscillation circuit that generates a second oscillation signal;
digital circuit and
Equipped with
During at least part of the startup period from when the first oscillation circuit starts operating until it starts stable operation, the digital circuit operates based on the second oscillation signal, and the digital circuit operates based on the second oscillation signal. The frequency of is controlled to vary,
The second oscillation circuit is
a phase comparison circuit that compares the phase of the first oscillation signal and the phase of the second oscillation signal;
a voltage controlled oscillation circuit that outputs a third oscillation signal based on the output signal of the phase comparison circuit;
a frequency dividing circuit that divides the frequency of the third oscillation signal and outputs it as the second oscillation signal;
circuit devices, including; 8. The circuit device according to claim 6, wherein the frequency of the second oscillation signal is controlled to change by controlling the frequency of the third oscillation signal. 8. The circuit device according to claim 6, wherein the frequency of the second oscillation signal is controlled to change by controlling the frequency division ratio of the frequency dividing circuit. comprising a storage unit that stores operation setting information for controlling the operation of the first oscillation circuit;
9. The circuit device according to claim 1, wherein the digital circuit includes a programmable logic controller that controls the operation of the first oscillation circuit based on the operation setting information. a first oscillation circuit that generates a first oscillation signal by oscillating a vibrator;
a second oscillation circuit that generates a second oscillation signal;
digital circuit and
Equipped with
During at least part of the startup period from when the first oscillation circuit starts operating until it starts stable operation, the digital circuit operates based on the second oscillation signal, and the digital circuit operates based on the second oscillation signal. The frequency of is controlled to vary,
comprising a storage unit that stores operation setting information for controlling the operation of the first oscillation circuit;
The digital circuit is a circuit device including a programmable logic controller that controls the operation of the first oscillation circuit based on the operation setting information. The circuit device according to any one of claims 1 to 11 ,
An oscillator comprising the vibrator. An electronic device comprising the circuit device according to claim 1 . A moving body comprising the circuit device according to claim 1 .

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