JP7388031B2 - semiconductor equipment - Google Patents

Description

The present invention relates to a semiconductor device suitable for a high voltage circuit such as an igniter.

In recent years, with the aim of improving fuel efficiency in automobiles, there has been a trend toward leaner fuel in internal combustion engines, creating an environment in which it is difficult for spark plugs to ignite. For this reason, ignition coils used in internal combustion engines are required to have high energy. One way to increase the energy of an ignition coil is to increase the withstand voltage of the igniter that controls the ignition of the ignition coil.

A high breakdown voltage of the igniter can be achieved by increasing the breakdown voltage of a Zener diode (protection diode) connected between the collector and gate of an insulated gate bipolar transistor (IGBT) built into the igniter. However, igniters are required to have high surge resistance and to not be destroyed or deteriorated even when used in harsh environments, so as the protection diodes become higher in voltage, the bulk voltage resistance of the IGBT section and the voltage resistance structure on the outer periphery of the chip are also increasing. Therefore, it is necessary to increase the voltage resistance.

Examples of methods for increasing the withstand voltage of the voltage-resistant structure include multi-stage guard ring structures and field plate structures disposed within the voltage-resistant structure (see Patent Documents 1 and 2). However, due to the multi-staged guard ring structure and field plate structure, electric field concentration occurs in the insulating film near the end of the field plate on the outer circumferential side of the chip when a transient surge is applied. Therefore, there is a problem that the insulating film is easily destroyed and the surge resistance is reduced.

International Publication No. 2014/142331 JP2017-59665A

In view of the above-mentioned problems, an object of the present invention is to provide a semiconductor device suitable for a high voltage circuit such as an igniter, which can ensure surge resistance while increasing voltage resistance.

One aspect of the present invention is a semiconductor device including a main semiconductor element portion disposed on the center side of a semiconductor chip, and a voltage withstanding structure portion placed on the outer peripheral side of the semiconductor chip, the voltage withstanding structure portion being a first a conductive type semiconductor substrate; a first insulating film selectively disposed on the semiconductor substrate; and a first insulating film disposed closer to the center of the semiconductor chip than the first insulating film on the semiconductor substrate and thinner than the first insulating film. a second insulating film, a protection diode at least partially disposed on the first insulating film, an interlayer insulating film disposed on the protection diode, and a field plate disposed on the interlayer insulating film; The gist is that the semiconductor device is such that the outer peripheral end of the semiconductor device is located on the central end of the first insulating film.

According to the present invention, it is possible to provide a semiconductor device suitable for a high voltage circuit such as an igniter, which can ensure surge resistance while achieving high voltage resistance.

1 is an equivalent circuit diagram of an ignition device to which a semiconductor device according to an embodiment of the present invention is applied. FIG. 1 is a plan view of a semiconductor device according to an embodiment. 3 is a partially enlarged view of area A in FIG. 2. FIG. FIG. 4 is a sectional view taken along the line AA in FIG. 3; 5 is a partially enlarged view of area A in FIG. 4. FIG. FIG. 3 is a cross-sectional view of a semiconductor device according to a comparative example. FIG. 7 is a cross-sectional view showing equipotential lines during normal operation of a semiconductor device according to a comparative example. 7 is a graph showing various waveforms when a surge is applied to a semiconductor device according to a comparative example. 9 is a graph showing various waveforms in which the broken line section of FIG. 8 is enlarged. FIG. 7 is a schematic cross-sectional view showing equipotential lines when a surge is applied to a semiconductor device according to a comparative example. FIG. 7 is a schematic plan view showing equipotential lines when a surge is applied to a semiconductor device according to a comparative example. FIG. 7 is a schematic cross-sectional view showing equipotential lines when a surge is applied to a semiconductor device according to a comparative example. FIG. 2 is a schematic cross-sectional view showing equipotential lines when a surge is applied to the semiconductor device according to the embodiment. FIG. 2 is a process cross-sectional view of a method for manufacturing a semiconductor device according to an embodiment. 15 is a process cross-sectional view following FIG. 14 of the method for manufacturing a semiconductor device according to the embodiment. FIG. 16 is a process cross-sectional view following FIG. 15 of the method for manufacturing a semiconductor device according to the embodiment. FIG. FIG. 17 is a process cross-sectional view following FIG. 16 of the method for manufacturing a semiconductor device according to the embodiment. FIG. 18 is a process cross-sectional view following FIG. 17 of the method for manufacturing a semiconductor device according to the embodiment. 19 is a process cross-sectional view following FIG. 18 of the method for manufacturing a semiconductor device according to the embodiment. FIG.

Embodiments of the present invention will be described below with reference to the drawings. In the description of the drawings referred to in the following description, the same or similar parts are denoted by the same or similar symbols. However, it should be noted that the drawings are schematic and the relationship between thickness and planar dimensions, the ratio of the thickness of each layer, etc. are different from reality. Therefore, the specific thickness and dimensions should be determined with reference to the following explanation. Furthermore, it goes without saying that the drawings include portions with different dimensional relationships and ratios.

The term "semiconductor device" in this specification may include both structures of individual devices (discrete devices) and semiconductor integrated circuits, depending on the level of integration. The "first main electrode region" of a main semiconductor element constituting a semiconductor device means a semiconductor region that becomes either a source region or a drain region in a field effect transistor (FET) or static induction transistor (SIT). . In an insulated gate bipolar transistor (IGBT), it refers to a semiconductor region that serves as either an emitter region or a collector region. Furthermore, in an insulated gate thyristor such as an MIS-controlled static induction thyristor (SI thyristor), it refers to a semiconductor region that becomes either an anode region or a cathode region. The "second main electrode region" means a semiconductor region that becomes either a source region or a drain region, but does not become the first main electrode region in an FET or SIT. In an IGBT, it means a region that does not become the first main electrode region but becomes either an emitter region or a collector region. In a MIS control SI thyristor, etc., it means a semiconductor region that is not the first main electrode region but is either an anode region or a cathode region.

In this way, if the "first main electrode region" is a source region, the "second main electrode region" means a drain region, and a "main current" flows between one and the second main electrode region. For example, in the case of an IGBT, the collector current corresponds to the main current, and if the "first main electrode region" is the emitter region, the "second main electrode region" means the collector region. If the "first main electrode region" is an anode region, the "second main electrode region" means a cathode region. In the case of a MISFET or the like, the function of the "first main electrode area" and the function of the "second main electrode area" may be interchangeable if the bias relationship is exchanged. Similarly, "first main electrode" means a main electrode made of a conductive layer connected to the first main electrode region, and "second main electrode" means a main electrode made of a conductive layer connected to the second main electrode region. means electrode.

Further, in the following description, a case where the first conductivity type is n type and the second conductivity type is p type will be exemplified. However, the conductivity types may be selected in a reverse relationship, with the first conductivity type being the p type and the second conductivity type being the n type. In addition, "+" and "-" appended to "n" and "p" refer to semiconductors with relatively high or low impurity concentrations, respectively, compared to semiconductor regions without "+" and "-". It means a territory. However, even if the semiconductor regions have the same "n" and "n", this does not mean that the impurity concentrations of the respective semiconductor regions are strictly the same.

Further, the definitions of directions such as up and down in the following description are simply definitions for convenience of explanation, and do not limit the technical idea of the present invention. For example, if the object is rotated 90 degrees and observed, the top and bottom will be converted to left and right and read, and if the object is rotated 180 degrees and observed, the top and bottom will of course be reversed and read.

(Embodiment)
<Semiconductor device>
As a semiconductor device (semiconductor chip) according to an embodiment of the present invention, a power semiconductor integrated circuit (power IC) constituting an igniter of an ignition device used in an internal combustion engine for an automobile will be exemplified. As shown in FIG. 1, the ignition device according to the embodiment of the present invention includes a semiconductor device (igniter) 100, a battery 110, an electronic control unit (ECU) 112, an ignition coil 113, and a spark plug 114.

Semiconductor device 100 is connected to ECU 112 via terminal 105. The semiconductor device 100 is connected to one end of the primary coil of the ignition coil 113 via the terminal 104. The other end of the primary coil of the ignition coil 113 is connected to the battery 110. One end of the secondary coil of the ignition coil 113 is connected to the battery 110, and the other end of the secondary coil is connected to the spark plug 114.

The semiconductor device 100 includes a main semiconductor element 101, a protection diode 102, and a control circuit section 103. The main semiconductor element 101 is composed of, for example, an IGBT. A gate of the main semiconductor element 101 is connected to a control circuit section 103. A collector of the main semiconductor element 101 is connected to a terminal 104. The emitter of the main semiconductor element 101 is grounded via a terminal 106.

The protection diode 102 is connected between the collector and gate of the main semiconductor element 101. The protection diode 102 is configured by connecting multiple (multistage) Zener diodes in reverse. The protection diode 102 prevents the application of overvoltage to the main semiconductor element 101 by clamping the high voltage generated at the collector when the main semiconductor element 101 is turned off.

When the ON signal is input from the ECU 112, the control circuit section 103 outputs the ON signal to the gate of the main semiconductor element 101. When the on signal is input to the gate of the main semiconductor element 101, the gate potential of the main semiconductor element 101 increases, and the main semiconductor element 101 is turned on. When the main semiconductor element 101 is turned on, current flows from the battery 110 to the primary coil of the ignition coil 113.

On the other hand, when the on signal from the ECU 112 is turned off, the control circuit section 103 outputs an off signal to the gate of the main semiconductor element 101. When the off signal is input to the gate of the main semiconductor element 101, the gate potential of the main semiconductor element 101 decreases, and the main semiconductor element 101 is turned off. At this turn-off time, a voltage corresponding to the inductance component (L component) of the ignition coil 113 and the di/dt of the main semiconductor element 101 at the time of turn-off is generated at the terminal 104 of the semiconductor device 100. A high voltage corresponding to the voltage generated in the primary coil of the ignition coil 113 and the turn ratio of the ignition coil 113 is generated in the secondary coil of the ignition coil 113, and spark discharge occurs at the spark plug 114.

As shown in FIG. 2, the semiconductor device 100 shown in FIG. It can be constructed from a one-chip igniter monolithically integrated into the igniter. A breakdown voltage structure section 203 is arranged around the main semiconductor element section 201 and the control circuit section 202 at the outer periphery of the chip. In the breakdown voltage structure section 203, the protection diode 10 is arranged adjacent to the main semiconductor element section 201. The main semiconductor element section 201, control circuit section 202, and protection diode 10 shown in FIG. 2 correspond to the main semiconductor element 101, control circuit section 103, and protection diode 102 shown in FIG. 1, respectively.

FIG. 3 is an enlarged plan view of a part of the voltage-resistant structure 203 within the area A surrounded by the broken line in FIG. Further, FIG. 4 is a cross-sectional view seen from the direction AA in FIG. 3. At the left end of FIG. 4, a part of the main semiconductor element section 201 adjacent to the breakdown voltage structure section 203 is shown expanded.

As shown at the left end of FIG. 4, the main semiconductor element section 201 includes a first main electrode region 21a of a first conductivity type (n ⁺ type) provided on the upper part of a semiconductor substrate 1 of a first conductivity type (n type). , 21b and the second main electrode region 14 of the second conductivity type (p ⁺ type) on the lower surface (rear surface) side of the semiconductor substrate 1 have power semiconductor elements facing each other in the vertical direction. For example, if the power semiconductor element is an IGBT, the first main electrode regions 21a and 21b function as emitter regions, and the second main electrode region 14 functions as a collector region. The first main electrode regions 21a and 21b are semiconductor regions having a lower resistivity (higher impurity concentration) than the semiconductor substrate 1.

In the upper part of the semiconductor substrate 1, a p ⁺ type first well region 5a and a second well region 5b are arranged apart from each other. The second well region 5b is provided in the upper part of the semiconductor substrate 1, extending from the main semiconductor element section 201 to the breakdown voltage structure section 203. In the upper part of the semiconductor substrate 1 sandwiched between the first well region 5a and the second well region 5b, a p-type first implantation control region 22a having a higher resistivity than the first well region 5a and the second well region 5b is provided. and a second injection control region 22b are provided, respectively. The first injection control region 22a is provided adjacent to the first main electrode region 21a so as to form a pn junction. The second injection control region 22b is provided adjacent to the first main electrode region 21b so as to form a pn junction.

If the main semiconductor element section 201 is an IGBT, the first injection control region 22a and the second injection control region 22b function as a base region of the main semiconductor element section 201. A first main electrode (emitter electrode) 2 is provided in ohmic contact with the first well region 5a, the second well region 5b, and the first main electrode regions 21a, 21b. Although not shown, a second main electrode (collector electrode) is provided in ohmic contact with the second main electrode region 14 .

The semiconductor substrate 1 constitutes a part of a semiconductor chip on which the semiconductor device 100 is monolithically integrated. The semiconductor substrate 1 is a semiconductor region in which majority carriers injected into the semiconductor substrate 1 from the first main electrode regions 21a and 21b can be transported by a drift electric field. If the main semiconductor element section 201 has an IGBT structure, the semiconductor substrate 1 functions as a drift region.

A gate electrode 24 is provided on the semiconductor substrate 1 sandwiched between the first implantation control region 22a and the second implantation control region 22b, and on the first implantation control region 22a and the second implantation control region 22b with a gate insulating film 23 interposed therebetween. It is located. The gate electrode 24 electrostatically controls the surface potentials of the first injection control region 22a and the second injection control region 22b via the gate insulating film 23. The gate insulating film 23 and the gate electrode 24 constitute an insulated gate structure (23, 24) that controls injection of majority carriers from the first main electrode regions 21a, 21b into the semiconductor substrate (drift region) 1.

For example, p ^- type impurity ions such as boron (B) are implanted into the back surface of a semiconductor substrate (Si wafer) made of n-type silicon (Si) so that the semiconductor substrate 1 functions as a drift region. The second main electrode region 14 may be formed of a semiconductor region. Alternatively, the second main electrode region 14 made of a p ⁺ -type semiconductor region may be formed by thermally diffusing a p-type impurity element on the back surface of an n-type semiconductor substrate. Alternatively, the n-type semiconductor substrate 1 may be epitaxially grown on the second main electrode region 14 made of a p ⁺ -type semiconductor substrate (Si wafer).

A first interlayer insulating film 25 is arranged on the gate electrode 24 so as to cover the gate electrode 24 . The first main electrode 2 is connected to the first well region 5a, the second well region 5b, the first main electrode region 21a and the first main electrode through an opening (contact hole) provided in the first interlayer insulating film 25. It is metallurgically bonded to region 21b.

On the other hand, in the voltage-resistant structure 203 shown on the right side from the center of FIG. 4, a p ⁺ type first guard ring 6a, second guard ring 6b, and third guard ring 6c are provided on the upper part of the semiconductor substrate 1. . The first guard ring 6a to the third guard ring 6c are arranged in an annular shape so as to surround the outer periphery of the semiconductor chip. In FIG. 4, a case is illustrated in which three first guard rings 6a to third guard rings 6c are arranged, but the number of guard rings may be one or two, four or more, and may be arranged as required. It can be selected as appropriate depending on the withstand voltage and the like.

In the voltage-resistant structure 203, when a voltage is applied to the second main electrode region 14 on the back side of the semiconductor chip, a depletion layer is formed from the pn junction region between the second well region 5b and the semiconductor substrate 1 to the outside of the semiconductor chip. Stretching ensures pressure resistance. The first guard ring 6a to the third guard ring 6c extend the depletion layer from the pn junction region between the second well region 5b and the semiconductor substrate 1 in the lateral direction (horizontal direction) to ensure the withstand voltage of the main semiconductor element section 201. It has the function of

As shown at the right end of FIG. 4, an n ⁺ -type stopper region 7 having a resistivity lower than that of the semiconductor substrate 1 is provided on the upper part of the semiconductor substrate 1 . The stopper region 7 has the same potential as the collector potential (high potential side potential).

On the semiconductor substrate 1, a first insulating film (first field insulating film) 11 and a second insulating film (first field insulating film) which is in contact with the first insulating film 11 on the center side (inner side) of the semiconductor chip than the first insulating film 11 are formed. 2 field insulating film) 12 are arranged. A part of the second well region 5b, the first guard ring 6a to the third guard ring 6c, are arranged directly under the second insulating film 12. The thickness T1 of the first insulating film 11 is thicker than the thickness T2 of the second insulating film 12. The thickness T1 of the first insulating film 11 is, for example, about 1000 nm to 2000 nm, and the thickness T2 of the second insulating film 12 is, for example, about 500 nm to 1000 nm.

In FIG. 4, the distance D1 from the outer edge of the second well region 5b (on the outer circumferential side of the semiconductor chip) to the inner edge of the first insulating film 11 (on the center side of the semiconductor chip) Although the distance D1 is longer than the distance D2 from the inner edge (the center side of the semiconductor chip) to the outer edge (the outer circumferential side of the semiconductor chip), the distance D1 may be shorter than the distance D2; D1 may be the same as distance D2. The distance D1 is, for example, about 100 μm to 200 μm, and can be adjusted as appropriate depending on the required breakdown voltage. The distance D2 is, for example, about 500 μm to 600 μm, and can be adjusted as appropriate depending on the required withstand voltage.

The first insulating film 11 and the second insulating film 12 may be made of the same material, or may be made of different materials. The first insulating film 11 may be configured by laminating the second insulating film 12 on an insulating film that constitutes a part of the first insulating film 11. As the first insulating film 11 and the second insulating film 12, for example, a silicon oxide film (SiO ₂ film) can be used, but in addition to the SiO ₂ film, a silicon oxynitride (SiON) film or the like may also be used.

A protection diode 10 is arranged on the first insulating film 11 and the second insulating film 12. The protection diode 10 has a stepped portion at the boundary between the first insulating film 11 and the second insulating film 12 . Note that the protection diode 10 may not extend onto the second insulating film 12 and may be disposed only on the first insulating film 11. That is, the protection diode 10 only needs to be placed on at least the first insulating film 11.

In the semiconductor device 100 according to the embodiment, when the main semiconductor element 101 is turned off, the induced electromotive force of the ignition coil 113 causes the collector voltage to jump up to about several hundred volts. At this time, the occurrence of overvoltage can be prevented by clamping the voltage between the collector gate and the collector gate to about 400 to 550 V, for example, using the protection diode 10. Furthermore, the protection diode 10 has a function of uniformly widening the interval between the equipotential lines extending across the semiconductor substrate 1 between the third guard ring 6c and the stopper region 7.

Although not shown in FIG. 4, the protection diode 10 is composed of, for example, a plurality of p-type semiconductor regions and n-type semiconductor regions arranged alternately in the horizontal direction (horizontal direction in FIG. 4). It can be configured by connecting (multistage) Zener diodes in series. The number of stages of Zener diodes connected in series may be, for example, about 50 to 100 stages, and can be selected as appropriate depending on the required breakdown voltage and the like.

A second interlayer insulating film 13 is arranged on the protection diode 10. The second interlayer insulating film 13 has a stepped portion at the boundary between the first insulating film 11 and the second insulating film 12 . As the second interlayer insulating film 13, phosphorus silica glass (PSG), boron silica glass (BSG), boron phosphorus silica glass (BPSG), silicon nitride (Si ₃ N ₃ ) film, etc. can be used. Further, as the second interlayer insulating film 13, a non-doped silicon oxide film (SiO ₂ film) called “NSG” that does not contain phosphorus (P) or boron (B) can be adopted.

As shown at the right end of FIG. 4, a stopper electrode 8 is arranged on the second interlayer insulating film 13. The outer end of the stopper electrode 8 is in ohmic contact with the stopper region 7 via a contact hole penetrating the second interlayer insulating film 13 and the first insulating film 11 . The inner end of the stopper electrode 8 is in ohmic contact with one outer end of the protection diode 10 via a contact hole provided in the second interlayer insulating film 13 . It is desirable that the protection diode 10 in ohmic contact with the stopper electrode 8 be of n-type.

As shown at the left end of FIG. 4, the first main electrode 2 is arranged to extend onto the second interlayer insulating film 13. A gate runner 3 is arranged on the second interlayer insulating film 13. The gate runner 3 is in ohmic contact with the other end inside the protection diode 10 via a contact hole penetrating the second interlayer insulating film 13 . It is desirable that the protection diode 10 in ohmic contact with the gate runner 3 be of n-type. The gate runner 3 is arranged along the outer periphery of the semiconductor chip. The gate runner 3 is electrically connected to a gate electrode 24 on the side of the main semiconductor element section 201 and a gate pad (not shown) arranged on the main semiconductor element section 201.

As shown in the center of FIG. 4, a first field plate 4a, a second field plate 4b, and a third field plate 4c are arranged on the second interlayer insulating film 13. The first field plate 4a to the third field plate 4c may be made of, for example, aluminum (Al), an alloy mainly composed of Al, such as Al-Si, Al-Copper (Cu)-Si, Al-Cu, etc. Conductive materials can be used.

Among the first field plates 4a to third field plates 4c, the second field plates 4b and the first The field plate 4a is arranged on the second insulating film 12. On the other hand, the outermost third field plate 4c is disposed extending from above the second insulating film 12 to above the first insulating film 11.

The first field plate 4a is arranged so as to partially overlap the first guard ring 6a as a planar pattern. The second field plate 4b is arranged on the second interlayer insulating film 13 so as to partially overlap the second guard ring 6b as a planar pattern. The third field plate 4c is arranged on the second interlayer insulating film 13 so as to partially overlap the third guard ring 6c as a planar pattern. The first field plate 4a to the third field plate 4c are electrically connected to the first guard ring 6a to the third guard ring 6c, respectively, on the front side or the back side of the page of FIG.

The first field plate 4a to the third field plate 4c are arranged in a ring shape so as to surround the outer periphery of the semiconductor chip. As shown in FIG. 3, the first to third field plates 4a to 4c may have a plane pattern extending in parallel. Furthermore, the respective widths and mutual intervals of the first field plate 4a to third field plate 4c do not need to be constant, and the widths and intervals may partially change. The planar patterns of the first to third field plates 4a to 4c extend in a curved manner along the planar pattern protruding toward the center of the semiconductor chip of the protection diode 10. In FIG. 3, the end portion 11a of the first insulating film 11 located directly below the third field plate 4c is schematically shown with a broken line.

In FIG. 4, a case is illustrated in which the width of the first field plate 4a to third field plate 4c increases as the first field plate 4a to third field plate 4c are located on the outer circumferential side. ~The width of the third field plate 4c may be the same. Further, although FIG. 4 illustrates a case where three first field plates 4a to third field plates 4c are arranged, the number of field plates may be one or two, or four or more. , can be selected as appropriate depending on the required withstand voltage, etc.

FIG. 5 shows an enlarged cross-sectional view of the vicinity of the first field plate 4a within the area A surrounded by the broken line in FIG. As shown in FIGS. 4 and 5, the third field plate 4c has a stepped portion at the boundary between the first insulating film 11 and the second insulating film 12. As shown in FIGS. The outer peripheral end of the third field plate 4c is located on the first insulating film 11. The distance D0 of the overlapping portion between the outer edge of the third field plate 4c and the inner edge of the first insulating film 11 is, for example, about 10 μm to 20 μm, but can be adjusted as appropriate.

As shown in FIG. 5, the protection diode 10 is configured by, for example, alternately arranging p-type semiconductor regions 10a, 10c, 10e, and 10g and n-type semiconductor regions 10b, 10d, and 10f. The third field plate 4c extends over the first insulating film 11 so as to cover at least one pn junction of the protection diode 10 disposed on the first insulating film 11. In FIG. 5, a case is illustrated in which the third field plate 4c extends so as to cover one pn junction composed of a p-type semiconductor region 10a and an n-type semiconductor region 10b on the first insulating film 11. However, the third field plate 4c may extend on the first insulating film 11 so as to cover the plurality of pn junctions.

A protective film (passivation film) 9 is arranged on the first field plate 4a to the third field plate 4c. The protective film 9 may be a resistive silicon nitride film (resistive Si ₃ N ₄ film), a polyimide film, or a chemical vapor deposition (CVD) method using tetraethoxysilane (TEOS) gas, which is an organosilicon compound. It can be composed of a single-layer insulating film (TEOS film) or a composite film of these. In particular, by forming the protective film 9 with a resistive Si ₃ N ₄ film, it can be made less susceptible to surface charges. Therefore, withstand voltage can be ensured, and the voltage withstand structure portion 203 can be made narrower.

As described above, in the semiconductor device 100 according to the embodiment, the voltage-resistant structure section 203 includes the first guard ring 6a to the third guard ring 6c, the first field plate 4a to the third field plate 4c, and the protective film 9. This ensures the breakdown voltage of the main semiconductor element section 201.

<Comparative example>
Next, a semiconductor device according to a comparative example will be described with reference to FIG. In the semiconductor device according to the comparative example, in the voltage withstanding structure, the inner end of the first insulating film 11 does not overlap with the outer end of the third field plate 4c at the outermost periphery, but extends from the third field plate 4c. This differs from the semiconductor device 100 according to the embodiment shown in FIG. 4 in that they are arranged apart from each other.

According to the semiconductor device according to the comparative example, by having the plurality of first field plates 4a to third field plates 4c and first guard rings 6a to third guard rings 6c, one field plate and one guard ring can be used. Whereas the breakdown voltage in the case where the voltage is 400V is, for example, about 400V, the breakdown voltage can be improved to about 500V or more, for example.

However, since the semiconductor device according to the comparative example has a plurality of first field plates 4a to third field plates 4c and first guard rings 6a to third guard rings 6c, it has one field plate and one guard ring. The area of the second insulating film 12, which is thinner than the first insulating film 11, is wider than in the case of the first insulating film 11, and electric field concentration is more likely to occur.

FIG. 7 schematically shows equipotential lines L during normal switching and DC application of the semiconductor device according to the comparative example with broken lines. As shown in FIG. 7, the depletion layer extending from the pn junction region between the second well region 5b and the semiconductor substrate 1 sufficiently spreads over the breakdown voltage structure, and the equipotential lines L also spread evenly.

However, while the collector voltage jump time during turn-off is several 100 V/several μs, when a transient surge such as an ignition surge is applied, a high dv/dt surge of several 100 V/several ns is applied. FIG. 8 is a high dv/dt transient surge application waveform, and shows the waveforms of the gate voltage Vg, collector current Ic, collector voltage Vc, and surge voltage Vs of the IGBT constituting the main semiconductor element section 201. The maximum value of the collector voltage Vc is about 500V, and is clamped by a protection diode 10 between the collector and the gate. FIG. 9 shows a representative waveform at the surge application point indicated by the broken line in FIG. 8. As shown in FIG. 9, the collector voltage Vc suddenly jumps up to 700V or more.

FIG. 10 schematically shows equipotential lines L during a high dv/dt surge of the semiconductor device according to the comparative example using broken lines. As shown in FIG. 10, during a high dv/dt surge, the depletion layer is difficult to expand, and the electric field strength increases at the portion where the protection diode 10 straddles the breakdown voltage structure. Therefore, as shown by a region A surrounded by a broken line in FIG. 10, an electric field is concentrated at and near the edge of the outermost field plate 4c, which may lead to breakdown of the insulating film.

Further, FIG. 11 schematically shows equipotential lines L during a high dv/dt surge in a planar layout of a semiconductor device according to a comparative example using broken lines. As shown in FIG. 11, a potential difference occurs between the portion where the protection diode 10 is placed and the other portions, causing distortion in the equipotential line L. As a result, as shown by a region A surrounded by a broken line in FIG. 11, an electric field is concentrated in the region where the third field plate 4c and the protection diode 10 intersect, which may lead to breakdown of the insulating film.

<Effect>
In contrast, in the semiconductor device according to the embodiment, as shown in FIG. 3 to FIG. The end portion is located on the inner end portion of the first insulating film 11 which is thicker than the second insulating film 12 . Therefore, when a high dv/dt surge is applied, electric field concentration at and near the outer end of the third field plate 4c can be alleviated, and breakdown of the insulating film can be prevented.

Furthermore, in the stepped portion between the second insulating film 12 and the first insulating film 11 where the thickness of the insulating film changes, potential changes are large and electric field concentration tends to occur. In contrast, by arranging the stepped portion between the second insulating film 12 and the first insulating film 11 directly under the end of the third field plate 4c, the second insulating film 12 and the first insulating film 11 It is possible to reduce the electric field strength at the boundary between the two and prevent breakdown of the insulating film. Therefore, according to the semiconductor device according to the embodiment, it is possible to achieve high breakdown voltage while ensuring high surge resistance.

Further, according to the semiconductor device according to the embodiment, it is possible to use an existing insulating film to prevent breakdown of the insulating film at high dv/dt. Therefore, it is possible to ensure high surge resistance without adding any additional steps or changing the basic structural dimensions of the pressure-resistant structure.

FIG. 12 schematically shows the equipotential line L during a high dv/dt surge of the semiconductor device according to the comparative example using a broken line. The equipotential lines L are shown thinner than in the case. Further, in FIG. 12, illustration of the protection diode 10, the second interlayer insulating film 13, etc. is omitted for convenience. As shown in FIG. 12, in the semiconductor device according to the comparative example, electric field concentration occurs in the second insulating film 12 near the outer end of the third field plate 4c when a high dv/dt surge is applied.

On the other hand, FIG. 13 schematically shows equipotential lines L during a high dv/dt surge of the semiconductor device according to the embodiment using broken lines. In FIG. 13, illustration of the protection diode 10, the second interlayer insulating film 13, etc. is omitted for convenience. As shown in FIG. 13, in the semiconductor device according to the embodiment, by arranging the outer end of the third field plate 4c on the first insulating film 11, the equipotential lines L in the first insulating film 11 are By widening the interval, the potential gradient can be made gentler. Therefore, electric field concentration at the outer end of the third field plate 4c can be alleviated, and breakdown of the insulating film can be prevented.

<Method for manufacturing semiconductor devices>
Next, an example of a method for manufacturing the semiconductor device 100 according to the embodiment will be described with reference to FIGS. 14 to 19. Note that the method for manufacturing the semiconductor device 100 according to the embodiment of the present invention described below is an example, and various other manufacturing methods including this modification are possible within the scope of the scope of the claims. Of course, this can be realized by any method.

First, a semiconductor substrate (Si substrate) made of n-type Si is prepared. P-type impurity ions are implanted into the back surface (lower surface) of this Si substrate. Thereafter, impurity ions are activated and thermally diffused by heat treatment. As a result, a p ⁺ -type collector region 14 is formed on the back surface of the Si substrate, and an n-type semiconductor substrate 1 is defined on the collector region 14 (see FIG. 4). Note that the semiconductor substrate 1 may be epitaxially grown on the upper surface of the collector region 14. Next, as shown in FIG. 14, a first insulating film 11 is deposited on the semiconductor substrate 1 by a thermal oxidation method, a chemical vapor deposition (CVD) method, or the like. Then, the first insulating film 11 is patterned using photolithography technology, etching technology, and the like.

Next, by photolithography technology, ^ion implantation, heat treatment, etc., as ^shown in FIG. A ring 6c and an n ⁺ type stopper region 7 are formed. Note that the p ⁺ type first well region 5a, the n ⁺ type main electrode regions 21a, 21b, and the p type injection control regions 22a, 22b on the main semiconductor element portion 201 side shown in FIG. 4 may also be formed at the same time. good.

Next, as shown in FIG. 16, a second insulating film 12 thinner than the first insulating film 11 is deposited on the semiconductor substrate 1 by a thermal oxidation method, a CVD method, or the like. The second insulating film 12 may also be laminated on the first insulating film 11, and in this case, the laminated film of the first insulating film 11 and the second insulating film 12 is defined as the "first insulating film 11". .

Next, polysilicon is deposited on the first insulating film 11 and the second insulating film 12 by CVD method or the like. Then, p-type regions and n-type regions are alternately formed in the polysilicon by photolithography, ion implantation, heat treatment, and the like. Thereafter, polysilicon and a portion of the second insulating film 12 are selectively removed using photolithography, etching, or the like. As a result, a protection diode 10 is formed on the second insulating film 12, as shown in FIG. Note that the gate electrode 24 made of polysilicon on the main semiconductor element portion 201 side shown in FIG. 4 may also be formed at the same time.

Next, a second interlayer insulating film 13 is deposited on the protection diode 10 by a CVD method or the like. Then, by selectively removing a portion of the second interlayer insulating film 13 using photolithography, etching, or the like, a portion of the upper surface of the protection diode 10 is exposed. Note that the first interlayer insulating film 25 on the main semiconductor element portion 201 side shown in FIG. 4 may also be formed at the same time as the second interlayer insulating film 13.

Next, a metal film is deposited on the second interlayer insulating film 13 by sputtering, vapor deposition, or the like. Then, the first main electrode 2, the gate runner 3, the first to third field plates 4a to 4c, and the stopper electrode 8 are formed by patterning the metal film using photolithography, etching, and the like. Next, the semiconductor device according to the embodiment shown in FIG. 100 is completed.

As described above, according to the method for manufacturing the semiconductor device 100 according to the embodiment, it is possible to realize the semiconductor device 100 that can ensure surge resistance while increasing the voltage resistance.

(Other embodiments)
As described above, the present invention has been described by way of embodiments, but the statements and drawings that form part of this disclosure should not be understood as limiting the present invention. Various alternative embodiments, implementations, and operational techniques will be apparent to those skilled in the art from this disclosure.

For example, as shown in FIG. 2, the semiconductor device 100 according to the embodiment is a one-chip igniter in which the main semiconductor element section 201 and the control circuit section 202 are monolithically integrated on the same chip. The semiconductor device according to the above may be a multi-chip igniter as a hybrid integrated circuit in which the main semiconductor element section 201 and the control circuit section 202 are mounted on separate chips. In this case, the semiconductor device 100 according to the embodiment may be included in the category of a discrete device having the main semiconductor element section 201 and the voltage-resistant structure section 203 built into the semiconductor chip. Whether it is a semiconductor integrated circuit or an individual device, the voltage-resistant structure section 203 of the semiconductor device 100 according to the embodiment is adjacent to the main semiconductor element section 201 and has a planar pattern, as shown in FIGS. 2 to 4. It is arranged at a position on the outer peripheral side of the upper semiconductor chip. Even in the configuration as an individual device, since the protection diode 10 is integrated on the surface of the semiconductor chip, the semiconductor device 100 according to the embodiment can be included in the category of a semiconductor integrated circuit in a broad sense.

Further, although a planar type vertical IGBT is illustrated as the main semiconductor element used in the semiconductor device of the embodiment, the present invention can also be applied to a trench gate type vertical IGBT and a planar type or trench gate type vertical MOSFET. The device is applicable. In the case of forming a MOSFET, the p ⁺ -type second main electrode region 14 shown in FIG. 4 may be replaced with an n ⁺ -type drain region. Furthermore, the main semiconductor element may be a power semiconductor element such as a vertical MOS SIT or a planar MOS SIT, or more generally, a power semiconductor element such as a vertical MIS transistor or a planar MIS transistor. good. Furthermore, the main semiconductor element may be an SI thyristor. Further, the semiconductor device according to the embodiment of the present invention is suitable as an igniter used in, for example, an internal combustion engine of an automobile, but it is also applicable to a structure in which various other main semiconductor elements are integrated.

Thus, it goes without saying that the present invention includes various embodiments not described here. Therefore, the technical scope of the present invention is determined only by the matters specifying the invention in the claims that are reasonable from the above description.

1...Semiconductor substrate 2...Main electrode (emitter electrode)
3...Gate runners 4a to 4c...Field plates 5a, 5b...Well regions 6a to 6c...Guard ring 8...Stopper electrode 9...Protective film 10...Protective diode 10a to 10g...Semiconductor region 13...Interlayer insulating film 14...Second main Electrode regions 21a, 21b...First main electrode regions 22a, 22b...Injection control region 23...Gate insulating film 24...Gate electrode 25...Interlayer insulating film 100...Semiconductor device (semiconductor chip)
101... Main semiconductor element 102... Protection diode 103... Control circuit section 104, 105, 106... Terminal 110... Battery 112... Electronic control unit (ECU)
113...Ignition coil 114...Spark plug 201...Main semiconductor element section 202...Control circuit section 203...Voltage-resistant structure section

Claims (8)

A semiconductor device having a main semiconductor element portion disposed on the center side of a semiconductor chip, and a withstand voltage structure portion disposed on the outer peripheral side of the semiconductor chip,
The pressure-resistant structure section is
a semiconductor substrate of a first conductivity type;
a first insulating film selectively disposed on the semiconductor substrate;
a second insulating film disposed closer to the center of the semiconductor chip than the first insulating film on the semiconductor substrate and thinner than the first insulating film;
a protection diode at least partially disposed on the first insulating film;
an interlayer insulating film disposed on the protection diode;
a field plate disposed on the interlayer insulating film;
Equipped with
The outer circumferential end of the field plate overlaps the protective diode disposed on the first insulating film, and is located on the central end of the first insulating film. Semiconductor equipment. A plurality of field plates are arranged spaced apart from each other on the interlayer insulating film,
2. The outer peripheral end of the field plate located closest to the outer peripheral side of the plurality of field plates is located on the central end of the first insulating film. 1. The semiconductor device according to 1. 3. The semiconductor device according to claim 1, further comprising a second conductivity type guard ring provided above the semiconductor substrate directly below the field plate. 4. The semiconductor device according to claim 3, wherein the guard ring is located directly under the second insulating film. 5. The semiconductor device according to claim 1, wherein the protection diode extends from above the first insulating film to above the second insulating film. 6. The semiconductor device according to claim 1, further comprising a protective film made of a resistive silicon nitride film and arranged to cover the field plate. a well region of a second conductivity type provided in an upper part of the semiconductor substrate extending from the main semiconductor element section to the breakdown voltage structure section;
a main electrode in contact with the surface of the well region in the main semiconductor element portion;
7. The semiconductor device according to claim 1, further comprising: The distance from the outer edge of the well region to the center edge of the first insulating film is the distance from the center edge of the first insulating film to the outer edge of the first insulating film. 8. The semiconductor device according to claim 7, wherein the semiconductor device is shorter than .

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