JP7379845B2 - Semiconductor devices, semiconductor device manufacturing methods, electronic devices, electronic equipment, and mobile objects - Google Patents

Description

The present invention relates to a semiconductor device, a method for manufacturing a semiconductor device, an electronic device, an electronic device, and a moving body.

Patent Document 1 describes an Al electrode provided on the surface of a semiconductor chip, a passivation film in which an opening is formed to expose the Al electrode, a TiN layer and a Cu layer provided on the Al electrode, A semiconductor device is disclosed that includes a metal post made of Cu, Au, etc. provided on a Cu layer, and a solder ball provided on the metal post.

Among these, the TiN layer is provided as a barrier metal on the Al electrode surface exposed from the passivation film through the opening. Further, in Patent Document 1, this TiN layer is provided so as to extend over the inner wall of the opening and the upper surface of the passivation film.

Japanese Patent Application Publication No. 2000-164621

However, the inventors have found that the TiN layer reduces adhesion to some metals. Such a decrease in adhesion causes porosity at the bonding interface when a conductor layer such as a Cu layer or a Ni layer is disposed on the TiN layer, resulting in a decrease in bonding strength.

On the other hand, the TiN layer also has the advantage of functioning as an antireflection film when patterning a passivation film using photolithography. That is, the TiN layer has a lower reflectance than Al at the wavelength of light used in photolithography. Therefore, by providing a TiN layer on an electrode pad such as an Al electrode, reflection of light can be suppressed when patterning a passivation film provided to cover the Al electrode. As a result, it is possible to suppress a decrease in patterning accuracy.

In light of the above, there is a need to suppress a decrease in bonding strength between an electrode pad and a conductor layer provided thereon while maintaining patterning accuracy of a passivation film.

A semiconductor device according to an application example of the present invention includes a semiconductor substrate;
an electrode pad provided on the semiconductor substrate;
a passivation film having an opening, provided on the semiconductor substrate and on a surface of the electrode pad opposite to the semiconductor substrate side, and overlapping a part of the electrode pad in plan view;
a first conductor layer provided on a surface of the electrode pad on a side opposite to the semiconductor substrate side inside the opening in a plan view;
a second conductor layer provided between the electrode pad and the passivation film in cross-sectional view and having a lower light reflectance than the electrode pad;
It is characterized by having the following.

FIG. 1 is a perspective view showing a semiconductor device including a semiconductor device according to a first embodiment. FIG. 2 is a cross-sectional view taken along line AA in FIG. 1. 3 is an enlarged view of part B in FIG. 2. FIG. This is a modification of the semiconductor chip shown in FIG. 2. 3 is a process diagram showing a method for manufacturing the semiconductor chip shown in FIG. 2. FIG. 3 is a diagram for explaining a method of manufacturing the semiconductor chip shown in FIG. 2. FIG. 3 is a diagram for explaining a method of manufacturing the semiconductor chip shown in FIG. 2. FIG. 3 is a diagram for explaining a method of manufacturing the semiconductor chip shown in FIG. 2. FIG. 3 is a diagram for explaining a method of manufacturing the semiconductor chip shown in FIG. 2. FIG. 3 is a diagram for explaining a method of manufacturing the semiconductor chip shown in FIG. 2. FIG. 3 is a diagram for explaining a method of manufacturing the semiconductor chip shown in FIG. 2. FIG. 3 is a diagram for explaining a method of manufacturing the semiconductor chip shown in FIG. 2. FIG. 3 is a diagram for explaining a method of manufacturing the semiconductor chip shown in FIG. 2. FIG. 3 is a diagram for explaining a method of manufacturing the semiconductor chip shown in FIG. 2. FIG. FIG. 3 is a partially enlarged view of a semiconductor device according to a second embodiment. FIG. 1 is a cross-sectional view showing an oscillator that is an electronic device according to an embodiment. FIG. 1 is a perspective view showing a mobile personal computer that is an electronic device according to an embodiment. FIG. 1 is a plan view showing a mobile phone that is an electronic device according to an embodiment. FIG. 1 is a perspective view showing a digital still camera, which is an electronic device according to an embodiment. FIG. 1 is a perspective view showing an automobile that is a moving object according to an embodiment.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor device, a method for manufacturing a semiconductor device, an electronic device, an electronic device, and a moving body of the present invention will be described in detail based on preferred embodiments shown in the accompanying drawings.

≪First embodiment≫
<Semiconductor device>
First, a semiconductor device according to a first embodiment will be described.

FIG. 1 is a perspective view showing a semiconductor device including a semiconductor device according to a first embodiment. FIG. 2 is a cross-sectional view taken along line AA in FIG. FIG. 3 is an enlarged view of part B in FIG. 2. In addition, in this specification, "provided on" as in "provided on a surface" or "provided on a substrate" refers to the state of being provided in contact with the surface, substrate, etc. , or a state in which it is provided on the surface, substrate, etc. with an arbitrary inclusion interposed therebetween.

A semiconductor device 1 shown in FIG. 1 includes a die pad 2, a semiconductor chip 3 (semiconductor device) provided on the die pad 2, and leads 4. Each of these parts is covered with a mold resin (not shown).

That is, the semiconductor device 1 shown in FIG. 1 is a device in which a semiconductor chip 3, which is a semiconductor device according to an embodiment, is mounted in a package. Note that the package structure shown in FIG. 1 is an example, and a lead frame type package such as a QFP (Quad Flat Package) shown in FIG. 1 may also be used. It may also be a face-down type package such as.

As shown in FIG. 2, the semiconductor chip 3 includes a semiconductor substrate 31, an electrode pad 32, a passivation film 33, a first conductor layer 34, a second conductor layer 35, an electrode pad 32, and a lead 4. and a bonding wire 51 connecting the two. Each part will be explained below.

The semiconductor substrate 31 is a small plate-shaped piece made of, for example, a Si substrate or other semiconductor material on which an integrated circuit (not shown) is formed.

The electrode pad 32 is a pad that serves as an electrode for external connection of the integrated circuit. The electrode pads 32 have a film shape, and a plurality of electrode pads 32 are arranged on the semiconductor substrate 31 at predetermined intervals.

The main material of the electrode pad 32 is not particularly limited as long as it is a conductive material, but is preferably Al or an Al alloy. These materials are useful as the main material for the electrode pad 32 because of their high conductivity. Note that in this specification, the main material refers to a constituent material having a content of 80% by mass or more.

The thickness of the electrode pad 32 is preferably 0.1 μm or more and 5.0 μm or less, more preferably 0.5 μm or more and 4.5 μm or less. By setting the thickness of the electrode pad 32 within the above range, even when the surface of the electrode pad 32 is subjected to a treatment such as etching, the thickness can be maintained to the extent that conductivity does not deteriorate.

The passivation film 33 is provided on the semiconductor substrate 31 and on the surface 322 of the electrode pad 32 opposite to the semiconductor substrate 31. The passivation film 33 has an opening 332 that overlaps with the electrode pad 32 in a plan view from the thickness direction. Note that the opening 332 is formed by etching a portion of the passivation film 33 that overlaps the electrode pad 32 in a plan view into a predetermined shape. Therefore, in plan view, the passivation film 33 is not formed inside the opening 332 of the electrode pad 32. In other words, the opening 332 is provided inside the outer edge of the electrode pad 32 and exposes the center portion 326 of the electrode pad 32 from the passivation film 33. The passivation film 33 extends from the top of the semiconductor substrate 31 through the side surface of the electrode pad 32 until it overlaps the outer edge 324 of the electrode pad 32.

The main material of the passivation film 33 is not particularly limited as long as it is an insulating material, and examples thereof include inorganic materials such as silicon oxide, silicon nitride, and silicon oxynitride, as well as organic materials.

The thickness of the passivation film 33 is not particularly limited, but is preferably 0.1 μm or more and 5.0 μm or less, more preferably 0.3 μm or more and 3.0 μm or less.

The first conductor layer 34 is provided within the opening 332 on the center portion 326 that is the surface of the electrode pad 32 opposite to the semiconductor substrate 31 . As shown in FIG. 2, the first conductor layer 34 fills the opening 332 and also extends outside the opening 332, specifically on the passivation film 33 covering the outer edge 324 of the electrode pad 32. It is preferable that the According to such a configuration, the passivation film 33 can be sandwiched between the electrode pad 32 and the first conductor layer 34.

The main material of the first conductor layer 34 is not particularly limited as long as it is a conductive material, but is preferably Ni or a Ni alloy. These materials are useful as the main material of the first conductor layer 34 because they have good bonding properties with Al and Al alloys that are often used as constituent materials of the electrode pads 32.

The thickness of the first conductor layer 34 is preferably 2.0 μm or more and 10.0 μm or less, more preferably 3.0 μm or more and 5.0 μm or less. By setting the thickness of the first conductor layer 34 within this range, a sufficient buffering function can be imparted to the first conductor layer 34. This makes it difficult for the load to be transmitted to the electrode pad 32 side even if a large load is applied when bonding wire 51 is bonded onto the first conductor layer 34, for example. As a result, the influence of the load on the electrode pads 32 and the semiconductor substrate 31 can be alleviated.

The second conductor layer 35 is provided between the electrode pad 32 and the passivation film 33, as shown in FIG. Specifically, the second conductor layer 35 is located between the outer edge 324 of the electrode pad 32 and the passivation film 33 covering it. Therefore, the second conductor layer 35 is not provided on the central portion 326 of the electrode pad 32, but is selectively provided on the outer edge portion 324. Note that the second conductor layer 35 will be detailed later.

Further, the semiconductor chip 3 shown in FIG. 2 further includes a third conductor layer 36 and a fourth conductor layer 37.

Of these, the third conductor layer 36 is provided on the first conductor layer 34, that is, on the surface of the first conductor layer 34 opposite to the electrode pad 32. This third conductor layer 36 is interposed between the first conductor layer 34 and the fourth conductor layer 37 to improve the adhesion between them and to prevent the first conductor layer 34 from diffusing into the fourth conductor layer 37. Acts as a barrier layer to prevent

The main material of the third conductor layer 36 is not particularly limited as long as it is a conductive material and has good adhesion to both the first conductor layer 34 and the fourth conductor layer 37, but for example, Pd Alternatively, a Pd alloy may be mentioned.

The thickness of the third conductor layer 36 is preferably 10 nm or more and 500 nm or less, more preferably 30 nm or more and 300 nm or less. Thereby, the effect of enhancing the adhesion and barrier properties described above is fully exhibited.

Note that the third conductor layer 36 may be provided as necessary; for example, when the adhesion between the first conductor layer 34 and the fourth conductor layer 37 is good, or when the first conductor layer 34 and the bonding wire 51 It may be omitted if the contact resistance with, etc. is small.

Further, the fourth conductor layer 37 is provided on the third conductor layer 36, that is, on the surface of the third conductor layer 36 opposite to the first conductor layer 34. This fourth conductor layer 37 contributes to bonding of the bonding wire 51, for example. Thereby, the contact resistance with the bonding wire 51 can be reduced.

If the main material of the fourth conductor layer 37 is a conductive material and has a low contact resistance with a member for electrical connection with the semiconductor chip 3, such as the bonding wire 51, there are no particular limitations. However, for example, Au or an Au alloy can be mentioned.

The thickness of the fourth conductor layer 37 is preferably 10 nm or more and 500 nm or less, more preferably 30 nm or more and 300 nm or less. Thereby, the effect of reducing the contact resistance described above is fully exhibited.

Note that the fourth conductor layer 37 may be provided as necessary, and may be omitted, for example, when the contact resistance between the first conductor layer 34 and the bonding wire 51 etc. is small.

One end of the bonding wire 51 is bonded to the fourth conductor layer 37 of the semiconductor chip 3, and the other end is bonded to the lead 4.

The main material of the bonding wire 51 is not particularly limited as long as it is a conductive material, and examples thereof include Cu or a Cu alloy, Au or an Au alloy, Al or an Al alloy, and the like.

The semiconductor chip 3 has been described above, and next, the die pad 2 and leads 4 will be described.

The die pad 2 is a member that supports and fixes the semiconductor chip 3. Furthermore, the leads 4 are provided adjacent to the die pad 2 and are electrically connected to the semiconductor chip 3 via bonding wires 51 . The leads 4 extend, for example, to the outside of the molded resin (not shown), and serve as external connection terminals of the semiconductor device 1.

Here, FIG. 4 shows a modification of the semiconductor chip 3 shown in FIG.
In FIG. 4, a stud bump 52 is arranged in place of the bonding wire 51 described above. The stud bumps 52 are used when the semiconductor chip 3 is mounted on various substrates or various packages by, for example, flip chip bonding.

Like the main material of the bonding wire 51, the main material of the stud bump 52 is not particularly limited as long as it is a conductive material, and examples thereof include Cu or a Cu alloy, Au or an Au alloy, Al or an Al alloy, and the like.

As described above, the semiconductor chip 3 (semiconductor device) is provided with the first conductor layer 34, the third conductor layer 36, and the fourth conductor layer 37 on the side of the electrode pad 32 opposite to the semiconductor substrate 31. A bonding wire 51 or stud bump 52 is provided. Thereby, the semiconductor chip 3 can be mounted by wire bonding or flip chip bonding. Note that during mounting, a load is applied to the electrode pad 32, but this load can be alleviated mainly due to the provision of the first conductor layer 34. This makes it possible to reduce the negative effects caused by loads during mounting. Further, due to this effect, it is not necessary to make the electrode pad 32 thicker than necessary, so that the manufacturing process of the semiconductor chip 3 can be simplified.

<Method for manufacturing semiconductor devices>
Next, a method for manufacturing a semiconductor device according to an embodiment will be described.

FIG. 5 is a process diagram showing a method for manufacturing the semiconductor chip 3 shown in FIG. 2. 6 to 14 are diagrams for explaining a method of manufacturing the semiconductor chip 3 shown in FIG. 2, respectively. Note that FIGS. 7 to 14 each show a region corresponding to the cross-sectional view taken along the line CC in FIG. 6.

As shown in FIG. 5, the method for manufacturing the semiconductor chip 3 to which the method for manufacturing a semiconductor device according to the embodiment is applied includes a preparation step S01, an antireflection film forming step S02, an insulating film forming step S03, and insulating film patterning. The method includes a step S04, a second conductor layer forming step S05, and a first conductor layer forming step S06. Each step will be explained in sequence below.

[1] Preparation process S01
First, a semiconductor wafer 310 shown in FIG. 6 is prepared. This semiconductor wafer 310 has a plurality of rectangular chip regions 30. These chip regions 30 are regions that will become semiconductor chips 3 by individualization. In each chip region 30, electrode pads 32 are formed, as shown in FIGS. 6 and 7. Note that the number of chip regions 30 that the semiconductor wafer 310 has may be one.

[2] Anti-reflection film forming step S02
Next, as shown in FIG. 8, an antireflection film 350 is formed to cover the electrode pad 32. The antireflection film 350 is a film for forming the second conductor layer 35 and has a lower light reflectance than the electrode pad 32. Such an antireflection film 350 is formed by various vapor deposition methods such as sputtering and ion plating. Then, the antireflection film 350 is obtained by patterning the obtained vapor deposited film by photolithography, etching, etc. as necessary.

[3] Insulating film forming step S03
Next, as shown in FIG. 9, an insulating film 330 is formed on the semiconductor wafer 310 and the antireflection film 350. The insulating film 330 is a film for forming the passivation film 33. The insulating film 330 is formed by, for example, a vapor deposition method such as CVD (Chemical Vapor Deposition).

[4] Insulating film patterning step S04
Next, the insulating film 330 is patterned. In patterning the insulating film 330, first, as shown in FIG. 10, a photoresist film 91 is formed to cover the insulating film 330.

Subsequently, as shown in FIG. 11, the photoresist film 91 is irradiated with light L through the transparent portion 922 of the mask 92 to perform photolithography processing, that is, exposure and development processing. As a result, if the photoresist film 91 has positive photosensitivity, for example, the exposed portion is removed and the photoresist film 91 is patterned, as shown in FIG.

Subsequently, the insulating film 330 is etched using the patterned photoresist film 91 as a mask. For the etching process, one or both of dry etching and wet etching is used. As a result, as shown in FIG. 13, an opening 332 is formed in the insulating film 330, a passivation film 33 is obtained, and the electrode pad 32 is exposed within the opening 332.

Here, the light L used in the photolithography process is irradiated onto the photoresist film 91, and also transmitted through the photoresist film 91 and the insulating film 330, and is also irradiated onto the antireflection film 350. At that time, if the antireflection film 350 were not present, the light L would be irradiated onto the electrode pad 32. However, the electrode pad 32 is made of a material with relatively high reflectance, such as Al or an Al alloy. For this reason, the irradiated light L is reflected by the electrode pad 32 and may also be irradiated onto a portion of the photoresist film 91 that is covered by the shielding portion 924 of the mask 92 . In this case, the exposure process is performed on unintended portions, resulting in a problem that the patterning accuracy of the insulating film 330 is reduced.

Therefore, in this embodiment, as described above, the antireflection film 350 is formed on the electrode pad 32. By forming such an antireflection film 350 in advance, the reflectance of the electrode pad 32 can be lowered. Thereby, reflection of the light L can be suppressed, and a decrease in resolution during exposure and development processing of the photoresist film 91 can be suppressed.

[5] Second conductor layer forming step S05
Next, the antireflection film 350 in the area corresponding to the opening 332 is removed. Specifically, after the opening 332 is formed in the insulating film 330 and the passivation film 33 is obtained, the antireflection film 350 is then etched using the passivation film 33 as a mask. For the etching process, one or both of dry etching and wet etching is used. In this way, the anti-reflection film 350 can be patterned, and the opening 352 can be formed in the anti-reflection film 350 at a portion corresponding to the central portion 326 of the electrode pad 32. On the other hand, the antireflection film 350 remains in a portion corresponding to the outer edge portion 324 of the electrode pad 32, that is, in a portion sandwiched between the electrode pad 32 and the passivation film 33. This antireflection film 350 becomes the second conductor layer 35 shown in FIG.

Note that since the antireflection film 350 is very thin, it may be removed together with the opening 332 at the stage of forming it. That is, the insulating film patterning step S04 and the second conductor layer forming step S05 may be performed simultaneously.

As the etching solution used in wet etching, for example, a dry etching residue removing agent, a resist stripping solution, a resist stripping solution for a bump process, etc. are used. Further, the etching solution is preferably organic, and the pH is preferably strongly alkaline with a pH of about 10 or more and 13 or less.

Further, after using the above-mentioned strong alkaline etching solution, a weakly alkaline etching solution having a pH of about 7.5 or more and 9.0 or less may be used, if necessary. Since the surface of the electrode pad 32 is thereby removed, the antireflection film 350 is also removed more reliably at that time.
After that, the photoresist film 91 is removed.

Note that the main material of the antireflection film 350 and the main material of the second conductor layer 35 are preferably TiN, TiON, or a Ti alloy. Since these have a lower reflectance of light L than the electrode pads 32, the patterning accuracy of the insulating film 330 is less likely to deteriorate. Therefore, it is useful as the main material of the antireflection film 350 and the main material of the second conductor layer 35.

The thickness of the antireflection film 350 and the second conductor layer 35 is preferably 10 nm or more and 100 nm or less, more preferably 20 nm or more and 30 nm or less. By setting the thickness of the antireflection film 350 and the second conductor layer 35 within this range, they function sufficiently as the above-mentioned antireflection film and are less likely to be interrupted even when the film thickness varies.

Here, although the antireflection film 350 has the function of preventing reflection as described above and is useful in that respect, on the other hand, the antireflection film 350 is disposed on the surface of the electrode pad 32 opposite to the semiconductor substrate 31. If so, a problem arises in that the formation of the first conductor layer 34 and the bonding between the electrode pad 32 and the first conductor layer 34 are obstructed.

To address this concern, in this step, the antireflection film 350 located within the opening 332 is removed as described above. This exposes the electrode pad 32, so that the electrode pad 32 and the first conductor layer 34 can be brought into direct contact by forming the first conductor layer 34 inside the opening 332 in a step described later. As a result, it is possible to suppress a decrease in the bonding strength between the electrode pad 32 and the first conductor layer 34, and it is possible to suppress the occurrence of defects such as defects and peeling during molding of the first conductor layer 34.

[6] First conductor layer forming step S06
Next, as shown in FIG. 14, a first conductor layer 34 is formed on the electrode pad 32 exposed in the opening 332. The first conductor layer 34 is formed by, for example, a plating method, particularly an electroless plating method.

Subsequently, a third conductor layer 36 and a fourth conductor layer 37 are sequentially formed. These films are formed by a plating method, particularly an electroless plating method.

In the manner described above, a semiconductor wafer 310 on which the chip region 30 shown in FIG. 6 is formed is obtained. Thereafter, the semiconductor wafer 310 is cut into individual pieces to obtain the semiconductor chip 3 including the semiconductor substrate 31.

Thereafter, the semiconductor chip 3 is placed on the die pad 2, and the semiconductor chip 3 and the leads 4 are connected using bonding wires 51. Then, by covering with a molding resin (not shown), a semiconductor chip 3 (semiconductor device) and a semiconductor device 1 are obtained.

As described above, the method for manufacturing a semiconductor device according to the present embodiment includes the preparation step S01 of preparing the semiconductor wafer 310 having the electrode pads 32, and the step of preparing the semiconductor wafer 310 having the electrode pads 32, and applying an anti-reflective material having a lower light reflectance than the electrode pads 32 on the electrode pads 32. An antireflection film forming step S02 in which a film 350 is formed, an insulating film formation step S03 in which an insulating film 330 is formed on the semiconductor wafer 310 and the antireflection film 350, and an opening 332 is formed by patterning the insulating film 330. , an insulating film patterning step S04 for obtaining the passivation film 33, removing the anti-reflection film 350 in a region corresponding to the inside of the opening 332, and forming a second conductor provided between the electrode pad 32 and the passivation film 33 in cross-sectional view. A second conductor layer forming step S05 to obtain the layer 35, and a first conductor layer forming the first conductor layer 34, the third conductor layer 36, and the fourth conductor layer 37 in a region corresponding to the inside of the opening 332 of the electrode pad 32. A layer forming step S06 is included.

According to the method for manufacturing a semiconductor device as described above, since the antireflection film 350 is provided on the electrode pad 32, the insulating film 330 can be patterned with high accuracy, and the passivation film 33 with high dimensional accuracy can be formed. can get. Furthermore, since the step of removing the antireflection film 350 located on the electrode pad 32 is included, it is possible to suppress a decrease in the bonding strength between the electrode pad 32 and the first conductor layer 34. As a result, even when the pitch between the electrode pads 32 is short, highly reliable semiconductor chips 3 can be manufactured with a high yield.

Further, the semiconductor chip 3 (semiconductor device) as described above has a semiconductor substrate 31, an electrode pad 32 provided on the semiconductor substrate 31, and an electrode pad 32 provided on the semiconductor substrate 31 and the electrode pad 32 on the semiconductor substrate 31 side. A passivation film 33 having an opening 332 provided on the side surface and overlapping a part of the electrode pad 32 in a plan view, and a semiconductor substrate 31 side of the electrode pad 32 inside the opening 332 in a plan view. is a first conductor layer 34 provided on the opposite surface, and a second conductor layer provided between the electrode pad 32 and the passivation film 33 in cross-sectional view and having a lower light reflectance than the electrode pad 32. It is equipped with 35.

According to such a semiconductor chip 3, the second conductor layer 35, which has a lower reflectance of light L than the electrode pad 32, is selectively provided between the electrode pad 32 and the passivation film 33. To take advantage of the low light reflectance of the second conductor layer 35 while eliminating the negative effect of inhibiting the bonding between the electrode pad 32 and the first conductor layer 34 by the second conductor layer 35. I can do it. Therefore, it is possible to realize a semiconductor chip 3 in which the patterning accuracy of the passivation film 33 is high and the bonding strength between the electrode pad 32 and the first conductor layer 34 provided thereon is high. As a result, even if the pitch between the electrode pads 32 is short, a highly reliable semiconductor chip 3 can be obtained.

Note that in the above, "planar view" refers to viewing from the thickness direction of the passivation film 33. Further, “cross-sectional view” refers to a view from a direction perpendicular to the thickness direction of the passivation film 33.

≪Second embodiment≫
Next, a semiconductor device and a method for manufacturing the same according to a second embodiment will be described.
FIG. 15 is a partially enlarged view of the semiconductor device according to the second embodiment.

Hereinafter, the second embodiment will be described. In the following explanation, the differences from the first embodiment will be mainly explained, and the explanation of similar matters will be omitted. Further, in FIG. 15, the same components as in the first embodiment are denoted by the same reference numerals.

The second embodiment is similar to the first embodiment except that the configurations of the electrode pad 32, the first conductor layer 34, and the second conductor layer 35 are different.

That is, in FIG. 15, the thickness of the second portion 328 of the electrode pad 32 where the second conductor layer 35 is provided is thicker than the thickness of the first portion 327 where the first conductor layer 34 is provided. . Since the thickness of the second portion 328 is thick in this manner, the thickness of the outer edge portion of the electrode pad 32 can be ensured, so that the reliability of the electrode pad 32 can be improved. On the other hand, since the thickness of the first portion 327 is thin, the second conductor layer 35 attached to the surface is reliably removed, so the bonding strength between the electrode pad 32 and the first conductor layer 34 is increased. can be increased.

It is preferable that the thickness t1 of the first portion 327 is at least 0.2 μm or more. Thereby, the mechanical strength of the first portion 327 can be ensured, and reliability can be improved.

The difference between the thickness t1 of the first portion 327 and the thickness t2 of the second portion 328 is not particularly limited. Thereby, the second conductor layer 35 can be removed more reliably in the first portion 327, and the thickness of the second portion 328 can be ensured.

In addition, in FIG. 15, the first portion 327 extends outside the opening 332 of the passivation film 33. In other words, the passivation film 33 overlaps the first portion 327, which is relatively thin. Thereby, the first conductor layer 34 provided on the first portion 327 is also provided so as to fit between the first portion 327 and the passivation film 33.

According to such a configuration, the first conductor layer 34 is in a state in which the passivation film 33 is sandwiched therebetween. That is, the first conductor layer 34 enters the electrode pad 32 side located below the passivation film 33 in FIG. 15, and also covers the upper side of the passivation film 33 in FIG. Therefore, the first conductor layer 34 is also provided between the electrode pad 32 and the passivation film 33 in cross-sectional view, and the passivation film 33 can be clamped by the first conductor layer 34. As a result, it is possible to improve the mechanical properties of the first conductor layer 34 and suppress peeling.

Note that the first portion 327 and the second portion 328 as shown in FIG. 15 are manufactured as follows.

First, in the first conductor layer forming step S06 described above, prior to forming the first conductor layer 34, the electrode pad 32 is subjected to an etching process. For the etching process, one or both of dry etching and wet etching is used. When the etching process is performed, a portion of the electrode pad 32 corresponding to the opening 332 of the passivation film 33 is etched, and the thickness of that portion is reduced. Note that in this etching, so-called side etching also progresses by increasing the etching amount. Side etching means that the portion of the electrode pad 32 covered with the passivation film 33 is also etched. Furthermore, by etching the electrode pad 32, the second conductor layer 35 provided thereon is also removed. As a result, a first portion 327 and a second portion 328 shown in FIG. 15 are formed.

The length L1 into which the first conductor layer 34 extends is not particularly limited, but is preferably 0.03 μm or more and 0.5 μm or less, more preferably 0.1 μm or more and 0.3 μm or less. Thereby, the passivation film 33 can be more reliably clamped by the first conductor layer 34 and the electrode pad 32, and the above-described peeling etc. can be suppressed.
In the second embodiment as described above, the same effects as in the first embodiment can be obtained.

<Electronic devices>
Next, an electronic device according to an embodiment will be described.

FIG. 16 is a cross-sectional view showing an oscillator that is an electronic device according to an embodiment. In the following description, for convenience of explanation, the upper part of FIG. 16 will be referred to as "upper" and the lower part will be referred to as "lower".

The oscillator 8 shown in FIG. 16 includes a vibrator 82, a semiconductor chip 3 that is the semiconductor device according to the embodiment described above, and a package 86 that accommodates them.

Examples of the resonator 82 include a crystal resonator. Further, the semiconductor chip 3 includes an oscillation circuit that causes the vibrator 82 to oscillate, as well as a temperature compensation circuit, an output circuit, a multiplier circuit, etc., provided as necessary.

The package 86 has a recess 862 opening on the upper surface, a recess 864 opening on the lower surface, and an external connection terminal 866. The vibrator 82 is housed in the recess 862. Furthermore, the recess 862 is sealed with a lid 88. On the other hand, the semiconductor chip 3 is accommodated in the recess 864. The semiconductor chip 3 has stud bumps 842 and is mounted on the bottom surface of the recess 864 by flip-chip bonding.

As described above, the oscillator 8 (electronic device) includes the vibrator 82, and the semiconductor chip 3 (semiconductor device) includes the oscillation circuit that causes the vibrator 82 to oscillate. As described above, the semiconductor chip 3 has high reliability even when the pitch between the electrode pads 32 is short. Therefore, it is possible to realize an oscillator 8 that can be made smaller, more densely packed, and highly reliable.

Note that examples of the oscillator 8 include a crystal oscillator (SPXO), a voltage controlled crystal oscillator (VCXO), a temperature compensated crystal oscillator (TCXO), a voltage controlled SAW oscillator (VCSO), a constant temperature oven integrated crystal oscillator (OCXO), It may be a SAW oscillator (SPSO), a MEMS oscillator, an atomic oscillator, or the like.

In addition to the oscillator 8, the electronic device according to the embodiment includes various sensors such as a gyro sensor, a force sensor, a pressure sensor, a pressure sensor, an image sensor, and a distance sensor. Thereby, it is possible to realize an electronic device that is small in size and highly reliable.

<Electronic equipment>
FIG. 17 is a perspective view showing a mobile personal computer that is an electronic device according to an embodiment.

In FIG. 17, a personal computer 1100 includes a main body 1104 including a keyboard 1102 and a display unit 1106 including a display 1108. movably supported. Such a personal computer 1100 has a built-in semiconductor device 1 for controlling its operation.

FIG. 18 is a plan view showing a mobile phone that is an electronic device according to an embodiment.
In FIG. 18, a mobile phone 1200 includes an antenna (not shown), a plurality of operation buttons 1202, an earpiece 1204, and a mouthpiece 1206, and a display section 1208 is arranged between the operation button 1202 and the earpiece 1204. There is. Such a mobile phone 1200 has a built-in semiconductor device 1 for controlling its operation.

FIG. 19 is a perspective view showing a digital still camera that is an electronic device according to an embodiment.

In FIG. 19, a display unit 1310 is provided on the back of a case 1302 in a digital still camera 1300, and is configured to display based on an imaging signal from a CCD, and the display unit 1310 displays a subject as an electronic image. Functions as a finder. Further, a light receiving unit 1304 including an imaging optical system such as an optical lens, a CCD, etc. is provided on the front side of the case 1302, that is, on the back side in the figure. Then, when the photographer confirms the subject image displayed on the display unit 1310 and presses the shutter button 1306, the CCD imaging signal at that time is transferred and stored in the memory 1308. Such a digital still camera 1300 has a built-in semiconductor device 1 for controlling its operation.

The electronic device as described above includes a semiconductor device 1 including a semiconductor chip 3 (semiconductor device). Since the semiconductor device 1 can be made smaller and more dense, and has higher reliability, it is possible to improve the reliability of electronic equipment.

In addition to the personal computer shown in FIG. 17, the mobile phone shown in FIG. 18, and the digital still camera shown in FIG. inkjet ejection devices, wearable terminals such as HMDs (head mounted displays), laptop personal computers, televisions, video cameras, video tape recorders, car navigation devices, pagers, electronic notebooks with communication functions, electronic dictionaries, calculators, Medical equipment such as electronic game machines, word processors, workstations, video phones, security TV monitors, electronic binoculars, POS terminals, electronic thermometers, blood pressure monitors, blood sugar meters, electrocardiogram measuring devices, ultrasound diagnostic devices, and electronic endoscopes. , fish finders, various measuring instruments, instruments such as vehicles, aircraft, and ships, base stations for mobile terminals, flight simulators, and the like.

<Mobile object>
FIG. 20 is a perspective view showing an automobile as a moving object according to the embodiment.

An automobile 1500 shown in FIG. 20 has the semiconductor device 1 described above built therein. The semiconductor device 1 is, for example, a keyless entry, an immobilizer, a car navigation system, a car air conditioner, an anti-lock brake system (ABS), an air bag, a tire pressure monitoring system (TPMS), an engine control, and a brake. It can be widely applied to electronic control units (ECUs) such as systems, battery monitors for hybrid vehicles and electric vehicles, and vehicle attitude control systems.

The mobile object as described above includes a semiconductor device 1 including a semiconductor chip 3 (semiconductor device). Since the semiconductor device 1 can be made smaller and more dense, and has higher reliability, it is possible to improve the reliability of the mobile object.

Note that the moving body including the semiconductor device 1 may be, for example, a robot, a drone, a two-wheeled vehicle, an aircraft, a ship, a train, a rocket, a spaceship, etc., in addition to the automobile shown in FIG.

Although the semiconductor device, semiconductor device manufacturing method, electronic device, electronic equipment, and moving body of the present invention have been described above based on the illustrated embodiments, the present invention is not limited to these embodiments. The components of can be replaced with any components having similar functions. Moreover, other arbitrary components may be added to the embodiment. Further, the method for manufacturing a semiconductor device of the present invention may include any steps added to the above embodiments. Furthermore, the order of the steps described above may be reversed, and a plurality of steps may be performed simultaneously or overlapping in time.

DESCRIPTION OF SYMBOLS 1... Semiconductor device, 2... Die pad, 3... Semiconductor chip, 4... Lead, 8... Oscillator, 30... Chip region, 31... Semiconductor substrate, 32... Electrode pad, 33... Passivation film, 34... First conductor layer, 35 ... second conductor layer, 36 ... third conductor layer, 37 ... fourth conductor layer, 51 ... bonding wire, 52 ... stud bump, 82 ... vibrator, 86 ... package, 88 ... lid, 91 ... photoresist film, 92... Mask, 310... Semiconductor wafer, 322... Surface, 324... Outer edge, 326... Center, 327... First part, 328... Second part, 330... Insulating film, 332... Opening, 350... Antireflection film , 352... opening, 842... stud bump, 862... recess, 864... recess, 866... external connection terminal, 922... transparent part, 924... shielding part, 1100... personal computer, 1102... keyboard, 1104... main body part, 1106... Display unit, 1108... Display section, 1200... Mobile phone, 1202... Operation button, 1204... Earpiece, 1206... Mouthpiece, 1208... Display section, 1300... Digital still camera, 1302... Case, 1304... Light receiving unit , 1306...Shutter button, 1308...Memory, 1310...Display section, 1500...Automobile, L...Light, S01...Preparation process, S02...Anti-reflection film forming process, S03...Insulating film forming process, S04...Insulating film patterning process, S05...Second conductor layer forming step, S06...First conductor layer forming step

Claims (12)

a semiconductor substrate;
an electrode pad provided on the semiconductor substrate;
a passivation film having an opening, provided on the semiconductor substrate and on a surface of the electrode pad opposite to the semiconductor substrate side, and overlapping a part of the electrode pad in plan view;
a first conductor layer provided on a surface of the electrode pad on a side opposite to the semiconductor substrate side inside the opening in a plan view;
a second conductor layer provided between the electrode pad and the passivation film in cross-sectional view and having a lower light reflectance than the electrode pad;
Equipped with
A semiconductor device, wherein the first conductor layer is also provided between the electrode pad and the passivation film in cross-sectional view. 2. The semiconductor device according to claim 1, wherein the thickness of the electrode pad in a portion where the second conductor layer is provided is thicker than the thickness of the electrode pad in a portion where the first conductor layer is provided. 2. The semiconductor device according to claim 1, wherein the main material of the first conductor layer is Ni or a Ni alloy, and the thickness of the first conductor layer is 2.0 μm or more and 10.0 μm or less. a third conductor layer provided on the opposite surface of the first conductor layer from the electrode pad, and whose main material is Pd or a Pd alloy;
a fourth conductor layer provided on a surface of the third conductor layer opposite to the first conductor layer, the fourth conductor layer being mainly made of Au or an Au alloy;
The semiconductor device according to claim 3, comprising: 5. The semiconductor device according to claim 1, wherein the main material of the second conductor layer is TiN, TiON, or a Ti alloy, and the thickness of the second conductor layer is 10 nm or more and 100 nm or less. 5. The semiconductor device according to claim 1, wherein the main material of the electrode pad is Al or an Al alloy, and the thickness of the electrode pad is 0.1 μm or more and 5.0 μm or less. 5. The semiconductor device according to claim 1, further comprising a bonding wire or a stud bump provided on a side of the electrode pad opposite to the semiconductor substrate. preparing a semiconductor wafer having electrode pads;
forming an antireflection film having a lower light reflectance than the electrode pad on the electrode pad;
forming an insulating film on the semiconductor wafer and on the antireflection film;
The insulating film is patterned to form an opening to obtain a passivation film, and the anti-reflection film in a region corresponding to the inside of the opening is removed to form an opening between the electrode pad and the passivation film in cross-sectional view. obtaining a second conductor layer provided on the
performing an etching process on the electrode pad, etching a part of the electrode pad covered with the passivation film;
forming a first conductor layer in a region of the electrode pad corresponding to the inside of the opening, and providing the first conductor layer between the electrode pad and the passivation film in a cross-sectional view;
A method of manufacturing a semiconductor device, comprising: An electronic device comprising the semiconductor device according to any one of claims 1 to 4. Equipped with a vibrator,
The electronic device according to claim 9, wherein the semiconductor device includes an oscillation circuit that causes the vibrator to oscillate. An electronic device comprising the semiconductor device according to any one of claims 1 to 4. A moving body comprising the semiconductor device according to claim 1 .

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