JP7379251B2 - semiconductor equipment - Google Patents

Description

The present invention relates to a semiconductor device.

2. Description of the Related Art As one field of semiconductor devices, there is a field of vertically structured semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors) in which a current flows vertically to a semiconductor substrate. An insulated gate is also called a trench gate, and is formed by forming a trench on the circuit surface side of a semiconductor substrate and filling the inside of the trench with a conductor such as metal. Therefore, it is important to reliably fill the entire inside of the trench with the conductor. Further, in a semiconductor device having a vertical structure, an electrode is formed on the surface of the semiconductor substrate opposite to the surface on which the trench gate is formed, that is, the back surface. Furthermore, in a semiconductor device having a vertical structure, the thickness of the semiconductor substrate is generally reduced (thinned) in order to reduce on-resistance.

When embedding a conductor, such as a metal, inside a trench, wettability between the embedding metal and the inside of the trench becomes a problem. For example, Patent Document 1 is known as a document that presents one solution to this wettability problem. Patent Document 1 describes an Al-based material forming method in which an Al-based material is formed on a base material, in which an oxygen-containing barrier metal structure is formed, and an antioxidant material and an Al-based material with wettability are formed on the barrier metal structure. A method for forming an Al-based material is disclosed, which is characterized by forming a good metallic material or an Al-based material that also serves as oxidation prevention and a metal material with good wettability, and forming an Al-based material thereon. There is. That is, in the Al-based material forming method according to Patent Document 1, in a semiconductor device having a trench structure, a barrier metal, an oxidation prevention film, and a Ti (titanium) film are formed in the trench, and then the trench is filled with an Al (aluminum)-based material. The structure is disclosed.

Japanese Patent Application Publication No. 06-013380

Here, in a vertically structured semiconductor device such as an IGBT, it is necessary to consider not only the embedding of a conductor into a trench but also the warping of a semiconductor wafer during the manufacturing stage of the semiconductor device. That is, as described above, in a semiconductor device having a vertical structure, the semiconductor substrate is generally made thin, so that warpage is likely to occur in the semiconductor wafer in the first place. In a semiconductor wafer for a semiconductor device having a vertical structure, a trench is further formed on the circuit surface side, and an electrode (back electrode) is formed on the back surface. Therefore, with regard to warpage of the semiconductor wafer, it is necessary to consider not only the thickness of the semiconductor wafer but also the configuration of the trench and back electrode.

With reference to FIG. 3, the above considerations will be explained in more detail. FIG. 3 shows a semiconductor wafer WAF thinned to, for example, about 100 μm, in which a trench (not shown) is formed on the circuit surface 40 side and a back electrode (not shown) is formed on the back surface 41. In such a semiconductor wafer WAF, the tensile stress of the back electrode is strong, and as shown in FIG. 3, convex warpage often occurs on the circuit surface side. Therefore, in a semiconductor device having a vertical structure, one problem is how to alleviate such warpage.

In this regard, Patent Document 1 optimizes the embeddability of the metal material and does not mention warping of the semiconductor wafer. Furthermore, in the technology disclosed in Patent Document 1, if the thickness of the Ti film or TiN (titanium nitride) film, which is the barrier metal on the circuit surface side, is increased in thickness in order to alleviate the occurrence of warpage, the aspect ratio changes and the metal This affects the embeddability of the material and causes voids and spikes.

In view of the above circumstances, it is an object of the present invention to provide a semiconductor device in which warping of the substrate is suppressed while ensuring embedding of a conductor into a trench.

In order to solve the above problems, a semiconductor device according to the present invention includes a semiconductor substrate, an insulating film formed inside a trench formed on a first surface of the semiconductor substrate, and a plurality of insulating films formed on the insulating film. a trench gate having a gate electrode formed on the base metal film, and a back electrode formed on the second surface of the semiconductor substrate, the base metal film having a metal film of The metal film in contact with the gate electrode of the film is a titanium film, and the thickness of the titanium film is in the range of 100 nm to 200 nm.

According to the present invention, it is possible to provide a semiconductor device in which warpage of the substrate is suppressed while ensuring embedding of the conductor into the trench.

1 is a cross-sectional view showing an example of the configuration of a semiconductor device according to an embodiment. 1A is a cross-sectional view showing an example of the structure of a gate electrode and a back electrode of a semiconductor device according to an embodiment, and FIG. 1B is a diagram for explaining an effect. FIG. 2 is a cross-sectional view for explaining warpage of a semiconductor wafer used in a semiconductor device according to the prior art.

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 1 and 2. In the following embodiments, an example in which a semiconductor device according to the present invention is applied to an IGBT will be described.

FIG. 1 shows an example of the configuration of a semiconductor device 10 according to this embodiment. The semiconductor device 10 is an IGBT with a trench gate structure as an example of a semiconductor device, and includes a trench gate 24, a gate oxide film 22, an N-type emitter layer 18, a P-type channel layer 20, an intermediate film 16, a surface metal electrode 12, and It has an active region (insulated gate structure) that controls the current flowing in the thickness direction of the substrate including the protective film 13. Further, under the active region, an N-type substrate 26, a buffer layer (field stop layer: FS layer) 28, a P-type collector layer 30, and a back metal electrode 32 are provided. As the N-type substrate 26, a silicon substrate is used, for example. The semiconductor substrate according to this embodiment is thinned to about 100 μm to 300 μm, and the thickness of the N-type substrate 26 of the semiconductor device 10 is, for example, about 100 μm.

In the semiconductor device 10, by applying a voltage to the trench gate 24, electrons are injected from the N-type emitter layer 18 to the N-type substrate 26 (functioning as a drift layer) via the P-type channel layer 20, and the P-type collector Holes are injected from layer 30 into N-type substrate 26 . As a result, a conductivity modulation effect occurs in the N-type substrate 26, and the resistance is significantly reduced, allowing a large current to flow. At this time, the buffer layer 28 has a function of stopping the depletion layer that has spread into the N-type substrate 26.

FIG. 2(a) shows the details of the structure of the trench gate 24 and the back metal electrode 32. As shown in FIG. 2A, the trench gate 24 of the semiconductor device 10 according to the present embodiment includes a Ti film 50, a TiN film 51, a Ti film 50, a TiN film 51, and a It is configured to include a Ti film 52 and an AlSiCu film 53. On the other hand, the back metal electrode 32 includes an Au film 54, a Ni film 55, a Ti film 56, and an AlSi film 57 formed in this order from the bottom layer side. Note that in manufacturing the semiconductor device 10 using a semiconductor wafer, the trench gate 24 is formed after the back metal electrode 32 is formed.

Here, as described above, in a semiconductor substrate that is thinned to about 100 μm, it is essential to take measures against warpage of the semiconductor substrate. Therefore, in the semiconductor device 10 according to the present embodiment, under the conditions of the structure of the trench gate 24 and the back surface metal electrode 32 shown in FIG. The warpage of the N-type substrate 26 is adjusted (corrected) by adjusting. Further, the Ti film 52 has the function of adjusting warpage, exhibiting wettability to the AlSiCu film 53, and maintaining embeddability.

An example of the trench gate 24 and back metal electrode 32 according to this embodiment will be described with reference to FIG. 2(b). In this embodiment, the film thicknesses of the Ti film 50/TiN film 51/Ti film 52/AlSiCu film 53 constituting the trench gate 24 are, for example, 50 nm/100 nm/X nm/4400 nm, respectively. That is, in the semiconductor device 10 according to the present embodiment, the amount of warpage of the N-type substrate 26 is adjusted by changing the film thickness X of the TiN film 52. Note that, as shown in FIG. 3, the amount of warpage d of the semiconductor wafer WAF is measured by the length of the semiconductor wafer WAF from the plane that is the most distant from the plane when the semiconductor wafer WAF is placed on the plane. On the other hand, the thicknesses of the Au film 54/Ni film 55/Ti film 56/AlSi film 57 constituting the back metal electrode 32 are, for example, 50 nm/400 nm/125 nm/200 nm (total film thickness 775 nm), respectively.

FIG. 2B shows an example of a change in the amount of warpage (μm) d using the thickness (nm) of the Ti film 52 as a parameter. As shown in FIG. 2(b), when the Ti film 52 is not formed (the thickness of the Ti film 52 is 0 nm), the amount of warpage d, which was 6000 μm or more, is reduced to 1500 μm by forming the Ti film 52 with a thickness of 100 nm to 200 nm. It can be seen that it improves to a certain degree. If the amount of warpage is at this level, there will be no practical problem. For this reason, the thickness of the TiN film 52 needs to be set depending on the configuration of the trench gate 24 and the back metal electrode 32, the thickness of the N-type substrate 26, etc., and is set to 100 nm to 200 nm as an example. It can be seen that by this, the amount of warpage when measured on a semiconductor wafer can be significantly improved.

Here, considering the thickness of the Ti film 52 in relation to the thickness of the back metal electrode 32, the total thickness of the back metal electrode 32 was 775 nm. By setting the film thickness ratio to 13% to 26%, the amount of warpage when measured on a semiconductor wafer can be significantly improved. Further, in this embodiment, since the thickness of the N-type substrate 26 was approximately 100 μm, by setting the ratio of the thickness of the Ti film 52 to the thickness of the substrate to be 0.1% to 0.2%, the semiconductor wafer It is possible to significantly improve the amount of warpage when measured by .

Note that since the Ti film 52 forms a eutectic layer with aluminum sputtered at high temperatures, it does not affect the embeddability of the aluminum alloy, and as a result, the generation of voids and spikes in the trench gate is suppressed. Here, if the thickness of the Ti film 52 exceeds 200 nm, the aspect ratio of the trench becomes large, which may lead to deterioration in embedding performance.

As described in detail above, according to the semiconductor device according to the present embodiment, it is possible to provide a semiconductor device in which warping of the substrate is suppressed while ensuring the embedding of the conductor into the trench.

10 Semiconductor device 12 Surface metal electrode 13 Protective film 16 Intermediate film 18 N-type emitter layer 20 P-type channel layer 22 Gate oxide film 24 Trench gate 26 N-type substrate 28 Buffer layer 30 P-type collector layer 32 Back metal electrode 40 Circuit surface 41 Back surface 50 Ti film 51 TiN film 52 Ti film 53 AlSiCu film 54 Au film 55 Ni film 56 Ti film 57 AlSi film WAF Semiconductor wafer

Claims (5)

a semiconductor substrate;
an insulating film formed inside a trench formed on the first surface of the semiconductor substrate, a base metal film having a plurality of metal films formed on the insulating film, and a base metal film formed on the base metal film. a trench gate with a gate electrode;
a back electrode formed on the second surface of the semiconductor substrate,
The metal film in contact with the gate electrode of the base metal film is a titanium film,
A semiconductor device, wherein the titanium film has a thickness in a range of 100 nm to 200 nm. a first impurity layer of a first conductivity type formed on both sides of the trench gate;
further comprising a second impurity layer of a second conductivity type formed on the second surface of the semiconductor substrate,
The semiconductor device according to claim 1, wherein the back electrode is formed on the second impurity layer. 3. The semiconductor device according to claim 1, wherein a ratio of the thickness of the titanium film to the thickness of the back electrode is in a range of 13% to 26%. The semiconductor device according to any one of claims 1 to 3, wherein a ratio of the thickness of the titanium film to the thickness of the semiconductor substrate is in a range of 0.1% to 0.2%. The thickness of the semiconductor substrate is in the range of 100 μm to 300 μm,
The base metal film is formed including a Ti film, a TiN film, and a Ti film in order from the bottom layer, and the gate electrode is formed of an AlSiCu film,
The semiconductor device according to any one of claims 1 to 4, wherein the back electrode is formed of an Au film, a Ni film, a Ti film, and an AlSi film in order from the bottom layer.