JP7367635B2 - display - Google Patents

Description

The present invention relates to displays.

In recent years, the practical use of light source elements using organic semiconductor elements has progressed, and displays using organic semiconductor elements as light source elements have become commercially available. In the development of displays that use organic semiconductor elements as light source elements, studies are still being conducted to further improve performance, such as higher brightness, higher definition, lower power consumption, and longer lifespan. It is being said.

A pixel of a conventional display using an organic semiconductor element as a light emitting element is composed of an organic light emitting diode (also referred to as "OLED") and a transistor that controls the current flowing through the organic light emitting diode. An organic light emitting diode is a device that emits light in response to current input from a thin film transistor (also called "TFT") formed on a substrate to an organic EL layer sandwiched between an anode electrode and a cathode electrode. be.

However, for this configuration, the following Patent Document 1 discloses that as an element for reducing the number of control elements and increasing the light emitting area to increase brightness, the flowing current is reduced by controlling the voltage applied to the gate electrode. A vertical organic light-emitting transistor (also referred to as a "VOLET") is described, which is a transistor that adjusts the amount of light and emits light according to the amount of current flowing through the transistor itself. Further, Patent Document 2 listed below describes a display using a vertical organic light emitting transistor, and is expected to significantly increase the brightness of the display.

International Publication No. 2009/036071 Special table 2014-505324 publication Japanese Patent Application Publication No. 2018-197864

Furthermore, in recent years, displays have been used for a variety of purposes, not only for home televisions and personal computers, but also for advertisements in train stations, backgrounds at event venues, and so on. Therefore, in the development of displays, in addition to the above-mentioned performance improvement, increasing the size of the display is also a major issue.

In a display using an organic semiconductor element, organic light emitting diodes, thin film transistors, etc. forming pixels are arranged in a display section, and drivers for driving these are arranged at the outer edge of the display section. This configuration is still commonly used in many displays.

According to this configuration, as the display becomes larger, the transmission distance of the signals output from each driver arranged at the outer edge becomes longer in order to control and drive each element over the entire display section. In this case, the wiring connecting the driver and each element becomes long, and the resistance value of the wiring between the driver and the element becomes large. When the resistance value of the wiring increases, it becomes a factor that causes, for example, a voltage drop due to flowing current (also referred to as "IR-Drop") and signal delay and deterioration.

In particular, when the resistance value of the wiring increases, the current supply line for supplying current to the light emitting elements becomes smaller, even if the same voltage is applied to flow the current from the current supply section to each light emitting element. As the distance from the supply section increases, the voltage drops depending on the resistance value of the wiring and the flowing current. In this case, the amount of current actually supplied will decrease relative to the current value required for displaying image data. When this effect becomes noticeable, a display defect occurs to the extent that a person can visually recognize that the brightness is gradually decreasing. Furthermore, since the current supply line is often shared by a group of light emitting elements arranged in a row, variations in the resistance value of the wiring of the current supply line will cause a difference in brightness between each line. Line-shaped display defects occur.

As a method to solve the above problem, a method is applied to the current supply line, as described in Patent Document 3, in which the luminance of each pixel is detected and a voltage is supplied to the data line in consideration of the voltage drop. It is possible to do so. However, if a complicated circuit is added, the light emitting area will be significantly compressed and high brightness will be hindered. Furthermore, since the number of elements increases, there is a risk that failures and defects will occur more easily.

In addition, it is possible to use the outer edge where the driver is located and add external devices, but increasing the size of the outer edge and adding external devices is necessary because the display is required to be used for a variety of purposes. This will limit how it can be used and where it can be placed.

Furthermore, when applying a voltage value that assumes fluctuations through feedback control, etc., there may be an error in the calculation method, and there is a small possibility that changes in brightness will not be corrected so that they cannot be visually recognized as display defects. Zuar. Therefore, it is more desirable to take measures against display defects through the structure of the device than by correcting changes in brightness.

Here, the present inventor investigated a display using a vertical organic light emitting transistor, and found that the vertical organic light emitting transistor also has the following problem.

A vertical organic light emitting transistor has a structure including a source electrode, a gate electrode, and a drain electrode, similar to a field effect transistor. However, unlike field effect transistors such as thin film transistors, vertical organic light emitting transistors have a light emitting layer including an organic EL layer and an organic semiconductor layer between a source electrode and a drain electrode. . Due to the characteristics of these materials, compared to field effect transistors such as thin film transistors, vertical organic light emitting transistors have a lower current flow between the source electrode (anode electrode) and the drain electrode (cathode electrode) than are applied between the electrodes. It has the characteristic that it is easily affected by the voltage applied to it.

In other words, a display using a vertical organic light-emitting transistor has a characteristic that the brightness fluctuates more with respect to the voltage drop in the current supply line than the conventional structure of an organic light-emitting diode and a thin film transistor, and the above-mentioned display defects are more likely to occur. be.

SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a display using a vertical organic light-emitting transistor that suppresses voltage fluctuations in a current supply line.

The display of the present invention includes:
A substrate and
Arranged on the substrate in an array in a first direction and a second direction perpendicular to the first direction, from the substrate side in a third direction perpendicular to the first direction and the second direction. a plurality of vertical organic light emitting transistors formed in the order of a gate electrode, a source electrode, and a drain electrode, and having a light emitting layer between the source electrode and the drain electrode;
a data line that supplies voltage to the gate electrode of the vertical organic light emitting transistor;
a thin film transistor connected between the gate electrode of each of the vertical organic light emitting transistors and the data line, and controlling supply of voltage to the gate electrode of the vertical organic light emitting transistor;
a gate line connected to the gate electrode of the thin film transistor and transmitting a signal for switching between energization and cutoff of the thin film transistor;
Outside the formation region of the vertical organic light emitting transistor, and with respect to the third direction, the distance from the substrate is the same as the gate electrode of the vertical organic light emitting transistor, or is farther from the substrate than the gate electrode. and a plurality of current supply lines that are wired in the first direction in the area where the organic light emitting transistor is connected to the source electrode of the vertical organic light emitting transistor to supply current to the vertical organic light emitting transistor. .

In this specification, the term "formation region of a vertical organic light emitting transistor" refers to the formation of a light emitting layer from the source electrode when a voltage equal to or higher than a threshold is applied between the gate electrode and the source electrode of the vertical organic light emitting transistor. A region where current flows toward the drain electrode through which light is emitted.

The semiconductor manufacturing process is performed by laminating materials on a substrate in a predetermined order depending on the material and growth direction, etc., and generally consists of a wiring layer that connects each element and a layer that forms the element itself. are formed separately. For this reason, for example, if a wiring such as a current supply line is made on the same layer as the underlying metal wiring, the wiring width may be limited to prevent current leakage from other wiring on the same layer, or many wiring lines may be fabricated. The thickness of the wiring layer is limited in order to prevent leakage between wirings caused by foreign matter when intersecting with wiring through an insulating film, and to prevent disconnections caused by climbing over wiring steps.

Furthermore, in order to electrically connect the current supply line formed in the lower layer to the source electrode of the vertical organic light emitting transistor, it is necessary to form a contact hole that penetrates many layers of insulating films.

However, contact holes cannot be formed very large due to restrictions on wiring width, variation in characteristics, and formation accuracy, and it is difficult to reduce the resistance value to a level that hardly contributes to voltage drop. There are concerns about poor contact in the hole area.

Therefore, by adopting the above configuration, restrictions on the wiring width and wiring thickness of the current supply line are relaxed, making it possible to create wiring with lower resistance, and restrictions on contact holes are also eased. Therefore, a low resistance connection can be obtained. Further, depending on the layer structure, the current supply line and the source electrode of the vertical organic light emitting transistor can be directly connected without using a contact hole.

Therefore, the resistance value of the path from the driver that supplies current to the source electrode of the vertical organic light emitting transistor is reduced by the amount of the contact hole not being used. These effects suppress fluctuations in the voltage supplied to the source electrode of the vertical organic light emitting transistor, thereby suppressing the occurrence of display defects.

In addition, in a display using an organic light emitting element, one light emitting method is a method in which light is emitted through a substrate. In this case, in this configuration, it is preferable that there are as few wiring lines, thin film transistors, etc. as possible on the substrate side relative to the vertical organic light emitting transistor so that the light emitted from the light emitting layer is not blocked. The method of emitting light by passing through the substrate is also called the "bottom emission method," and has the advantage of easy wiring connections between electrodes and easy manufacturing. Further, a method of emitting light to the side opposite to the substrate is also referred to as a "top emission method", and the above configuration can also form a top emission method display.

With the above structure, no current supply line is formed on the substrate side of the vertical organic light emitting transistor, and a wider light emitting area is secured. Therefore, the display having the above configuration also has the effect of having higher brightness than the conventional display.

In the above display,
The light emitting layer of the vertical organic light emitting transistor is formed so as to straddle the plurality of vertical organic light emitting transistors,
A bank layer may be formed between the current supply line and the light emitting layer.

In addition, in the above display,
The bank layer may be formed between the source electrode and the light emitting layer in a region different from the gate electrode when viewed in the third direction.

The current supply line is a line that supplies current to the source electrode, and if the current supply line and the light emitting layer are energized, light may be emitted regardless of the voltage applied to the gate electrode.

Therefore, with the above structure, the light-emitting layer and the current supply line are not electrically connected, and unintended current including leakage current is suppressed, and unintended light emission is suppressed.

Note that a layer other than the bank layer may be included between the current supply line and the light emitting layer. For example, a configuration may be considered in which an electrode material made of carbon nanotubes is formed on a surface layer on which the source electrode is a base. In this case, a bank layer and a source electrode made of carbon nanotubes are formed between the current supply line and the light emitting layer.

The above display is
An organic resin layer may be provided between the current supply line and the gate electrode of the vertical organic light emitting transistor.

Furthermore, in the above display,
Regarding the third direction, the organic resin layer is arranged between the gate electrode of the vertical organic light emitting transistor and the source electrode of the vertical organic light emitting transistor, and between the peripheral edge of the gate electrode of the vertical organic light emitting transistor. It may be formed so as to overlap with the section.

In this specification, the "peripheral end" of each layer is the outermost region having a certain width from the edge when each layer is viewed from the third direction. The width of the peripheral edge portion overlapping with the organic resin layer is in the range of several tens of nanometers to several micrometers. More specifically, the width is preferably in the range of 200 nm to 5 μm, more preferably in the range of 500 nm to 2 μm, from the viewpoint of ensuring a light emitting region, the size of the thin film transistor, and reducing leakage current and parasitic capacitance.

If the current supply line is near a gate electrode or the like, there is a risk of generating leakage current. For example, when leakage current occurs to the gate electrode, the voltage of the gate electrode fluctuates so as to approach the source electrode voltage, which is the voltage of the current supply line.

Furthermore, even if the current supply line is formed in a layer separate from the gate electrode via an insulating film, if the gate electrode and the current supply line overlap, parasitic capacitance will occur, causing voltage fluctuations in either side. may affect one voltage, or a larger current may be required when charging the electrodes.

Then, in the vertical organic light emitting transistor, the voltage supplied from the data line to the gate electrode changes slightly so as to achieve a predetermined brightness, and the vertical organic light emitting transistor no longer emits light at the predetermined brightness.

Further, assuming that the direction in which the layers are stacked on the substrate is upward, the vertical organic light emitting transistor is formed above the thin film transistor, as described above. The layer formed above the thin film transistor has large irregularities and edges depending on the shape of the thin film transistor. If irregularities that extend between layers or edges that are severe enough to separate layers are formed, a leakage current path is formed and there is a risk of leakage current from the current supply line. be.

With the above structure, it is possible to suppress leakage current and parasitic capacitance generated in the layer formed on the substrate side of the current supply line.

Furthermore, when the current supply line is formed in a layered manner above the thin film transistor, the organic resin layer covers the unevenness and edges formed by the thin film transistor, and has the effect of leveling the surface. This allows another layer, including wiring, to be formed on a surface that is more planar than before, thereby suppressing variations in the quality of the wiring and improving yield.

Note that in order to further suppress leakage current and parasitic capacitance, the organic resin layer is formed of a material with a lower dielectric constant than the insulating film layer formed between the gate electrode and source electrode of the vertical organic light emitting transistor. It is preferable that Further, the organic resin layer does not need to be configured to be in contact with the current supply line and the gate electrode of the vertical organic light emitting transistor.

The organic resin layer in this specification is sometimes referred to as an "overcoat layer" because it is formed as an insulating film so as to cover part of the layer in order to reduce leakage current and parasitic capacitance.

The above display is
At least one auxiliary line may be provided that is wired in the second direction and connects at least two of the plurality of current supply lines.

Furthermore, in the above display,
The auxiliary line may be formed in the same layer as the current supply line.

With the above configuration, the current supply lines are wired in a grid pattern, so that the resistance value from the driver that supplies current to the source electrode of each vertical organic light emitting transistor is reduced. In addition, even if wiring deterioration or disconnection occurs in some current supply lines, the vertical organic light emitting transistor connected to the faulty current supply line can be connected to another current supply line via the auxiliary line. Current is supplied.

Furthermore, by forming the current supply line and the auxiliary line in the same layer, the current supply line and the auxiliary line are directly connected without using a contact hole. Thereby, the resistance value from the driver to the source electrode of the vertical organic light emitting transistor can be reduced.

The above display is
A bank layer may be provided between the current supply line and the light emitting layer.

With the above configuration, as in the case of the current supply line described above, there is no fear that the light emitting layer and the auxiliary line will be energized, and it is possible to suppress unintended light emission and unintended current generation including leakage current. can. Therefore, the leakage current generated from the auxiliary line is almost eliminated, and the influence on the amount of current flowing through the current supply line is also reduced. Therefore, voltage fluctuations in the current supply line are further suppressed.

In the above display,
The source electrode of the vertical organic light emitting transistor may be formed across at least two or more of the vertical organic light emitting transistors.

With the above configuration, the current supplied from the driver to each vertical organic light emitting transistor is not a current supply line wired with a predetermined width, but the source electrode functions as a current supply line, and the current is supplied from the driver to each vertical organic light emitting transistor. Current is supplied to each vertical organic light emitting transistor in a diffused manner. Therefore, the resistance value from the driver to the source electrode of each vertical organic light emitting transistor is greatly suppressed.

In addition, for example, in a region near the driver where many contact holes can be formed, by connecting it to the layer that forms the source electrode of the vertical organic light emitting transistor, it is possible to connect the current supply line and the source electrode of each vertical organic light emitting transistor. The resistance value generated in this way can be minimized.

Note that when the above configuration is adopted, from the viewpoint of reducing the resistance value from the driver to each vertical organic light emitting transistor, the material constituting the source electrode has a lower resistance than the material of the current supply line formed as a wiring. It is preferable that the material is made of a material such as, for example, carbon nanotubes.

According to the present invention, a display using vertical organic light emitting transistors in which voltage fluctuations in a current supply line are suppressed is realized.

1 is a schematic diagram of a portion of an embodiment of a display; FIG. 2 is a circuit diagram of a light emitting section in area A1 of the display in FIG. 1. FIG. FIG. 2 is a top view of a schematic element configuration of an embodiment of a light emitting section and its surroundings. It is a drawing with the current supply line 12 removed from FIG. 3A. FIG. 3A is a sectional view taken along the line AA' in FIG. 3A. FIG. 2 is a schematic drawing of the vicinity of one vertical organic light emitting transistor of a display in the middle of a manufacturing process when viewed from the +Z side. FIG. 2 is a schematic drawing of the vicinity of one vertical organic light emitting transistor of a display in the middle of a manufacturing process when viewed from the +Z side. FIG. 2 is a schematic drawing of the vicinity of one vertical organic light emitting transistor of a display in the middle of a manufacturing process when viewed from the +Z side. FIG. 2 is a schematic drawing of the vicinity of one vertical organic light emitting transistor of a display in the middle of a manufacturing process when viewed from the +Z side. FIG. 2 is a schematic drawing of the vicinity of one vertical organic light emitting transistor of a display in the middle of a manufacturing process when viewed from the +Z side. FIG. 2 is a schematic drawing of the vicinity of one vertical organic light emitting transistor of a display in the middle of a manufacturing process when viewed from the +Z side. FIG. 2 is a schematic drawing of the vicinity of one vertical organic light emitting transistor of a display in the middle of a manufacturing process when viewed from the +Z side. FIG. 2 is a schematic drawing of the vicinity of one vertical organic light emitting transistor of a display in the middle of a manufacturing process when viewed from the +Z side. FIG. 2 is a schematic drawing of the vicinity of one vertical organic light emitting transistor of a display in the middle of a manufacturing process when viewed from the +Z side. FIG. 2 is a top view of a schematic element configuration of an embodiment of a light emitting section and its surroundings. 7 is a sectional view taken along line BB' in FIG. 6. FIG. 7 is a sectional view taken along line BB' in FIG. 6. FIG. FIG. 7 is a cross-sectional view of a schematic element configuration of another embodiment of a light emitting portion and its surroundings, taken along the YZ plane.

Hereinafter, the configuration of the display of the present invention will be explained with reference to the drawings. It should be noted that the following drawings are all schematically illustrated, and the dimensional ratios and numbers on the drawings do not necessarily match the actual dimensional ratios and numbers.

[First embodiment]
FIG. 1 is a schematic diagram of a portion of an embodiment of a display 1. As shown in FIG. As shown in FIG. 1, the display 1 of the present embodiment includes a light emitting section 10 including vertical organic light emitting transistors 20 (described later) arranged in an array, a data line 11, a current supply line 12, and a gate. It includes a line 13 and an auxiliary line 14.

In addition, the display 1 includes a source driver 15a that supplies a voltage corresponding to image data to be displayed on the gate electrode of the vertical organic light-emitting transistor 20 to the data line 11 at the outer edge portion, and a source driver 15a that supplies current to the current supply line 12, It includes a current supply section 15b that supplies current to the source electrode of the vertical organic light emitting transistor 20, and a gate driver 15c that outputs a control signal for the thin film transistor 21 to the gate line 13.

FIG. 2 is a detailed circuit diagram of the light emitting section 10 in the area A1 of the display 1 in FIG. As shown in FIG. 2, the light emitting unit 10 includes a vertical organic light emitting transistor 20, a thin film transistor 21 that controls voltage supply to the gate electrode of the vertical organic light emitting transistor 20, and a source electrode of the vertical organic light emitting transistor 20. A capacitor 23 is provided between the gate electrodes. In the explanation of FIGS. 1 and 2, the direction in which the current supply line 12 is wired is the X direction (first direction), and the direction in which the auxiliary line 14 is wired is the Y direction (second direction). do.

The data line 11 supplies the voltage output from the source driver 15a to the gate of the vertical organic light emitting transistor 20 via the thin film transistor 21 in order to adjust the luminance of the vertical organic light emitting transistor 20 according to the image to be displayed. This is the wiring that applies voltage to the electrode. In this embodiment, the data lines 11 are formed in the X direction, but may be formed in the Y direction.

A plurality of current supply lines 12 are wired in the X direction outside the formation region of the vertical organic light emitting transistors 20 so as to be connected to each group of vertical organic light emitting transistors 20 arranged in the X direction. Each current supply line 12 supplies the current output from the current supply section 15b to the source electrode of each vertical organic light emitting transistor 20 included in the group of vertical organic light emitting transistors 20.

The gate line 13 is connected to the gate electrode of the thin film transistor 21, transmits a control signal output from the gate driver 15c toward the gate electrode of the thin film transistor 21, and switches the thin film transistor 21 on/off, thereby generating a vertical organic light emitting device. The energization between the gate electrode of the transistor 20 and the data line 11 is controlled. In this embodiment, the gate line 13 is formed in the Y direction, but may be formed in the X direction.

The auxiliary line 14 is wired in the Y direction between the light emitting units 10 arranged in the X direction, and connects the plurality of current supply lines 12. Note that the auxiliary line 14 does not have to be formed between all the light emitting parts 10 arranged in the X direction. In this embodiment, the current supply line 12 is formed in the X direction and the auxiliary line 14 is formed in the Y direction, but the current supply line 12 may be formed in the Y direction and the auxiliary line 14 may be formed in the X direction.

The capacitor 23 is arranged to maintain a displayed image for a predetermined period of time while the thin film transistor 21 is in an off state, and is used to maintain a voltage between the gate electrode and the source electrode of the vertical organic light emitting transistor 20. It is element.

Next, the structure of each element formed on the substrate will be explained. FIG. 3A is a top view of a schematic element configuration of an embodiment of the light emitting section 10 and its surroundings, and FIG. 3B is a diagram with the current supply line 12 removed from FIG. 3A. FIG. 4 is a cross-sectional view taken along line AA' in FIG. 3A. As shown in FIGS. 3B and 4, a pair of vertical organic light emitting transistors 20 and thin film transistors 21 are formed in a region divided by data lines 11 and gate lines 13.

Further, as described above, the vertical organic light emitting transistor 20 illustrated in FIGS. 3A and 3B is illustrated with a part of the region also called a formation region cut out, but the vertical organic light emitting transistor 20 of this embodiment As shown in FIG. 4, the drain electrode layer 20d, the light emitting layer (organic semiconductor layer 20a, organic EL layer 20c), the source electrode layer 20s, etc. are formed across the plurality of vertical organic light emitting transistors 20. .

The substrate 30 is transparent to light and emits the light emitted from the vertical organic light emitting transistor 20 to the outside. Specific materials will be described later.

In the following description, the direction in which the data line 11 and the current supply line 12 are wired is the X direction (first direction), the direction in which the gate line 13 is wired is the Y direction (second direction), and the direction perpendicular to these is the direction in which the data line 11 and the current supply line 12 are wired. This will be explained as the Z direction (third direction). When expressing directions, when distinguishing between positive and negative directions, they are written with positive and negative signs, such as "+Z direction" and "-Z direction," without distinguishing between positive and negative directions. When expressing a direction, it is simply written as "Z direction."

The configuration of the vertical organic light emitting transistor 20 includes, from the layer on the +Z side, a drain electrode layer 20d corresponding to a cathode electrode, an organic EL layer 20c and an organic semiconductor layer 20a forming a light emitting layer, and a conductive layer 31 containing carbon on the surface. A gate electrode layer 20g is formed via a source electrode layer 20s configured to apply a magnetic material (carbon nanotubes in this embodiment) and a gate insulating film layer 20h configured of a dielectric material on the −Z side. has been done.

In the vertical organic light emitting transistor 20 having the above configuration, when a voltage is applied to the gate electrode layer 20g, the Schottky barrier between the organic semiconductor layer 20a and the source electrode layer 20s changes, and when the Schottky barrier exceeds a predetermined threshold, the source Light is emitted when a current flows from the electrode layer 20s to the organic semiconductor layer 20a and the organic EL layer 20c.

A bank layer 24 is formed between the organic semiconductor layer 20a and the current supply line 12 to electrically insulate them. Although the X direction is not shown in FIG. 4, the source electrode layer 20s is applied to the XY plane on the +Z side of the current supply line 12 and is formed to be in direct contact with the current supply line 12. That is, the bank layer 24 is formed between the organic semiconductor layer 20a and the current supply line 12, and the organic semiconductor layer 20a and the current supply line 12 (source electrode layer 20s) are electrically insulated.

Further, an organic resin layer 32 is formed on the current supply line 12 on the substrate 30 side (-Z side) for electrically insulating them. Here, the organic resin layer 32 in this embodiment is made of a material having a lower dielectric constant than the material constituting the gate insulating film layer 20h in order to suppress leakage current generated from the current supply line 12. The gate insulating film layer 20h may be made of a material having a higher dielectric constant than the material forming the gate insulating film layer 20h. Specific materials constituting the organic resin layer 32 will be described later.

Furthermore, the organic resin layer 32 in this embodiment is arranged in the source electrode layer 20s so as to overlap the peripheral edge of the gate electrode layer 20g in order to suppress leakage current generated between the source electrode layer 20s and the gate electrode layer 20g. More preferably, the gate electrode layer 20g is formed between the gate electrode layer 20g and the gate electrode layer 20g.

In the display 1 of this embodiment, the substrate 30 is made of a material that is transparent to visible light, and the gate electrode layer 20g and the source electrode layer 20s are configured to have a gap through which visible light can pass. By doing so, the light emitted from the organic EL layer 20c passes through the substrate 30 and is emitted to the outside, thereby displaying an image.

In the thin film transistor 21, a source electrode layer 21s and a drain electrode layer 21d are connected via an oxide semiconductor layer 21a, and a gate electrode layer 21g is formed below the oxide semiconductor layer 21a via an insulating film layer or a dielectric layer. has been done. When a voltage is applied to the gate electrode layer 21g, a channel is formed in the oxide semiconductor layer 21a, and the source electrode layer 21s and the drain electrode layer 21d are energized.

The thin film transistor 21 has a source electrode layer 21s connected to the data line 11, and a drain electrode layer 21d connected to the gate electrode layer 20g of the vertical organic light emitting transistor 20.

As shown in FIG. 3B, the vertical organic light-emitting transistor 20 is formed to fill almost the entire area divided by the data line 11 and the gate line 13 in order to increase brightness. The thin film transistor 21 is formed as small as possible at the corner of the divided area so as to have a small influence on the light emitting area of the vertical organic light emitting transistor 20.

Although the capacitor 23 is not shown in FIG. 3A to FIG. 4, as shown in FIG. are placed so as to face each other via the Thereby, the vertical organic light emitting transistor 20 has the capacitor 23 as a parasitic element, and the capacitor 23 can also perform a voltage maintenance function. If such a parasitic element capacitor 23 does not have sufficient capacitance, another capacitor may be additionally formed.

Examples of materials used for each layer are listed below.

The gate line 13 and the auxiliary line 14 are made of aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W), niobium (Nb), magnesium (Mg), silver (Ag), copper (Cu), and the like. A combination of alloys, etc. can be used.

The substrate 30 may be made of a glass material, or a plastic material such as PET (Poly Ethylene Terephthalate), PEN (Poly Ethylene Naphthalate), or polyimide.

The drain electrode layer 20d of the vertical organic light emitting transistor 20 is made of single or multilayer graphene, carbon nanotubes, aluminum (Al), lithium fluoride (LiF), molybdenum oxide (Mo _x O _y ), indium tin oxide (ITO), An alloy made of combinations of zinc oxide (ZnO), magnesium (Mg), silver (Ag), gold (Au), and others may be used.

The gate electrode layer 20g of the vertical organic light emitting transistor 20 is made of zinc oxide (ZnO) doped with a metal such as aluminum (Al), tin (Sn), yttrium (Y), scandium (Sc), or gallium (Ga). Materials containing metal doped, undoped transparent conductive oxides such as indium oxide (In ₂ O ₃ ), tin dioxide (SnO ₂ ), cadmium oxide (CdO), and combinations thereof, or aluminum (Al), gold ( Au), silver (Ag), platinum (Pt), cadmium (Cd), nickel (Ni) and tantalum (Ta), and combinations thereof, as well as p- or n-doped silicon (Si) and gallium arsenide (GaAs). etc. may be adopted.

The gate insulating film layer 20h between the surface layer 31 and the gate electrode layer 20g of the vertical organic light emitting transistor 20 is made of silicon oxide (SiO _x ), aluminum oxide (Al ₂ O ₃ ), silicon nitride (Si ₃ N ₄ ), Adopts organic compounds such as yttrium oxide ( _{Y 2} O ₃ ), lead titanate ₍ PbTiO It is possible.

The organic semiconductor layer 20a of the vertical organic light emitting transistor 20 is made of a linear condensed polycyclic aromatic compound (or an acene compound) such as naphthalene, anthracene, rubrene, tetracene, pentacene, hexacene, and derivatives thereof, and, for example, copper phthalocyanine ( Pigments such as CuPc)-based compounds, azo compounds, perylene-based compounds, and derivatives thereof, and pigments such as hydrazone compounds, triphenylmethane-based compounds, diphenylmethane-based compounds, stilbene-based compounds, allylvinyl compounds, pyrazoline-based compounds, and triphenylamine. derivative (TPD), allylamine compound, low molecular weight amine derivative (a-NPD), 2,2',7,7'-tetrakis(diphenylamino)-9,9'-spirobifluorene (spiro-TAD), N, N'-di(1-naphthyl)-N,N'-diphenyl-4,4'-diamonobiphenyl (spiro-NPB), 4,4',4''-tris[N-3-methylphenyl-N- phenylamino]triphenylamine (mMTDATA), 2,2',7,7'-tetrakis(2,2-diphenylvinyl)-9,9-spirobifluorene (spiro-DPVBi), 4,4'-bis( 2,2-diphenylvinyl)biphenyl (DPVBi), (8-quinolinolato)aluminum (Alq), tris(8-quinolinolato)aluminum (Alq3), tris(4-methyl-8quinolinolato)aluminum (Almq3), and these Low molecular weight compounds such as derivatives, such as polythiophene, poly(p-phenylenevinylene) (PPV), biphenyl group-containing polymers, dialkoxy group-containing polymers, alkoxyphenyl PPV, phenyl PPV, phenyl/dialkoxy PPV copolymers, poly( 2-methoxy-5-(2'-ethylhexyloxy)-1,4-phenylene vinylene) (MEH-PPV), poly(ethylenedioxythiophene) (PEDOT), poly(styrene sulfonic acid) (PSS), poly( Aniline) (PAM), poly(N-vinylcarbazole), poly(vinylpyrene), poly(vinylanthracene), pyrene formaldehyde resins, ethylcarbazole formaldehyde halogenated resins, and modified versions thereof; 5,5_-diperfluorohexylcarbonyl-2,2_:5_,2_:5_,2_-quaterthiophene (DFHCO-4T), DFH-4T, DFCO-4T, P(NDI2OD-T2), PDI8-CN2, n-type transporting small organic molecules, oligomers, or polymers such as PDIF-CN2, F16CuPc, and fullerenes, naphthalenes, perylenes, and oligothiophene derivatives, as well as thieno[3,2-b]thiophene, dinaphthyl[2,3 -b:2',3'-f]thieno[3,2-b]thiophene (DNTT), 2-decyl-7-phenyl[1]benzothieno[3,2-b][1]benzothiophene (BTBT) Aromatic compounds having a thiophene ring such as the following may be employed.

Here, the vertical organic light emitting transistor 20 can be constructed by appropriately selecting an organic semiconductor having a matching energy level to form a hole injection layer, a hole transport layer, an organic EL layer, a hole transport layer, an organic EL layer, etc., which are standardly used in OLED displays. An electron transport layer, an electron injection layer, etc. can be suitably used. The color of the light emitted to the outside is adjusted by selecting the material constituting the above-mentioned organic EL layer 20c so that light of colors such as red, green, and blue is emitted. Further, the vertical organic light emitting transistor 20 may be configured to emit white light, or the same vertical organic light emitting transistor 20 may be configured to select and emit light of a desired color using a color filter. You can also.

The surface layer 31 is a layer formed on the gate insulating film layer 20h for the purpose of fixing the source electrode layer 20s (in particular, the CNT layer). As a material for forming the surface layer 31, it can be formed by applying a composition containing a binder resin formed from a silane coupling material, an acrylic resin, or the like.

The bank layer 24 is made of inorganic insulating materials such as silicon oxide (SiO), silicon nitride (Si ₃ N ₄ ), aluminum oxide (Al ₂ O ₃ ), and aluminum nitride (AlN), polyimide resin, siloxane resin, acrylic resin, Organic insulating materials such as novolak resin can be used.

The organic resin layer 32 may be made of an insulating photosensitive material such as an organic insulating material such as polyimide resin, siloxane resin, acrylic resin, or novolac resin.

The oxide semiconductor layer 21a included in the thin film transistor 21 is made of an In-Ga-Zn-O-based semiconductor, a Zn-O-based semiconductor (ZnO), an In-Zn-O-based semiconductor (IZO (registered trademark)), or Zn-Ti. -O based semiconductor (ZTO), Cd-Ge-O based semiconductor, Cd-Pb-O based semiconductor, CdO (cadmium oxide), Mg-Zn-O based semiconductor, In-Sn-Zn-O based semiconductor (e.g. In ₂ O ₃ --SnO ₂ --ZnO), In--Ga--Sn--O based semiconductors, etc. can be employed.

In this embodiment, the thin film transistor 21 is a thin film transistor made of an oxide semiconductor, but may be a thin film transistor made of amorphous silicon. Further, it may be either p-type or n-type. Further, as a specific configuration, any configuration such as a staggered type, an inverted staggered type, a coplanar type, an inverted coplanar type, etc. can be adopted.

Note that as the vertical organic light emitting transistor 20, the vertical organic light emitting transistor 20 described in the above-mentioned Patent Documents 1 and 2 can also be adopted, and furthermore, the structure of the above-mentioned Patent Document 3 can also be adopted. can.

Next, the manufacturing process of each layer will be briefly explained. 5A to 5X are schematic drawings of the vicinity of one vertical organic light emitting transistor 20 of the display 1 in the middle of the manufacturing process, when viewed from the +Z side. Each step will be explained below with reference to the drawings.

In addition, three vertical organic light-emitting transistors arranged in the Y direction are shown so that the positional relationship with adjacent vertical organic light-emitting transistors 20 and the structure between the vertical organic light-emitting transistors 20, that is, the structure outside the formation region, are shown. A description will be given with reference to a drawing in which an organic light emitting transistor 20 is formed.

Note that the same pattern does not need to be repeated outside the illustrated area. For example, as shown in FIG. 5D, the thin film transistor 21 is formed on the (+X, -Y) side, but in the entire display 1, on the -X side from the center in the X direction, the thin film transistor 21 is formed on the (-X, +Y) side. ) may be formed in any desired pattern.

As shown in FIG. 5A, first, the substrate 30 is prepared (step S1).

After step S1, as shown in FIG. 5B, the gate electrode layer 21g of the thin film transistor 21 and the gate line 13 connected to the gate electrode layer 21g are formed on the substrate 30 (step S2).

After step S2, an insulating film (not shown) is formed over the entire surface, and as shown in FIG. 5C, an oxide semiconductor layer 21a is formed on the +Z side of the gate electrode layer 21g of the thin film transistor 21 (step S3). .

Here, "formed over the entire area" means that it is formed over the entire image display area where the vertical organic light emitting transistor 20 is formed, and does not mean that it is formed over the entire outer edge where the driver is arranged. . This also applies to the following description.

After step S3, as shown in FIG. 5D, the drain electrode layer 21d and the data line 11 are formed on the oxide semiconductor layer 21a of the thin film transistor 21, spaced apart in the Y direction (step S4). The data line 11 constitutes a source electrode layer 21s of the thin film transistor 21 in a portion overlapping with the oxide semiconductor layer 21a in the Z direction.

After step S4, a passivation film (not shown) is formed over the entire surface, and then, as shown in FIG. 5E, a contact hole 21c connecting the drain electrode layer 21d of the thin film transistor 21 and the gate electrode layer 20g of the vertical organic light emitting transistor 20 is formed. is formed (step S5).

After step S5, as shown in FIG. 5F, a gate electrode layer 20g of the vertical organic light emitting transistor 20 is formed (step S6).

After step S6, as shown in FIG. 5G, an organic resin layer 32 is formed on the surface layer 31 outside the formation region of the vertical organic light emitting transistor 20 (step S7). Note that the region indicated by a broken line in FIG. 5G indicates the entire gate electrode layer 20g of the vertical organic light emitting transistor 20. That is, the organic resin layer 32 is formed so as to overlap the peripheral edge of the gate electrode layer 20g of the vertical organic light emitting transistor 20 in the Z direction. In this embodiment, the organic resin layer 32 is configured such that the width of the overlapping region is 2 μm from the outer edge of the gate electrode layer 20g, excluding the region where the thin film transistor 21 is formed.

After step S7, the gate insulating film layer 20h of the vertical organic light emitting transistor 20 is formed over the entire gate insulating film layer 20h, and the surface layer 31 is formed on the gate insulating film layer 20h (step S8). The gate insulating film layer 20h and the surface layer 31 are not shown in FIGS. 5G to 5I because they are formed over the entirety and the entire structure of the lower layer cannot be seen if shown.

After step S8, as shown in FIG. 5H, current supply lines 12 are formed on the organic resin layer 32 in the X direction, and auxiliary lines 14 are formed to connect each current supply line 12 in the Y direction ( Step S9). In this embodiment, since the current supply line 12 and the auxiliary line 14 are formed in different layers, a contact hole 14c is also formed to connect the layers. Note that the contact hole 14c may be formed at any location and in any suitable shape or number.

After step S9, a contact hole for connecting the source electrode is opened at a predetermined position of the current supply line 12 by photolithography (step S10).

After step S10, the source electrode layer 20s of the vertical organic light emitting transistor 20 made of carbon nanotubes is formed over the entirety (step S11). The source electrode layer 20s is not shown in FIG. 5I below because if it is shown, the entire structure of the underlying layer cannot be seen.

After step S11, as shown in FIG. 5I, bank layer 24 is formed (step S12).

After step S12, the organic semiconductor layer 20a serving as a light emitting layer, the organic EL layer 20c, and the drain electrode layer 20d are formed over the entire structure, forming the structure shown in FIGS. 3A to 4.

By making the display 1 with the above configuration through the above manufacturing process, the current supply line 12 is connected by the auxiliary line 14, and at the connection part with the auxiliary line 14, the other current supply line 12 connected The voltage value of the connection is shared. In other words, even if an extreme voltage drop occurs in one part due to variations in the resistance value of the current supply line 12, the voltage will be raised by the other current supply lines 12 connected to the auxiliary line 14. As in this embodiment, as the number of connection points between the current supply line 12 and the auxiliary line 14 increases, the voltage of the current supply line 12 becomes more uniform throughout the display 1.

In this way, the voltages of the current supply lines 12 connected by the auxiliary line 14 are equalized. Therefore, a display 1 with improved display quality in which local voltage drops are less likely to occur in each current supply line 12 and display defects are less likely to be visually recognized is realized.

In this embodiment, the drain electrode layer 20d, the organic semiconductor layer 20a, the organic EL layer 20c, and the source electrode layer 20s of the vertical organic light emitting transistor 20 are arranged so as to straddle the plurality of vertical organic light emitting transistors 20. However, they may be formed for each vertical organic light emitting transistor 20.

Moreover, in the case where each layer is formed for each vertical organic light emitting transistor 20 and leakage current from the current supply line 12 is not generated, the bank layer 24 and the organic resin layer 32 may not be formed.

[Second embodiment]
The configuration of the second embodiment of the display 1 of the present invention will be described focusing on the differences from the first embodiment.

FIG. 6 is a top view of a schematic element configuration of the light emitting section 10 and its surroundings in an embodiment different from the first embodiment. As shown in FIG. 6, the current supply line 12 and the auxiliary line 14 are not connected through the contact hole 14c, but may be integrally formed in the same layer and made of the same material. Further, the current supply line 12 and the auxiliary line 14 may be formed of the same layer and different materials, or may be formed of different layers and the same material.

FIG. 7 is a sectional view taken along line BB' in FIG. As shown in FIG. 7, the auxiliary line 14 may be configured to be sandwiched between the bank layer 24 and the organic resin layer 32.

With the above configuration, even in the auxiliary line 14 formed integrally with the current supply line 12, leakage current generated between the organic semiconductor layer 20a and the organic EL layer 20c can be suppressed.

Note that the bank layer 24 may be formed in a region between the source electrode layer 20s and the organic semiconductor layer 20a and different from the gate electrode layer 20g when viewed from the Z direction. Also in the second embodiment, when each layer such as the drain electrode layer 20d is formed for each vertical organic light emitting transistor 20 and almost no leakage current from the auxiliary line 14 occurs, the bank layer 24 and the organic resin layer 32 may not be formed.

8 is a sectional view taken along line BB' in FIG. 6, which is different from FIG. 7. As shown in FIG. 8, the organic resin layer 32 may be formed on the same plane as the gate electrode layer 20g. In the case of this configuration, a contact hole connecting the source electrode layer 20s of the vertical organic light emitting transistor 20 and the current supply line 12 is formed in the surface layer 31 and the gate insulating film layer 20h.

Furthermore, in the case of this configuration, if the distance between the gate electrode layer 20g of the vertical organic light emitting transistor 20 and the current supply line 12 is sufficiently far on the XY plane, the organic resin layer 32 will not be formed and the vertical The gate electrode layer 20g of the organic light emitting transistor 20 and the current supply line 12 may be formed on the same plane.

In the second embodiment, even when viewed in the cross section of the YZ plane as shown in FIG. 4, the bank layer 24, source electrode layer 20s, current supply line 12, organic resin layer 32, surface The positional relationship at which the layer 31 and the gate insulating film layer 20h are formed is the same. Note that the layers must be the same so that the organic resin layer 32 is formed on the -Z side of the auxiliary line 14 and the organic resin layer 32 is not formed on the -Z side of the current supply line 12. There isn't.

[Another embodiment]
Another embodiment will be described below.

<1> FIG. 9 is a cross-sectional view of a schematic element configuration of another embodiment of the light emitting section 10 and its surroundings, taken along the YZ plane. As shown in FIG. 9, the organic resin layer 32 is not formed in a part between the gate electrode layer 20g and the source electrode layer 20s, that is, it does not overlap with the peripheral edge of the gate electrode layer 20g. I don't mind if it is. Further, a structure may be adopted in which no organic resin layer 32 is formed between the gate electrode layer 20g and the source electrode layer 20s.

<2> The configurations, materials, and manufacturing steps included in the display 1 described above in each embodiment are merely examples, and the present invention is not limited to each configuration described above or each illustrated configuration.

1: Display 10: Light emitting section 11: Data line 12: Current supply line 13: Gate line 14: Auxiliary line 14c: Contact hole 15a: Source driver 15b: Current supply section 15c: Gate driver 20: Vertical organic light emitting transistor 20a: Organic semiconductor layer 20c: Organic EL layer 20d: Drain electrode layer 20g: Gate electrode layer 20h: Gate insulating film layer 20s: Source electrode layer 21: Thin film transistor 21a: Oxide semiconductor layer 21c: Contact hole 21d: Drain electrode layer 21g: Gate Electrode layer 21s: Source electrode layer 23: Capacitor 24: Bank layer 30: Substrate 31: Surface layer 32: Organic resin layer

Claims (8)

A substrate and
Arranged on the substrate in an array in a first direction and a second direction perpendicular to the first direction, from the substrate side in a third direction perpendicular to the first direction and the second direction. a plurality of vertical organic light emitting transistors formed in the order of a gate electrode, a source electrode, and a drain electrode, and having a light emitting layer between the source electrode and the drain electrode;
a data line that supplies voltage to the gate electrode of the vertical organic light emitting transistor;
a thin film transistor connected between the gate electrode of each of the vertical organic light emitting transistors and the data line, and controlling supply of voltage to the gate electrode of the vertical organic light emitting transistor;
a gate line connected to the gate electrode of the thin film transistor and transmitting a signal for switching between energization and cutoff of the thin film transistor;
Outside the formation region of the vertical organic light emitting transistor, and with respect to the third direction, the distance from the substrate is the same as the gate electrode of the vertical organic light emitting transistor, or is farther from the substrate than the gate electrode. a plurality of current supply lines that are wired in the first direction in the region and are in contact with the source electrode of the vertical organic light emitting transistor to supply current to the vertical organic light emitting transistor ;
A display characterized in that the source electrode of the vertical organic light emitting transistor is formed across at least two or more of the vertical organic light emitting transistors. The light emitting layer of the vertical organic light emitting transistor is formed so as to straddle the plurality of vertical organic light emitting transistors,
The display according to claim 1, further comprising a bank layer between the current supply line and the light emitting layer. 3. The bank layer is formed between the source electrode and the light emitting layer in a region different from the gate electrode when viewed in the third direction. Display as described. 4. The display according to claim 1, further comprising an organic resin layer between the current supply line and the gate electrode of the vertical organic light emitting transistor. The organic resin layer is arranged between the gate electrode of the vertical organic light emitting transistor and the source electrode of the vertical organic light emitting transistor, and the gate electrode of the vertical organic light emitting transistor when viewed from the third direction. 5. The display according to claim 4, wherein the display is formed so as to overlap the peripheral edge of the electrode. Any one of claims 1 to 5, further comprising at least one auxiliary line that is wired in the second direction and connects at least two of the plurality of current supply lines. Display as described in section. The display of claim 6, wherein the auxiliary line is formed in the same layer as the current supply line. 8. The display according to claim 6, further comprising a bank layer between the auxiliary line and the light emitting layer.