JP7361567B2 - electronic components - Google Patents

Description

The present invention relates to an electronic component including a plurality of resistive films.

Patent Document 1 discloses a resistance element as an example of an electronic component including a resistance film. The resistance element includes a substrate (chip), an oxide film, a plurality of resistance element parts (resistance films), an interlayer insulating film, and a plurality of connection wirings (metal films). The oxide film covers the main surface of the substrate. The plurality of resistive element portions are arranged at intervals on the oxide film. The interlayer insulating film covers the plurality of resistor elements. The plurality of connection wirings are respectively disposed on the interlayer insulating film, and overlap the plurality of resistance element portions in an irregular pattern when viewed from above.

JP2012-94642A

In conventional electronic components, where multiple metal films overlap multiple resistive films in an irregular pattern when viewed from above, the stress caused by the multiple metal films is applied unevenly to the multiple resistive films. . As a result, variations in resistance value due to the piezoresistive effect occur in the plurality of resistive films, and the accuracy of the resistance ratio between the plurality of resistive films decreases.
One embodiment of the present invention provides an electronic component that can improve the accuracy of the resistance ratio between a plurality of resistive films.

One embodiment of the present invention includes a chip having a main surface, an insulating layer formed on the main surface, and a plurality of resistive films disposed within the insulating layer and arranged at intervals in a plan view. and a plurality of metal films disposed above the plurality of resistive films in the insulating layer and arranged at intervals so as to overlap the plurality of resistive films in a one-to-one correspondence in a plan view. We provide electronic components, including .

According to this electronic component, stress caused by the plurality of metal films can be suppressed from being applied unevenly to the plurality of resistive films. This makes it possible to suppress variations in the amount of variation in resistance value caused by the piezoresistive effect in the plurality of resistive films, thereby improving the accuracy of the resistance ratio between the plurality of resistive films.

FIG. 1 is a plan view showing an electronic component according to an embodiment of the present invention. FIG. 2 is an enlarged view of region II shown in FIG. FIG. 3 is a sectional view taken along the line III-III shown in FIG. 2. FIG. 4 is a sectional view taken along the line IV-IV shown in FIG. FIG. 5 is a sectional view taken along the line V-V shown in FIG. 2. FIG. 6 is a sectional view taken along the line VI-VI shown in FIG. 2. FIG. 7 is a cross-sectional view taken along line VII-VII shown in FIG. FIG. 8 is a sectional view taken along the line VIII-VIII shown in FIG. 2. FIG. 9 is a sectional view taken along line IX-IX shown in FIG. 2. FIG. 10 is a plan view showing the arrangement of a plurality of resistive films shown in FIG. 2. FIG. FIG. 11 is a plan view showing the arrangement of the plurality of metal films shown in FIG. 2. FIG. FIG. 12 is a plan view showing the arrangement of the plurality of intermediate metal films shown in FIG. 2. FIG. FIG. 13 is a plan view showing the arrangement of a plurality of wiring films shown in FIG. 2. FIG.

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
FIG. 1 is a plan view showing an electronic component 1 according to an embodiment of the present invention. FIG. 2 is an enlarged view of region II shown in FIG. FIG. 3 is a sectional view taken along the line III-III shown in FIG. 2. FIG. 4 is a sectional view taken along the line IV-IV shown in FIG. FIG. 5 is a sectional view taken along the line VV shown in FIG. 2. FIG. 6 is a sectional view taken along the line VI-VI shown in FIG. 2. FIG. 7 is a cross-sectional view taken along line VII-VII shown in FIG. FIG. 8 is a sectional view taken along the line VIII-VIII shown in FIG. 2.

FIG. 9 is a sectional view taken along line IX-IX shown in FIG. 2. FIG. 10 is a plan view showing the arrangement of the plurality of resistive films 21 shown in FIG. 2. FIG. FIG. 11 is a plan view showing the arrangement of the plurality of metal films 41 shown in FIG. 2. FIG. 12 is a plan view showing the arrangement of the plurality of intermediate metal films 71 shown in FIG. 2. As shown in FIG. FIG. 13 is a plan view showing the arrangement of the plurality of wiring films 101 shown in FIG.
Referring to FIGS. 1 to 13, electronic component 1, in this embodiment, is a semiconductor device including semiconductor chip 2 (chip) made of silicon. The semiconductor chip 2 is formed into a rectangular parallelepiped shape. The semiconductor chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4.

The first main surface 3 and the second main surface 4 are formed into a rectangular shape when viewed in plan from the normal direction Z thereof. The side surface 5A and the side surface 5B extend along the first direction X, and are opposed to the second direction Y that is orthogonal to the first direction X. The side surface 5C and the side surface 5D extend along the second direction Y and face the first direction X.
The electronic component 1 includes one or more (in this embodiment, plural) device regions 6 and one or more (in this embodiment, one) resistance region 7 formed on the first main surface 3 side. The number and arrangement of device regions 6 and resistance regions 7 are arbitrary.

The device area 6 is an area where various functional devices are formed. The functional device is formed using the first main surface 3 and/or the surface layer portion of the first main surface 3. The functional device may include at least one of a semiconductor rectifying device and a semiconductor switching device. The functional device may include a network of combined semiconductor rectifying devices and semiconductor switching devices. The circuitry may form part or all of an integrated circuit.

The semiconductor rectifier device may include at least one of a pn junction diode, a pin junction diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The semiconductor switching device may include at least one of a BJT (Bipolar Junction Transistor), a MISFET (Metal Insulator Field Effect Transistor), an IGBT (Insulated Gate Bipolar Junction Transistor), and a JFET (Junction Field Effect Transistor). good.

The resistance region 7 is formed at intervals from the plurality of device regions 6. The resistance region 7 is a region in which a resistance circuit 8 is formed. The resistance circuit 8 is electrically connected to a power source and an arbitrary functional device, and provides the arbitrary functional device with a predetermined output voltage (output current) according to the resistance value. In this form, the resistance circuit 8 is not formed directly above the functional device. Of course, the resistance circuit 8 may be formed directly above the functional device in other forms.

Referring to FIGS. 2 to 9, electronic component 1 includes an insulating layer 10 formed on first main surface 3. Referring to FIGS. The insulating layer 10 has a laminated structure in which a plurality of insulating films are laminated. The number of layers of a plurality of insulating films is arbitrary. In this embodiment, the plurality of insulating films include a first insulating film 11 , a second insulating film 12 , a third insulating film 13 , a fourth insulating film 14 , and a fifth insulating film 15 .
The first insulating film 11 covers the first main surface 3. The first insulating film 11 may include at least one of a silicon oxide film (oxide film) and a silicon nitride film (nitride film). In this form, the first insulating film 11 is made of a silicon oxide film. The first insulating film 11 may include a field oxide film formed between the plurality of device regions 6. The field oxide film may be a LOCOS (local oxidation of silicon) film. The first insulating film 11 may be buried in a trench formed in the first main surface 3. The first insulating film 11 buried in the trench may form an STI (shallow trench isolation) structure.

The second to fifth insulating films 12 to 15 are each made of interlayer insulating films laminated in this order from the first insulating film 11 side. The second to fifth insulating films 12 to 15 each include at least one of a silicon oxide film and a silicon nitride film. The second to fifth insulating films 12 to 15 may each have a laminated structure in which a silicon oxide film and a silicon nitride film are laminated in any order. In this embodiment, the second to fifth insulating films 12 to 15 each have a single layer structure made of a silicon oxide film.

Referring to FIGS. 2 to 10, electronic component 1 includes a resistive film group 20 disposed within insulating layer 10 in resistive region 7. Referring to FIGS. The resistive film group 20 includes a plurality of (two or more) resistive films 21. Preferably, the resistive film group 20 includes three or more resistive films 21. In this embodiment, the resistive film group 20 includes 13 resistive films 21. The resistance film 21 forms a resistance portion of the resistance circuit 8.
In this embodiment, the plurality of resistive films 21 are arranged on the first insulating film 11 and covered with the second insulating film 12. The plurality of resistive films 21 each extend in a strip shape in the first direction X in a plan view, and are arranged in a stripe shape at intervals in the second direction Y. The plurality of resistive films 21 each have one end portion 22 on one side (side surface 5C side) and the other end portion 23 on the other side (side surface 5D side).

The plurality of resistive films 21 each have the same resistance value. Specifically, the plurality of resistive films 21 are arranged at equal intervals in the second direction Y at a first pitch P1, and each has an equal first length L1, an equal first width W1, and an equal first thickness T1. are doing. The first pitch P1 is the distance between the plurality of resistive films 21 along the second direction Y. The first length L1 is the length of the resistive film 21 along the first direction X. The first width W1 is the width of the resistive film 21 along the second direction Y. The first thickness T1 is the thickness along the normal direction Z of the resistive film 21.

The first pitch P1 is arbitrary and may be any value as long as the plurality of resistive films 21 are not electrically connected to each other. The first pitch P1 may be 1 μm or more and 10 μm or less. The first pitch P1 is preferably 1 μm or more and 5 μm or less. The first length L1 is arbitrary and adjusted according to the resistance value to be achieved in the plurality of resistive films 21. The first length L1 may be 5 μm or more and 100 μm or less. The first length L1 is preferably 10 μm or more and 50 μm or less.

The first width W1 is arbitrary and adjusted according to the resistance value to be achieved in the plurality of resistive films 21. The first width W1 is less than the first length L1. The first width W1 may be 1 μm or more and 25 μm or less. The first width W1 is preferably 1 μm or more and 10 μm or less. The first thickness T1 is arbitrary and adjusted according to the resistance value to be achieved in the plurality of resistive films 21. The first thickness T1 may be 0.1 μm or more and 2 μm or less. The first thickness T1 is preferably 0.1 μm or more and 1 μm or less.

Each of the plurality of resistive films 21 includes at least one of a Poly-Si film, a TaN film, a TiN film, a CrSi film, a CrSiN film, and a CrSiO film. In this embodiment, each of the plurality of resistive films 21 is made of a Poly-Si film. The conductivity type of the Poly-Si film may be p-type or n-type.
One or both (in this embodiment, both) of the plurality of resistance films 21 disposed on both sides are formed as dummy resistance films 24 in an electrically floating state. The dummy resistive film 24 suppresses differences in process environment between the resistive films 21 adjacent to the dummy resistive film 24 and the other resistive films 21 . In other words, the plurality of dummy resistive films 24 are arranged on both sides to suppress process errors of the plurality of resistive films 21 arranged between them. This suppresses a difference in resistance value between the plurality of resistive films 21.

Referring to FIGS. 2 to 10, electronic component 1 includes a plurality of first vias embedded in insulating layer 10 so as to be connected to a plurality of resistive films 21 in a one-to-one correspondence in resistive region 7. Includes an electrode pair 30. In FIG. 10 and the like, the first via electrode pair 30 is indicated by an x mark.
In this embodiment, the plurality of first via electrode pairs 30 are embedded in the second insulating film 12. The plurality of first via electrode pairs 30 each have a pair of first via electrodes 31 and a second via electrode 32 connected to the upper surface of the corresponding resistive film 21 at intervals in the first direction X. In this form, the first via electrode pairs 30 are connected to all the resistive films 21, but the first via electrode pairs 30 do not necessarily need to be connected to the dummy resistive films 24. However, the first via electrode pair 30 connected to the dummy resistive film 24 is effective in suppressing differences in process environments between the plurality of resistive films 21.

The first via electrode 31 is connected to the one end 22 side of the corresponding resistive film 21. The second via electrode 32 is connected to the other end 23 side of the corresponding resistive film 21 at an arbitrary distance in the first direction X from the first via electrode 31 . The plurality of first via electrode pairs 30 take out a resistance component between two points, the first via electrode 31 and the second via electrode 32, from the corresponding resistance film 21.
In this embodiment, the plurality of first via electrode pairs 30 are embedded in the insulating layer 10 such that the first via electrodes 31 are arranged in a line along the second direction Y. Thereby, the resistance component to be extracted from each of the plurality of resistive films 21 is determined by the distance from the first via electrode 31 to the second via electrode 32.

The via distance D between the first via electrode 31 and the second via electrode 32 is set to an arbitrary value for each of the plurality of resistive films 21 depending on the resistance component to be extracted. The plurality of first via electrode pairs 30 may include one or more via groups constituted by the plurality of first via electrode pairs 30 in which the via distances D are set to the same value.
FIG. 10 shows an example in which the via distance D includes a first distance D1, a second distance D2, and a third distance D3, and a plurality of first via electrode pairs 30 constitute three via groups. . The via distance D becomes shorter in the order of the first distance D1, the second distance D2, and the third distance D3. The plurality of first via electrode pairs 30 connect the first resistance component R1, the second resistance component R2, and the third resistance component R3 corresponding to the first distance D1, the second distance D2, and the third distance D3 to the resistive film 21. Take them out from each. The resistance ratio of the plurality of resistance films 21 is determined by the ratio of the first resistance component R1, the second resistance component R2, and the third resistance component R3.

The first via electrode 31 and the second via electrode 32 each have a laminated structure including a first main electrode 33 and a first barrier electrode 34. The first main electrode 33 is embedded in the insulating layer 10 (second insulating film 12) in a columnar shape. The first main electrode 33 may include at least one of a W film and a Cu film. The first barrier electrode 34 is interposed between the first main electrode 33 and the insulating layer 10 (second insulating film 12). The first barrier electrode 34 may include at least one of a Ti film and a TiN film.

Referring to FIGS. 2 to 9 and 11, electronic component 1 includes a metal film group 40 disposed above a plurality of resistance films 21 in insulating layer 10 of resistance region 7. The metal film group 40 includes a plurality of (two or more) metal films 41. The number of metal films 41 is equal to the number of resistive films 21 included in the resistive film group 20. In this form, the metal film group 40 includes thirteen metal films 41.
In this embodiment, the plurality of metal films 41 are arranged on the second insulating film 12 and covered with the third insulating film 13. The plurality of metal films 41 each extend in a strip shape in the first direction X when viewed from above, and are arranged in a stripe shape at intervals in the second direction Y. That is, the plurality of metal films 41 are arranged in the same pattern as the plurality of resistive films 21. The plurality of metal films 41 each have one end portion 42 on one side (side surface 5C side) and the other end portion 43 on the other side (side surface 5D side).

The plurality of metal films 41 overlap the plurality of resistive films 21 in a one-to-one correspondence in a plan view. In other words, the plurality of metal films 41 overlap the corresponding resistive film 21 with an interval from the resistive film 21 adjacent to the corresponding resistive film 21 in plan view. The plurality of metal films 41 overlap only one corresponding resistance film 21 in a plan view, and do not overlap the resistance films 21 adjacent to the one resistance film 21.

It is preferable that the plurality of metal films 41 face each other over the entire area of the corresponding resistance film 21. Further, it is preferable that the entire area of the plurality of metal films 41 faces the corresponding resistance film 21, respectively. It is more preferable that the plurality of metal films 41 overlap the plurality of resistive films 21 with equal opposing areas in plan view.
Specifically, the plurality of metal films 41 are arranged at equal intervals in the second direction Y at a second pitch P2, and each has an equal second length L2, an equal second width W2, and an equal second thickness T2. are doing. The second pitch P2 is the distance between the plurality of metal films 41 along the second direction Y. The second length L2 is the length of the metal film 41 along the first direction X. The second width W2 is the width of the metal film 41 along the second direction Y. The second thickness T2 is the thickness along the normal direction Z of the metal film 41.

The second pitch P2 is arbitrary and may be any value as long as the plurality of metal films 41 are not electrically connected to each other. The second pitch P2 may be 1 μm or more and 10 μm or less. The second pitch P2 is preferably 1 μm or more and 5 μm or less. The second pitch P2 is preferably approximately equal to the first pitch P1 of the plurality of resistive films 21. The second pitch P2 being substantially equal to the first pitch P1 means that the second pitch P2 has a value within a range of ±10% of the first pitch P1.

The second length L2 is adjusted according to the first length L1 of the plurality of resistive films 21. It is preferable that the second length L2 is approximately equal to the second length L2 of the plurality of resistive films 21. The second length L2 being substantially equal to the second length L2 means that the second length L2 has a value within a range of ±10% of the second length L2. The second length L2 may be 5 μm or more and 100 μm or less. The second length L2 is preferably 10 μm or more and 50 μm or less.

The second width W2 is less than the second length L2. The second width W2 is adjusted according to the first width W1 of the plurality of resistive films 21. The second width W2 is preferably approximately equal to the first width W1 of the plurality of resistive films 21. The second width W2 being substantially equal to the first width W1 means that the second width W2 has a value within a range of ±10% of the first width W1. The second width W2 may be 1 μm or more and 25 μm or less. The first width W1 is preferably 1 μm or more and 10 μm or less.

The second thickness T2 may be 0.1 μm or more and 2 μm or less. The second thickness T2 is preferably 0.1 μm or more and 1 μm or less. The second thickness T2 may exceed the first thickness T1 of the plurality of resistive films 21.
It is preferable that the plurality of metal films 41 have a planar area (=W2×L2) approximately equal to the planar area (=W1×L1) of the plurality of resistive films 21 in plan view. The plane area of the metal film 41 being approximately equal to the plane area of the resistive film 21 means that the plane area of the metal film 41 has a value within ±10% of the plane area of the resistive film 21. .

One or both (in this embodiment, both) of the metal films 41 disposed on both sides of the plurality of metal films 41 are formed as dummy metal films 44 in an electrically floating state. The plurality of dummy metal films 44 overlap the plurality of dummy resistive films 24 in plan view. The dummy metal film 44 suppresses differences in process environment between the metal film 41 adjacent to the dummy metal film 44 and other metal films 41 . In other words, the plurality of dummy metal films 44 are arranged on both sides to suppress process errors of the plurality of metal films 41 arranged between them. Thereby, the plurality of metal films 41 can be overlapped with the plurality of resistive films 21 with appropriate opposing areas.

Each of the plurality of metal films 41 has a first slit 50 (slit) formed in a region between one end 22 and the other end 23, and the first slit 50 separates a portion on the one end 22 side and the other end. It is separated into 23 side parts. Specifically, the plurality of first slits 50 are each formed in a portion of the corresponding metal film 41 that covers the region between the first via electrode 31 and the second via electrode 32. As a result, the plurality of metal films 41 are connected to the first metal wiring film 51 connected to the first via electrode 31 and the second metal wiring film 52 connected to the second via electrode 32 through the first slit 50. Each is separated.

The plurality of first slits 50 each extend in the second direction Y. That is, the first slits 50 each extend in a direction intersecting the direction in which the first via electrode 31 and the second via electrode 32 face each other. The plurality of first slits 50 further form one line slit 53 that is located on the same straight line and extends continuously in the second direction Y.
The line slit 53 passes through a region between the first via electrode 31 and the second via electrode 32, which are spaced apart from each other by a third distance D3. In other words, the line slit 53 is the first via electrode of the first via electrode pair 30 in which the distance between the first via electrode 31 and the second via electrode 32 is set to be the shortest among the plurality of first via electrode pairs 30. 31 and the second via electrode 32.

As a result, the plurality of metal films 41 are formed into a plurality of first metal wiring films 51 each having the same size and a plurality of second metal wiring films 52 each having the same size through the plurality of first slits 50. Each is separated. The size of the second metal wiring film 52 exceeds the size of the first metal wiring film 51.
The plurality of first slits 50 each have the same first slit width WS1 in the first direction X. The first slit width WS1 is arbitrary as long as it does not allow the first metal wiring film 51 and the second metal wiring film 52 to be electrically connected to each other. The first slit width WS1 is preferably less than the second width W2 of the metal film 41. The first slit width WS1 may be 0.1 μm or more and 5 μm or less. The first slit width WS1 is preferably 0.1 μm or more and 1 μm or less. The above-mentioned planar area of the metal film 41 is defined by the planar area of the metal film 41 including the first slit 50.

The plurality of metal films 41 each have a stacked structure including a first lower barrier electrode 45, a first intermediate electrode 46, and a first upper barrier electrode 47 stacked in this order from the resistive film 21 side (second insulating film 12 side). have. The first lower barrier electrode 45 is formed in a film shape on the second insulating film 12 . The first intermediate electrode 46 is formed in a film shape on the first lower barrier electrode 45 . The first intermediate electrode 46 is thicker than the first lower barrier electrode 45 . The first upper barrier electrode 47 is formed in a film shape on the first intermediate electrode 46 . The first upper barrier electrode 47 is thinner than the first intermediate electrode 46 .

The first lower barrier electrode 45 may include at least one of a Ti film and a TiN film. The first intermediate electrode 46 is at least one of a pure Cu film (a Cu film with a purity of 99% or more), a pure Al film (an Al film with a purity of 99% or more), an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film. It may contain one. The first upper barrier electrode 47 may include at least one of a Ti film and a TiN film.

The electronic component 1 includes a first insulating separation section 54 that is formed of a part of the insulating layer 10 and fills the plurality of first slits 50 . In this embodiment, the first insulating isolation portion 54 is made up of a part of the third insulating film 13 . That is, the first slit width WS1 of the first slit 50 is set to a value that allows a portion of the insulating layer 10 (the third insulating film 13) to be buried therein. The first insulating isolation portion 54 improves the electrical insulation of the plurality of first metal wiring films 51 and the plurality of second metal wiring films 52.

2 to 9 and FIG. 11, electronic component 1 includes a plurality of metal films 41 embedded in insulating layer 10 so as to be connected to a plurality of metal films 41 in a one-to-one correspondence in resistance region 7. A second via electrode pair 60 is included. In FIG. 11 and the like, the second via electrode pair 60 is indicated by an x mark.
In this embodiment, the plurality of second via electrode pairs 60 are embedded in the third insulating film 13 and connected to the plurality of metal films 41 other than the dummy metal film 44, respectively. That is, the dummy metal film 44 is insulated from the other metal films 41 by the third insulating film 13 and is formed in an electrically floating state. When the dummy resistive film 24 has the conditions to be in an electrically floating state, the second via electrode pair 60 may be connected to the plurality of dummy metal films 44.

The plurality of second via electrode pairs 60 each have a pair of third via electrodes 61 and a fourth via electrode 62 connected to the upper surface of the corresponding metal film 41 at intervals in the first direction X.
The third via electrode 61 is connected to an arbitrary position of the corresponding first metal wiring film 51. It is preferable that the third via electrode 61 is connected to a position overlapping the corresponding first via electrode 31 in the corresponding first metal wiring film 51 in a plan view. In this case, the third via electrode 61 faces the first via electrode 31 with the first metal wiring film 51 in between, and is electrically connected to the first via electrode 31 via the first metal wiring film 51. . In this form, the third via electrodes 61 are arranged in a line along the second direction Y.

The fourth via electrode 62 is connected to an arbitrary position of the second metal wiring film 52 corresponding to the third via electrode 61 at an arbitrary interval in the first direction X. It is preferable that the fourth via electrode 62 is connected to a position overlapping the corresponding second via electrode 32 in the corresponding second metal wiring film 52 in plan view. In this case, the fourth via electrode 62 faces the second via electrode 32 with the second metal wiring film 52 in between, and is electrically connected to the second via electrode 32 via the second metal wiring film 52. .

The third via electrode 61 and the fourth via electrode 62 each have a laminated structure including a second main electrode 63 and a second barrier electrode 64. The second main electrode 63 is buried in the insulating layer 10 (third insulating film 13) in a columnar shape. The second main electrode 63 may include at least one of a W film and a Cu film. The second barrier electrode 64 is interposed between the second main electrode 63 and the insulating layer 10 (third insulating film 13). The second barrier electrode 64 may include at least one of a Ti film and a TiN film.

Referring to FIGS. 2 to 9 and 12, electronic component 1 includes an intermediate metal film group 70 disposed above a plurality of metal films 41 in insulating layer 10 of resistance region 7. The intermediate metal film group 70 includes a plurality (two or more) of intermediate metal films 71. The number of intermediate metal films 71 is equal to the number of resistive films 21 included in resistive film group 20. In this embodiment, the intermediate metal film group 70 includes thirteen intermediate metal films 71.

In this embodiment, the plurality of intermediate metal films 71 are arranged on the third insulating film 13 and covered with the fourth insulating film 14. The plurality of intermediate metal films 71 each extend in a strip shape in the first direction X in a plan view, and are arranged in a stripe shape at intervals in the second direction Y. That is, the plurality of intermediate metal films 71 are arranged in the same pattern as the plurality of resistive films 21 (the plurality of metal films 41). The plurality of intermediate metal films 71 each have one end portion 72 on one side (side surface 5C side) and the other end portion 73 on the other side (side surface 5D side).

The plurality of intermediate metal films 71 overlap the plurality of metal films 41 in a one-to-one correspondence in a plan view. In other words, the plurality of intermediate metal films 71 overlap the corresponding metal films 41 at intervals from the metal films 41 adjacent to the corresponding metal films 41 in plan view. The plurality of intermediate metal films 71 overlap only one corresponding metal film 41 in plan view, and do not overlap the metal films 41 adjacent to the one metal film 41 .

It is preferable that the plurality of intermediate metal films 71 each face the entire area of the corresponding metal film 41 in plan view. Further, it is preferable that the entire area of the plurality of intermediate metal films 71 faces the corresponding metal film 41 in plan view. It is more preferable that the plurality of intermediate metal films 71 overlap the plurality of metal films 41 with equal opposing areas in plan view.
Specifically, the plurality of intermediate metal films 71 are arranged at equal intervals in the second direction Y at a third pitch P3, and have an equal third length L3, an equal third width W3, and an equal third thickness T3. have. The third pitch P3 is the distance between the plurality of intermediate metal films 71 along the second direction Y. The third length L3 is the length of the intermediate metal film 71 along the first direction X. The third width W3 is the width of the intermediate metal film 71 along the second direction Y. The third thickness T3 is the thickness along the normal direction Z of the intermediate metal film 71.

The third pitch P3 is arbitrary and may be any value as long as the plurality of intermediate metal films 71 are not electrically connected to each other. The third pitch P3 may be 1 μm or more and 10 μm or less. The third pitch P3 is preferably 1 μm or more and 5 μm or less. It is preferable that the third pitch P3 is approximately equal to the first pitch P1 of the plurality of resistive films 21. The third pitch P3 being substantially equal to the first pitch P1 means that the third pitch P3 has a value within a range of ±10% of the first pitch P1.

The third length L3 is arbitrary and adjusted according to the first length L1 of the plurality of resistive films 21. The third length L3 may be 5 μm or more and 100 μm or less. The third length L3 is preferably 10 μm or more and 50 μm or less. It is preferable that the third length L3 is approximately equal to the first length L1 of the plurality of resistive films 21. The third length L3 being substantially equal to the first length L1 means that the third length L3 has a value within ±10% of the first length L1.

The third width W3 is less than the third length L3. The third width W3 is arbitrary and adjusted according to the first width W1 of the plurality of resistive films 21. The third width W3 may be 1 μm or more and 25 μm or less. The third width W3 is preferably 1 μm or more and 10 μm or less. It is preferable that the third width W3 is approximately equal to the first width W1 of the plurality of resistive films 21. The third width W3 being substantially equal to the first width W1 means that the third width W3 has a value within a range of ±10% of the first width W1.

The third thickness T3 may be 0.1 μm or more and 2 μm or less. The third thickness T3 is preferably 0.1 μm or more and 1 μm or less. The third thickness T3 may exceed the first thickness T1 of the plurality of resistive films 21.
Preferably, the plurality of intermediate metal films 71 have a planar area (=W3×L3) approximately equal to the planar area (=W2×L2) of the plurality of metal films 41 in plan view. The plane area of the intermediate metal film 71 being approximately equal to the plane area of the metal film 41 means that the plane area of the intermediate metal film 71 has a value within the range of ±10% of the plane area of the metal film 41. means.

One or both (in this embodiment, both) of the plurality of intermediate metal films 71 disposed on both sides are formed as dummy intermediate metal films 74 in an electrically floating state. The plurality of dummy intermediate metal films 74 overlap the plurality of dummy metal films 44 in plan view. The dummy intermediate metal film 74 suppresses differences in process environment between the intermediate metal film 71 adjacent to the dummy intermediate metal film 74 and the other intermediate metal films 71. That is, by disposing the plurality of dummy intermediate metal films 74 on both sides, process errors of the plurality of intermediate metal films 71 disposed between them are suppressed. This allows the plurality of intermediate metal films 71 to overlap the plurality of metal films 41 with appropriate opposing areas.

Each of the plurality of intermediate metal films 71 has a second slit 80 formed in a region between one end 72 and the other end 73, and the second slit 80 separates a portion on the one end 72 side and a portion on the other end 73 side. It is separated into each part. Although FIG. 12 shows an example in which the intermediate metal film 71 other than the dummy intermediate metal film 74 includes the second slit 80, the dummy intermediate metal film 74 including the second slit 80 is formed at an arbitrary position. It's okay.

Specifically, the plurality of second slits 80 are each formed in a portion covering the region between the third via electrode 61 and the fourth via electrode 62 in the corresponding intermediate metal film 71. As a result, the plurality of intermediate metal films 71 are connected to the third metal wiring film 81 connected to the third via electrode 61 through the second slit 80 and the fourth metal wiring film 82 connected to the fourth via electrode 62. Each is separated.

Unlike the first slits 50, the plurality of second slits 80 do not necessarily need to be located on the same straight line. The plurality of second slits 80 each extend in the second direction Y at arbitrary positions between the corresponding third via electrode 61 and fourth via electrode 62 with respect to the first direction X. The arrangement of the plurality of second slits 80 is adjusted according to the arrangement of the plurality of third via electrode pairs 90 (the plurality of wiring films 101), which will be described later.

In this form, the second slits 80 of the plurality of intermediate metal films 71 arranged second to third and sixth to ninth from the left side of the paper are formed on the same straight line in a region on the one end 72 side of the intermediate metal film 71. has been done. Further, the second slits 80 of the plurality of intermediate metal films 71 arranged 10th to 12th from the left side in the drawing are formed on the same straight line in the region on the other end 73 side of the intermediate metal film 71. Further, the second slits 80 of the plurality of intermediate metal films 71 arranged fourth to fifth from the left side in the drawing are formed on the same straight line in the central region of the intermediate metal film 71.

The plurality of second slits 80 each have the same second slit width WS2 in the first direction X. The second slit width WS2 may be less than the third width W3 of the intermediate metal film 71. The second slit width WS2 is arbitrary and may be any value as long as the third metal wiring film 81 and the fourth metal wiring film 82 are not electrically connected to each other. The second slit width WS2 is preferably less than the third width W3 of the intermediate metal film 71. The second slit width WS2 may be 0.1 μm or more and 5 μm or less. The second slit width WS2 is preferably 0.1 μm or more and 1 μm or less. The above-mentioned planar area of the intermediate metal film 71 is defined by the planar area of the intermediate metal film 71 including the second slit 80.

The plurality of intermediate metal films 71 have a stacked structure including a second lower barrier electrode 75, a second intermediate electrode 76, and a second upper barrier electrode 77 stacked in this order from the metal film 41 side (third insulating film 13 side). have. The second lower barrier electrode 75 is formed in a film shape on the third insulating film 13 . The second intermediate electrode 76 is formed in a film shape on the second lower barrier electrode 75. The second intermediate electrode 76 is thicker than the second lower barrier electrode 75. The second upper barrier electrode 77 is formed in a film shape on the second intermediate electrode 76 . The second upper barrier electrode 77 is thinner than the second intermediate electrode 76.

The second lower barrier electrode 75 may include at least one of a Ti film and a TiN film. The second intermediate electrode 76 may include at least one of a pure Cu film, a pure Al film, an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film. The second upper barrier electrode 77 may include at least one of a Ti film and a TiN film.
The electronic component 1 includes a second insulating separation part 84 that is formed of a part of the insulating layer 10 and fills the second slit 80. In this embodiment, the second insulating isolation section 84 is made up of a part of the fourth insulating film 14 . That is, the second slit width WS2 of the second slit 80 is set to a value that allows a portion of the insulating layer 10 (fourth insulating film 14) to be buried therein. The second insulating isolation portion 84 increases electrical insulation between the plurality of third metal wiring films 81 and the plurality of fourth metal wiring films 82.

2 to 9 and FIG. 12, electronic component 1 includes a plurality of intermediate metal films 71 embedded in insulating layer 10 so as to be connected to a plurality of intermediate metal films 71 in a one-to-one correspondence in resistance region 7. A third via electrode pair 90 is included. In FIG. 12 and the like, the third via electrode pair 90 is indicated by an x mark.
In this embodiment, the plurality of third via electrode pairs 90 are embedded in the fourth insulating film 14 and connected to the intermediate metal film 71 other than the dummy intermediate metal film 74 . That is, the dummy intermediate metal film 74 is insulated from the other intermediate metal films 71 by the fourth insulating film 14 and is formed in an electrically floating state. If the dummy resistive film 24 has the conditions to be in an electrically floating state, the third via electrode pair 90 may be connected to the plurality of dummy intermediate metal films 74.

The plurality of third via electrode pairs 90 each have a pair of fifth via electrodes 91 and a sixth via electrode 92 connected to the upper surface of the corresponding intermediate metal film 71 at intervals in the first direction X. .
The plurality of fifth via electrodes 91 are each connected to an arbitrary position of the corresponding third metal wiring film 81. The plurality of sixth via electrodes 92 are respectively connected to arbitrary positions of the corresponding fourth metal wiring film 82. The arrangement of the plurality of fifth via electrodes 91 and the plurality of sixth via electrodes 92 is adjusted according to the arrangement of the plurality of wiring films 101, which will be described later.

The fifth via electrode 91 and the sixth via electrode 92 each have a laminated structure including a third main electrode 93 and a third barrier electrode 94. The third main electrode 93 is embedded in the insulating layer 10 (fourth insulating film 14) in a columnar shape. The third main electrode 93 may include at least one of a W film and a Cu film. The third barrier electrode 94 is interposed between the third main electrode 93 and the insulating layer 10 (fourth insulating film 14). The third barrier electrode 94 may include at least one of a Ti film and a TiN film.

Referring to FIGS. 2 to 9 and 13, electronic component 1 includes a wiring film group 100 disposed above a plurality of intermediate metal films 71 in insulating layer 10 of resistance region 7. The wiring film group 100 includes a plurality of (two or more) wiring films 101. The number of wiring films 101 is arbitrary, and is adjusted depending on the number of resistance components to be taken out (first to third resistance components R1 to R3 in this embodiment) and the connection form of the resistance components. In this embodiment, the wiring film group 100 includes five wiring films 101.

In this embodiment, the plurality of wiring films 101 are arranged on the fourth insulating film 14 and covered with the fifth insulating film 15. The plurality of wiring films 101 are electrically connected to a power source in a region outside the resistance region 7 and are routed to the resistance region 7 . The plurality of wiring films 101 are further routed from the resistance region 7 to any device region 6, and are electrically connected to any functional device via wiring (not shown).

The plurality of wiring films 101 each extend in a line shape in the second direction Y so as to intersect the plurality of resistive films 21 (the plurality of metal films 41 and the plurality of intermediate metal films 71) in a plan view, and extend in the first direction X. They are arranged in stripes at intervals. Any pair of wiring films 101 among the plurality of wiring films 101 is connected to the fifth via electrode 91 and the sixth via electrode 92 of any one or more third via electrode pairs 90 .

The plurality of wiring films 101 are a pair of wiring films 101 electrically connected to any one of the plurality of resistance films 21, and a pair of wiring films 101 that are separate from the above-mentioned arbitrary resistance film 21 among the plurality of resistance films 21. includes another pair of wiring films 101 electrically connected to the resistive film 21 of. The pair of wiring films 101 is formed by connecting the resistance components (first to third resistance components R1 to R3) of one or more arbitrary resistance films 21 in series or in parallel. Components R1 to R3) are taken out.

A pair of wiring films 101 placed first and second from the bottom of the page are electrically connected to third via electrode pairs 90 (resistance films 21) that are third, eighth, and ninth from the left side of the page. There is. A pair of wiring films 101 arranged first and third from the bottom in the paper are electrically connected to a third via electrode pair 90 (resistance film 21) second from the left in the paper. A pair of wiring films 101 placed first and fourth from the bottom of the paper are electrically connected to third via electrode pairs 90 (resistance films 21) that are sixth and seventh from the left side of the paper.

A pair of wiring films 101 arranged second and fifth from the bottom in the paper are electrically connected to third via electrode pairs 90 (resistance films 21) fourth and fifth from the left in the paper. A pair of wiring films 101 placed third and fifth from the bottom of the page are electrically connected to third via electrode pairs 90 (resistance films 21) that are 10th, 11th, and 12th from the left side of the page. There is.

The plurality of wiring films 101 are arranged at equal intervals in the second direction Y at a fourth pitch P4, and each has an equal fourth width W4 and an equal fourth thickness T4. The fourth pitch P4 is the distance along the first direction X between the plurality of wiring films 101. The fourth width W4 is the width of the wiring film 101 along the first direction X. The fourth thickness T4 is the thickness along the normal direction Z of the intermediate metal film 71.
The fourth pitch P4 is arbitrary, and may be any value as long as the plurality of wiring films 101 are not electrically connected to each other and are electrically connected to any third via electrode pair 90. The fourth pitch P4 may be 0.1 μm or more and 10 μm or less. The fourth width W4 is arbitrary. The fourth width W4 may be 0.1 μm or more and 5 μm or less. The fourth thickness T4 is arbitrary. The fourth thickness T4 may be 0.1 μm or more and 5 μm or less.

The plurality of wiring films 101 has a stacked structure including a third lower barrier electrode 105, a third intermediate electrode 106, and a third upper barrier electrode 107 stacked in this order from the metal film 41 side (fourth insulating film 14 side). are doing. The third lower barrier electrode 105 is formed in a film shape on the fourth insulating film 14 . The third intermediate electrode 106 is formed in a film shape on the third lower barrier electrode 105. The third intermediate electrode 106 is thicker than the third lower barrier electrode 105. The third upper barrier electrode 107 is formed in a film shape on the third intermediate electrode 106. The third upper barrier electrode 107 is thinner than the third intermediate electrode 106.

The third lower barrier electrode 105 may include at least one of a Ti film and a TiN film. The third intermediate electrode 106 may include at least one of a pure Cu film, a pure Al film, an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film. The third upper barrier electrode 107 may include at least one of a Ti film and a TiN film.
As described above, the electronic component 1 includes the semiconductor chip 2, the insulating layer 10, the plurality of resistive films 21, and the plurality of metal films 41. The insulating layer 10 is formed on the first main surface 3 of the semiconductor chip 2. The plurality of resistive films 21 are arranged within the insulating layer 10 and arranged at intervals in a plan view. The plurality of metal films 41 are arranged above the plurality of resistive films 21 in the insulating layer 10, and are arranged at intervals so as to overlap the plurality of resistive films 21 in a one-to-one correspondence.

According to this structure, stress caused by the plurality of metal films 41 can be suppressed from being applied unevenly to the plurality of resistive films 21. This makes it possible to suppress variations in the amount of variation in resistance values caused by the piezoresistive effect in the plurality of resistive films 21, thereby improving the accuracy of the resistance ratio between the plurality of resistive films 21.
Specifically, the plurality of resistive films 21 each extend in a strip shape in the first direction X in a plan view, and are arranged in a stripe shape at intervals in the second direction Y. Specifically, the plurality of metal films 41 each extend in a strip shape in the first direction They overlap due to correspondence. According to this structure, it is possible to appropriately suppress stress applied to the plurality of resistive films 21 from becoming uneven.

It is preferable that the plurality of metal films 41 overlap the plurality of resistive films 21 in a one-to-one correspondence with equal facing areas. According to this structure, it is possible to more appropriately suppress stress applied to the plurality of resistive films 21 from becoming uneven.
Further, the electronic component 1 includes a plurality of first via electrode pairs 30, and each of the plurality of metal films 41 has a first slit 50. The plurality of first via electrode pairs 30 each have a first via electrode 31 on one side and a second via electrode 32 on the other side, which are spaced apart in the first direction X and connected to the upper surface of the corresponding resistive film 21. and is buried within the insulating layer 10.

The plurality of first slits 50 are each formed in a portion of the corresponding metal film 41 that covers the region between the first via electrode 31 and the second via electrode 32. As a result, the plurality of metal films 41 are connected to the first metal wiring film 51 connected to the first via electrode 31 through the first slit 50 and the second metal wiring film 52 connected to the second via electrode 32, respectively. Separated. According to this structure, it is possible to suppress variations in stress, and at the same time, the resistance component between the first via electrode 31 and the second via electrode 32 can be appropriately taken out by the first metal wiring film 51 and the second metal wiring film 52. I can do it.

Furthermore, in the electronic component 1, a plurality of first via electrode pairs 30 are embedded in the insulating layer 10 such that the plurality of first via electrodes 31 are arranged in a line in the second direction Y. According to this structure, the resistance component to be extracted from each of the plurality of resistive films 21 can be easily set based on the distance from the first via electrode 31 to the second via electrode 32.
Moreover, in the electronic component 1, the plurality of first slits 50 are located on the same straight line and form one line slit 53 that continuously extends in the second direction Y. According to this structure, the plurality of metal films 41 are formed by the plurality of first slits 50 to form a plurality of first metal wiring films 51 each having the same size and a plurality of second metal wirings each having the same size. They are separated into membranes 52, respectively. Thereby, stress caused by the plurality of first metal wiring films 51 and the plurality of second metal wiring films 52 can be suppressed from being applied unevenly to the plurality of resistive films 21. Moreover, at the same time, variations in stress caused by the arrangement of the plurality of first slits 50 can be suppressed.

When the via distance D is different for each first via electrode pair 30, the line slit 53 is connected to the first via of the first via electrode pair 30 for which the via distance D is set to be the shortest among the plurality of first via electrode pairs 30. Preferably, it passes through a region between the electrode 31 and the second via electrode 32. In this case, even if the via distance D is different for each first via electrode pair 30, one line slit 53 connects the plurality of metal films 41 to the plurality of first metal wiring films 51 and the plurality of second metal wiring films. It can be separated into 52 parts.

Further, the electronic component 1 includes a plurality of intermediate metal films 71. The plurality of intermediate metal films 71 are arranged above the plurality of metal films 41 in the insulating layer 10 . The plurality of intermediate metal films 71 overlap the plurality of metal films 41 in a one-to-one correspondence. According to this structure, stress caused by the plurality of intermediate metal films 71 can be suppressed from being applied unevenly to the plurality of resistive films 21 via the plurality of metal films 41.

Specifically, the plurality of intermediate metal films 71 each extend in a strip shape in the first direction X in a plan view, and are arranged in a stripe shape at intervals in the second direction Y. They overlap in a 1-correspondence relationship. According to this structure, it is possible to appropriately suppress stress applied to the plurality of resistive films 21 via the plurality of metal films 41 from becoming uneven.
It is preferable that the plurality of intermediate metal films 71 overlap the plurality of metal films 41 in a one-to-one correspondence with equal facing areas. According to this structure, it is possible to more appropriately suppress stress applied to the plurality of resistive films 21 via the plurality of metal films 41 from becoming uneven.

Further, the electronic component 1 includes a resistance circuit 8 built three-dimensionally in the resistance region 7. Specifically, the resistance circuit 8 includes a plurality of three-dimensionally formed resistance films 21, a plurality of first via electrode pairs 30, and a plurality of metal films 41. According to this structure, the area of the resistance circuit 8 (resistance region 7) can be reduced and the area of the device region 6 can be expanded.
Further, in this embodiment, the resistance circuit 8 includes a plurality of second via electrode pairs 60 and a plurality of intermediate metal films 71 that are three-dimensionally formed on the plurality of metal films 41 . Further, the resistance circuit 8 includes a plurality of third via electrode pairs 90 and a plurality of wiring films 101 that are three-dimensionally formed on the plurality of intermediate metal films 71 . These structures are effective in reducing the area of the resistor circuit 8.

Embodiments of the invention may be implemented in other forms.
In the embodiment described above, an example was described in which a plurality of resistive films 21 were arranged on the first insulating film 11. However, the plurality of resistive films 21 do not necessarily need to be placed on the first insulating film 11, and may be placed on an insulating film other than the first insulating film 11. For example, when the insulating layer 10 includes a plurality of insulating films stacked in six or more layers, the plurality of resistive films 21 may be arranged on any insulating film stacked above the first layer. good.

In the embodiment described above, an example was described in which the plurality of intermediate metal films 71 overlapped with the plurality of metal films 41 in a one-to-one correspondence with equal facing areas. However, the stress applied to the plurality of resistive films 21 from the plurality of intermediate metal films 71 is smaller than the stress applied to the plurality of resistive films 21 from the plurality of metal films 41. Therefore, the plurality of intermediate metal films 71 do not necessarily need to overlap the plurality of metal films 41 in a one-to-one correspondence with equal opposing areas.

For example, the plurality of intermediate metal films 71 are formed by a plurality of second slits 80 each having an arbitrary second slit width WS2, and a third metal interconnection film 81 having an arbitrary size and a fourth metal interconnection film having an arbitrary size. 82, respectively. The third metal wiring film 81 may have a size that connects the corresponding third via electrode 61 and fifth via electrode 91 at the shortest distance, for example. Furthermore, the fourth metal wiring film 82 may have a size that connects the corresponding fourth via electrode 62 and sixth via electrode 92 at the shortest distance.

In the embodiment described above, an example was described in which the plurality of wiring films 101 were electrically connected to the plurality of resistive films 21 via the plurality of intermediate metal films 71 and the plurality of metal films 41. However, a structure in which the plurality of wiring films 101 are electrically connected to the plurality of resistive films 21 via the plurality of metal films 41 without providing the plurality of intermediate metal films 71 may be adopted. In this case, the plurality of wiring films 101 are electrically connected to the metal film 41 via the third via electrode 61 and the fourth via electrode 62. The connection form of the plurality of wiring films 101 to the plurality of resistance films 21 is adjusted by the arrangement of the fourth via electrode 62.

In the embodiment described above, an example in which the semiconductor chip 2 made of silicon was employed was described. However, a semiconductor chip 2 made of a semiconductor material other than silicon may also be used. Examples of semiconductor materials other than silicon include compound semiconductors and wide bandgap semiconductors that exceed the bandgap of silicon. Semiconductor materials other than silicon may be, for example, SiC, GaN, GaP, GaAs, Ga ₂ O ₃ , ZnO, diamond and sapphire. Of course, instead of the semiconductor chip 2, an insulator chip made of an inorganic insulator such as glass or ceramic may be used.

Although the embodiments of the present invention have been described in detail, these are only specific examples used to clarify the technical content of the present invention, and the present invention is to be construed as limited to these specific examples. Rather, the scope of the invention is limited by the appended claims.

1 Electronic components 2 Semiconductor chips (chips)
3 First principal surface (principal surface)
10 Insulating layer 21 Resistive film 24 Dummy resistive film 30 First via electrode pair 31 First via electrode 32 Second via electrode 41 Metal film 44 Dummy metal film 50 First slit (slit)
51 First metal wiring film 52 Second metal wiring film 53 Line slit 55 First insulation isolation part (insulation isolation part)
101 Wiring film

Claims (19)

a chip having a main surface;
an insulating layer formed on the main surface;
a plurality of resistive films disposed within the insulating layer and arranged at intervals in a plan view;
a plurality of via electrode pairs embedded in the insulating layer, each having a first via electrode on one side and a second via electrode on the other side connected to the upper surface of the corresponding resistive film;
a plurality of metal films disposed above the plurality of resistive films in the insulating layer and arranged at intervals so as to overlap the plurality of resistive films in a one-to-one correspondence in plan view; including,
Each of the plurality of metal films has a slit formed in a portion covering a region between the first via electrode and the second via electrode, and the first via electrode is connected to the first via electrode by the slit. An electronic component separated into a metal wiring film and a second metal wiring film connected to the second via electrode . The electronic component according to claim 1, wherein the plurality of slits are located on the same straight line and form one line slit that extends continuously in one direction. The distance between the first via electrode and the second via electrode is set to an arbitrary value for each of the plurality of resistive films,
The line slit is formed between the first via electrode and the second via electrode of the via electrode pair in which the distance between the first via electrode and the second via electrode is set to be the shortest among the plurality of via electrode pairs in a plan view. The electronic component according to claim 2, wherein the electronic component passes through a region between two via electrodes. The electronic component according to claim 1, wherein the width of the plurality of slits is less than the width of the plurality of metal films. The electronic component according to any one of claims 1 to 4, further comprising an insulating separation part that is made of a part of the insulating layer and fills the plurality of slits. 6. The electronic component according to claim 1, wherein the plurality of pairs of via electrodes are embedded in the insulating layer such that the plurality of first via electrodes are arranged in a line. Any one of claims 1 to 6, further comprising a plurality of wiring films disposed above the plurality of metal films in the insulating layer and each extending in a line shape intersecting the plurality of metal films in plan view. Electronic components listed in section. a chip having a main surface;
an insulating layer formed on the main surface;
a plurality of resistive films disposed within the insulating layer and arranged at intervals in a plan view;
a plurality of metal films disposed above the plurality of resistive films in the insulating layer and arranged at intervals so as to overlap the plurality of resistive films in a one-to-one correspondence in a plan view;
a plurality of wiring films disposed above the plurality of metal films in the insulating layer and each extending in a line shape intersecting the plurality of metal films in plan view;
The plurality of wiring films include a pair of wiring films electrically connected to any one of the plurality of resistance films, and a resistance film other than the one of the plurality of resistance films. An electronic component that includes another pair of wiring membranes that are electrically connected to one another. further comprising a plurality of via electrodes connected to the upper surfaces of the plurality of resistive films,
The electronic component according to claim 8, wherein each of the plurality of metal films is electrically connected to the corresponding via electrode. The plurality of resistive films each extend in a rectangular shape when viewed from above, and are arranged in stripes at intervals,
10. The electronic component according to claim 1, wherein the plurality of metal films each extend in a rectangular shape in a plan view and are arranged in stripes at intervals. The electronic component according to any one of claims 1 to 10 , wherein the plurality of metal films overlap the plurality of resistive films with equal opposing areas in a plan view. The plurality of resistive films are arranged at equal intervals,
The electronic component according to claim 1, wherein the plurality of metal films are arranged at equal intervals. The electronic component according to claim 1, wherein the plurality of resistive films each have an equal resistance value. The electronic component according to any one of claims 1 to 13, wherein the plurality of resistive films each have equal length, equal width, and equal thickness. The electronic component according to any one of claims 1 to 14, wherein the plurality of metal films each have an equal length and an equal width. The electronic component according to any one of claims 1 to 15, wherein the plurality of resistive films include at least one of a Poly-Si film, a TaN film, a TiN film, a CrSi film, a CrSiN film, and a CrSiO film. . The electronic component according to any one of claims 1 to 16, wherein the plurality of metal films include at least one of a pure Cu film, a pure Al film, an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film. . One or both of the plurality of resistive films disposed on both sides are formed as dummy resistive films in an electrically floating state,
The electronic device according to any one of claims 1 to 17, wherein one or both of the metal films disposed on both sides of the plurality of metal films overlap the dummy resistive film in plan view. parts. 19. The electronic component according to claim 18, wherein one or both of the metal films disposed on both sides of the plurality of metal films are formed as dummy metal films in an electrically floating state.

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