JP2011040497A - Electronic device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electronic device containing an resistor element having such structure as a resistance value is easily and precisely set. <P>SOLUTION: A resistive film (metal thin film 11) that regulates resistance value of a resistor element is arranged at one of conductive film arrangement layers between insulating layers in a laminate structure formed on a substrate such as semiconductor. The metal thin film 11 has two or more kinds of resistivities. The metal thin film 11 is preferred to be a metal thin film 11W of double resistive area type having a plurality of surface areas of different resistivity (high resistive surface area RH and low resistive surface areas RL1 and RL2). <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an electronic device in which a resistance element is arranged by a thin film or the like in one of conductive film arrangement layers between insulating layers in a laminated structure formed on a substrate.

As an electronic device in which an insulating layer is formed on a substrate and a thin film resistor element is formed thereon, there are electronic components having an insulating substrate. However, a typical example is a semiconductor device in which the substrate is a semiconductor. It has been.
Semiconductor devices can be broadly classified into discrete devices and IC devices.

  Among IC devices, especially in analog and mixed signal LSIs, resistor elements play an important role in controlling signal ratio, feedback, or gain, in addition to applications that apply bias and load to active elements. Yes. In such a field, high accuracy is particularly required for the resistance value of the resistance element.

  In the past, resistance elements formed in IC devices were mainly made of polysilicon formed before the wiring process. However, due to variations in the grain generation of the polysilicon film, thermal history, variations in processing, and the like, the completed resistance element has a low resistance value accuracy.

By the way, a manufacturing apparatus that performs polysilicon film formation and subsequent heat treatment may not satisfy the required accuracy of the resistance value depending on the position where the semiconductor wafer is disposed. In that case, for the purpose of improving the accuracy of the polysilicon thin film resistance element, a high precision thin film resistance element can be obtained by taking measures such as specifying only a specific region in the processing chamber of the manufacturing apparatus. Ingenuity is required.
In addition, in order to adjust the conditions for each process by providing a dummy pattern in the same wafer, the resistance value of the completed thin film resistor is monitored by measuring the dummy pattern, and the results are fed back to mass production one after another. Control may be performed using a simple management system.
In these measures, productivity and cost are all sacrificed, and high thin film resistors cannot be manufactured at low cost.

  In addition, since a polysilicon resistor is formed in a layer close to the substrate, the parasitic capacitance between the resistor element and the substrate is large, and especially in an LSI that requires high-speed operation, the operation is slow. There are disadvantages.

In recent years, as a resistance element that has solved these disadvantages, a technique of forming a resistance element with a metal thin film, particularly a metal nitride film, in a wiring layer is being adopted.
For example, by processing TaN or the like used as a diffusion barrier for copper wiring into a shape as a resistance element as it is and connecting it to the wiring, a resistance element with high accuracy and low parasitic capacitance can be formed.
The metal thin film resistor formed by this method is not exposed to a high temperature (up to 500 [° C.]) higher than the temperature at which an interlayer film or wiring is formed, and the resistance value can be substantially determined by the film forming conditions. it can.

  A metal nitride film such as TaN used for a diffusion barrier of copper wiring has a very low resistivity. However, the resistance elements required in analog and mixed signal LSIs are not limited to high resistances, and not all polysilicon resistors are replaced by metal thin film resistors, but rather are used in a rather limited manner. Currently.

  In view of such a current situation, a technique has been proposed in which two types of resistance films, a low sheet resistance film and a high sheet resistance film, are formed with a plurality of layers of metal thin films to cope with high resistance ( For example, see Patent Document 1).

JP-T-2001-511316

  However, in the technique described in Patent Document 1, it is necessary to form a plurality of resistance films, and to make different resistance elements such as single layer films and multilayer films in different places. Therefore, this known technique has a disadvantage that the number of processes is greatly increased. In addition, since it is not possible to make an efficient resistive film by diverting the barrier layer of the wiring, it is necessary to redesign the laminated structure for arranging the wiring and the resistive element between the insulating layers, which is low cost. This is an impediment to the production of highly accurate resistance elements.

  The present invention provides a low-cost electronic device having a resistance element having a structure in which a resistance value can be accurately and easily set, and a conductive film arrangement layer between insulating layers in a laminated structure formed on a substrate. And a method for manufacturing an electronic device including a method for forming the device.

  In an electronic device according to the present invention, a resistance film that defines a resistance value of a resistance element is arranged in one of conductive film arrangement layers between insulating layers in a laminated structure formed on a substrate, and the resistance film includes two or more types of resistance films. An electronic device with resistivity.

In the present invention, it is preferable that the resistance film is a multi-resistance region type metal thin film having a plurality of surface regions having different resistivity.
In the present invention, preferably, as the plurality of resistance films having different resistance values, a plurality of metal thin films of the multi-resistance region type are provided, and the plurality of metal thin films of the multi-resistance region type have a thickness, a length, and a width. The area ratios of the plurality of surface regions that all have the same shape and differ in resistivity are different. The multi-resistance region type metal thin film having such a shape is particularly useful as a plurality of trimming resistor films that determine the resistance value of the trimming resistor element.

  According to the above configuration, since one resistive film has a plurality of resistivities, for example, the resistance value can be changed by changing the ratio of regions having different resistivities within the resistive film. In other words, it is possible to form resistance films having various resistance values by controlling only one parameter, that is, the ratio of the regions having different resistivities.

  The regions having different resistivities can be, for example, the surface regions of the metal thin film, which facilitates the setting of the resistivity for each region even after the metal thin film is formed.

  In another electronic device according to the present invention, a plurality of resistance films defining a resistance value of a resistance element are arranged in one of conductive film arrangement layers between insulating layers in a laminated structure formed on a substrate. The film is a plurality of metal thin films having two or more types of resistivity. The plurality of metal thin films include two metal thin films having the same shape and different resistivity, and one of the two metal thin films is covered with a silicon nitride film and the other upper surface is a silicon oxide film. Covered.

  In an electronic device having such a configuration, it is possible to provide a difference in resistivity depending on whether the upper surface is covered with a silicon nitride film or a silicon oxide film. Setting is extremely easy.

An electronic device manufacturing method according to the present invention includes a step of forming a resistance film of a resistance element on an insulating film supported by a substrate, and the step of forming the resistance film includes the following steps.
(1) A step of forming a metal thin film on the insulating film.
(2) A step of covering a region including a portion to be the resistance film of the metal thin film with a mask layer.
(3) The step of opening the mask layer in at least a part of the portion to be the resistance film and oxidizing the region of the resistance film exposed from the opening to change the resistivity.
(4) A step of patterning the metal thin film into the shape of the resistance film.
As a processing procedure, the step (4) may be either after (1) or after (3).

An electronic device manufacturing method according to the present invention includes a step of forming a resistance film of a resistance element on an insulating film supported by a substrate, and the step of forming the resistance film includes the following steps.
(1) A step of forming a metal thin film on the insulating film.
(2) The oxidation is performed by performing a heat treatment in a state in which at least a part of a region of the metal thin film serving as the resistance film having different resistivity is coated with a silicon oxide film and the other region is covered with a silicon nitride film. Selectively changing resistivity in a region of a metal thin film coated with a silicon film.
(3) A step of patterning the metal thin film into the shape of the resistance film.
As a processing procedure, the step (3) may be either after (1) or after (2).

  ADVANTAGE OF THE INVENTION According to this invention, the electronic device which has a resistive element of a structure which can set a resistance value accurately and easily can be provided. Further, according to the present invention, there is provided an electronic device manufacturing method including a method for forming such a resistive element at a low cost in one of conductive film arrangement layers between insulating layers in a laminated structure formed on a substrate. be able to.

It is a fragmentary sectional view of the laminated structure of a semiconductor device for demonstrating the structure and manufacturing method of the resistive element concerning 1st Embodiment. It is a fragmentary sectional view of the laminated structure of a semiconductor device for demonstrating the structure and manufacturing method of the resistive element concerning 2nd Embodiment. It is the top view and sectional drawing of a high resistance process about the metal thin film of the resistive element in connection with 3rd Embodiment, and a completed top view. It is a graph of the sheet resistance change in connection with the first selective oxidation technique that can be employed in the third embodiment. It is a graph of the sheet resistance change in connection with the second selective oxidation technique that can be employed in the third embodiment. It is a top view of a plurality of resistance elements concerning a 4th embodiment. 6 is a plan view of a plurality of resistance elements according to Comparative Example 1. FIG. It is a top view of the trimming resistance element in connection with 5th Embodiment. 12 is a plan view of a trimming resistor element according to Comparative Examples 2 and 3. FIG. It is a graph which shows the relationship between the trimming resistance value in 5th Embodiment, and the number of resistors. 10 is a graph showing the relationship between a trimming resistance value and the number of resistors in Comparative Example 3.

Embodiments of the present invention will be described in the following order with reference to the drawings by taking a semiconductor device having a metal thin film resistor as an example.
1. 1st Embodiment: Embodiment which shows the 1st structural example in the case of making high resistance the whole metal thin film, and a 1st manufacturing method example (The example of the metal material and the modification 1 of an oxidation method are included).
2. Second Embodiment: An embodiment showing a second structure example and a second manufacturing method example when the resistance of the entire metal thin film is increased.
3. Third Embodiment: Third Structure Example and Third Manufacturing Method Example (First and Second Manufacturing Methods) Including a Preferential Oxidation Step Utilizing the Opening of the Mask Layer When Partially Increasing the Resistance of the Entire Metal Thin Film Embodiment which shows the 4th example of a manufacturing method selectively oxidized by the kind of film material.
4). Fourth Embodiment: An embodiment in which a plurality of metal thin films have the same shape.
5). Fifth Embodiment: Embodiment in which a plurality of metal thin films of the fourth embodiment are applied to a trimming resistor element.

<1. First Embodiment>
FIG. 1 shows a partial cross-sectional view of a laminated structure of a semiconductor device as an electronic device including a resistance element according to the first embodiment.

[Device structure]
First, a device structure is described with reference to FIG.
The semiconductor device 1 is, for example, an LSI or a discrete device. In the case of an LSI, the semiconductor device 1 is formed with an arrangement or connection relationship determined by design in order to form a circuit that requires an active element such as a transistor on a semiconductor substrate (not shown). Yes.
A multilayer wiring structure is formed by stacking multiple layers of insulating layers and conductive layers on a semiconductor substrate on which active elements are formed, and wiring and passive elements (resistors, capacitors, inductors, etc.) are formed in the multilayer wiring structure. ing.

FIG. 1G is a partial cross-sectional view centered on one of conductive film arrangement layers between insulating layers in a multilayer wiring structure.
This conductive film arrangement layer refers to a layer between the underlying insulating layer 10 and the next insulating layer (interlayer insulating film 13).
More specifically, on the insulating layer 10, a high-resistance metal thin film 11H having a relatively high resistivity and a low-resistance metal thin film 11L having a relatively low resistivity are formed at different locations. The planar shape of the high-resistance metal thin film 11H and the low-resistance metal thin film 11L is arbitrary, and an example thereof will be described later. In the embodiment of the present invention, the “same shape” refers to a shape having the same thickness (film thickness), length, and width. However, a slight film reduction due to oxidation is included in the category of “same shape”.

  The high-resistance metal thin film 11H and the low-resistance metal thin film 11L are covered with an interlayer insulating film 13, and in the low-resistance metal thin film 11L, a silicon nitride film or a silicon oxide film (between the interlayer insulating film 13 and the low-resistance metal film 11L). Here, a SiN film 12) is interposed. On the other hand, no silicon nitride film or silicon oxide film (here, SiN film 12) is interposed between the high-resistance metal thin film 11H and the interlayer insulating film 13. Whether this silicon nitride film or silicon oxide film (SiN film 12 in this case) is present or not is important, and this causes a difference in resistivity of the metal thin film resistor.

  Although details will be described later, the silicon nitride film or the silicon oxide film (here, the SiN film 12) functions as a mask layer in the oxidation process. Therefore, the high-resistance metal thin film 11H has a difference in resistivity with the low-resistance metal thin film 11L that is oxidized due to the base material being oxidized.

  A common base material for the high-resistance metal thin film 11H and the low-resistance metal thin film 11L is preferably a metal nitride film, for example. More preferably, the common base material is made of any one of metal oxides of ZrN, TaN, HfN, NbN, WN, and TiN.

  The first wiring 14_1 is connected to one end in the longitudinal direction of the high-resistance metal thin film 11H, and the second wiring 14_2 is connected to the other end. The first wiring 14_1 and the second wiring 14_2 are formed from an upper wiring layer wired on the interlayer insulating film 13, and the high-resistance metal thin film 11H or the low wiring is formed through a contact formed in the interlayer insulating film 13. It is in contact with a predetermined portion of the resistive metal thin film 11L.

[Production method]
A method for manufacturing the device structure shown in FIG.
First, in the step shown in FIG. 1A, a metal thin film 11 is formed on the insulating layer 10. Here, for example, an atomic layer deposition (ALD) method is used to form a zirconium nitride (ZrN) film having a sheet resistance of 250 [Ω / □] to a thickness of 100 [nm]. The metal thin film 11 may be other than a metal nitride film, but in the case of a metal nitride film, any one of TaN, HfN, NbN, WN, and TiN metal oxides may be used.

  In the next step shown in FIG. 1B, the element formation region of the metal thin film 11 is patterned using a photolithography technique. At this time, for example, the metal thin film 11 is processed into the shape of a resistance element using reactive ion etching (RIE).

  In the next step of FIG. 1C, a resist R1 for lift-off is applied, and after pre-baking, the resist R1 is applied only to an oxidized region that is slightly larger than the region where the high-resistance metal thin film 11H is formed by mask exposure and development. Leave. This resist R1 has a reverse pattern of the mask layer pattern of selective oxidation. In the lift-off method, it is desirable that the edge shape of the resist R1 is a reverse taper type. In order to effectively form an inversely tapered shape, it is preferable to use a negative resist or a multilayer resist whose surface layer has solvent resistance by light irradiation.

After the post-baking, in the next step of FIG. 1D, an SiN film 12 is formed as a selective oxidation mask layer. Here, the SiN film 12 is formed to a thickness of about 100 [nm] by using plasma chemical vapor deposition (CVD).
When lift-off is performed in this state, a low-resistance metal thin film 11L masked by the plasma SiN film 12 and a high-resistance metal thin film 11H not masked (opened) are formed (FIG. 1E). In the lift-off method, when immersed in a resist solvent such as acetone, the SiN film 12 on the resist R1 is peeled off and the SiN film 12 is patterned when the resist R1 is dissolved.

  In the step of FIG. 1E, oxygen plasma is applied to the low resistance metal thin film 11L covered with the SiN film and the high resistance metal thin film 11H not covered with the SiN film, for example, at 400 [° C.], 30 Irradiate under conditions of seconds. The method of oxidation is not limited to oxygen plasma as will be described later. However, in any method, the metal nitride of the high-resistance metal thin film 11H is uniformly oxidized and reformed in the film thickness (depth) direction from the surface, and the resistivity of the high-resistance metal thin film 11H is reduced to the low-resistance metal thin film. Increased from 11L resistivity. This causes a difference in resistivity between the two. Here, “uniformly oxidized in the film thickness (depth) direction” means “all the film thickness direction is oxidized almost uniformly”, and the degree of oxidation is in the film thickness direction. It is not required to be completely uniform. That is, non-uniformity that allows a slight oxygen concentration gradient in the film thickness direction is allowed.

After the oxidation treatment in FIG. 1E, the high-resistance metal thin film 11H is in a state of only the high-resistance surface region RH. This is represented by reference numeral “11H (RH)” in FIGS.
In the next step of FIG. 1F, a plasma silicon oxide film (plasma SiO ₂ film) is formed as the interlayer insulating film 13 using a high-density plasma apparatus.

Subsequently, in the step of FIG. 1G, a wiring contact portion is formed in the interlayer insulating film 13, and the resistance element formed by the metal wiring is connected to another element. Specifically, the metal wiring layer is formed by a metal film forming apparatus, and the metal wiring layer is patterned by a photolithography technique. At this time, contact is made between the high resistance metal thin film 11H and the low resistance metal thin film 11L and the first wiring 14_1 and the second wiring 14_2. The high resistance metal thin film 11H and the low resistance metal thin film 11L are appropriately connected to other elements.
Through the above steps, the resistance element structure of FIG.

  The high resistance metal thin film 11H formed in this way can obtain a sheet resistance value of, for example, about 1500 [Ω / □]. On the other hand, the low-resistance metal thin film 11L has a sheet resistance value of, for example, about 250 [Ω / □] immediately after film formation (as Depo.). In the case of a thin film, the sheet resistance value substantially represents the resistivity, but instead of the sheet resistance value, for example, a cross-sectional resistance value may be used as a parameter representing the resistivity.

[Modification 1]
Here, an example in which oxygen plasma is used for the oxidation of the high resistance metal thin film 11H in the present embodiment is shown. This is because the most commonly used plasma CVD apparatus can be used, and this apparatus can be introduced relatively easily. Furthermore, if the sheet resistance value is controlled with high accuracy, it is possible to oxidize using a device such as rapid thermal annealing. Alternatively, annealing using O ₃ (ozone) or H ₂ O as an oxidizing agent is also effective. In this case, an ALD apparatus or a TEOS (Tetraethoxysilane) -O ₃ CVD apparatus can also be used.
However, in any case, it is desirable that the process is performed at a temperature range of 500 [° C.] or lower, for example, in a temperature range that does not affect other wiring processes and materials.

  In the first embodiment and the first modification described above, the entire area of a plurality of (two in this example) different metal thin films is defined as a single resistivity, and the difference in resistivity between the metal thin films is simplified by a method. Proposed method to have. Hereinafter, such a resistance film is referred to as a “single resistance type metal thin film”. In the following description, the term “entire region” refers to the entire effective resistance region of the metal thin film sandwiched between the inner edges of two contacts that are in contact with both ends of the metal thin film.

<2. Second Embodiment>
In the second embodiment, another method for forming a single resistance type metal thin film is illustrated.

  In the first embodiment, a high resistance region can be formed relatively easily by using a lift-off process, but this method has a disadvantage that miniaturization is not good. Therefore, a second embodiment including an example applicable to the advanced silicon process will be described below. In the following description, the same components as those in the first embodiment are denoted by the same reference numerals, and the description of the structure is omitted or simplified. In addition, steps that are not particularly mentioned in the manufacturing method are the same as those in the first embodiment.

  FIG. 2 shows a partial cross-sectional view of a stacked structure of a semiconductor device as an electronic device including the resistance element according to the first embodiment.

[Device structure]
First, a device structure will be described with reference to FIG. FIG. 2H is a partial cross-sectional view mainly showing one of conductive film arrangement layers between insulating layers in a multilayer wiring structure.
On the underlying insulating layer 10, a high-resistance metal thin film 11H having a relatively high resistivity and a low-resistance metal thin film 11L having a relatively low resistivity are formed at different locations. The high-resistance metal thin film 11H and the low-resistance metal thin film 11L are common to the first embodiment in that the effective resistance region between the contact inner edges is a single resistance type having a single conductivity.

  However, in the high resistance metal thin film 11H of the second embodiment, the entire effective resistance region is modified by increasing the resistance. This region is referred to as a “high resistance surface region RH”. The “surface region” means that the range of the region is defined in a top view, and the surface region also has a thickness. The thickness (depth from the upper surface) of the high resistance surface region RH is usually the same as the thickness of the high resistance metal thin film 11H.

Another structural difference between the first and second embodiments is that an SiO ₂ film (ALD-SiO ₂ film 15) is formed on the upper surfaces of the high-resistance metal thin film 11H and the low-resistance metal thin film 11L by the ALD method. It has been done. The ALD-SiO ₂ film 15 is formed on the upper surface of the high-resistance metal thin film 11H and the low-resistance metal thin film 11L on the region excluding the contact contact surface and the high-resistance surface region RH. The upper surface of the ALD-SiO ₂ film 15 and the side surface of the stacked body of the metal thin films (11H, 11L) and the SiN film 12 are covered with the SiN film 12.

The ALD-SiO ₂ film 15 functions as an etching stopper and / or a protective layer (mask layer) that is necessary when the SiN film 12 alone is insufficient to prevent moisture and the like from entering. Therefore, when the controllability of etching of the SiN film 12 is high, the ALD-SiO ₂ film 15 is not necessary when the protection is sufficient only by the SiN film 12.
If the protection is sufficient with only the ALD-SiO ₂ film 15, the SiN film 12 can be omitted by covering the side surfaces of the metal thin films (11 H, 11 L).

Other configurations are the same as those in FIG. 1G showing the first embodiment, including the material selection of the base material of the metal thin film.
In the second embodiment, the high resistance surface region RH is formed by modifying the base material in the entire effective resistance region of the high resistance metal thin film 11H, and the presence thereof provides a difference in resistivity from the low resistance metal thin film 11L. It has been.

[Production method]
A method for manufacturing the device structure shown in FIG. 2H will be described with reference to FIGS.
First, in the step shown in FIG. 2A, the metal thin film 11 is formed on the insulating layer 10 as in the first embodiment (FIG. 1A). Here, for example, an atomic layer deposition (ALD) method is used to form a zirconium nitride (ZrN) film having a sheet resistance of 250 [Ω / □] to a thickness of 100 [nm]. The metal thin film 11 may be other than a metal nitride film, but in the case of a metal nitride film, any one of TaN, HfN, NbN, WN, and TiN metal oxides may be used.

In the next step shown in FIG. 2 (B), a SiO ₂ thin film, here a 15 [nm] SiO ₂ film, is formed by ALD method continuously from FIG. 2 (A). As a result, an ALD-SiO ₂ film 15 is formed on the metal thin film 11. The ALD-SiO ₂ film 15 may be formed by a so-called “In-situ” film that is continuously formed using a film forming apparatus for the metal thin film 11 or by another film forming apparatus. It may be “ex-situ”. This oxidation method may not be the ALD method, but a film formation method in which a film containing no impurities can be formed as much as possible by stoichiometry, and oxidation does not proceed into the resistance film (metal thin film 11) during film formation. Is preferably selected. The purpose of providing the ALD-SiO ₂ film 15 is an etching stopper and / or protection in a subsequent high resistance process.

In the next step shown in FIG. 2C, the element formation regions of the ALD-SiO ₂ film 15 and the metal thin film 11 are patterned using a photolithography technique. At this time, a patterned resist R2 is formed, and using this as a mask, the ALD-SiO ₂ film 15 and the metal thin film 11 are processed into the shape of a resistive element using, for example, reactive ion etching (RIE).

  After removing the resist R2, in the next step of FIG. 2D, the SiN film 12 is formed over the entire region. Here, 100 [nm] of silicon nitride is formed using plasma CVD.

In the next step of FIG. 2E, a mask layer (not shown) such as a resist is formed by photolithography. The formed mask layer has a pattern that opens at least an effective resistance region (region excluding contact portions at both ends) of the metal thin film 11. With the mask layer having this opening formed, the SiN film 12 is etched by a plasma etching apparatus using an etching mixed gas (CF ₄ , O _2, etc.) containing a fluorine-based gas. The SiN film 12 is removed in the opening of the mask layer such as a resist. At that time, the ALD-SiO ₂ film 15 previously formed serves as an etching stopper.

Subsequently, the ALD-SiO ₂ film 15 remaining in the opening of the mask layer is removed by a reactive ion etching (RIE) apparatus using an etching mixed gas containing a fluorine-based gas (CF ₄ , CHF ₃ , Ar, etc.). . At this time, it is preferable to perform the etching under conditions that can ensure a sufficient selection ratio with the metal thin film 11.
Incidentally, or if the resistance value does not seek accuracy, if the etching selection ratio of the SiN film 12 and the ALD-SiO ₂ film 15 can be sufficiently secured, it is possible to omit the ALD-SiO ₂ film 15.

After removing the mask layer such as a resist (not shown), in the next step of FIG. 2F, an oxidation treatment is performed by oxygen plasma and other methods shown in Modification 1 as in the first embodiment. In this process, there may be etching residues, damage, or other factors that inhibit oxidation on the surface of the metal thin film 11 exposed from the openings of the SiN film 12 and the ALD-SiO ₂ film 15 by etching in the previous step. is there. In that case, it is desirable to normalize the exposed surface state by cleaning with chemicals, low-temperature oxygen plasma treatment (ashing), mild sputtering with Ar or the like, and then performing oxidation treatment.
By the oxidation treatment, the entire effective resistance region of the high-resistance metal thin film 11H is modified to the high-resistance surface region RH, and the resistivity of the high-resistance metal thin film 11H becomes higher than the resistivity of the low-resistance metal thin film 11L.

  Thereafter, in the steps of FIGS. 2G and 2H, when the interlayer insulating film 13 and the first wiring 14_1 and the second wiring 14_2 are formed as in the first embodiment, FIG. The resistance element structure shown in (H) is completed. At this time, the resistance value of the high-resistance metal thin film 11H is several times to tens of times the resistance value of the low-resistance metal thin film 11L (in the combination of oxidation treatment with ZrN and oxygen plasma, about 6 times as in the first embodiment). )It has become.

<3. Third Embodiment>
In the first and second embodiments (FIGS. 1 and 2), an example in which the entire resistance element or almost the entire effective resistance area of the resistance element is increased is shown.
On the other hand, the third embodiment shows an example of a resistance element that increases the resistance by an arbitrary area ratio within the effective resistance region.

  The method used for forming the mask layer in the third embodiment may be the lift-off method shown in the first embodiment, but the opening of the mask layer by etching shown in the second embodiment is more desirable. The lift-off process is not a problem in the case of the first embodiment that completely covers the metal thin film, but is not suitable as a method for defining a surface region that remains on a part of the metal thin film. This is because the resist thickness of the lift-off process is relatively thick and the pattern dimensions are likely to vary. Therefore, when the lift-off process is applied to the third embodiment, the area ratio of the surface regions with different resistivity varies and the resistance value is set with high accuracy. Because it is difficult.

[Resistance element structure]
FIG. 3 shows a plan view (A) and a cross-sectional view (B) of the process of increasing the resistance of the metal thin film of the resistance element according to this embodiment, and a plan view (C) after the resistance formation. This FIG. 3 is based on the mask layer opening method by etching, similar to the second embodiment.
The mask layer 20 shown in FIGS. 3A and 3B corresponds to the SiN film 12 and the ALD-SiO ₂ film 15 in correspondence with FIG. Since the mask material that can be used for region definition is not limited to SiN or ALD-SiO ₂ , the mask layer 20 is generalized as shown in FIG.

As shown in FIG. 3A, the mask layer 20 has an opening 20A that exposes a part of the low-resistance metal thin film 11L. The shape of the opening 20A of the mask layer 20 is not necessarily rectangular, and may be a rectangle that obliquely crosses the long side of the low-resistance metal thin film 11L. Furthermore, a plurality of openings 20A may exist. Here, as an example, the opening 20A has a size and shape that exposes a substantially central portion in the length direction of the low-resistance metal thin film 11L with a predetermined length and a width wider than the width of the metal thin film.
With such an opening 20A formed, an oxidation treatment is performed as shown in FIG. Then, after removing the mask layer in FIG. 3C, the high resistance surface region RH is formed in the central portion exposed at the opening 20A, and the low resistance surface regions RL1 and RL2 are provided on both sides thereof. The metal thin film 11W is formed.

  In the present embodiment, the number and the planar shape of the high resistance surface region RH are arbitrary, and the formation of the mask layer 20 having different openings and the oxidation treatment are repeated twice or more, so that there are three or more types of resistivity. Can be. Therefore, the characteristic of the resistance element in the present embodiment is that “one resistance film has two or more types of resistivity”.

Such a structural feature is advantageous in the following points as compared with a resistance element in which the resistance film has a difference in resistivity by multilayering or single layering the resistance film or changing the kind of the base material. It is.
First, at the time of manufacturing, only one parameter of the ratio of regions having different resistivity, that is, the area ratio in the effective resistance region of the high resistance surface region RH and the low resistance surface region (RL1 + RL2) in the example of FIG. 3 is controlled. Thus, it is possible to form resistance films having various resistance values.
Second, the manufacturing of the resistance element is facilitated. That is, this structural feature suggests that the resistivity can be set for each region even after the metal thin film is formed, thereby simplifying the manufacturing process.
Thirdly, as shown in FIG. 3C, for example, the portions to be contacted (both ends in this example) are low resistance regions. For this reason, the resistance value of the portion to be contacted is the resistance value at the time of forming the base material, and is not affected by the oxidation treatment of FIG. The resistance value of the element is difficult to vary.
Fourth, the area ratio of the regions is unlikely to vary due to a combination with the technique of opening the mask layer by etching, and the resistance value is also unlikely to vary. This is because the opening 20A of the mask layer 20 is determined by the transfer accuracy of the mask pattern, and not only the accuracy is high, but even if the opening 20A is displaced with respect to the metal thin film, there is almost no influence on the resistance value.

[Selective oxidation method]
Next, two examples of selective oxidation methods that can be employed in the third embodiment will be described with reference to FIGS.

As an example of the selective oxidation, in the plasma oxidation described in the first embodiment, the sheet resistance is controlled by temperature control.
FIG. 4 is a graph showing the measured values indicating the plasma oxidation temperature dependence of the sheet resistance value Rs as Arrhenius plots. In FIG. 4, plasma conditions other than temperature are not changed.
As shown in FIG. 4, in the plasma oxidation, the sheet resistance value Rs of the completed resistance element changes exponentially with respect to the reciprocal of the temperature T. From this, it can be easily inferred that the resistance value change is caused by the constant source diffusion of oxygen into the resistance film.

Another example of selective oxidation is a method of oxidizing a resistance film by supplying oxygen and moisture from a silicon oxide film.
FIG. 5 is a graph of actual measurement values showing changes in the sheet resistance value Rs before and after plasma oxidation (P-TEOS oxidation) using TEOS.
In FIG. 5, for example, a P-TEOS oxide film is formed to 300 [nm] on the resistance element formed up to the state of FIG. 1E or FIG. 2F, and then 460 [° C.] for 5 minutes. The heat treatment is performed. Since a plasma oxide film using TEOS contains a large amount of moisture, the resistance value can be increased more efficiently than a silicon oxide film formed using ALD or high-density plasma. However, the resistance value of the resistance element often depends on the film thickness and film quality of the P-TEOS oxide film, and appropriate management thereof is necessary.
Under the heat treatment conditions for the P-TEOS oxide film of FIG. 5, a high sheet resistance value Rs of about 1200 [Ω / □] was obtained.

  Note that the interlayer insulating film 13 shown in FIG. 1F or FIG. 2G may be a P-TEOS oxide film, but in that case, regions other than the region where the resistance of the metal thin film is increased or other elements may be used as moisture. It is necessary to protect from the influence of oxygen and oxygen.

4 is an example of an electronic device manufacturing method including a step of changing the resistivity of the metal thin film by selective oxidation through the opening of the mask layer. On the other hand, the method of FIG. 5 manufactures an electronic device including a step of selectively oxidizing only a metal thin film region immediately below a silicon oxide film by overheating after adjusting the coating state of the silicon nitride film and the silicon oxide film. It is an example of a method.
The manufacturing methods of the first and second embodiments belong to the method shown in FIG.

<4. Fourth Embodiment>
FIG. 6 shows a plan view of a plurality of resistance elements according to this embodiment. FIG. 7 shows a plan view of Comparative Example 1.
In an LSI or the like, a resistor string or a resistor ladder is sometimes used for the purpose of voltage division or the like, but in order to minimize the arrangement area, the metal thin films 11_1 to 11_5 of a plurality of resistor elements are arranged close to each other as shown in FIG. Thus, for example, it may be desirable to arrange them in parallel.

FIG. 7 is an explanatory diagram of a resistor arrangement example (Comparative Example 1) to which the present invention is not applied.
In order to obtain different resistance values by patterning resistive thin films of the same material, there are usually two ways of changing the length and changing the width as shown in FIG.
Of these, when the width is changed, the line width controllability greatly affects the resistance value, and the line width is greatly influenced by the coarse density of the peripheral pattern at the time of exposure as known as the proximity effect. Therefore, as shown in FIG. 7, it is common to change the resistance value of the resistance element by changing the length with the same designed line width.

However, although not as much as when changing the resistance value only by the line width, due to the proximity effect, the finished line width becomes thicker at the place where the pattern is dense (denoted as “dense”), and the place where the pattern is not dense ( There is a tendency to become thinner.
Specifically, it is assumed that the metal thin film 11 (S) having a short length, the metal thin film 11 (L) having a short length, and the metal thin film 11 (M) having an intermediate length are arranged as illustrated. To do. In this case, the metal thin film 11 (S) is formed thick, its resistance value is likely to be smaller than the design value, and the ratio of the thin portion of the metal thin film 11 (L) is the largest, so the resistance value is lower than the design value. Easy to grow. Further, since the ratio of the thin portion of the metal thin film 11 (M) is smaller than that of the metal thin film 11 (L), the measurement value of the finished product is not as deviated from the design value as the metal thin film 11 (L).

In contrast, the metal thin films 11_1 to 11_5 in the present embodiment shown in FIG. 6 have five metal thin films arranged in parallel with the same shape.
Among them, the second metal thin film 11_2, like the metal thin film 11 (L) in FIG. 7, should have the highest resistance value, and this forms the high resistance surface region RH over the entire effective resistance region. Has been achieved. In addition, the third metal thin film 11_3 should have the next highest resistance value, and this is achieved by limiting this to the middle portion of the effective resistance region and forming the high resistance surface region RH. The other three metal thin films 11_1, 11_4, and 11_5 do not have the high resistance surface region RH.

  The multi-resistance region type metal thin film 11_3 can be manufactured by, for example, the method described in the third embodiment, and the other single resistance type metal thin films (11_1 to 2 and 11_4 to 5) are, for example, first to third. It can be manufactured by the method described in the embodiment. When the metal thin film 11_2 is manufactured by the method described in the third embodiment, the mask layer 20 of FIG. 3 is used in which the dimension of the opening 20A in the resistance element length direction is expanded to the full effective resistance region. Good.

  Note that, when a plurality of metal thin films are arranged close to each other as shown in FIG. 6, the widths of both ends, that is, the metal thin film 11_1 and the metal thin film 11_5 may differ from other metal thin films due to the proximity effect. When the influence is not negligible for the variation in resistance value, for example, a dummy having the same shape in the outer region (region opposite to 11_2) of the metal thin film 11_1 and the outer region (region opposite to 11_4) of the metal thin film 11_5. It is desirable to arrange the metal thin film.

In the present embodiment and the third embodiment, the sheet resistance (equivalent to resistivity in a thin film) can be partially increased in one resistive element, so that the low resistance region RL and the high resistance surface region The resistance value of the entire resistance element is defined by the combined resistance value of RH. That is, even if the resistance film (in this example, a metal thin film) is a resistance element having the same shape as shown in FIG. 6, different resistance values can be obtained by appropriately designing the length of the high resistance surface region RH. it can.
As a result, the processing accuracy between the elements is improved, the accuracy of the resistance value is improved, and the length of the resistor can be shortened, so that the waste of the LSI chip area can be eliminated.

<5. Fifth embodiment>
FIG. 8 is a plan view showing an example in which the technique of arranging a plurality of resistors described in the fourth embodiment is applied to a trimming resistor element. The trimming resistor element includes a type in which a current is passed through a polysilicon film and is blown, and a type in which wiring is mechanically cut with a laser beam. FIGS. 9A and 9B show two comparative examples of cutting the wiring.
10 and 11 show the relationship between the overall trimming resistance value Rtrm and the number of resistors Nr that are separated so as not to contribute to Rtrm. FIG. 10 shows a linear type in which the relationship between the number of resistors Nr and the trimming resistance value Rtrm is almost linear, and FIG. 11 shows a non-linear type in which this relationship is not linear.

As shown in FIG. 10, a preferable change in resistance value as the trimming resistor is a linear type in which the entire trimming resistance value Rtrm and the number of resistors Nr are linear.
In Comparative Example 2 shown in FIG. 9A, the trimming resistor element is configured simply by arranging resistors of the same shape in parallel. In this case, since the combined resistance value changes non-linearly as shown in FIG. 11, the combined resistance value changes gently when the number of resistors is large. However, when this number decreases, the amount of change in one line increases. There is a drawback that adjustment of the combined resistance value is difficult.

As a trimming resistor element improved in this respect, there is an element in which the length of the resistor is sequentially changed in order to change the resistance value by a digit or a constant multiple, as in Comparative Example 3 of FIG. 9B. . Further, although not particularly illustrated, there is a trimming resistor element that outputs a combined resistance value of two trimming resistor units that perform coarse adjustment and fine adjustment.
However, in these cases, while linear characteristics as shown in FIG. 10 or characteristics close to linear can be obtained, the exclusive area of the entire trimming resistor element (module) becomes large as shown in FIG. 9B. There is another drawback.

In the trimming resistor element 30 according to the fifth embodiment shown in FIG. 8, the shape of the resistors (metal thin films 11_1 to 11_10) is the same as in the comparative example 2 of FIG. 9A. However, the resistance value is changed by gradually increasing the area ratio of the high resistance surface region RH. Therefore, the step of gradually increasing the area ratio of the high resistance surface region RH can be changed nonlinearly so as to cancel the nonlinear characteristic of FIG. 11, and thus a clean linear characteristic as shown in FIG. 10 can be obtained.
In the trimming resistor element 30 of FIG. 8, a metal thin film (resistor) in which the high resistance surface region RH does not exist may be added.

As described above, in the fifth embodiment, it is possible to realize an excellent trimming resistor element 30 that satisfies both the small occupied area that is the advantage of the comparative example 2 and the linear characteristic that is the advantage of the comparative example 3.
The selection of the resistor may be a method of cutting the wiring with a laser or the like, but may be controlled by the presence or absence of a contact for connecting the first wiring 14_1 and the resistor or the second wiring 14_2 and the resistor. . In the method of cutting with a laser or the like, it is possible to set the trimming resistance value according to the final characteristic measurement result. The control based on the presence / absence of contact can be used when, for example, characteristics can be measured by TEG or the like during the manufacture of the transistor and its wiring, and the measurement result is reflected in the trimming resistance value.
In any case, a desired resistance value can be obtained for the entire trimming resistor 30 by controlling the connection or non-connection between the end of the metal thin film (resistor) and the wiring.

  According to the first to fifth embodiments described above, a single resistance film (for example, a metal thin film) can be formed from a low resistance to a high resistance. Accordingly, it is not necessary to form a resistance element using a plurality of resistance films, and the number of processes can be reduced, so that the manufacturing period can be shortened and the cost can be reduced.

  Further, it is possible to design a desired resistance value in a state where the elements are formed with the same resistance width and resistance length. For this reason, it is possible to improve the processing accuracy by unifying the size of the resistance elements as in the fourth and fifth embodiments and aligning them at the same location, and therefore the resistance element accuracy can be improved. .

  Furthermore, in the fifth embodiment, since a plurality of resistance values can be formed with one type of resistance element size, it is possible to realize a trimming resistance element that can arbitrarily design the rate of change of the resistance value. As a result, the module-occupying area of the high-precision trimming resistor element can be greatly reduced, and the LSI can be miniaturized.

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 10 ... Insulating layer, 11 ... Metal thin film, 11H ... High resistance metal thin film, 11L ... Low resistance metal thin film, 11W ... Multi-resistance region type metal thin film, 12 ... SiN film, 14_1 ... 1st wiring, 14_2 ... second wiring, 15 ... ALD-SiO ₂ film, 20 ... mask layer, 20A ... opening, 30 ... trimming resistor element, RH ... high resistance surface region, RL1, RL2 ... low resistance surface area, Rs ... sheet resistance value

Claims (17)

An electronic device in which a resistance film that defines a resistance value of a resistance element is arranged in one of conductive film arrangement layers between insulating layers in a laminated structure formed on a substrate, and the resistance film has two or more types of resistivity. The electronic device according to claim 1, wherein the resistance film is a multi-resistance region type metal thin film having a plurality of surface regions having different resistivity. As a plurality of the resistance films having different resistance values, the plurality of metal thin films of the multi-resistance region type,
The electronic device according to claim 2, wherein the plurality of metal thin films of the multi-resistance region type have the same shape, all having the same thickness, length, and width, and different area ratios of the plurality of surface regions having different resistivity. A plurality of metal thin films including the multi-resistance region type metal thin film are arranged as a plurality of trimming resistance films that determine a resistance value of one trimming resistance element,
A first wiring that can be connected to one end of each metal thin film and a second wiring that can be connected to the other end of each metal thin film with respect to the plurality of metal thin films as the trimming resistance film. Arranged,
With respect to the plurality of metal thin films as the trimming resistance film, a trimming resistance value between the first wiring and the second wiring is determined by electrical connection or non-connection of the first wiring or the second wiring. The electronic device according to claim 3. The electronic device according to claim 4, wherein the multi-resistance region type metal thin film has a different area ratio between two surface regions having different resistivity. Of the two surface regions having different resistivities, the upper surface of one region is covered with a silicon oxide film, and the upper surface of the other region is covered with a silicon nitride film,
The first surface region covered with the silicon nitride film is formed of any one of metal nitrides of ZrN, TaN, HfN, NbN, WN, TiN,
The electronic device according to claim 5, wherein the second surface region covered with the silicon oxide film is formed of the same metal nitride oxide as the first surface region. The plurality of metal thin films serving as the trimming resistance film are spaced apart from each other in parallel, and the area ratio of the two surface regions having different resistivity gradually increases from 0 to 1 from one side to the other side in the separation direction. The electronic device according to claim 6. At least one multi-resistance region type metal thin film and at least one single resistance type metal thin film having a single resistivity are arranged as a trimming resistor film that determines a resistance value of one trimming resistor element;
For the plurality of metal thin films as the trimming resistance film, a first wiring that can be connected to each one end of each metal thin film and a second wiring that can be connected to each other end are arranged,
With respect to the plurality of metal thin films as the trimming resistance film, a trimming resistance value between the first wiring and the second wiring is determined by electrical connection or non-connection of the first wiring or the second wiring. The electronic device according to claim 3. The electronic device according to claim 2, wherein the multi-resistance region type metal thin film has a different area ratio between two surface regions having different resistivity. Of the two surface regions having different resistivity, one region upper surface is coated with a silicon oxide film, and the other region upper surface is coated with a silicon nitride film,
The first surface region covered with the silicon nitride film is formed of any one of metal nitrides of ZrN, TaN, HfN, NbN, WN, TiN,
The electronic device according to claim 9, wherein the second surface region covered with the silicon oxide film is formed of the same metal nitride oxide as the first surface region. As another resistance film having a different resistance value from the plurality of metal thin films of the multi-resistance region type, the same shape as the metal thin film of the multi-resistance region type has the same shape, and the resistivity is a single resistance type The electronic device according to claim 2, further comprising a plurality of metal thin films. Having two single resistance type metal thin films having different resistivity from each other;
Of the two single-resistance metal thin films, at least the entire upper surface of one is covered with a silicon oxide film, and at least the entire upper surface of the other is covered with a silicon nitride film,
One single resistance type metal thin film covered with the silicon nitride film is formed of any one of metal nitrides of ZrN, TaN, HfN, NbN, WN, TiN,
12. The electron according to claim 11, wherein the other single-resistance type metal thin film covered with the silicon oxide film is formed of the same metal nitride oxide as the one single-resistance type metal thin film. device. The electronic device according to claim 12, wherein the two single-resistance metal thin films have the same shape, all having the same thickness, length, and width. A plurality of resistance films defining the resistance value of the resistance element are arranged in one of the conductive film arrangement layers between the insulating layers in the laminated structure formed on the substrate, and the plurality of resistance films have two or more types of resistivity. A plurality of metal thin films, the plurality of metal thin films including two metal thin films having the same shape and different resistivities, and one of the two metal thin films is covered with a silicon nitride film and the other upper surface Is an electronic device covered with a silicon oxide film. The electronic device according to claim 14, wherein the plurality of metal thin films include a metal thin film having both a surface region covered with a silicon nitride film and a surface region covered with a silicon oxide film. Forming a resistive film of the resistive element on the insulating film supported by the substrate, and forming the resistive film,
Depositing a metal thin film on the insulating film;
Covering a region including a portion to be the resistance film of the metal thin film with a mask layer;
Opening the mask layer in at least a partial region of the portion to be the resistance film, oxidizing the region of the resistance film exposed from the opening, and changing the resistivity;
Patterning the metal thin film into the shape of the resistive film;
A method of manufacturing an electronic device comprising: Forming a resistive film of the resistive element on the insulating film supported by the substrate, and forming the resistive film,
Depositing a metal thin film on the insulating film;
By performing heat treatment in a state where at least a part of the metal thin film to be a plurality of the resistance films having different resistivity is coated with a silicon oxide film and the other area is covered with a silicon nitride film, Selectively changing the resistivity in the area of the coated metal film;
Patterning the metal thin film into the shape of the resistive film;
A method of manufacturing an electronic device comprising:

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