JP7351425B1 - Gate drive circuit, power converter, and gate drive circuit control method - Google Patents

Abstract

The present invention alleviates restrictions on the minimum on-pulse width while suppressing biased magnetism when driving a pulse transformer with a DC/AC modulation circuit. A gate drive circuit includes modulation circuits 2, 3, an on-side rectifier circuit 4, and an off-side rectifier circuit 5. The modulation circuits 2 and 3 make the frequencies of the first modulation signal vTr1 and the second modulation signal vTr2 variable according to the ON command width and OFF command width of the gate command. The ON command width and the period of one positive pulse of the first modulation signal vTr1 are the same, the ON command width and the period of one negative pulse of the first modulation signal vTr1 are the same, and each time the ON command is issued, the first modulation signal A positive pulse and a negative pulse of vTr1 are output alternately. [Selection diagram] Figure 1

Description

The present invention relates to a method for modulating gate drive circuits in power converters that are simultaneously driven in series.

In a circuit that drives semiconductor devices in series, a pulse transformer is used to drive the gates to ensure simultaneous switching performance.

JP2006-271041A

However, when driving a pulse transformer using a DC/AC modulation circuit, it is necessary to make the periods of the output positive pulse and negative pulse the same to prevent biased magnetization.

FIG. 17 shows operating waveforms when the minimum on-pulse width is limited due to the influence of hardware such as the drive IC in driving the DC/AC modulation circuit. Since the positive and negative pulses are limited, the minimum on-pulse width is twice as long. For example, if the minimum pulse width is 100 ns, the modulation circuit cannot output a pulse of 200 ns or less, resulting in a limit on the command value.

This leads to an increase in the error between the gate command and the actual switching operation of the semiconductor device, that is, a deterioration in the output voltage accuracy of the inverter.

In view of the above, it is an issue to provide a gate drive circuit that alleviates restrictions on the minimum on-pulse width while suppressing biased magnetism when driving a pulse transformer with a DC/AC modulation circuit.

The present invention has been devised in view of the above-mentioned conventional problems, and one aspect thereof includes a modulation circuit that outputs a first modulation signal and a second modulation signal based on an ON command and an OFF command of a gate command. , an on-side primary winding to which the first modulation signal is applied, an on-side secondary winding that transforms and outputs the voltage applied to the on-side primary winding, and an on-side tertiary winding. an on-side rectifier circuit comprising a first pulse transformer, a first diode circuit that rectifies the output of the on-side secondary winding, and a second diode circuit that rectifies the output of the on-side tertiary winding; , an off-side primary winding to which the second modulation signal is applied, an off-side secondary winding that transforms and outputs the voltage applied to the off-side primary winding, and an off-side tertiary winding. an off-side rectifier circuit comprising a second pulse transformer, a third diode circuit that rectifies the output of the off-side secondary winding, and a fourth diode circuit that rectifies the output of the off-side tertiary winding; , and controls a semiconductor element to be driven according to the outputs of the first to fourth diode circuits, wherein the modulation circuit is configured to control a semiconductor element to be driven according to the outputs of the first to fourth diode circuits, wherein the modulation circuit is configured to control the semiconductor device according to the ON command width and the OFF command width of the gate command. the frequencies of the first modulation signal and the second modulation signal are made variable, the ON command width and the period of one positive pulse of the first modulation signal are made the same, and the ON command width and the period of one positive pulse of the first modulation signal are made variable. It is characterized in that the period of one negative pulse is the same, and the positive pulse and the negative pulse of the first modulation signal are alternately output every time the ON command is issued.

Further, as another aspect, a modulation circuit that outputs a first modulation signal and a second modulation signal based on an on command and an off command of the gate command, and an on-side primary winding to which the first modulation signal is applied. and a first pulse transformer having an on-side secondary winding and an on-side tertiary winding that transform and output the voltage applied to the on-side primary winding, and a first pulse transformer that transforms and outputs the voltage applied to the on-side primary winding. an on-side rectifier circuit comprising a first diode circuit for rectifying and a second diode circuit for rectifying the output of the on-side tertiary winding; and an off-side primary winding to which the second modulation signal is applied. and a second pulse transformer having an off-side secondary winding and an off-side tertiary winding that transform and output the voltage applied to the off-side primary winding, and a second pulse transformer that transforms and outputs the voltage applied to the off-side primary winding. an off-side rectifier circuit comprising a third diode circuit that rectifies the output of the off-side tertiary winding and a fourth diode circuit that rectifies the output of the off-side tertiary winding according to the output of the first to fourth diode circuits; a gate drive circuit that controls a semiconductor device to be driven, the modulation circuit varying the frequencies of the first modulation signal and the second modulation signal according to an ON command width and an OFF command width of the gate command; and the off command width and the period of one positive pulse of the second modulation signal are the same, the off command width and the period of one negative pulse of the second modulation signal are the same, and each time the off command is The positive pulse and the negative pulse of the second modulation signal are alternately output.

Further, in one aspect, the modulation circuit includes a rising edge detection circuit that detects a rising edge of the gate command, latches at a timing when the rising edge of the gate command is detected, and further includes a rising edge detection circuit of the gate command in the latched state. a latch circuit that releases the latch at the timing when the gate command is detected; a first AND circuit that outputs a logical product of the gate command and the output of the latch circuit; a NOT circuit that inverts the output of the latch circuit; a second AND circuit that outputs a logical product of the outputs of the NOT circuit; a drive IC that controls a DC/AC modulation circuit based on the output of the first AND circuit and the output of the second AND circuit; and a drive IC that controls the drive IC. and the DC/AC modulation circuit that outputs the first modulation signal based on the DC/AC modulation circuit.

Further, as another aspect, a modulation circuit that outputs a first modulation signal and a second modulation signal based on an on command and an off command of the gate command, and an on-side primary winding to which the first modulation signal is applied. and a first pulse transformer having an on-side secondary winding and an on-side tertiary winding that transform and output the voltage applied to the on-side primary winding, and a first pulse transformer that transforms and outputs the voltage applied to the on-side primary winding. an on-side rectifier circuit comprising a first diode circuit for rectifying and a second diode circuit for rectifying the output of the on-side tertiary winding; and an off-side primary winding to which the second modulation signal is applied. and a second pulse transformer having an off-side secondary winding and an off-side tertiary winding that transform and output the voltage applied to the off-side primary winding, and a second pulse transformer that transforms and outputs the voltage applied to the off-side primary winding. an off-side rectifier circuit comprising a third diode circuit that rectifies the output of the off-side tertiary winding and a fourth diode circuit that rectifies the output of the off-side tertiary winding according to the output of the first to fourth diode circuits; a gate drive circuit that controls a semiconductor device to be driven, the modulation circuit varying the frequencies of the first modulation signal and the second modulation signal according to an ON command width and an OFF command width of the gate command; and the first modulation signal outputs a positive pulse or a negative pulse during the ON command period of the gate command, and the polarity at the time of output start of the first modulation signal is reversed every cycle of the gate command, and the The present invention is characterized in that the polarity of the first modulation signal is inverted when the output period of the first modulation signal has elapsed for a predetermined time.

Further, as another aspect, a modulation circuit that outputs a first modulation signal and a second modulation signal based on an on command and an off command of the gate command, and an on-side primary winding to which the first modulation signal is applied. and a first pulse transformer having an on-side secondary winding and an on-side tertiary winding that transform and output the voltage applied to the on-side primary winding, and a first pulse transformer that transforms and outputs the voltage applied to the on-side primary winding. an on-side rectifier circuit comprising a first diode circuit for rectifying and a second diode circuit for rectifying the output of the on-side tertiary winding; and an off-side primary winding to which the second modulation signal is applied. and a second pulse transformer having an off-side secondary winding and an off-side tertiary winding that transform and output the voltage applied to the off-side primary winding, and a second pulse transformer that transforms and outputs the voltage applied to the off-side primary winding. an off-side rectifier circuit comprising a third diode circuit that rectifies the output of the off-side tertiary winding and a fourth diode circuit that rectifies the output of the off-side tertiary winding according to the output of the first to fourth diode circuits; a gate drive circuit that controls a semiconductor device to be driven, the modulation circuit varying the frequencies of the first modulation signal and the second modulation signal according to an ON command width and an OFF command width of the gate command; During the off command period of the gate command, the second modulation signal outputs a positive pulse or a negative pulse, and the polarity at the start of output of the second modulation signal is reversed every cycle of the gate command, and the second modulation signal outputs a positive pulse or a negative pulse. The present invention is characterized in that the polarity of the second modulation signal is inverted when the output period of the second modulation signal has elapsed for a predetermined time.

Further, as one aspect, an inversion permission signal generation unit that generates an inversion permission signal that switches between “1” and “0” at a falling edge of the gate command; A gate signal GATE1 that outputs "1" until a predetermined time after being output and becomes "0" at other times, the gate command is on, and a predetermined time has elapsed since the gate command outputs on. After that, a gate signal generation section that generates a gate signal GATE2 that outputs "1" and becomes "0" otherwise, and when the inversion permission signal is "0", the gate signal GATE1 is "0". When the gate signal GATE2 is "1", the positive output gate signal GATE_P is "1"; when the gate signal GATE2 is "1", the negative output gate signal GATE_N is "1"; otherwise, the positive output gate signal GATE_P, the negative output gate When the signal GATE_N is "0" and the inversion permission signal is "1", the negative output gate signal GATE_N is "1" when the gate signal GATE1 is "1", and the gate signal GATE2 is "1". a polarity selector section that sets the positive output gate signal GATE_P to "1" at one time and sets the positive output gate signal GATE_P and the negative output gate signal GATE_N to "0" at other times; A drive IC that controls a DC/AC modulation circuit based on an output gate signal GATE_N, and the DC/AC modulation circuit that outputs the first modulation signal based on control of the drive IC. do.

Further, in one embodiment, the DC/AC modulation circuit is a modulation signal generation circuit, and the modulation circuit includes a synchronization circuit that synchronizes the gate command with a clock signal, and a rising edge that detects a rising edge of an output of the synchronization circuit. an edge detection section; a falling edge detection section that detects a falling edge of the output of the synchronous circuit; and a falling edge detection section that starts counting when the falling edge of the output of the synchronous circuit is detected, and detects the rising edge of the output of the synchronous circuit; an off-pulse width measuring section that stops counting when detected and adds a count value every time the clock signal is input; an off-side 1-bit shift circuit that reduces the output of the off-pulse width measuring section to 1/2; an off-side latch circuit that latches the output of the side 1-bit shift circuit at the timing of the rising edge of the output of the synchronous circuit; a first down counter that subtracts a count value from the first down counter, and a second down counter that receives the output of the off-side latch circuit, the output of the first down counter, and the clock signal, and subtracts the count value every time the clock signal is input. 2 down counter, and the modulation signal generation circuit is characterized in that it outputs the second modulation signal until the counters of the first and second down counters reach zero.

In one embodiment, the DC/AC modulation circuit includes a capacitor, first and second on-side semiconductor elements connected in series between both ends of the capacitor, and an on-side semiconductor element connected in series between both ends of the capacitor. a full-bridge circuit for generating an on signal having third and fourth semiconductor elements; and off-side first and second semiconductor elements connected in series between both ends of the capacitor; an off-side third and fourth semiconductor element, and a full-bridge circuit for generating an off-signal having a connection point between the on-side first and second semiconductor elements and the on-side third and fourth semiconductor elements; The on-side primary winding of the first pulse transformer is connected between the connection point of the off-side first and second semiconductor elements and the off-side third and fourth semiconductor elements. The off-side primary winding of the second pulse transformer is connected between the point and the point.

Further, in one aspect, the modulation circuit includes a synchronization circuit that synchronizes the gate command with a clock signal, a rising edge detection section that detects a rising edge of an output of the synchronization circuit, and a falling edge of the output of the synchronization circuit. a falling edge detection unit that detects the output of the synchronous circuit, starts counting when it detects a falling edge of the output of the synchronous circuit, stops counting when it detects the rising edge of the output of the synchronous circuit, and receives the clock signal. an OFF-side 1-bit shift circuit that reduces the output of the OFF-side 1-bit shift circuit to half the output of the OFF-side 1-bit shift circuit; An off-side latch circuit that latches at the timing of a rising edge, and the output of the off-side latch circuit and the clock signal are input, and each time the clock signal is input, a count value is subtracted until the count value becomes 0. a first down counter that outputs gate commands for the off-side first and fourth semiconductor elements, an output of the off-side latch circuit, an output of the first down counter, and the clock signal; and a second down counter that subtracts a count value each time the count value reaches zero, and outputs a gate command for the off-side second and third semiconductor elements until the count value reaches zero.

In one embodiment, the off-pulse width measurement section has n (n: an integer of 1 or more) stages, and the clock signal is input to the D-FF terminal in the first stage, and the first on-side D The first on-side D flip-flop circuit receives the output of the /Q terminal of the flip-flop circuit and the output of the Q terminal becomes a 1-bit signal, and the second stage includes the first on-side D flip-flop circuit. a second on-side XOR circuit inputting the output of the Q terminal of the second on-side D flip-flop circuit and the output of the Q terminal of the second on-side D flip-flop circuit; the second on-side D flip-flop circuit which inputs the output of the XOR circuit and whose output from the Q terminal is a 2-bit signal; a third on-side AND circuit into which the output and the output of the Q terminal of the second on-side D flip-flop circuit are input; and the output of the third on-side AND circuit and the output of the Q terminal of the third on-side D flip-flop circuit. and a third on-side XOR circuit which inputs the clock signal to the D-FF terminal, inputs the output of the third on-side XOR circuit to the D terminal, and outputs from the Q terminal as a 3-bit signal. 3 on-side D flip-flop circuits, and the fourth to nth stages have a k (k: an integer from 4 to n)-1 bit signal, (k-2) bit, (k-3) bit... a k-th on-side AND circuit that receives 2-bit/1-bit signals; a k-th on-side XOR circuit that receives the output of the k-th on-side AND circuit and the output of the Q terminal of the k-th on-side D flip-flop circuit; - the k-th on-side D flip-flop circuit which inputs the clock signal to the FF terminal, inputs the output of the k-th on-side XOR circuit to the D terminal, and whose output from the Q terminal is a kbit signal; It is characterized by

Further, in one aspect, the first and second down counters have an n-stage configuration (n: an integer of 1 or more), and the clock signal is input to the D-FF terminal in the first stage, and the clock signal is input to the D-FF terminal in the first stage. the first off-side D flip-flop circuit inputs the output of the /Q terminal of the first off-side D flip-flop circuit, and the output of the Q terminal becomes a 1-bit signal; A second off-side XOR circuit inputs the output of the /Q terminal of the D flip-flop circuit and the output of the /Q terminal of the second off-side D flip-flop circuit; the second off-side D flip-flop circuit inputs the output of the second off-side XOR circuit, and the output of the Q terminal becomes a 2-bit signal; a third off-side AND circuit inputting the output of the /Q terminal of the flip-flop circuit and the output of the /Q terminal of the second off-side D flip-flop circuit; A third off-side XOR circuit inputs the output of the /Q terminal of the flip-flop circuit, inputs the clock signal to the D-FF terminal, inputs the output of the third off-side XOR circuit to the D terminal, and inputs the output of the third off-side XOR circuit to the Q terminal. the third off-side D flip-flop circuit whose output is a 3-bit signal; 2) A k-th off-side AND circuit that inputs a bit·/(k-3)bit.../2bit·/1-bit signal, and the output of the k-th off-side AND circuit and the /Q of the k-th off-side D flip-flop circuit. A k-th off-side XOR circuit inputs the output of the terminal, the clock signal is inputted to the D-FF terminal, the output of the k-th off-side XOR circuit is inputted to the D terminal, and the output of the Q terminal is a kbit signal. The k-th off-side D flip-flop circuit is characterized in that it has the k-th off-side D flip-flop circuit.

According to the present invention, it is possible to provide a gate drive circuit in which the restriction on the minimum on-pulse width is relaxed while suppressing biased magnetism when driving a pulse transformer with a DC/AC modulation circuit.

3 is a circuit configuration diagram showing a gate drive circuit in embodiments 1 and 2. FIG. A time chart showing each waveform of the gate drive circuit. FIG. 3 is a block diagram showing a modulation circuit 3 in embodiments 1 and 2. FIG. 5 is a time chart showing each waveform of the modulation circuit 3 in the first and second embodiments. FIG. 3 is a diagram showing an off-pulse width measuring section (n-stage up counter). FIG. 3 is a diagram showing an n-stage down counter. 3 is a diagram showing other examples of modulation circuits 2 and 3 in Embodiments 1 and 2. FIG. FIG. 3 is a block diagram showing a control section of the modulation circuit 3 in embodiments 1 and 2. FIG. 5 is a time chart showing each waveform of the control section of the modulation circuit 3 in the first and second embodiments. FIG. 3 is a diagram showing a conventional modulation signal and a modulation signal according to the first embodiment. FIG. 3 is a block diagram showing a control section of the modulation circuit 2 in the first embodiment. 5 is a time chart showing each waveform of the control section of the modulation circuit 2 in the first embodiment. 13 is a diagram showing output waveforms and characteristics of the modulation circuit in FIGS. 2 and 12. FIG. FIG. 2 is a block diagram showing a control section of a modulation circuit 2 according to a second embodiment. 5 is a time chart showing each waveform of the modulation circuit 2 in the second embodiment. 5 is a time chart showing other examples of each waveform of the modulation circuit 2 in the second embodiment. A time chart showing conventional gate commands and modulation signals.

Embodiments 1 and 2 of the gate drive circuit according to the present invention will be described in detail below based on FIGS. 1 to 16.

[Embodiment 1]
Embodiment 1 measures the gate command and changes the drive frequency of the pulse transformer according to the pulse width, thereby increasing the output pulse (pulse width of the gate command) of the device without increasing the switching loss of the modulation circuit. Improve time resolution.

Figure 1 shows a circuit diagram of the gate drive circuit in Embodiment 1, Figure 2 shows a time chart showing each waveform of the gate drive circuit, Figure 3 shows a block diagram of the modulation circuit, and Figure 4 shows a time chart of each waveform of the modulation circuit. show.

First, the gate drive circuit shown in FIG. 1 will be explained. As shown in FIG. 1, the gate drive circuit of the first embodiment includes modulation circuits 2 and 3, an on-side rectifier circuit 4, an off-side rectifier circuit 5, a demodulation circuit 6, and a gate circuit 7. and controls the semiconductor element 8 to be driven.

A gate command ON command is output to the modulation circuit 2. Further, an off command of the gate command is output to the modulation circuit 3. Although FIG. 1 shows a modulation circuit 2 to which an ON command is input and a modulation circuit 3 to which an OFF command is input, a configuration may be adopted in which an ON command and an OFF command are input to one modulation circuit.

The on-side primary winding of the first pulse transformer Tr<b>1 of the on-side rectifier circuit 4 is connected to the modulation circuit 2 . The first pulse transformer Tr1 has an on-side primary winding, an on-side secondary winding that transforms and outputs the voltage applied to the on-side primary winding, and an on-side tertiary winding. A first diode circuit db1 is connected to the on-side secondary winding of the first pulse transformer Tr1, and a second diode circuit db2 is connected to the on-side tertiary winding of the first pulse transformer Tr1.

The off-side primary winding of the second pulse transformer Tr2 of the off-side rectifier circuit 5 is connected to the modulation circuit 3. The second pulse transformer Tr2 has an off-side primary winding, an off-side secondary winding that transforms and outputs the voltage applied to the off-side primary winding, and an off-side tertiary winding. A third diode circuit db3 is connected to the off-side secondary winding of the second pulse transformer Tr2, and a fourth diode circuit db4 is connected to the off-side tertiary winding of the second pulse transformer Tr2. The first to fourth diode circuits db1 to db4 are, for example, full bridge circuits.

Next, the demodulation circuit 6 will be explained. The anode of the first diode D1 is connected to one terminal of the first diode circuit db1. The anode of the second diode D2 is connected to one terminal of the second diode circuit db2. The anode of the third diode D3 is connected to one terminal of the third diode circuit db3. The anode of the fourth diode D4 is connected to one terminal of the fourth diode circuit db4.

First and second capacitors C1 and C2 are connected in series between the cathodes of the first and third diodes D1 and D3 and the other terminals of the second and fourth diode circuits db2 and db4. The other terminals of the first and third diode circuits db1 and db3 are connected to the connection point of the first and second capacitors C1 and C2. Moreover, the cathodes of the second diode D2 and the fourth diode D4 are connected to the connection point of the first and second capacitors C1 and C2.

One end of the first resistor R1 is connected to the anode of the first diode D1. The other end of the first resistor R1 is the second terminal (drain terminal) of the second semiconductor element Q2, the first terminal (gate terminal) of the third semiconductor element Q3, and the first terminal (gate terminal) of the fourth semiconductor element Q4. is connected.

One end of the fourth resistor R4 and the first terminal (gate terminal) of the first semiconductor element Q1 are connected to the anode of the second diode D2. The other terminals of the second and fourth diode circuits db2 and db4 are connected to the other end of the fourth resistor R4.

One end of the second resistor R2 is connected to the anode of the fourth diode D4. The second terminal (drain terminal) of the first semiconductor element Q1 and one end of the third resistor R3 are connected to the other end of the second resistor R2. The third terminal (source terminal) of the first semiconductor element Q1 is connected to the other terminals of the second and fourth diode circuits db2 and db4.

One end of the fifth resistor R5 and the first terminal (gate terminal) of the second semiconductor element Q2 are connected to the other end of the third resistor R3. The other end of the fifth resistor R5 is connected to the other terminals of the second and fourth diode circuits db2 and db4. The third terminal (source terminal) of the second semiconductor element Q2 is connected to the other terminals of the second and fourth diode circuits db2 and db4.

Next, the gate circuit 7 will be explained. The first terminal (gate terminal) of the third semiconductor element Q3 is connected to the other end of the first resistor R1 and the second terminal (drain terminal) of the second semiconductor element Q2. The second terminal (drain terminal) of the third semiconductor element Q3 is connected to the cathode of the first diode D1. The third terminal (source terminal) of the third semiconductor element Q3 is connected to one end of the on-side resistor Ron.

The first terminal (gate terminal) of the fourth semiconductor element Q4 is connected to the other end of the first resistor R1 and the second terminal (drain terminal) of the second semiconductor element Q2. The second terminal (drain terminal) of the fourth semiconductor element Q4 is connected to one end of the off-side resistor Roff. The third terminal (source terminal) of the fourth semiconductor element Q4 is connected to the other terminals of the second and fourth diode circuits db2 and db4.

The other ends of the on-side resistance Ron and the off-side resistance Roff are connected to the first terminal (gate terminal) of the semiconductor element 8 to be driven. The third terminal (source terminal) of the semiconductor element 8 to be driven is connected to the cathodes of the second and fourth diodes D2 and D4.

Here, the first modulation signal (voltage) applied to the on-side primary winding of the first pulse transformer Tr1 is vTr1, and the second modulation signal (voltage) applied to the off-side primary winding of the second pulse transformer Tr2 is vTr1. ) is vTr2. Further, the voltage of the first capacitor C1 is set to Vg+, and the voltage of the second capacitor C2 is set to Vg-. Furthermore, the gate voltage (voltage between gate and source) of the semiconductor element 8 to be driven is assumed to be Vgs.

The circuit of FIG. 1 drives the first and second pulse transformers Tr1 and Tr2 by modulating the ON signal and the OFF signal with a frequency that drives the first and second pulse transformers Tr1 and Tr2, as in Patent Document 1. At the same time as transmitting power, a signal is input to the demodulation circuit 6 to transmit an on/off command to the gate circuit 7. At this time, the pulse width input as a gate command is measured by a counter, and the second pulse transformer Tr2 is driven at a frequency whose width is one period, and the first pulse transformer Tr2 is driven at a frequency whose width is one half period. By driving Tr1, the first and second pulse transformers Tr1 and Tr2 can be modulated at a frequency suitable for the pulse width of the gate command, so high resolution can be achieved.

The circuit shown in FIG. 1 is characterized in that it includes a first pulse transformer Tr1 for generating a gate-on command and a second pulse transformer Tr2 for generating a gate-off command. If you want to send an on command, you can apply a voltage to the first pulse transformer Tr1, and if you want to send an off command, you can apply a voltage to the second pulse transformer Tr2.

By providing a tertiary winding in the first and second pulse transformers Tr1 and Tr2, a negative bias can be applied to the gate voltage Vgs. Vg+ is a voltage obtained by rectifying the voltage generated by the secondary winding, and Vg- is a voltage obtained by rectifying the voltage generated by the tertiary winding. The magnitude of the voltages Vg+ and Vg- is determined by the turns ratio of the first and second pulse transformers Tr1 and Tr2 and the voltages (first and second modulation signals) vTr1 and vTr2 applied to the first and second pulse transformers Tr1 and Tr2. Can be adjusted.

The outputs of the third and fourth semiconductor elements Q3 and Q4 that constitute the push-pull circuit are configured to omit diodes by connecting them through resistors, assuming that the gate resistance values are divided between the on side and the off side. . The output of the push-pull circuit may be connected without using a resistor.

First, we will outline the operation when turned on. An operation time chart is shown in FIG. In the time chart of FIG. 2, in order to simplify the explanation, it is assumed that the gate voltage threshold values of the first to fourth semiconductor elements Q1, Q2, Q3, and Q4 are ignored. As shown in FIG. 2, when the gate command becomes high, the voltage of the first modulation signal vTr1 is applied to the first pulse transformer Tr1, and the voltage of the first modulation signal vTr1 is applied to the first and second capacitor C1, C2 is charged.

At this time, a voltage is applied between the gate and source of the first semiconductor element Q1, making the first semiconductor element Q1 conductive and turning the second semiconductor element Q2 off. Since the second semiconductor element Q2 is turned off, the gate voltages of the third and fourth semiconductor elements Q3 and Q4 are charged via the first resistor R1. Then, the gate voltages of the third and fourth semiconductor elements Q3 and Q4 become the same potential as the first capacitor C1, the third semiconductor element Q3 becomes conductive, and the gate voltage Vgs rises to the charging voltage vg+ of the first capacitor C1.

Next, the operation when turned off will be outlined. As shown in FIG. 2, when the gate command becomes low, the voltage of the second modulation signal vTr2 is applied to the second pulse transformer Tr2, and the voltage of the second modulation signal vTr2 is applied to the first and second capacitors C1, C1, and VTr2 via the third and fourth diode circuits db3 and db4. C2 is charged.

At this time, the gate and source of the second semiconductor element Q2 are charged through the second resistor R2, so the second semiconductor element Q2 becomes conductive. Then, the gate voltages of the third and fourth semiconductor elements Q3 and Q4 become the same potential as the second capacitor C2, so the fourth semiconductor element Q4 becomes conductive and the gate voltage Vgs reaches the charging voltage of the second capacitor C2 -vg-. descend. By performing the above operation in one cycle, the on/off operation of the semiconductor element 8 to be driven can be controlled.

Next, a method of generating the second modulation signal vTr2 in the first embodiment will be described. Generation of the second modulation signal vTr2 can be realized by using the configuration example of the modulation circuit 3 shown in FIG. Further, a time chart of each waveform of the modulation circuit 3 is shown in FIG.

The synchronization circuit 9 receives a gate command (oscillator output) and a clock signal, and synchronizes the gate command (oscillator output) with the clock signal. The rising edge detection section 10 detects the rising edge of the synchronization circuit 9. The falling edge detection section 11 detects the falling edge of the synchronization circuit 9.

The off-pulse width measuring section (up counter) 12 starts counting when it detects a falling edge of the synchronization circuit 9, stops counting when it detects a rising edge, and adds the count value every time a clock signal is input.

At this time, it is assumed that the rising edge and the falling edge are synchronized with the clock signal by the function of the synchronization circuit 9. This makes it possible to measure the off-pulse width.

The off-side 1-bit shift circuit 13 reduces the output (count value) of the off-pulse width measuring section 12 to 1/2.

The off-side latch circuit 14 latches the output of the off-side 1-bit shift circuit 13 at the timing when a rising edge is detected.

The modulation signal generation counter (first down counter) 15 receives the output of the off-side latch circuit 14 and a clock signal, and subtracts a count value every time the clock signal is input. The modulation signal generation counter (second down counter) 16 receives the output of the off-side latch circuit 14, the output of the first down counter 15, and a clock signal, and subtracts the count value every time the clock signal is input.

The modulation signal generation circuit 17 inputs the outputs of the first and second down counters 15 and 16 and assembles a circuit (AC/DC conversion circuit) to output a modulation signal until the count value becomes 0. It is possible to generate a second modulation signal vTr2 with a duty of 50% in which one cycle is the commanded pulse width.

Therefore, it is possible to suppress the frequency of the second modulation signal vTr2 to twice the switching frequency of the semiconductor element 8 to be driven, and the time resolution of the pulse width of the gate command can be improved without increasing the drive frequency of the second pulse transformer Tr2. can be improved.

Next, the off-pulse width measuring section 12 (up counter) will be explained. FIG. 5 shows an up counter having n (n: an integer equal to or greater than 1) stages as an example.

In the first stage, the first on-side D flip-flop circuit 18a inputs the clock signal CLK to the D-FF terminal. The output of the /Q terminal of the first on-side D flip-flop circuit 18a is input to the D terminal. The output of the Q terminal of the first on-side D flip-flop circuit 18a is output as a 1-bit signal.

In the second stage, the second on-side XOR circuit 19b receives the output of the Q terminal of the first on-side D flip-flop circuit 18a and the output of the Q terminal of the second on-side D flip-flop circuit 18b.

The clock signal CLK is input to the D-FF terminal of the second on-side D flip-flop circuit 18b, and the output of the second on-side XOR circuit 19b is input to the D terminal. The output of the Q terminal of the second on-side D flip-flop circuit 18b is output as a 2-bit signal.

In the third stage, the third on-side AND circuit 20c receives a 1-bit signal and a 2-bit signal.

The third on-side XOR circuit 19c receives the output of the third on-side AND circuit 20c and the output of the Q terminal of the third on-side D flip-flop circuit 18c.

The third on-side D flip-flop circuit 18c inputs the clock signal CLK to its D-FF terminal, and inputs the output of the third on-side XOR circuit 19c to its D terminal. The output of the Q terminal of the third on-side D flip-flop circuit 18c is output as a 3-bit signal.

In this way, the up counter is composed of n stages. At the k-th stage (k: an integer from 4 to n), the k-1 bit signal and (k-2) bit, (k-3) bit, . . . 2 bit, 1 bit signals are input to the k-th AND circuit 20k.

The k-th XOR circuit 19k receives the output signal of the k-th AND circuit 20k and the output of the Q terminal of the k-th D flip-flop circuit 18k.

The k-th D flip-flop circuit 18k inputs the clock signal CLK to its D-FF terminal, and inputs the output signal of the k-th XOR circuit 19k to its D terminal. The output of the Q terminal of the k-th D flip-flop circuit 18k becomes a kbit signal.

Next, the first and second down counters 15 and 16 will be explained. FIG. 6 shows an n-stage down counter.

In the first stage, the first off-side D flip-flop circuit 21a inputs the clock signal CLK to the D-FF terminal, and inputs the output of the /Q terminal of the first off-side D flip-flop circuit 21a to the D terminal. The output of the Q terminal of the first off-side D flip-flop circuit 21a is output as a 1-bit signal.

In the second stage, the second off-side XOR circuit 22b receives the output of the /Q terminal of the first off-side D flip-flop circuit 21a and the output of the /Q terminal of the second off-side D flip-flop circuit 21b.

The second off-side D flip-flop circuit 21b inputs the clock signal CLK to its D-FF terminal, and inputs the output of the second off-side XOR circuit 22b to its D terminal. The output of the Q terminal of the second off-side D flip-flop circuit 21b is output as a 2-bit signal.

In the third stage, the third off-side AND circuit 23c receives the output of the /Q terminal of the first off-side D flip-flop circuit 21a and the output of the /Q terminal of the second off-side D flip-flop circuit 21b.

The third off-side XOR circuit 22c receives the output of the third off-side AND circuit 23c and the output of the /Q terminal of the third off-side D flip-flop circuit 21c.

The third off-side D flip-flop circuit 21c inputs the clock signal CLK to its D-FF terminal, and inputs the output of the third off-side XOR circuit 22c to its D terminal. The output of the Q terminal of the third off-side D flip-flop circuit 21c is output as a 3-bit signal.

In this way, the down counter is composed of n stages. In the k-th stage (k: an integer from 4 to n), the k-th AND circuit 23k receives the /k-1 bit signal and the /(k-2) bit/(k-3) bit.../2 bit//1 bit signal. Ru.

The k-th XOR circuit 22k receives the output signal of the k-th AND circuit 23k and the output of the /Q terminal of the k-th D flip-flop circuit 21k.

The k-th D flip-flop circuit 21k inputs the clock signal CLK to its D-FF terminal, and inputs the output signal of the k-th XOR circuit 22k to its D terminal. The output of the Q terminal of the k-th D flip-flop circuit 26k becomes a kbit signal.

The up counter and down counter in FIGS. 5 and 6 have a configuration in which the count value is changed when a clock signal is input. In FIG. 5, bits are added each time it counts, and in FIG. The count value is decremented.

The pulse width can be determined by multiplying the binary output (1 bit to n bit) by the reading clock period. The number of counter stages can be increased depending on the pulse width to be measured.

By using the circuit configuration and control method as described above, it becomes possible to output a gate voltage with high resolution in response to a gate command.

Next, a case will be described in which the configuration of FIG. 7 is applied as the modulation circuit of the first embodiment. It includes a full-bridge circuit for generating an on-signal 24 that drives the first pulse transformer Tr1 that transmits an on-signal, and a full-bridge circuit for generating an off-signal 25 that drives a second pulse transformer Tr2 that transmits an off signal. There are characteristics.

A full bridge circuit 24 for generating an ON signal and a full bridge circuit 25 for generating an OFF signal are connected to the capacitor C in parallel. On-side first and second semiconductor elements S1on and S2on are connected in series between both ends of the capacitor C. Further, third and fourth on-side semiconductor elements S3on and S4on are connected in series between both ends of the capacitor C. The on-side first to fourth semiconductor elements S1on to S4on constitute a full bridge circuit 24 for generating an on signal.

A capacitor Ch1 and an on-side primary winding of the first pulse transformer Tr1 are connected between the connection point between the on-side first and second semiconductor elements S1on and S2on and the connection point between the on-side third and fourth semiconductor elements S3on and S4on. is connected.

Off-side first and second semiconductor elements S1off and S2off are connected in series between both ends of the capacitor C. Further, third and fourth off-side semiconductor elements S3off and S4off are connected in series between both ends of the capacitor C. The off-side first to fourth semiconductor elements S1off to S4off constitute a full bridge circuit 25 for generating an off signal.

A capacitor Ch2 and an off-side primary winding of the second pulse transformer Tr2 are connected between the connection point of the off-side first and second semiconductor elements S1off and S2off and the connection point of the off-side third and fourth semiconductor elements S3off and S4off. is connected.

The capacitors Ch1 and Ch2 are connected to cut the DC component and prevent magnetic saturation of the first and second pulse transformers Tr1 and Tr2, but may be omitted.

Generation of the second modulation signal vTr2 can be realized by controlling the off-signal generation full-bridge circuit 25 using the control section shown in FIG. An operation time chart is shown in FIG. The basic operation is the same as in FIGS. 3 and 4.

The off-pulse width measurement unit (up counter) 12 shown in FIG. 8 starts counting when it detects a falling edge of the synchronization circuit 9, stops counting when it detects a rising edge, and increases the count value every time a clock signal is input. Add. At this time, it is assumed that the rising edge and the falling edge are synchronized with the clock by the function of the synchronization circuit 9.

This makes it possible to measure the off-pulse width. Then, the off-side 1-bit shift circuit 13 reduces the count value to 1/2.

The off-side latch circuit 14 latches the output of the off-side 1-bit shift circuit 13 at the timing when a rising edge is detected.

By inputting the output of the off-side latch circuit 14 to the subsequent gate generation counters (first and second down counters) 15 and 16, and constructing a circuit to output gate commands until the count value reaches 0, It is possible to generate a modulation signal with a duty of 50% in which one cycle is the commanded pulse width.

As a specific operation, when generating an off signal, the gates of the off-side first and fourth semiconductor elements S1off and S4off are activated during the period when the first down counter 15 is counting (until the count value reaches 0). The command is set high, and the gate commands for the off-side second and third semiconductor elements S2off and S3off are set low.

During the period when the second down counter 16 is counting (until the count value reaches 0), the gate commands of the off-side second and third semiconductor elements S2off and S3off are set high, and the off-side first and fourth semiconductor elements S1off are set to high. , S4off gate command is set to low.

This makes it possible to suppress the frequency of the second modulation signal vTr2 to twice the switching frequency of the driving target, and it is possible to improve the time resolution of the pulse width of the gate command without increasing the drive frequency of the second pulse transformer Tr2. Therefore, the resolution can be improved while reducing the loss of the full-bridge circuit.

Next, a method of generating the first modulation signal vTr1 will be explained. FIG. 10 shows operating waveforms of the DC/AC modulation circuit in the first embodiment. In FIG. 2, the positive pulse and the negative pulse of the first modulation signal vTr1 are output once each for one cycle of the ON command, but in the present embodiment, the positive pulse and the negative pulse of the first modulation signal vTr1 are output once each. Divide the output into two ON commands. That is, the ON command width is the same as the period of one positive pulse of the first modulation signal vTr1, the ON command width and the period of one negative pulse of the first modulation signal vTr1 are the same, and each time the ON command is given, the positive pulse is and negative pulses are output alternately. Thereby, the limitation of the first modulation signal vTr1, which is limited by the minimum on-pulse width, can be minimized.

FIG. 11 shows an example of gate command generation for the DC/AC modulation circuit in the first embodiment. FIG. 12 shows signals of each part in FIG. 11. A latch circuit is used to generate an enable signal in response to a gate command, and a signal to the drive IC is generated by performing a logical product with the original command.

In FIG. 11, the rising edge detection circuit 26 detects the rising edge of the gate command. The latch circuit 27 latches at the timing when a rising edge is detected, and releases the latch at the timing when a new rising edge is detected in the latched state.

The AND circuit 28 outputs the logical product of the gate command and the output of the latch circuit 27. NOT circuit 29 inverts the output of latch circuit 27. The AND circuit 30 outputs the logical product of the gate command and the output of the NOT circuit 29.

The drive IC 31 outputs a gate command for the DC/AC modulation circuit based on the outputs of the AND circuits 28 and 30.

This DC/AC modulation circuit is the modulation signal generation circuit 17 in FIG. 3 or the modulation circuit (on signal generation full bridge circuit 24) in FIG. A modulated signal vTr1 is output.

In the first embodiment, for example, if the minimum pulse width is 100 ns, the modulation circuit can output a pulse of 100 ns or more. Therefore, the semiconductor element can perform a switching operation closer to the gate command, and the accuracy of the output voltage of the inverter can be improved.

Additionally, if the frequency or duty of the gate command changes in a ramp-like manner, the excitation current will be biased toward either the positive or negative side, but this can be countered by inserting capacitances ch1 and ch2 in series on the primary side of the first pulse transformer Tr1. will be taken. However, while capacitances ch1 and ch2 can cut the DC component to the pulse transformer, if DC is applied over a long period of time, the capacitance itself will be charged, so it is effective only when the excitation component is biased in the short term. It is.

As described above, according to the first embodiment, the frequencies of the first and second modulation signals vTr1 and vTr2 can be made variable according to the gate signal. This reduces the switching loss of the modulation signal generation circuit (DC/AC conversion circuit) that drives the first and second pulse transformers Tr1 and Tr2 while suppressing the magnetic saturation of the first and second pulse transformers Tr1 and Tr2. Can be suppressed to a minimum. Furthermore, since the time resolution of the pulse width of the gate command is not reduced, the command pulse can be reproduced and output with higher accuracy.

Furthermore, the limitation of the first modulation signal vTr1, which is limited by the minimum on-pulse width, can be minimized.

[Embodiment 2]
In Fig. 2, in order to counter magnetic bias, the positive pulse and negative pulse of the first modulation signal vTr1 are output once each within the pulse width (on command) of the X gate command, and the period of the positive pulse and negative pulse is The gate command is kept the same within one cycle of the ON command. Therefore, biased magnetism can be eliminated within one cycle of the ON command of the X gate command, but a short gate pulse width cannot be output because one positive and one negative pulse is output.

On the other hand, in the method shown in FIG. 12, the output of one positive pulse and one negative pulse of the first modulation signal vTr1 is divided into two outputs of the pulse width (ON command) of the X gate command. Therefore, it is advantageous if the pulse width of the X-gate command is short, but if the pulse width of the X-gate command becomes long, the application time of the voltage on the primary side of the transformer becomes longer, and damage due to magnetic saturation is more likely to occur.

The output waveforms and characteristics of the modulation circuits in FIGS. 2 and 12 are summarized in FIG. 13. In addition to these characteristics, when the output period Ton (see FIG. 2) of the first modulation signal Vtr1 becomes long, an unintended voltage is applied to the secondary side due to the back electromotive force of the first pulse transformer Tr1, resulting in a pulse of the gate voltage Vgs. There are also problems such as a decrease in width accuracy and an increase in the size of the pulse transformer in order to improve the saturation magnetic flux density and take measures against heat generation.

In order to solve these two problems, it is necessary to set a limit on the length of the output period Ton of the first modulation signal Vtr1. For example, when a DC/AC modulation circuit is used as the modulation circuit 2, biased magnetization (deviation of voltage time integral to one polarity above a certain level) is not affected by the pulse width of the X gate command. Control is required to operate the pulse transformer during the short output period Ton of the first modulation signal Vtr1 while preventing magnetic saturation of the pulse transformer caused by the pulse transformer.

In the second embodiment, in order to solve the above problems, a method that achieves both the advantages of FIGS. 2 and 12 will be described.

In the second embodiment, in order to achieve both the advantages of FIGS. 2 and 12, the polarity of the first modulation signal vTr1 is inverted according to the pulse width of the X gate command. By inverting the output polarity of the DC/AC modulation circuit under the following two conditions, it is possible to prevent biased magnetization of the pulse transformer without placing any limit on the pulse width of the X gate command.
(1) Every cycle of the gate command (every cycle of the X gate command in FIG. 2).
(2) When the output period Ton has passed a predetermined time.

That is, in the modulation circuit 2 of the second embodiment, the first modulation signal vTr1 outputs a positive pulse or a negative pulse during the ON command period of the X gate command, and the first modulation signal vTr1 outputs a positive pulse or a negative pulse for each period of the X gate command. The polarity at the start of output is inverted, and when the output period Ton of the first modulation signal vTr1 has elapsed for a predetermined time, the polarity of the first modulation signal vTr1 is inverted.

FIG. 14 shows a control block diagram of the second embodiment. The block diagram in FIG. 14 shows a reversal permission signal generating section 32 that generates a reversal permission signal for manipulating the output polarity under the conditions (1) and (2) above, and a reversal permission signal generating section 32 that generates an X gate command based on a given periodic command. It has a gate signal generation section 33 and a polarity selector section 34.

The X gate command is the same as that shown in FIG. 2, and is a command signal to the modulation circuit 2. The period command Tinv is a constant determined in advance by the designer. The output period Ton of the modulation circuit 2 (first modulation signal vTr1) is Tinv/2. The period command Tinv is set as a length that does not cause magnetic saturation of the pulse transformer even when DC is applied.

As shown in FIG. 14, the inversion permission signal generation unit 32 counts the period command Tinv while the X gate command is "1" in the period counter 35, and clears it when the X gate command becomes "0". The negative edge detection unit 36 detects the falling edge of the period counter 35. The negative edge detection unit 37 detects the falling edge of the X gate command.

The output of the negative edge detection section 36 is input to the C terminal of the multiplexer 38. The buffer 39 outputs the value of the output of the multiplexer 38 one calculation time ago. NOT circuit 40 inverts the output of buffer 39. The output of the buffer 39 is input to the 0 terminal of the multiplexer 38, and the output of the NOT circuit 40 is input to the 1 terminal.

The output of the negative edge detection section 37 is input to the C terminal of the multiplexer 41. The buffer 42 outputs the value of the output of the multiplexer 41 one calculation time ago. The output of the buffer 42 is input to the 0 terminal of the multiplexer 41, and the output of the multiplexer 38 is input to the 1 terminal. The output of the multiplexer 41 becomes the inversion permission signal EN_POL. That is, the inversion permission signal generation unit 32 generates an inversion permission signal EN_POL that switches between "1" and "0" at the falling edge of the X gate command.

The gate signal generation unit 33 uses a divider 43 to halve the cycle command Tinv. The comparator 44 compares the output of the divider 43 and the output of the period counter 35, and if the output of the divider 43 is larger, it outputs "1", and if it is smaller, it outputs "0". The comparator 45 compares the output of the period counter 35 and the output of the divider 43, and outputs "1" if the output of the period counter 35 is larger, and outputs "0" if it is smaller.

The AND circuit 46 inputs the output of the comparator 44 and the X gate command, and outputs "1" when both are "1", and otherwise outputs "0" as the gate signal GATE1. The AND circuit 47 inputs the output of the comparator 45 and the X gate command, and outputs "1" when both are "1", and otherwise outputs "0" as the gate signal GATE2.

That is, the gate signal generation unit 33 becomes "1" when the X gate command is on and until a predetermined time (1/2 of the periodic command Tinv) after the X gate command outputs "on", and otherwise "1". Gate signal GATE1 becomes "0", the X gate command is on, and becomes "1" after a predetermined time (1/2 of the periodic command Tinv) has elapsed since the X gate command was outputted, and at other times. A gate signal GATE2 that becomes "0" is generated.

The polarity selector section 34 includes a multiplexer 48 and a multiplexer 49. The inversion permission signal EN_POL is input to the C terminal of the multiplexer 48, the gate signal GATE1 is input to the 0 terminal, and the gate signal GATE2 is input to the 1 terminal. The inversion permission signal EN_POL is input to the C terminal of the multiplexer 49, the gate signal GATE2 is input to the 0 terminal, and the gate signal GATE1 is input to the 1 terminal. The output of multiplexer 48 becomes positive output gate signal GATE_P, and the output of multiplexer 49 becomes negative output gate signal GATE_N.

That is, when the inversion permission signal is "0", the polarity selector section 34 sets the positive output gate signal GATE_P to "1" when the gate signal GATE1 is "1", and sets the negative output gate signal GATE_P to "1" when the gate signal GATE2 is "1". The signal GATE_N is set to "1"; otherwise, the positive output gate signal GATE_P and the negative output gate signal GATE_N are set to "0". When the inversion permission signal is "1", the negative output gate signal GATE_N is "1" when the gate signal GATE1 is "1", the positive output gate signal GATE_P is "1" when the gate signal GATE2 is "1", and so on. In other cases, the positive output gate signal GATE_P and the negative output gate signal GATE_N are set to "0".

The drive IC 50 outputs a gate command for the DC/AC modulation circuit based on the positive output gate signal GATE_P and the negative output gate signal GATE_N.

Here, the multiplexers 38, 41, 48, and 49 are configured as follows. The NOT circuit 51 inverts the signal input to the C terminal. The AND circuit 52 inputs the output signal of the NOT circuit 51 and the signal input to the 0 terminal, and outputs "1" when both are "1", and outputs "0" otherwise. The AND circuit 53 inputs the signal input to the C terminal and the signal input to the 1 terminal, and outputs "1" when both are "1", and outputs "0" otherwise. The OR circuit 54 inputs the output signal of the AND circuit 52 and the output signal of the AND circuit 53, and outputs "1" when at least one of them is "1", and outputs "0" when both are "0". . The output of the OR circuit 54 becomes the output signal of the multiplexer.

FIG. 15 shows signals of each part of the control circuit in the second embodiment. The inversion permission signal generation section 32 and the polarity selector section 34 are control blocks for satisfying polarity inversion condition (1).

The inversion permission signal EN_POL is switched when the period counter 35 is cleared (at the time of falling), and updating of the inversion permission signal EN_POL is permitted only at the falling edge of the gate command. This inversion permission signal EN_POL is used to invert the positive and negative outputs of the polarity selector section 34.

On the other hand, the gate signal generation section 33 is a control block for satisfying the polarity reversal condition (2). A signal corresponding to the output period Ton is generated by comparing half of the cycle command Tinv and the output of the cycle counter 35, and gate signals GATE1 and GATE2 are generated by ANDing with the X gate command.

The polarity selector unit 34 determines a positive output gate signal GATE_P and a negative output gate signal GATE_N of the DC/AC modulation circuit based on the gate signals GATE1 and GATE2 and the inversion permission signal EN_POL.

When the pulse width of the gate command is long, as shown in Figure 2, the positive and negative pulses of the first modulation signal vTr1 are output alternately in the on-pulse width of the X gate command, and when the pulse width of the X gate command is short, as shown in Figure 12. Positive control of the first modulation signal can be achieved in two cycles. As a result, it is possible to achieve both the advantages of FIGS. 2 and 12, and to expand the setting range of the pulse width and downsize the pulse transformer without depending on the length of the pulse width of the gate command.

Biased magnetism is a phenomenon in which the time integral of voltage is biased as shown in equation (1) below. Only the deviation equivalent to one cycle command Tinv is within the permissible range, and the problem arises because it is integrated. In the second embodiment, if the pulse width of the X gate command is an even number of Tinv/4, then within that cycle, and if an odd number of Tinv/4 is repeated in an even number of cycles, then within that range, an odd number of Tinv/4. Even if the cycle becomes an odd number, it can be handled when the cycle becomes an odd number again.

Examples in which the on-pulse width of the X gate command is 3 divisions, 3 divisions, and 4 divisions will be described with reference to FIG. 16. Here, one scale = Tinv/4.

When the first X gate command is on, the output of the period counter 35 is smaller than 1/2 of the period command Tinv until the second scale, so the first modulation signal vTr1 outputs a positive pulse, and after the second scale, the output of the period counter 35 Since the output becomes larger than 1/2 of the period command Tinv, the first modulation signal vTr1 inverts the polarity and outputs a negative pulse.

When the second X gate command is on, the output of the period counter 35 is smaller than 1/2 of the period command Tinv up to the second scale. Here, since the polarity at the time of output start changes every cycle of the X gate command, the first modulation signal vTr1 outputs a negative pulse. After the second scale, the output of the period counter 35 becomes larger than 1/2 of the period command Tinv, so the first modulation signal vTr1 inverts the polarity and outputs a positive pulse. The third time when the X gate command is on is the same as in FIG. 15.

In this way, even if the pulse width of the X gate command is not an even number of 1/4 of the period command Tinv, the bias in the magnetic flux can be canceled in two periods. Moreover, even if the period is not an even number period but an odd number period, the bias of the magnetic flux can be canceled again in the case of the odd number period. Even if there is no odd cycle again, there is no problem as long as the magnetic flux bias is not integrated.

The reason for preventing biased magnetization is damage caused by heat generation and magnetic saturation, so if the average value of the excitation current becomes 0 over a long period of one cycle or more, there is no problem (or if the current is periodically excessive). There is no problem if it does not increase).

As described above, according to the second embodiment, in a high-voltage, high-frequency pulse power supply that has a driver that drives a pulse transformer with a DC/AC modulation circuit, it can handle short gate pulse widths while preventing biased magnetization of the pulse transformer. It is possible to achieve highly accurate gate pulse width.

Although only the specific examples described in the present invention have been described in detail above, it is obvious to those skilled in the art that various modifications and modifications can be made within the scope of the technical idea of the present invention. Naturally, such variations and modifications fall within the scope of the claims.

For example, the semiconductor element 8 to be driven in Embodiments 1 and 2 is used in a power conversion device (converter, inverter, etc.).

Furthermore, the method of controlling the first modulation signal vTr1 of the first and second embodiments is also applicable to the second modulation signal vTr2. The present invention may be applied to either one or both of Embodiment 1 and Embodiment 2.

When applying the control method of the first embodiment to the second modulation signal vTr2, the off command width and the period of one positive pulse of the second modulation signal vTr2 are made the same, and the period of the off command width and one positive pulse of the second modulation signal vTr2 is The period of the negative pulse is made the same, and a positive pulse and a negative pulse of the second modulation signal vTr2 are alternately output every time an off command is issued.

When applying the control method of the second embodiment to the second modulation signal vTr2, the second modulation signal outputs a positive pulse or a negative pulse during the period of the OFF command of the gate command, and the second modulation signal is output for each cycle of the gate command. The polarity of the signal vTr2 at the start of output is inverted, and when the output period of the second modulation signal vTr2 has elapsed for a predetermined time, the polarity of the second modulation signal vTr2 is inverted.

2, 3... Modulation circuit 4... On-side rectifier circuit 5... Off-side rectifier circuit 6... Demodulation circuit 7... Gate circuit 8... Semiconductor element to be driven db1 to db4... First to fourth diode circuits 9... Synchronous circuit 10... Rising edge detection circuit 11...Falling edge detection circuit 12...Off pulse width measuring section (up counter)
13... Off-side 1-bit shift circuit 14... Off-side latch circuit 15, 16... Modulation signal generation counter (first, second down counter)
17... Modulation signal generation circuit 18, 21... D flip-flop circuit 19, 22... XOR circuit 20, 23, 28, 30, 46, 47, 52, 53... AND circuit 24... Full bridge circuit for generating on signal 25... Off Full bridge circuit for signal generation 26... Rising edge detection circuit 27... Falling edge detection circuit 29, 40, 51... NOT circuit 31, 50... Drive IC
32... Inversion permission signal 33... Gate signal generation section 34... Polarity selector section 35... Period counter 36, 37... Negative edge detection section 38, 41, 48, 49... Multiplexer 39, 42... Buffer 43... Divider 44, 45... Comparator 54...OR circuit

Claims (16)

a modulation circuit that outputs a first modulation signal and a second modulation signal based on an on command and an off command of the gate command;
A primary winding having an on-side primary winding to which the first modulation signal is applied, an on-side secondary winding that transforms and outputs the voltage applied to the on-side primary winding, and an on-side tertiary winding. an on-side rectifier circuit comprising a 1-pulse transformer, a first diode circuit that rectifies the output of the on-side secondary winding, and a second diode circuit that rectifies the output of the on-side tertiary winding;
A secondary winding having an off-side primary winding to which the second modulation signal is applied, an off-side secondary winding that transforms and outputs the voltage applied to the off-side primary winding, and an off-side tertiary winding. an off-side rectifier circuit comprising a 2-pulse transformer, a third diode circuit that rectifies the output of the off-side secondary winding, and a fourth diode circuit that rectifies the output of the off-side tertiary winding;
A gate drive circuit that controls a semiconductor element to be driven according to the outputs of the first to fourth diode circuits,
The modulation circuit is
The frequencies of the first modulation signal and the second modulation signal are made variable according to the ON command width and OFF command width of the gate command, and the ON command width and the period of one positive pulse of the first modulation signal are the same. and the ON command width and the period of one negative pulse of the first modulation signal are the same, and the positive pulse and the negative pulse of the first modulation signal are alternately output each time the ON command is issued. Characteristic gate drive circuit. a modulation circuit that outputs a first modulation signal and a second modulation signal based on an on command and an off command of the gate command;
A primary winding having an on-side primary winding to which the first modulation signal is applied, an on-side secondary winding that transforms and outputs the voltage applied to the on-side primary winding, and an on-side tertiary winding. an on-side rectifier circuit comprising a 1-pulse transformer, a first diode circuit that rectifies the output of the on-side secondary winding, and a second diode circuit that rectifies the output of the on-side tertiary winding;
A secondary winding having an off-side primary winding to which the second modulation signal is applied, an off-side secondary winding that transforms and outputs the voltage applied to the off-side primary winding, and an off-side tertiary winding. an off-side rectifier circuit comprising a 2-pulse transformer, a third diode circuit that rectifies the output of the off-side secondary winding, and a fourth diode circuit that rectifies the output of the off-side tertiary winding;
A gate drive circuit that controls a semiconductor element to be driven according to the outputs of the first to fourth diode circuits,
The modulation circuit is
The frequencies of the first modulation signal and the second modulation signal are made variable according to the ON command width and OFF command width of the gate command, and the period of one positive pulse of the OFF command width and the second modulation signal are the same. and the off command width and the period of one negative pulse of the second modulation signal are the same, and the positive pulse and the negative pulse of the second modulation signal are alternately output each time the off command is issued. Characteristic gate drive circuit. The modulation circuit is
a rising edge detection circuit that detects a rising edge of the gate command;
a latch circuit that latches at a timing when a rising edge of the gate command is detected, and releases the latch at the timing when a rising edge of the gate command is further detected in the latched state;
a first AND circuit that outputs a logical product of the gate command and the output of the latch circuit;
a NOT circuit that inverts the output of the latch circuit;
a second AND circuit that outputs a logical product of the gate command and the output of the NOT circuit;
a drive IC that controls a DC/AC modulation circuit based on the output of the first AND circuit and the output of the second AND circuit;
the DC/AC modulation circuit that outputs the first modulation signal based on control of the drive IC;
2. The gate drive circuit according to claim 1, further comprising: a modulation circuit that outputs a first modulation signal and a second modulation signal based on an on command and an off command of the gate command;
A primary winding having an on-side primary winding to which the first modulation signal is applied, an on-side secondary winding that transforms and outputs the voltage applied to the on-side primary winding, and an on-side tertiary winding. an on-side rectifier circuit comprising a 1-pulse transformer, a first diode circuit that rectifies the output of the on-side secondary winding, and a second diode circuit that rectifies the output of the on-side tertiary winding;
A secondary winding having an off-side primary winding to which the second modulation signal is applied, an off-side secondary winding that transforms and outputs the voltage applied to the off-side primary winding, and an off-side tertiary winding. an off-side rectifier circuit comprising a 2-pulse transformer, a third diode circuit that rectifies the output of the off-side secondary winding, and a fourth diode circuit that rectifies the output of the off-side tertiary winding;
A gate drive circuit that controls a semiconductor element to be driven according to the outputs of the first to fourth diode circuits,
The modulation circuit is
The frequencies of the first modulation signal and the second modulation signal are made variable according to the ON command width and OFF command width of the gate command, and during the ON command period of the gate command, the first modulation signal is a positive pulse or a negative pulse. outputting a pulse, reversing the polarity at the start of output of the first modulation signal every cycle of the gate command, and changing the polarity of the first modulation signal when the output period of the first modulation signal has elapsed for a predetermined time; A gate drive circuit characterized by inversion. a modulation circuit that outputs a first modulation signal and a second modulation signal based on an on command and an off command of the gate command;
A primary winding having an on-side primary winding to which the first modulation signal is applied, an on-side secondary winding that transforms and outputs the voltage applied to the on-side primary winding, and an on-side tertiary winding. an on-side rectifier circuit comprising a 1-pulse transformer, a first diode circuit that rectifies the output of the on-side secondary winding, and a second diode circuit that rectifies the output of the on-side tertiary winding;
A secondary winding having an off-side primary winding to which the second modulation signal is applied, an off-side secondary winding that transforms and outputs the voltage applied to the off-side primary winding, and an off-side tertiary winding. an off-side rectifier circuit comprising a 2-pulse transformer, a third diode circuit that rectifies the output of the off-side secondary winding, and a fourth diode circuit that rectifies the output of the off-side tertiary winding;
A gate drive circuit that controls a semiconductor element to be driven according to the outputs of the first to fourth diode circuits,
The modulation circuit is
The frequencies of the first modulation signal and the second modulation signal are made variable according to the ON command width and OFF command width of the gate command, and during the period of the OFF command of the gate command, the second modulation signal is a positive pulse or a negative pulse. outputting a pulse, inverting the polarity at the start of output of the second modulation signal every cycle of the gate command, and changing the polarity of the second modulation signal when the output period of the second modulation signal has elapsed for a predetermined time; A gate drive circuit characterized by inversion. an inversion permission signal generation unit that generates an inversion permission signal that switches between “1” and “0” at a falling edge of the gate command;
a gate signal GATE1 that outputs "1" until a predetermined time after the gate command is on and outputs "on" and becomes "0" at other times; , a gate signal generating unit that generates a gate signal GATE2 that outputs "1" after a predetermined time has elapsed since the gate command outputs ON, and becomes "0" at other times;
When the inversion permission signal is "0", the positive output gate signal GATE_P is set to "1" when the gate signal GATE1 is "1", and the negative output gate signal GATE_N is set to "1" when the gate signal GATE2 is "1". ”, otherwise, the positive output gate signal GATE_P and the negative output gate signal GATE_N are set to “0”, and when the inversion permission signal is “1”, when the gate signal GATE1 is “1”, the negative output gate signal GATE_P and the negative output gate signal GATE_N are set to “0”. The output gate signal GATE_N is "1", and when the gate signal GATE2 is "1", the positive output gate signal GATE_P is "1"; otherwise, the positive output gate signal GATE_P and the negative output gate signal GATE_N are "1". a polarity selector section that sets the polarity to "0";
a drive IC that controls a DC/AC modulation circuit based on the positive output gate signal GATE_P and the negative output gate signal GATE_N;
the DC/AC modulation circuit that outputs the first modulation signal based on control of the drive IC;
5. The gate drive circuit according to claim 4, further comprising: The DC/AC modulation circuit is a modulation signal generation circuit,
The modulation circuit is
a synchronization circuit that synchronizes the gate command with a clock signal;
a rising edge detection section that detects a rising edge of the output of the synchronous circuit;
a falling edge detection section that detects a falling edge of the output of the synchronous circuit;
Off-pulse width measurement that starts counting when a falling edge of the output of the synchronous circuit is detected, stops counting when a rising edge of the output of the synchronous circuit is detected, and adds the count value every time the clock signal is input. Department and
an off-side 1-bit shift circuit that halves the output of the off-pulse width measuring section;
an off-side latch circuit that latches the output of the off-side 1-bit shift circuit at the timing of a rising edge of the output of the synchronous circuit;
a first down counter that receives the output of the off-side latch circuit and the clock signal, and subtracts a count value each time the clock signal is input;
a second down counter that receives the output of the off-side latch circuit, the output of the first down counter, and the clock signal, and subtracts a count value each time the clock signal is input;
Equipped with
7. The gate drive circuit according to claim 3, wherein the modulation signal generation circuit outputs the second modulation signal until the counters of the first and second down counters reach zero. The DC/AC modulation circuit is
capacitor and
A full bridge for generating an on signal, comprising first and second on-side semiconductor elements connected in series between both ends of the capacitor, and third and fourth on-side semiconductor elements connected in series between both ends of the capacitor. circuit and
A full bridge for off-signal generation, comprising first and second off-side semiconductor elements connected in series between both ends of the capacitor, and third and fourth off-side semiconductor elements connected in series between both ends of the capacitor. circuit and
The on-side primary winding of the first pulse transformer is connected between the connection point of the on-side first and second semiconductor elements and the connection point of the on-side third and fourth semiconductor elements. , the off-side primary winding of the second pulse transformer is connected between the connection point of the off-side first and second semiconductor elements and the connection point of the off-side third and fourth semiconductor elements; The gate drive circuit according to claim 3 or 6, characterized in that: The modulation circuit is
a synchronization circuit that synchronizes the gate command with a clock signal;
a rising edge detection section that detects a rising edge of the output of the synchronous circuit;
a falling edge detection section that detects a falling edge of the output of the synchronous circuit;
Off-pulse width measurement that starts counting when a falling edge of the output of the synchronous circuit is detected, stops counting when a rising edge of the output of the synchronous circuit is detected, and adds the count value every time the clock signal is input. Department and
an off-side 1-bit shift circuit that halves the output of the off-pulse width measuring section;
an off-side latch circuit that latches the output of the off-side 1-bit shift circuit at the timing of a rising edge of the output of the synchronous circuit;
The output of the off-side latch circuit and the clock signal are input, and each time the clock signal is input, a count value is subtracted, and gate commands are given to the off-side first and fourth semiconductor elements until the count value becomes 0. a first down counter that outputs
The output of the off-side latch circuit, the output of the first down counter, and the clock signal are input, and each time the clock signal is input, a count value is subtracted, and the second down counter is subtracted until the count value becomes 0. , a second down counter that outputs a gate command for the third semiconductor element;
9. The gate drive circuit according to claim 8, further comprising: The off-pulse width measuring section has an n (n: an integer of 1 or more) stage configuration,
In the first row,
The first on-side D flip-flop inputs the clock signal to the D-FF terminal, inputs the output of the /Q terminal of the first on-side D flip-flop circuit to the D terminal, and outputs the Q terminal as a 1-bit signal. has a circuit,
In the second row,
a second on-side XOR circuit inputting the output of the Q terminal of the first on-side D flip-flop circuit and the output of the Q terminal of the second on-side D flip-flop circuit;
The second on-side D flip-flop circuit inputs the clock signal to a D-FF terminal, inputs the output of the second on-side XOR circuit to a D terminal, and outputs a 2-bit signal from a Q terminal. death,
In the third row,
a third on-side AND circuit inputting the output of the Q terminal of the first on-side D flip-flop circuit and the output of the Q terminal of the second on-side D flip-flop circuit;
a third on-side XOR circuit inputting the output of the third on-side AND circuit and the output of the Q terminal of the third on-side D flip-flop circuit;
The third on-side D flip-flop circuit inputs the clock signal to the D-FF terminal, inputs the output of the third on-side XOR circuit to the D terminal, and outputs the Q terminal as a 3-bit signal. death,
From the 4th stage to the nth stage,
a k-th on-side AND circuit that inputs a k (k: an integer from 4 to n)-1 bit signal and a (k-2) bit/(k-3) bit...2 bit/1 bit signal;
a k-th on-side XOR circuit inputting the output of the k-th on-side AND circuit and the output of the Q terminal of the k-th on-side D flip-flop circuit;
The k-th on-side D flip-flop circuit inputs the clock signal to a D-FF terminal, inputs the output of the k-th on-side XOR circuit to the D terminal, and outputs a k-bit signal from the Q terminal;
8. The gate drive circuit according to claim 7, further comprising: The first and second down counters have n stages (n: an integer of 1 or more),
In the first row,
The first off-side D flip-flop inputs the clock signal to the D-FF terminal, inputs the output of the /Q terminal of the first off-side D flip-flop circuit to the D terminal, and outputs the Q terminal as a 1-bit signal. has a circuit,
In the second row,
a second off-side XOR circuit inputting the output of the /Q terminal of the first off-side D flip-flop circuit and the output of the /Q terminal of the second off-side D flip-flop circuit;
The second off-side D flip-flop circuit has a D-FF terminal inputted with the clock signal, a D terminal inputted with the output of the second off-side XOR circuit, and a Q terminal outputted as a 2-bit signal. death,
In the third row,
a third off-side AND circuit inputting the output of the /Q terminal of the first off-side D flip-flop circuit and the output of the /Q terminal of the second off-side D flip-flop circuit;
a third off-side XOR circuit inputting the output of the third off-side AND circuit and the output of the /Q terminal of the third off-side D flip-flop circuit;
The third off-side D flip-flop circuit inputs the clock signal to a D-FF terminal, inputs the output of the third off-side XOR circuit to a D terminal, and outputs a 3-bit signal from a Q terminal. death,
From the 4th stage to the nth stage,
a k-th off-side AND circuit inputting a /k (k: an integer from 4 to n)-1 bit signal and a /(k-2) bit/(k-3) bit.../2 bit/1 bit signal;
a k-th off-side XOR circuit inputting the output of the k-th off-side AND circuit and the output of the /Q terminal of the k-th off-side D flip-flop circuit;
the k-th off-side D flip-flop circuit that inputs the clock signal to a D-FF terminal, inputs the output of the k-th off-side XOR circuit to the D terminal, and outputs a k-bit signal from the Q terminal;
8. The gate drive circuit according to claim 7, further comprising: A power conversion device comprising the semiconductor element to be driven according to any one of claims 1 to 2 and 4 to 5. a modulation circuit that outputs a first modulation signal and a second modulation signal based on an on command and an off command of the gate command;
A primary winding having an on-side primary winding to which the first modulation signal is applied, an on-side secondary winding that transforms and outputs the voltage applied to the on-side primary winding, and an on-side tertiary winding. an on-side rectifier circuit comprising a 1-pulse transformer, a first diode circuit that rectifies the output of the on-side secondary winding, and a second diode circuit that rectifies the output of the on-side tertiary winding;
A secondary winding having an off-side primary winding to which the second modulation signal is applied, an off-side secondary winding that transforms and outputs the voltage applied to the off-side primary winding, and an off-side tertiary winding. an off-side rectifier circuit comprising a 2-pulse transformer, a third diode circuit that rectifies the output of the off-side secondary winding, and a fourth diode circuit that rectifies the output of the off-side tertiary winding;
A gate drive circuit control method for controlling a semiconductor element to be driven according to the outputs of the first to fourth diode circuits, comprising:
The modulation circuit is configured to vary the frequencies of the first modulation signal and the second modulation signal according to the ON command width and OFF command width of the gate command, and to vary the frequencies of the first modulation signal and the second modulation signal depending on the ON command width and one of the first modulation signals. The periods of the positive pulses are the same, the ON command width and the period of one negative pulse of the first modulation signal are the same, and each time the ON command is issued, the positive pulse and the negative pulse of the first modulation signal are A control method for a gate drive circuit characterized by alternately outputting. a modulation circuit that outputs a first modulation signal and a second modulation signal based on an on command and an off command of the gate command;
A primary winding having an on-side primary winding to which the first modulation signal is applied, an on-side secondary winding that transforms and outputs the voltage applied to the on-side primary winding, and an on-side tertiary winding. an on-side rectifier circuit comprising a 1-pulse transformer, a first diode circuit that rectifies the output of the on-side secondary winding, and a second diode circuit that rectifies the output of the on-side tertiary winding;
A secondary winding having an off-side primary winding to which the second modulation signal is applied, an off-side secondary winding that transforms and outputs the voltage applied to the off-side primary winding, and an off-side tertiary winding. an off-side rectifier circuit comprising a 2-pulse transformer, a third diode circuit that rectifies the output of the off-side secondary winding, and a fourth diode circuit that rectifies the output of the off-side tertiary winding;
A gate drive circuit control method for controlling a semiconductor element to be driven according to the outputs of the first to fourth diode circuits, comprising:
The modulation circuit makes the frequencies of the first modulation signal and the second modulation signal variable in accordance with the ON command width and the OFF command width of the gate command, and the frequency of the OFF command width and one of the second modulation signals. The periods of the positive pulses are the same, the off command width and the period of one negative pulse of the second modulation signal are the same, and each time the off command is issued, the positive pulse and the negative pulse of the second modulation signal are A control method for a gate drive circuit characterized by alternately outputting. a modulation circuit that outputs a first modulation signal and a second modulation signal based on an on command and an off command of the gate command;
A primary winding having an on-side primary winding to which the first modulation signal is applied, an on-side secondary winding that transforms and outputs the voltage applied to the on-side primary winding, and an on-side tertiary winding. an on-side rectifier circuit comprising a 1-pulse transformer, a first diode circuit that rectifies the output of the on-side secondary winding, and a second diode circuit that rectifies the output of the on-side tertiary winding;
A secondary winding having an off-side primary winding to which the second modulation signal is applied, an off-side secondary winding that transforms and outputs the voltage applied to the off-side primary winding, and an off-side tertiary winding. an off-side rectifier circuit comprising a 2-pulse transformer, a third diode circuit that rectifies the output of the off-side secondary winding, and a fourth diode circuit that rectifies the output of the off-side tertiary winding;
A gate drive circuit control method for controlling a semiconductor element to be driven according to the outputs of the first to fourth diode circuits, comprising:
The modulation circuit makes the frequencies of the first modulation signal and the second modulation signal variable according to the ON command width and OFF command width of the gate command, and the frequency of the first modulation signal and the second modulation signal is varied according to the ON command width and OFF command width of the gate command, and the frequency of the first modulation signal is changed during the ON command period of the gate command. outputs a positive pulse or a negative pulse, inverts the polarity at the start of output of the first modulation signal every cycle of the gate command, and when the output period of the first modulation signal has elapsed for a predetermined time, the first modulation signal outputs a positive pulse or a negative pulse. A method for controlling a gate drive circuit, the method comprising inverting the polarity of a modulation signal. a modulation circuit that outputs a first modulation signal and a second modulation signal based on an on command and an off command of the gate command;
A primary winding having an on-side primary winding to which the first modulation signal is applied, an on-side secondary winding that transforms and outputs the voltage applied to the on-side primary winding, and an on-side tertiary winding. an on-side rectifier circuit comprising a 1-pulse transformer, a first diode circuit that rectifies the output of the on-side secondary winding, and a second diode circuit that rectifies the output of the on-side tertiary winding;
A secondary winding having an off-side primary winding to which the second modulation signal is applied, an off-side secondary winding that transforms and outputs the voltage applied to the off-side primary winding, and an off-side tertiary winding. an off-side rectifier circuit comprising a 2-pulse transformer, a third diode circuit that rectifies the output of the off-side secondary winding, and a fourth diode circuit that rectifies the output of the off-side tertiary winding;
A gate drive circuit control method for controlling a semiconductor element to be driven according to the outputs of the first to fourth diode circuits, comprising:
The modulation circuit makes the frequencies of the first modulation signal and the second modulation signal variable according to the ON command width and OFF command width of the gate command, and the frequency of the second modulation signal is varied during the OFF command period of the gate command. outputs a positive pulse or a negative pulse, inverts the polarity at the start of output of the second modulation signal every cycle of the gate command, and outputs the second modulation signal when the output period of the second modulation signal has elapsed for a predetermined time. A method for controlling a gate drive circuit, the method comprising inverting the polarity of a modulation signal.

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