JP7334472B2 - Semiconductor integrated circuit and imaging device - Google Patents

Description

The present invention relates to semiconductor integrated circuits, for example for imaging devices.

A CMOS linear image sensor used in an imaging device has a structure in which signals photoelectrically converted by photodiodes in pixels arranged linearly are amplified by an amplifier and extracted in time series. The extracted signal is subjected to processing such as amplification and analog/digital conversion in circuits arranged in columns, one for each one or more pixels.

In recent years, analog circuits such as image sensors are required to have higher performance and lower costs. A CMOS linear image sensor has a short side of up to several millimeters and a long side of about 10 to several tens of millimeters. As a result, the reduction in the short side direction is large, leading to cost reduction. As a method of configuring a circuit on a small scale and in a small area, a post-stage processing circuit such as an amplifying means is shared in the post-stage of a circuit that outputs a signal such as a pixel, and the circuit that outputs the signal is sequentially switched to form a time-series circuit. A signal processing technique has been considered and is already known (see, for example, Patent Document 1).

However, when the post-stage processing circuit is shared, the wiring area for connecting the pre-stage signal output circuit and the post-stage processing circuit is expanded, and the wiring load (for example, parasitic resistance and parasitic capacitance) increases. There was a problem that the circuit could not be operated at high speed, or that the circuit area increased in order to increase the driving capability.

Here, as a supplementary explanation, the pixels are formed in a small area of several micrometers to ten and several micrometers square, and the amplifiers for amplifying the output of the pixels are also formed in the immediate vicinity of the pixels, so they must be formed small. In other words, it is difficult to form an amplifier with a large driving capability in the vicinity of the pixel, and there is a problem that the amplifier that amplifies the output of the pixel is greatly affected by the parasitic resistance and parasitic capacitance of the output wiring.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems, and to reduce the area or power consumption of a semiconductor integrated circuit for an imaging device, for example, as compared with the prior art.

A semiconductor integrated circuit according to the present invention includes a circuit group including at least a plurality of signal output circuits, signal wiring, and an amplifier circuit,
the signal wiring is connected to each of the plurality of signal output circuits and the amplifier circuit;
The amplifier circuit comprises an input stage transistor,
the input stage transistor is formed in a first conductivity type well region or a second conductivity type well region separated by a semiconductor substrate;
the gate electrode of the transistor and the signal wiring are connected,
a source electrode of the transistor and a back gate electrode of the transistor are connected;
the source potential fluctuates following the gate potential applied to the gate electrode of the transistor;
The input stage transistor is of the second conductivity type over at least a predetermined length of the wiring length of the signal wiring wired between one end of each of the signal output circuits and the other end of each of the signal output circuits. arranged along the signal wiring so that the signal wiring passes over the well region;
It is characterized in that the ratio of the short side to the long side of the second conductivity type well region is at least a predetermined ratio or more.

According to the semiconductor integrated circuit of the present invention, for example, a semiconductor integrated circuit for an imaging device can be made smaller in area or consume less power and can operate at higher speeds than in the prior art.

2 is a plan view showing a configuration example of a semiconductor integrated circuit for the imaging device according to Embodiment 1; FIG. 1B is a circuit diagram showing a connection relationship of transistors 4 in the semiconductor integrated circuit of FIG. 1A; FIG. 1B is a longitudinal sectional view showing a structural example of a transistor 4 of FIG. 1A; FIG. 1B is a longitudinal sectional view showing another structural example of the transistor 4 of FIG. 1A; FIG. 1B is a vertical cross-sectional view showing parasitic capacitances C1 to C4 generated in signal wiring 2 in the structural example of transistor 4 of FIG. 1A; FIG. 1B is a vertical cross-sectional view showing a case where there is no element such as a transistor below the signal wiring 2 in the structural example of the transistor 4 of FIG. 1A. FIG. 3B is a top view of FIG. 3A; FIG. 1B is a plan view showing another arrangement example of the transistor 4 of FIG. 1A; FIG. FIG. 11 is a plan view showing a configuration example of a semiconductor integrated circuit for an imaging device according to Embodiment 2; 6 is a plan view showing an arrangement example of back gate electrodes of transistors in the semiconductor integrated circuit of FIG. 5; FIG. 6 is a plan view showing another arrangement example of back gate electrodes of transistors in the semiconductor integrated circuit of FIG. 5; FIG. 6 is a plan view showing a layout method for further reducing parasitic capacitance of signal wiring 2 in the semiconductor integrated circuit of FIG. 5; FIG. 6 is a plan view showing a configuration example in which signal wiring 2 is made of polysilicon in the semiconductor integrated circuit of FIG. 5; FIG.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments according to the present invention will be described with reference to the drawings. In addition, the same code|symbol is attached|subjected about the same or similar component.

Embodiment 1.
1A is a plan view showing a configuration example of a semiconductor integrated circuit for an imaging device according to Embodiment 1. FIG.

In FIG. 1A, the semiconductor integrated circuit comprises a plurality of n signal output circuits 1-1 to 1-n, a signal wiring 2, and an amplifier circuit 3 as one circuit group. The amplifier circuit 3 includes at least one transistor 4 , which is arranged along part of the signal line 2 . Here, the transistor 4 is a MOS transistor, for example, and has a gate electrode G, a drain electrode D, a source electrode S, and a back gate electrode B. FIG.

FIG. 1B is a circuit diagram showing the connection relationship of transistors 4 in the semiconductor integrated circuit of FIG. 1A.

In FIG. 1B, the signal wiring 2 is made of metal wiring, for example, and is connected to the gate electrode of the transistor 4 at a plurality of locations by means of contacts or the like. The source electrode S and the back gate electrode B of the transistor 4 are connected, and the well forming the back gate is electrically isolated from other wells of the same conductivity type. A source electrode S and a drain electrode D of the transistor 4 are connected to another circuit (including a voltage supply source) 5 that constitutes the amplifier circuit 3. For example, a power supply voltage source, a ground voltage source (GND), other An active element such as a transistor and a passive element such as a resistor or capacitor are connected, and a signal is output from the output terminal 6 of the other circuit 5 .

Due to the configuration of this embodiment, the W/L ratio (W is the width and L is the length in the longitudinal direction) of the transistor 4 is very large, so it is divided into a plurality of fingers and arranged. Further, since the transistor 4 is formed and the well region forming the back gate is also formed along the signal wiring 2, the aspect ratio between the short side and the long side is large. At least, the long sides have an aspect ratio of two digits or more with respect to the short sides. Here, it is preferable that the ratio of short side to long side is 1:10 or more.

When the amplifier circuit 3 is composed of, for example, a general source follower circuit, the drain electrode D is connected to a power supply voltage source or a ground voltage source (GND), and the source electrode S is connected to the drain of the transistor 4 forming a current source. The electrode D and the output terminal 6 are connected.

Here, in the amplifier circuit 3 including the source follower circuit, it is common practice to connect the source electrode S and the back gate electrode B of the input stage transistor 4 for use. When the source electrode S and the back gate electrode B are connected, the source potential and the back gate potential become equal, so that the influence of the back gate bias effect disappears and the gain can be improved. Also, the parasitic capacitance attached to the gate electrode G and the well of the input stage transistor 4 can be charged and discharged by the input stage transistor 4 or other transistors connected to the input stage transistor 4 . In general, the drivability of the post-stage circuit is set higher than that of the pre-stage circuit. Since the parasitic capacitance attached to the gate electrode G and the well of the transistor 4 can be treated as substantially small when viewed from the preceding circuit, the responsiveness and frequency characteristics can be improved.

FIG. 2A is a longitudinal sectional view showing a structural example of the transistor 4 of FIG. 1A. FIG. 2B is a longitudinal sectional view showing another structural example of the transistor 4 of FIG. 1A. In FIGS. 2A to 3B below, the insulating layer between each electrode and the semiconductor substrate is omitted.

For example, when the transistor 4 is an N-channel transistor, in FIG. A transistor 4 is formed in a biconductivity type (P type) well 102 . In FIG. 2B, a transistor 4 is formed in a well 102 of second conductivity type (P type) separated by a semiconductor substrate 101 of first conductivity type (N type). As previously mentioned, the second conductivity type well 102 is electrically isolated from other same conductivity type wells. If the transistor 4 is a P-channel transistor, the first conductivity type should be replaced with the P-type, and the second conductivity type with the N-type.

FIG. 3A is a longitudinal sectional view showing parasitic capacitances C1 to C4 generated in signal wiring 2 in the structural example of transistor 4 in FIG. 1A. FIG. 3B is a vertical cross-sectional view showing the structure example of the transistor 4 in FIG. 1A in which there is no element such as a transistor below the signal wiring 2. As shown in FIG. 4A is a top view of FIG. 3A, and FIG. 4B is a plan view showing another arrangement example of the transistor 4 of FIG. 1A.

3A to 4B, 2 and 201 to 203 are signal wirings, particularly 203 is an upper layer metal wiring, 4 is a transistor, and C1 to C4 are parasitic capacitances. Also, 101 is a first conductivity type well or semiconductor substrate, 102 is a second conductivity type well, and 103 is a second conductivity type semiconductor substrate. Furthermore, 201a to 203a are signal wirings or shield wirings, and C1a to C3a are parasitic capacitances.

3A and 3B are diagrams schematically showing parasitic capacitance attached to the signal wiring 2. FIG. Parasitic capacitances such as oblique capacitance and fringe capacitance are actually attached, but are omitted for simplicity. Note that FIG. 4A shows an example of a top view of FIG. 3A (however, the upper layer wiring 203 is excluded). A cross-sectional view of the A-A' plane of FIG. 4A corresponds to FIG. 3A.

For the transistor 4, for example, transistor elements obtained by dividing a transistor having a large W/L ratio are connected in parallel. The gate electrode G of the transistor 4 and the signal wiring 2 are connected by contacts at the boundaries of the plurality of divided transistor elements. In FIG. 4A, source diffusion and drain diffusion are separated for each divided transistor element. It is not limited to this.

Here, the signal wiring 2 has a parasitic capacitance between the semiconductor substrate and wells or between wirings. The parasitic capacitance attached to the signal wiring 2 is
(A) a parasitic capacitance C1 between the signal wiring 2 and the source node signal wiring 201;
(B) a parasitic capacitance C2 between the signal wiring 2 and the drain node signal wiring 202;
(C) a parasitic capacitance C3 between the signal wiring 2 and the gate electrode G of the transistor 4;
(D) Parasitic capacitance C4 between signal wiring 2 and upper metal wiring 203
exists. In addition to C1 to C4, the parasitic capacitance attached to the signal wiring 2 is attached to the gate capacitance of the transistor 4, the well, the source electrode S, the drain electrode D, etc., because the signal wiring 2 and the gate electrode G of the transistor 4 are connected. Parasitic capacitance is also included.

The signal wiring 2 and the gate electrode of the transistor 4 are connected by a contact, and even if the potential of the signal wiring 2 fluctuates, the gate electrode of the transistor 4 immediately becomes the same potential as the signal wiring 2, so the actual capacitance value of C3 is very small and equivalently negligible. Similarly, the source electrode and the back gate electrode of the transistor 4 are connected, and the source potential of the transistor 4 fluctuates following the gate potential. The actual visible capacitance of the parasitic capacitance C1 with the wiring 201 is very small. In other words, the parasitic capacitance visible on the signal line 2 is almost only C2 and C4.

FIG. 3B is a diagram schematically showing parasitic capacitance attached to the signal wiring 2 when there is no transistor element under the signal wiring 2. In FIG.

In FIG. 3B, signal wirings 201a and 202a are shield wirings inserted for the purpose of preventing coupling between other signal wirings and signal wirings. The parasitic capacitance attached to the signal wiring 2 is
(A) Parasitic capacitance C1a between signal wiring 2 and signal wiring 201a,
(B) a parasitic capacitance C2a between the signal wiring 2 and the signal wiring 202a;
(C) a parasitic capacitance C3a between the signal wiring 2 and the well;
(D) Parasitic capacitance C4a between signal wiring 2 and upper metal wiring 203
exists. Here, in FIGS. 3A and 3B, if the distance between the signal wiring 2 and the adjacent signal wiring is equal, the parasitic capacitances are also equal, so C1=C1a, C2=C2a, and C4=C4a. Further, since the distance between the semiconductor substrate 103 and the signal wiring 2 is configured to be gate electrode<well, C3>C3a, but as described above, the parasitic capacitances C1 and C3 can be equivalently regarded as zero. Therefore, the configuration in FIG. 3A can reduce the capacitance by (C1a+C3a) as compared to FIG. 3B.

In the layout of an actual semiconductor integrated circuit, FIG. 3A requires that the signal wirings 201 and 202 be connected to the source electrode S and the drain electrode D, so layout restrictions such as wiring width and wiring spacing are imposed. On the other hand, although the configuration of FIG. 3B affects the chip size, there are almost no layout restrictions on the signal wiring width and signal wiring spacing. For example, it is possible to eliminate the signal wirings 201a and 202a or to increase the distance. In FIG. 3B, when the adjacent signal lines 201a and 202a of the signal line 2 are removed and the parasitic capacitances C1a and C2a are assumed to be zero, C2 If the signal wiring 2 and the signal wiring 202 in FIG. 3A are laid out so as to satisfy <C3a+α (fringe capacitance), the parasitic capacitance attached to the signal wiring 2 is superior in FIG. 3A.

In FIG. 3A, a higher effect can be obtained by laying out the parasitic capacitances C2 and C4 to be smaller. For example, the upper metal wiring 203 is not routed over the entire surface, the signal wiring 2 is moved closer to the signal wiring 201 so that C2<C1, the drain region is widened more than the source region to keep the signal wiring 202 away, and the signal wiring 2 is removed. For example, polysilicon of the transistor 4 is used instead of metal wiring (see FIG. 7).

FIG. 4B shows another example of arrangement of the transistors 4, in which transistors with a large W/L ratio are divided and connected in parallel, as in FIG. 4A. The signal wiring 2 and the gate of the transistor 4 are connected by contacts, and the source electrodes S are connected by vias (indicated by squares on the entire surface in FIG. 4B, etc.) via the metal signal wiring 203 in the upper layer. . The source electrode S and the drain electrode D are shared between the two divided transistor elements, respectively, and the area occupied by the source electrode S and the drain electrode D can be made smaller than in FIG. can be constructed with less parasitic components. In addition, the configuration of FIG. 4B has a small effect on the area, and the length L of the transistor 4 can be increased. Of course, it is not necessary to share the source electrode S and the drain electrode D, and the layout of the signal wiring and the like is not limited to this.

According to the first embodiment configured as described above, the source potential fluctuates following the gate potential applied to the gate electrode G of the transistor 4, and the input stage transistor 4 is connected to one end of each signal output circuit and each At least a predetermined length (preferably ⅕ of the total length) of the wiring length of the signal wiring wired between the other end of the signal output circuit and the upper portion of the second conductivity type well region It is arranged along the signal wiring so as to pass the signal wiring, and is configured so that the ratio of the short side to the long side of the second conductivity type well region is at least a predetermined ratio (preferably 1:10). . As a result, for example, a semiconductor integrated circuit for an imaging device can operate at high speed by reducing the area or power consumption compared to the conventional technology.

Embodiment 2.
FIG. 5 is a plan view showing a configuration example of a semiconductor integrated circuit for an imaging device according to Embodiment 2. FIG.

In FIG. 5, 1-1-1 to 1-4-n are signal output circuits, 2-1 to 2-4 are signal wirings, and 4-1 to 4-4 are one of transistors constituting an amplifier circuit. is.

A plurality of n signal output circuits 1-1-1 to 1-1-n, 1-2-1 to 1-2-n, 1-3-1 to 1-3-n, 1-4-1 to 1 -4-n are connected to the signal wirings 2-1 to 2-4 without duplication. The signal wirings 2-1 to 2-4 are connected to the transistors 4-1 to 4-4 forming the amplifier circuit in one-to-one correspondence. Transistors 4-1 to 4-4 are formed in second conductivity type well regions separated by first conductivity type wells or semiconductor substrates, respectively. The transistors 4-1 to 4-4 are arranged in a 2×2 matrix, and the upper portion of the second conductivity type well region is one-to-one with the transistors 4-1 to 4-4 formed in the second conductivity type well region. Wiring is performed so that the correspondingly connected signal wirings 2-1 to 2-4 pass through.

Here, regarding the signal wiring that is not connected correspondingly, if signal coupling is not taken into consideration, it passes through the upper part of the second conductivity type well region, and if signal coupling is taken into consideration, the shield wiring is interposed between the second conductivity type well region and the second conductive well region. It is wired through the upper part of the two-conductivity type well region or to the upper part of the first-conductivity type well or the semiconductor substrate region.

In FIG. 5, the effect of reducing the parasitic capacitance of the signal wirings 2-1 to 2-4 passes through the second conductivity type well region in which the transistors 4-1 to 4-4 connected in one-to-one correspondence are formed. Since it is limited to wiring, it is about 1/2 compared with the configuration of FIG. 1A. However, in the configuration of FIG. 5, since the transistors 4-1 to 4-4 are arranged in a matrix, there is no need to configure the transistor 4 excessively, and the area efficiency in element arrangement is better than that of the configuration of FIG.

When a plurality of n signal output circuits, one signal wiring, and one amplifier circuit form one circuit group, FIG. 5 is composed of four circuit groups. For example, when the number of circuit groups is 32, the transistors 4 are arranged in an X×Y matrix shape such as 2×16, 3×11, and 4×8. Here, X indicates the number in the horizontal direction in FIG. 5, and Y indicates the number in the vertical direction in FIG. However, in the case of 3×11, one transistor region is left over, so in that region nothing is placed, or another element is placed where the transistor is placed but the gate electrode G is fixed at a high level or a low level. , and so on.

If the number of transistors arranged in the X direction is increased, it is possible to arrange the transistors 4 with better area efficiency. Capacity may increase. Therefore, it is appropriate to set X to 2 to 4, and if it is more than that, the characteristics may deteriorate. That is, for example, of the wiring length of the signal wiring 2-1 (meaning the red line portion in the reference diagram) connecting between the signal output circuits 1-1-1 and 1-1-n shown in FIG. , at least ⅕ are wired to overlap the second conductivity type well region forming the transistor. The same applies to other circuit groups.

6A is a plan view showing an arrangement example of back gate electrodes of transistors in the semiconductor integrated circuit of FIG. 5. FIG. 6B is a plan view showing another arrangement example of back gate electrodes of transistors in the semiconductor integrated circuit of FIG.

6A and 6B, 2, 201 and 202 are signal wirings, 101 is a first conductivity type well or semiconductor substrate, 102 is a second conductivity type well, and 104 is a second conductivity type diffusion region.

6A and 6B show an example of the arrangement of the back gate electrodes B. FIG. The back gate electrode B is connected to a second conductivity type diffusion region formed in the second conductivity type well 102 by a contact. Since the source electrode S and the back gate electrode B of the transistor 4 are connected, the signal wiring 201 connected to the source electrode S and the back gate electrode B are connected.

FIG. 6A shows an example in which the back gate electrode B is provided at one end of the second conductivity type well, the other end, and between transistors. In this configuration, although the connection resistance of the back gate electrode B is increased, the back gate electrode B can be provided without affecting the area. Further, by increasing the number of back gate electrodes B provided between transistors, the resistance of the back gate electrodes B can be reduced accordingly. In that case, it is effective to disperse them widely instead of collectively providing them in one place.

FIG. 6B shows an example in which back gate electrodes are arranged over a wide range in parallel with transistors. In this configuration, the connection resistance of the back gate electrode B can be made very small, so that the potential response of the second-conductivity-type well becomes faster, but the area becomes larger.

A back gate electrode may be provided by using the configurations of FIGS. 6A and 6B together.

7A is a plan view showing a layout method for further reducing the parasitic capacitance of the signal wiring 2 in the semiconductor integrated circuit of FIG. 5. FIG. FIG. 7B is a plan view showing a configuration example in which the signal wiring 2 is made of polysilicon in the semiconductor integrated circuit of FIG. That is, as is clear from FIGS. 7A and 7B, the parasitic capacitance of a portion of the signal wiring to which a plurality of signal output circuits with low driving capability are connected is substantially reduced to a very small capacitance.

According to the second embodiment configured as described above, each of the input stage transistors is arranged in a matrix, and each of the input stage transistors is connected to the plurality of signal wirings corresponding to the natural number n:1. , of the wiring length of each of the signal wirings wired between one end of each signal output circuit and the other end of each signal output circuit, over at least a predetermined length of the second conductivity type well It is arranged along the signal wiring so that each of the signal wirings passes over the region. As a result, a semiconductor integrated circuit for, for example, an imaging device can be made smaller in area or consume less power and can operate at higher speed than in the prior art.

Moreover, it is preferable that a plurality of circuit groups are provided, and the respective input stage transistors of the plurality of circuit groups are arranged in a matrix.

Furthermore, as is clear from FIG. 4 of Embodiment 1 and FIG. 6A of Embodiment 2, the input stage transistor is composed of two or more transistor elements connected in parallel, and the back gate electrode is at least the second conductivity type. It is preferably placed at two points, one end and the other end of the well region. As a result, the back gate electrodes can be arranged on the semiconductor substrate with improved area efficiency as compared with the prior art.

As is clear from FIG. 6A of Embodiment 2, the back gate electrode is arranged between the transistor elements, and the back gate electrode arranged between the transistor elements is
It is preferable that (A) it is provided at one location in the center of the second conductivity type well region, or (B) it is provided at a plurality of locations dispersed in the long side direction of the second conductivity type well region. As a result, the back gate electrodes can be arranged on the semiconductor substrate with improved area efficiency compared to the conventional technique, and the resistance value of the back gate electrodes can be reduced.

Moreover, as is clear from FIG. 6B of Embodiment 2, the back gate electrode is preferably provided over a predetermined range of the second conductivity type well region in parallel with the input stage transistor. Thereby, the resistance value of the back gate electrode can be further reduced.

Furthermore, as is clear from FIG. 7 of Embodiment 2, it is preferable that the wiring using the metal in the upper layer than the signal wiring is configured so that the wiring is not formed on the entire surface above the signal wiring. As a result, the parasitic capacitance of the signal wiring can be significantly reduced as compared with the prior art.

Further, as is clear from FIG. 7 of Embodiment 2, the signal wiring is wired so as to cover the gate wiring of the input stage transistor, and is wired closer to the source electrode than the center of the gate electrode of the input stage transistor. preferably. As a result, the parasitic capacitance of the signal wiring can be significantly reduced as compared with the prior art.

Furthermore, as is clear from FIG. 7 of Embodiment 2, the second conductivity type diffusion region forming the drain of the input stage transistor has a larger area than the second conductivity type diffusion region forming the source of the input stage transistor. It is preferably configured to be large. As a result, the parasitic capacitance of the signal wiring can be significantly reduced as compared with the prior art.

Furthermore, in Embodiments 1 and 2, it is preferable that part of the signal wiring is formed using polysilicon that forms the gate electrode of the input stage transistor. As a result, the parasitic capacitance of the signal wiring can be significantly reduced as compared with the prior art.

Further, in an image pickup apparatus having a plurality of image pickup elements, by providing the semiconductor integrated circuit according to the above-described first or second embodiment, area saving or power consumption can be reduced and high-speed operation can be achieved as compared with the conventional technology. It is possible to configure an imaging device capable of

Comparison with Patent Document 1.
In Patent Document 1, for the purpose of reducing the chip size, an amplification stage is shared by a plurality of photoelectric conversion units, and one amplification stage is provided for each pixel group representing a set of a predetermined number of pixels to reduce the load on the output line. A configuration that does not increase (parasitic resistance, parasitic capacitance) is disclosed.

However, Japanese Patent Laid-Open No. 2002-200000 does not particularly describe the arrangement of the elements or the layout method thereof. In particular, FIG. 10 of Patent Document 1 illustrates an example configured by a photoelectric conversion section, a control section, a wiring section, and an amplification section. A plurality of photoelectric conversion units are connected to the amplifier unit via the same wiring unit. Other photoelectric conversion units, wiring units, and amplification units are similarly connected with regularity. In such a configuration, a person skilled in the art would understand that the elements should be placed under the wiring in order to minimize the load on the wiring section or to avoid coupling with the node of the element whose voltage fluctuates dynamically. A region is provided only for wiring, or a static element such as a MOS cap is placed even if an element is provided.

In addition, in order to avoid extra parasitic components and to suppress variations in the characteristics of the transistor elements, the amplifier section should be laid out in a form that is close to a square if there are no restrictions, so that the aspect ratio of the vertical and horizontal sides is as small as possible. . In other words, the number of pixels forming a pixel group depends on the driving capability of the photoelectric converter, the load on the wiring (parasitic resistance, parasitic capacitance, gate capacitance of the amplifier), and the output load of the amplifier (wiring parasitic resistance, parasitic capacitance). , output load), etc., but as described above, it is difficult to increase the driving capability of the photoelectric conversion units, so the number of photoelectric conversion units connected to the wiring unit is limited. It is practically difficult to dramatically reduce the number, and the effect of chip size reduction described in the prior art is not large.

On the other hand, according to the embodiment of the present invention, the parasitic capacitance of a portion of the signal wiring to which a plurality of signal output circuits with low drive capability are connected is substantially reduced to a very small capacitance, thereby speeding up the circuit. Either or all of area saving and power consumption reduction can be achieved.

In the conventional configuration, regarding the signal wiring to which multiple signal output circuits with low drive capability are connected, the parasitic capacitance attached to the wells and nodes that do not fluctuate electrically in synchronization with the voltage change of the signal wiring is removed from the signal wiring. By attaching it to wells and nodes that fluctuate electrically in synchronization with voltage changes in the wiring, even if the absolute value of the parasitic capacitance increases, it will not electrically synchronize with the voltage changes in the signal wiring. Parasitic capacitance attached to fluctuating wells and nodes can be treated as equivalently small. By reducing the substantial capacitance component, the responsiveness and frequency characteristics can be improved, and the speed of the semiconductor integrated circuit can be increased by that amount, or the circuit driving capability can be lowered, so that the circuit area can be reduced and the power consumption can be reduced. .

1-1 to 1-n, 1-1-1 to 1-4-n Signal output circuit 2, 2-1 to 2-4 Signal wiring 3 Amplifier circuit 4, 4-1 to 4-4 Transistor 5 Other circuit 6 Output terminal 101 First conductivity type well or semiconductor substrate 102 Second conductivity type well 103 Second conductivity type semiconductor substrate 104 Second conductivity type diffusion regions 201 to 203 Signal wiring 201a, 202a, 203a Signal wiring or shield wiring B Back gate electrode C1 to C4, C1a to C4a parasitic capacitance D drain electrode G gate electrode S source electrode

JP 2019-009691 A

Claims (11)

A semiconductor integrated circuit comprising a circuit group comprising at least a plurality of signal output circuits, signal wiring, and an amplifier circuit,
the signal wiring is connected to each of the plurality of signal output circuits and the amplifier circuit;
The amplifier circuit comprises an input stage transistor,
the input stage transistor is formed in a first conductivity type well region or a second conductivity type well region separated by a semiconductor substrate;
the gate electrode of the transistor and the signal wiring are connected,
a source electrode of the transistor and a back gate electrode of the transistor are connected;
the source potential fluctuates following the gate potential applied to the gate electrode of the transistor;
The input stage transistor is of the second conductivity type over at least a predetermined length of the wiring length of the signal wiring wired between one end of each of the signal output circuits and the other end of each of the signal output circuits. arranged along the signal wiring so that the signal wiring passes over the well region;
A semiconductor integrated circuit, wherein a ratio of a short side to a long side of the second conductivity type well region is equal to or greater than a predetermined ratio. A semiconductor integrated circuit comprising a plurality of signal output circuits, a plurality of signal wirings, and a plurality of amplifier circuits,
the plurality of signal wirings and the plurality of amplifier circuits are connected in a one-to-one correspondence,
the plurality of signal output circuits and the plurality of signal wirings are connected in correspondence with a natural number n to 1 so as not to overlap;
each of the plurality of amplifier circuits includes at least one input stage transistor;
each of the input stage transistors is formed in a second conductivity type well region separated for each transistor by a first conductivity type well region or a semiconductor substrate;
the gate electrode of the transistor and the signal wiring are connected,
a source electrode of the transistor and a back gate electrode of the transistor are connected;
the source potential fluctuates following the gate potential applied to the gate electrode of the transistor;
each of the input stage transistors arranged in a matrix,
each of the input stage transistors is connected to the plurality of signal wirings corresponding to a natural number n to 1;
out of the wiring length of each of the signal wirings wired between one end of each of the signal output circuits and the other end of each of the signal output circuits, at least over a predetermined length, the second conductivity type arranged along the signal wirings so that each of the signal wirings passes over the well region
The ratio of the short side to the long side of the second conductivity type well region is configured to be a predetermined ratio or more.
A semiconductor integrated circuit characterized by: comprising a plurality of the circuit groups,
2. The semiconductor integrated circuit according to claim 1, wherein said input stage transistors of said plurality of circuit groups are arranged in a matrix. the input stage transistor is composed of a parallel connection of two or more transistor elements;
The back gate electrode is placed at least at two points, one end and the other end of the second conductivity type well region,
3. The semiconductor integrated circuit according to claim 1, wherein: the input stage transistor is composed of a parallel connection of two or more transistor elements;
the back gate electrode is arranged between the transistor elements,
the back gate electrode arranged between the transistor elements,
(A) provided at one location in the center of the second conductivity type well region, or (B) provided at a plurality of locations dispersed in the longitudinal direction of the second conductivity type well region,
3. The semiconductor integrated circuit according to claim 1 , wherein: The back gate electrode is provided over a predetermined range of the second conductivity type well region in parallel with the input stage transistor.
5. The semiconductor integrated circuit according to claim 1, characterized by: 6. The wiring according to any one of claims 1 to 5, wherein the wiring using a metal in a layer above the signal wiring is configured so as not to form wiring over the entire surface above the signal wiring. The semiconductor integrated circuit according to . The signal wiring is wired so as to cover the gate wiring of the input stage transistor,
wired closer to the source electrode than the center of the gate electrode of the input stage transistor;
7. The semiconductor integrated circuit according to claim 1, characterized by: the second conductivity type diffusion region forming the drain of the input stage transistor is configured to have a larger area than the second conductivity type diffusion region forming the source of the input stage transistor;
8. The semiconductor integrated circuit according to any one of claims 1 to 7, characterized by: 9. The semiconductor integrated circuit according to claim 1, wherein a part of said signal wiring is formed using polysilicon which forms a gate electrode of said input stage transistor. circuit. An imaging device comprising a plurality of imaging elements,
An imaging device comprising the semiconductor integrated circuit according to any one of claims 1 to 10.

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