JP7321079B2 - game machine - Google Patents

Description

TECHNICAL FIELD The present invention relates to a gaming machine that performs lottery processing based on game operations and executes image effects corresponding to the lottery results, and more particularly to a gaming machine with an improved power supply circuit.

A pinball game machine such as a pachinko machine is equipped with a pattern starting port provided on a game board, a pattern display section for displaying a series of pattern variations by a plurality of display patterns, and a prize winning port in which an opening/closing plate is opened and closed. configured as follows. When the detection switch provided at the symbol start port detects the passage of the game ball, the winning state is entered, and after the game ball is paid out as a prize ball, the displayed symbols are changed in the symbol display unit for a predetermined period of time. After that, when the symbols stop in a predetermined manner such as 7, 7, 7, etc., a big hit state is entered, and the big winning opening is repeatedly opened to generate a game state advantageous to the player.

Whether or not to generate such a game state is determined by a jackpot lottery that is executed on the condition that a game ball has entered the symbol start port, and the above-described symbol variation operation is based on the results of this lottery. It is a thing. For example, when the lottery result is a winning state, a performance operation called reach action is executed for about 20 seconds, and then the special symbols are arranged. On the other hand, a similar ready-to-win action may be executed even in the case of a losing state, and in this case, the player will pay attention to the transition of the performance action while strongly hoping for a big win state. Then, when the predetermined symbols are aligned on the stop line at the end of the symbol variation operation, the player is guaranteed a big hit state.

JP 2018-130320 A Japanese Unexamined Patent Application Publication No. 2018-000601 JP 2015-205117 A JP 2015-198716 A

In this type of game machine, there is a high demand for complex and rich presentations, especially image presentations and character presentations. Therefore, in addition to enriching the character effects, it is desirable to enrich the lamp effects and image effects. .

Therefore, it is necessary to enrich various effects within the range of electric power available for each game machine, and the applicant has also proposed various power supply circuits (References 1 to 4). . Specifically, in Cited Documents 1 to 4, there is a configuration in which the power supply board is made into a component, a configuration in which a thermistor is provided in the path to the performance control board, a configuration in which the DC converter is cut off all at once, and a switch circuit is ON. Each discloses a configuration that bypasses the thermistor.

However, there is a demand for further improvement of the power supply circuit, and further sophistication of various effects control within a limited range of power consumption. Also, in any case, it is necessary to avoid power supply troubles.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a game machine that further suppresses wasteful power consumption. It is another object of the present invention to provide a gaming machine that prevents power supply troubles and realizes various high-level performances without problems.

In order to achieve the above objects, the present invention provides a gaming machine that executes various control operations based on a lottery result caused by a predetermined switch signal, comprising: a power supply terminal for receiving an AC voltage received from the outside; A relay circuit having a relay coil through which a coil current for turning on a relay contact is energized, and an energization cutoff circuit for controlling energization of the relay coil are provided between the rectifier circuit that rectifies the voltage, and A DC/DC conversion means is provided downstream of the rectifier circuit, and the energization cutoff circuit includes a switch circuit that is normally ON and a predetermined DC current based on the AC voltage when the switch circuit is ON. and a direct current generation circuit for generating a voltage, and when the alternating voltage exceeds a predetermined level, the switch circuit turns off, thereby de-energizing the relay coil and turning off the relay contact. Having a configuration to operate, the DC / DC conversion means is an asynchronous rectification converter that generates a first type DC voltage that is distributed to the main control means that is centrally responsible for the game control operation, and the main control means and a synchronous rectifying converter that generates a second type of DC voltage that is distributed to the performance control means that controls various performance operations based on commands received from.

According to the above-described present invention, it is possible to prevent power supply troubles and realize various kinds of advanced performances without problems.

It is a perspective view showing the pachinko machine of the present embodiment. 2 is a front view showing a game area of the gaming machine of FIG. 1; FIG. 2 is a block diagram showing the overall circuit configuration of the gaming machine of FIG. 1; FIG. 3 is a block diagram showing the configuration of a power supply substrate; FIG. 4 is a circuit diagram showing a relay circuit together with related circuits; FIG. It is a circuit diagram showing a full-wave rectifier circuit and a power factor correction circuit. 4 is a circuit diagram showing a voltage monitoring circuit; FIG. 1 is a circuit diagram showing a synchronous rectification DC/DC converter; FIG. FIG. 3 is a circuit diagram showing another DC/DC converter with synchronous rectification; 1 is a circuit diagram showing an asynchronous rectifying DC/DC converter; FIG. It is a schematic diagram showing the back side of the power supply board. FIG. 4 is a schematic diagram showing the configuration of first to third connectors of the power board; 2 is a block diagram showing in some detail the circuit configuration of an effect control unit in the gaming machine of FIG. 1; FIG. It is drawing explaining the composite chip|tip which comprises a production|presentation control part. 14 is a block diagram showing an internal configuration of a CPU circuit shown in FIG. 13; FIG. The memory map of built-in CPU (production control CPU) of the CPU circuit is illustrated. 4 is a drawing for explaining various transfer operation modes (a) to (b) and transfer operation procedures (c) to (e) for the DMAC; 4A and 4B are diagrams for explaining an index space, an index table, a virtual drawing space, and a drawing area; 2 is a block diagram describing the internal configuration of a data transfer circuit together with related circuit configurations; FIG. 2 is a block diagram describing the internal configuration of a display circuit together with related circuit configurations; FIG. 4 is a flowchart for explaining power reset operation after CPU reset; FIG. 22 is a flowchart for explaining memory section initialization processing, which is a part of FIG. 21; FIG. 22 is a flowchart illustrating main control processing and interrupt processing, which are a part of FIG. 21; 10 is a flowchart for explaining CGROM initialization processing, which is part of the main control processing; FIG. 11 is a flowchart for explaining a part of processing contents of another interrupt processing; FIG. It is a flowchart explaining the control operation of production|presentation control CPU63 about the case where a preloader is not used. 4 is a time chart showing an example of memory READ operation and memory WRITE operation; 4 is a diagram for explaining the configuration of a display list; FIG.

The present invention will be described in detail below based on examples. FIG. 1 is a perspective view showing the pachinko machine GM of this embodiment. This pachinko machine GM consists of a rectangular wooden outer frame 1 detachably attached to an island structure, and an inner frame 3 pivotally attached via hinges 2 fixed to the outer frame 1 so as to be openable and closable. It is configured. A game board 5 is detachably attached to the inner frame 3 not from the back side but from the front side, and a glass door 6 and a front plate 7 are pivotably attached to the front side thereof so as to be openable and closable. In addition, in this specification, the glass door 6 and the front plate 7 are generically called a front door member. The inner frame 3 to which the front door member (the glass door 6 and the front plate 7) is pivotally attached is sometimes referred to as a game frame.

Illuminated lamps such as LED lamps are arranged in a substantially C shape around the outer periphery of the glass door 6 . On the other hand, a total of three speakers are arranged on the upper left and right positions of the glass door 6 and on the lower side. The two upper speakers are configured to output left and right channel R and L sounds, respectively, and the lower speaker is configured to output bass sounds.

An upper plate 8 for storing game balls to be shot is attached to the front plate 7, and a lower plate 9 for storing game balls overflowing or extracted from the upper plate 8 and a shooting handle are provided at the lower part of the inner frame 3. 10 are provided. A shooting handle 10 is interlocked with a shooting motor, and a game ball is shot by a hitting mallet that operates according to the rotation angle of the shooting handle 10.例文帳に追加

A chance button 11 is provided on the outer peripheral surface of the upper plate 8. - 特許庁The chance button 11 is provided at a position where it can be operated with the player's left hand, and the player can operate the chance button 11 without releasing the right hand from the shooting handle 10.例文帳に追加The chance button 11 does not function normally, but when the game state becomes the button chance state, the built-in lamp lights up and becomes operable. Note that the button chance state is a game state provided as necessary.

A rotary switch-type volume switch VLSW is arranged below the chance button 11, and the player operates the volume switch VLSW to change the level from silent level (=0) to maximum level (=7). The speaker volume can be adjusted in eight steps. The volume of the speaker is initially set by a setting switch (not shown) that can be operated only by the staff, and the initially set volume is maintained unless the player operates the volume switch VLSW. Also, the abnormal notification sound for notifying that an abnormal situation has occurred is emitted at the maximum volume regardless of the initial volume set by the staff or the volume set by the player.

On the right side of the upper plate 8, an operation panel 12 for ball lending operation for the card-type ball lending machine is provided, and a frequency display section for displaying the remaining card amount in three digits and a predetermined amount of game balls are provided. A ball lending switch for instructing lending and a return switch for instructing card return at the end of the game are provided.

As shown in FIG. 2, on the surface of the game board 5, a guide rail 13 consisting of a metallic outer rail and an inner rail is provided in an annular shape, and a central opening HO is provided substantially in the center thereof. Under the central opening HO, a movable effect body (not shown) is housed in a concealed state. We have realized the preview performance. Here, the notice performance is a performance that uncertainly notifies the occurrence of a big win state advantageous to the player, and the reliability of the notice performance means the probability of the occurrence of the big win state.

A main display device DS1 composed of a large liquid crystal color display (LCD) (for example, 1280 pixels wide by 1024 pixels long) is arranged in the central opening HO. A movable sub-display device DS2 composed of a liquid crystal color display of 480×800 pixels is arranged. The main display device DS1 is a device that variably displays specific symbols related to a big win state and also displays a background image, various characters, and the like in an animated manner. This display device DS1 has special symbol display portions Da to Dc in the central portion and a normal symbol display portion 19 in the upper right portion. Then, in the special pattern display parts Da to Dc, a ready-to-win performance to expect the arrival of a big hit state is sometimes executed, and in and around the special pattern display parts Da to Dc, an appropriate advance notice performance is executed.

The sub-display device DS2 normally displays image information in a stationary state in which the display screen is tilted at an angle that is easy for the player to see. However, during a predetermined notice effect, it moves to the left side of the drawing while changing the tilt angle to an angle that is easy for the player to see, and displays a predetermined notice image.

In other words, the sub-display device DS2 of the embodiment functions not only as a display device but also as a movable effect body for executing the advance notice effect. Here, the advance notice effect by the sub-display device DS2 is set to have a high degree of reliability, and the player pays attention to the moving action of the sub-display device DS2 with great anticipation.

By the way, the game area where the game ball falls and moves includes the first symbol starting port 15a, the second symbol starting port 15b, the first big winning port 16a, the second big winning port 16b, the normal winning port 17, and the gate 18. are arranged. Each of these winning holes 15 to 18 has a detection switch inside so that the passage of a game ball can be detected.

Above the first symbol starting port 15a, a production stage 14 is arranged so that the first symbol starting port 15 can win after the game ball entering from the introduction port IN moves in a seesaw or roulette shape. there is Then, when a game ball wins the first symbol starting port 15, the special symbol display portions Da to Dc are configured to start varying operations.

The second symbol start port 15b is configured to be opened and closed by an electric tulip provided with a pair of left and right opening and closing claws, and when the stop symbol after the change of the normal symbol display unit 19 is displayed as a winning symbol, a predetermined The opening/closing claw is opened for a period of time or until a predetermined number of game balls are detected.

The normal symbol display unit 19 displays normal symbols, and when a game ball that has passed through the gate 18 is detected, the normal symbol changes for a predetermined period of time, and is extracted when the game ball passes through the gate 18. A stop pattern determined by the selected random number for lottery is displayed and stopped.

The first big prize winning port 16a has a sliding board that advances and retreats in the front-rear direction, and the second big prize winning port 16b has an opening/closing plate whose lower end is pivotally supported and which opens forward. . Although the operations of the first big winning hole 16a and the second big winning hole 16b are not particularly limited, in this embodiment, the first big winning hole 16a corresponds to the first symbol starting hole 15a, and the second big winning hole 16b is configured to correspond to the first symbol starting port 15b.

That is, when the game ball wins in the first symbol start port 15a, the special symbol display portions Da to Dc start to fluctuate, and after that, when the predetermined jackpot symbols are arranged in the special symbol display portions Da to Dc, the first jackpot. A special game is started, and the slide board of the first big winning hole 16a is opened forward to facilitate the winning of game balls.

On the other hand, as a result of the fluctuation operation started by the winning of the game ball to the second symbol starting port 15b, when the predetermined big winning symbols are arranged in the special symbol display parts Da to Dc, the second big winning special game is started. The opening/closing plate of the second prize winning port 16b is opened to facilitate winning of game balls. The game value of the special game (jackpot state) varies depending on the jackpot symbols to be arranged, but which game value is given is determined in advance based on the lottery result corresponding to the winning timing of the game ball. It is determined.

In a typical jackpot state, after the opening/closing plate of the big winning hole 16 is opened, the opening/closing plate closes when a predetermined time elapses or when a predetermined number (for example 10) of game balls win. Such actions are continued up to, for example, 15 times, and are controlled in a state advantageous to the player. In addition, when the stop symbol after the change of the special symbol display parts Da to Dc is a specific symbol among the special symbols, there is a privilege that the game after the special game ends will be in a high probability state (definite variable state). Granted.

FIG. 3(a) is a block diagram showing the overall circuit configuration of the pachinko machine GM that implements the operations described above. Further, FIG. 3(b) is a circuit diagram showing the circuit configuration of the power monitor unit MNT arranged on the payout control board 25. As shown in FIG.

As shown in FIG. 3( a ), this pachinko machine GM includes a power supply board 20 that receives AC24V and outputs various DC voltages (35V, 12V, 5V) together with AC24V, and a main unit responsible for centrally and centrally responsible for game control operations. A control board 21, a presentation interface board 22 on which a circuit element SND for voice presentation is mounted, and a lamp presentation, a voice presentation, and an image presentation are collectively executed based on a control command CMD received from the main control board 21.例文帳に追加A performance control board 23, a liquid crystal interface board 24 positioned between the performance control board 23 and the display devices DS1 and DS2, and a payout motor M are controlled based on a control command CMD' received from the main control board 21 to play the game. It is mainly composed of a payout control board 25 for putting out balls and a shooting control board 26 for shooting game balls in response to the player's operation.

The effect interface board 22, the effect control board 23, and the liquid crystal interface board 24 are directly connected through male connectors and female connectors without wiring cables. Therefore, even if the circuit configuration of each electronic circuit is complicated and advanced, the storage space for the entire board can be minimized, and noise resistance can be enhanced by shortening the connection line.

As shown, the control command CMD' output by the main control board 21 is transmitted to the payout control board 25. On the other hand, the control command CMD output by the main control board 21 is transmitted to the effect control board 23 via the effect interface board 22 . Here, each of the control commands CMD and CMD' has a 16-bit length, but is divided into two 8-bit lengths and transmitted in parallel.

A computer circuit including a one-chip microcomputer is mounted on the main control board 21 and the payout control board 25 . Also, the performance control board 23 is equipped with a composite chip 50 in which computer circuits such as a VDP circuit (Video Display Processor) 52 and a built-in CPU circuit 51 are built. Therefore, in this specification, these control boards 21, 25, 23, the circuits mounted on the effect interface board 22 and the liquid crystal interface board 24, and the operations realized by these circuits are collectively functionally referred to as , the main control unit 21, the effect control unit 23, and the payout control unit 25. Note that the effect control unit 23 and the payout control unit 25 are sub-control units for the main control unit 21 .

Further, the pachinko machine GM is roughly divided into a frame-side member GM1 surrounded by a dashed line in FIG. The frame-side member GM1 includes an inner frame 3 to which a glass door 6 and a front panel 7 are pivotally attached, and a wooden outer frame 1 on the outside thereof, so that the game hall can be used for a long period of time regardless of model changes. fixedly installed in the On the other hand, the board-side member GM2 is replaced in response to the model change, and the new board-side member GM2 is attached to the frame-side member GM1 instead of the original board-side member. All except the frame side member 1 are board side members GM2.

As shown in the dashed frame in FIG. 3A, the frame-side member GM1 includes a power supply board 20, a backup power supply board 33, a payout control board 25, a launch control board 26, a frame relay board 36, a motor/ A lamp drive board 37 is included, and these circuit boards are each fixed in place on the inner frame 3 . On the other hand, on the back surface of the game board 5, a main control board 21 and an effect control board 23 are fixed together with the display devices DS1, DS2 and other circuit boards. The frame-side member GM1 and the board-side member GM2 are electrically connected by centralized connectors C1 to C3 arranged centrally in one place.

The power supply board 20 generates three types of DC voltages (35V, 12V, 5V) based on the AC 24V power distributed from the game hall, and each DC voltage is sent via the central connection connector C2 to the production interface. Power is distributed to the face substrate 22 . In addition, the three types of DC voltages (35V, 12V, 5V) are distributed to the payout control board 25 together with the AC voltage AC24V. The DC voltage (35V, 12V, 5V) distributed to the payout control board 25 is configured to be distributed to the main control board 21 together with the backup power supply BAK via the central connection connector C1.

DC 35V is used as the driving power source for the ball feeding solenoid and the shooting solenoid, and for the electric tulip (variable prize winning device) and the electromagnetic solenoid that opens and closes the big prize winning port 16 in relation to the game ball shooting operation. In addition, DC 12V is used as the drive power supply for the LED lamps and motors controlled from each control board, and the power supply voltage for the digital amplifier, while DC 5V is used for the one-chip microcomputer of the payout control board 25 and the main control board 21 and the power supply voltage of the logic elements mounted on each control board. In addition, after the DC 5V is level-dropped by the DC/DC converter of the effect interface board 22, the level-dropped voltages of various levels are used as power supply voltages for various computer circuits (composite chip 50, audio processor 27, etc.). used.

The backup power supply BAK is a DC5V DC power supply for holding data in the built-in RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 25 after the power is cut off, and is realized by, for example, an electric double layer capacitor. In this embodiment, a dedicated backup power supply board 33 is provided, and an electric double layer capacitor arranged on the backup power supply board 33 is configured to be charged during game operation by a DC voltage of 5 V received from the payout control board 25. It is

On the other hand, after the power is cut off, the backup power supply BAK retains the data in the built-in RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 25, so the main control unit 21 and the payout control unit 25 The game operation can be restarted after the power is turned on. The backup power supply board 33 is provided with an electric double layer capacitor capable of retaining the contents of the internal RAM of each one-chip microcomputer for at least several days.

By the way, in the present embodiment, unlike the conventional equipment configuration, the power supply abnormality signal ABN indicating an abnormal drop in the AC voltage AC24V is configured to be generated not by the power supply board 20 but by the power supply monitoring unit MNT of the payout control board 25. (see FIGS. 3 and 4). As shown in FIG. 3B, the power monitor unit MNT includes a full-wave rectifier circuit that rectifies AC 24 received from the power supply board 20, a photodiode D that receives the output of the full-wave rectifier circuit and emits light, and the power supply board 20. A phototransistor TR which is powered by a DC voltage of 5V received from a photodiode D and is turned ON based on the light emission of the photodiode D, and an output section which outputs an H-level detection signal ABN (power failure signal) based on the ON operation of the phototransistor TR. and The photodiode D and the phototransistor TR constitute a photocoupler PH.

In the above configuration, the photocoupler PH is quickly turned on after the power is turned on, so that the power failure signal ABN becomes the normal level (H). However, after that, if the AC power supply abnormally drops for some reason (normally, the power supply is cut off), the photocoupler PH changes to the OFF state before the timing at which the monitor signals Wm5 and Wm5 shown in FIG. 7 are output. The power failure signal ABN changes to the failure level (L). This power failure signal ABN is transmitted to the one-chip microcomputer of the payout control board 25, and is also transmitted to the one-chip microcomputer of the main control board 21 via the central connection connector C1. Therefore, each one-chip microcomputer that has received the power failure signal ABN of the abnormal level executes backup processing for storing necessary information in its internal RAM (see the upper right portion of FIG. 7). As described above, the information in the built-in RAM is maintained by the backup power supply BAK, so the game operation before the power shutdown can be resumed after the power is turned on.

FIG. 4A is a block diagram showing in some detail the circuit configuration of the power supply substrate 20. As shown in FIG. As shown in the figure, the power supply board 20 includes a filter circuit Fi that receives 24 VAC, a relay circuit RL that cuts off 100 VAC under the control of a cut-off circuit CUT, a synchronous full-wave rectifier circuit RECT, and a booster circuit. A power factor correction circuit (such as a power factor correction component PFC), a voltage monitoring circuit WTCH, and four types of step-down DC/DC converters are installed. Each of the four types of DC/DC converters drops the DC 35V output by the power factor correction circuit, but according to the output voltage level (5V/12V), the 5V converters CV5m and CV5s and the 12V converters CV12m and CV12s. and

Further, these converters are classified into asynchronous rectification converters CV12m and CV5m and synchronous rectification converters CV12s and CV5s based on the rectification method. A specific circuit configuration of the DC/DC converter will be described later with reference to FIGS. Technically speaking, it refers to a type in which the energization operation is performed by a MOSFET), while the asynchronous rectification type refers to a type in which the energization operation is performed by a rectifier diode that is not ON/OFF controlled.

As shown in FIG. 3(a), various voltages are distributed from the power supply board 20 to the payout control board 25 and the production interface board 22. In FIG. 4(a), the first connector Main and the AC connector AC , and that the power supply board 20 and the effect interface board 22 are connected through the second connector Sub. there is Further, it is shown that DC 12V is directly supplied to the effect motors and LED lamps arranged on the front door members such as the glass door 6 and the front panel 7 via the third connector Aux.

Corresponding to this configuration, a blue LED and a red LED, which indicate that normal energization is realized via the first connector Main and the second connector Sub, are used as energization notification lamps on the surface side of the power supply board 20. are arranged at each edge (see FIG. 4(b)). Specifically, the power supply board 20 is arranged on the back side, and the payout control board 25 is arranged on top of it. , an energization notification lamp is arranged on the edge of the surface side of the power supply substrate 20 . It should be noted that these LEDs are preferably configured in a cannonball shape.

Regarding the energization notification lamp, first, a total of three red LEDs are arranged on the downstream side of the fuse Fu3 and on the downstream side of each of the two asynchronous converters CV12m and CV5m, corresponding to the first connector Main. ing. These indicate that 35V, 12V, and 5V are respectively distributed to the payout control board 25 by lighting in red, and extinguishing of any LED indicates a power distribution stop state.

On the other hand, corresponding to the second connector Sub, a total of three blue LEDs are arranged downstream of the fuse Fu2 and downstream of each of the two synchronous converters CV12s and CV5s. These indicate that 35 V, 12 V, and 5 V are being distributed, respectively, by lighting in blue, and turning off any of them indicates that the distribution is stopped.

As shown in FIG. 4(b), a pair of red and blue LEDs are positioned adjacent to each other on the edge of the power supply board 20, depending on the voltage level (5/12/35V) to be distributed. Only by opening the inner frame 3 and looking at the back side of the game machine, the presence/absence of lighting of the six energization notification lamps and the lighting color can be immediately recognized. Therefore, from the position of the LED in the off state among the six energization notification lamps, the voltage level of the voltage not distributed and the circuit board to which the distribution is stopped are the payout control board 25 or the presentation interface board 22. can be easily recognized.

By the way, as described above, in this embodiment, the motor driver of the effect motor and the LED driver of the LED lamp arranged on the front door member such as the glass door 6 and the front panel 7 are connected via the third connector Aux. is directly supplied with 12V DC. In a normal equipment configuration, DC12V is distributed from the production control board 23 and the production interface board 22 to the production motor and the LED lamp arranged on the front door member, but in this embodiment, the production motor and the LED Since 12 VDC is supplied directly to the lamp, not only is the power distribution path simplified, but power loss in the power distribution path is greatly reduced, and wasteful power consumption is suppressed.

The internal configuration of the power supply substrate 20 shown in FIG. 4A will be described below with reference to FIGS. 5 to 10. FIG. First, FIG. 5 is a circuit diagram showing the energization cutoff circuit CUT. As shown in the figure, the energization cutoff circuit CUT includes a bridge rectifier circuit BRG that receives AC 24V, a Zener diode ZD1 with a breakdown voltage of about 48V, a Zener diode ZD2 with a breakdown voltage of about 16V, a Zener diode ZD3 with a breakdown voltage of about 27V, When the Zener diode ZD1 is in a non-breakdown state, a transistor TR1 (NPN bipolar) that continues to operate OFF, a transistor Q0 (n-type MOSFET) that continues to operate normally, a half-wave rectifier diode Drec, and a half-wave rectifier diode Drec. It comprises a smoothing capacitor Crec that is charged with the current passing through the wave rectifier diode Drec, and relay coils RL1 and RL2 that turn on the relay contacts CN1 and CN2.

The relay coils RL1 and RL2 and the relay contacts CN1 and CN2 surrounded by rectangular frames are integrated relay components RL, which are arranged on the front side of the power supply substrate 20. FIG. Further, the electrolytic capacitor Crec and the film capacitor Cbr, which will be described below, are also inserted and arranged from the front side of the power supply board 20, but all other parts are surface-mounted parts and mounted on the back side of the power supply board 20. is surface-mounted.

Since the peak value of AC 24V is approximately 34V, the Zener diode ZD1 does not break down and the bridge rectifier circuit BRG does not function as a full-wave rectifier circuit under normal conditions. On the other hand, since the breakdown voltage of the Zener diode ZD2 is about 16 V, the Zener diode ZD2 enters a breakdown state (conducting current I2) based on AC 24 V, and the transistor Q0 operates based on the voltage 16 V across the Zener diode ZD2. is turned ON.

Therefore, the smoothing capacitor Crec is charged to a level close to the peak value of AC 24V based on the current I3, causing the Zener diode ZD3 to break down. Therefore, a current corresponding to the breakdown voltage of 27 V of the Zener diode ZD3 steadily flows through the relay coils RL1 and RL2 in a state limited by the current limiting resistor R, and the relay contacts CN1 and CN2 are constantly ON state is maintained. Since the relay contacts CN1 and CN2 are kept ON, the AC 24V through the filter circuit Fi is steadily supplied to the full-wave rectifier circuit RECT and the ball dispenser RNT. The AC 24 V is distributed to the ball dispenser RNT via the AC connector AC and the payout control board 25 .

The current I _normal flowing through the half-wave rectifier diode Drec in the normal state is the total sum of the total current I1 (=IL1+IL2) of the relay coils RL1 and RL2, the current I2 to the Zener diode ZD3, and the current I3 to the smoothing capacitor Crec ( I _normal =I1+I2+I3). The smoothing capacitor Crec is composed of a large-capacity columnar electrolytic capacitor of about 700 μF, and is erected on the surface side of the power supply substrate 20 .

By the way, for example, it is possible that 100V AC power is distributed to the game machine instead of 24V AC power due to misunderstanding of the staff. However, in such a case, the Zener diode ZD1 breaks down, the film capacitor Cbr is charged, and the off-state transistor TR1 transitions to the on state, so the transistor Q0 transitions to the off state. As a result, the path of the current I3 shown in the figure is interrupted, and the current flowing through the relay coils RL1 and RL2 is interrupted, so that the relay contacts CN1 and CN2 immediately transition to the OFF state, blocking the transmission of AC 100V. Here, since two relay contacts are provided, even if either line is a ground line connected to the frame ground (not shown), it is possible to reliably stop the supply of 100V AC. Since the operation until the relay contacts CN1 and CN2 make the OFF transition is completed in an instant, the fuse Fu1 at the most upstream position will not blow.

As described above, in this embodiment, even if the staff makes an installation error, the staff can recognize the operation error because the game machine does not start regardless of whether the power switch is turned on. In addition, not only is the game machine prevented from being damaged, but the most upstream fuse Fu1 and the other fuses Fu1 to FU6 are not melted, eliminating the need for fuse replacement. The AC 24V is configured to be transmitted to the ball lending machine RNT via the payout control board 25 (see the right side of FIG. 4(a)), but the AC 100V may damage the ball lending machine RNT. neither.

Next, a synchronous rectification type full-wave rectifier circuit (full-wave rectifier chip) RECT composed of a single circuit component will be described with reference to FIG. 6(a). As shown in the figure, for example, the full-wave rectifier chip RECT, which is a hybrid IC, supplies appropriate control voltages TGa and TGb to four N-type MOS transistors Q1 to Q4 and gate terminals G of each MOS transistor. , and a drive control circuit CTL for realizing a synchronous rectification operation. In this specification, a hybrid IC is a term that is contrasted with a monolithic IC, and is generally constructed by bonding individual components onto a single insulating substrate and connecting them with metal wiring to integrate them. , is not particularly limited. It should be noted that, in the following description, except for those described as composite circuit components, they are positioned as monolithic ICs.

This full-wave rectifier chip RECT has two AC input terminals (AC+, AC-) and two pulsating current output terminals (V+, V-), but is not provided with power supply voltage terminals. The control circuit CTL should be supplied between the gate terminal G and the source terminal S of the N-type MOS transistors Q1 to Q4 based on the AC voltage (AC+, AC-) and the pulsating current output (V+, V-). driving voltage Vg is generated.

Since body diodes (parasitic diodes D1 to D4) are attached to the four MOS transistors Q1 to Q4, respectively, if all the MOS transistors are in an OFF state, the four body diodes D1 to D4 As a whole, an asynchronous rectification type full-wave rectification circuit (bridge rectification circuit) is configured. Further, this full-wave rectification chip RECT incorporates the previously described drive control circuit CTL, and the drive control circuit CTL controls the voltage Va between the AC+ terminal and the V+ terminal, A voltage Vb between terminals is constantly monitored.

When Va>0, the drive control circuit CTL increases the drive voltage Vg of the MOS transistor Q1 and the MOS transistor Q3 to an appropriate H level before the body diode D1 starts conducting, so that the two transistors Q1 and Q3 are turned on. Therefore, the body diodes D1 and D3 are bypassed, and the current flows through the AC+ terminal→transistor Q1→downstream load→transistor Q3→AC− terminal. In this case, the voltage drop between the drain terminal D and the source terminal S of each of the transistors Q1 and D3 is significantly higher than the voltage drop (forward voltage 0.6 to 1.0 V) when the body diodes D1 and D3 are conductive. Since it is low, wasteful power consumption is greatly reduced.

Furthermore, in this embodiment, since the N-type MOS transistor is used, the on-resistance is reduced as compared with the case of using the P-type MOS transistor, and in this sense also the power supply efficiency is improved. Incidentally, since the full-wave rectifier chip RECT has a power supply efficiency of 96% or more (approximately 99%) even in the operating state of AC 24V input and pulsating current average current output of 10A, mounting of a heat sink is unnecessary. As described above, in this embodiment, four N-type MOS transistors are used. However, if power supply efficiency may be slightly lowered, two N-type MOS transistors and two rectifying diodes may be used to form a bridge rectifier circuit. can be

In any case, when Va<0 after Va>0, the drive control circuit CTL controls the transistors Q1 and Q2 to turn off. Before starting conduction, drive voltage Vg of MOS transistor Q2 and MOS transistor Q4 is increased to an appropriate H level. In this case as well, the body diodes D2 and D4 are bypassed, and the current flows through the path of the AC- terminal→transistor Q2→downstream load→transistor Q4→AC+ terminal, thereby greatly reducing wasteful power consumption.

As shown in FIG. 4A, a high frequency bypass capacitor C1 of about 2 to 3 μF and a choke coil L1 of about 40 μH are arranged downstream of the full-wave rectifier chip RECT. It absorbs noise and is charged with a pulsating current voltage with a peak value of about 34V. The high-frequency bypass capacitor C<b>1 has a square plate shape and is erected on the surface side of the power supply substrate 20 .

By the way, although the internal power consumption of the full-wave rectifier chip RECT is greatly reduced based on the above configuration, a large current constantly flows through each connection terminal. Therefore, in this embodiment, the full-wave rectifier chip RECT is not directly soldered to the power supply board 20, but is a composite first circuit component in which a plurality of circuit connection bars are connected to the terminals of the full-wave rectifier chip RECT. and

That is, for the two AC input terminals (AC+, AC-) and the two pulsating current output terminals (V+, V-) of the full-wave rectifier chip RECT, a plurality of circuit connection bars are connected to each terminal. Then, the whole is appropriately molded to complete a thin plate-like composite first circuit component. In this way, the input and output currents to the full-wave rectifier chip RECT all pass through a plurality of circuit connection bars, so transmission loss in transmission lines to other circuit components can be effectively reduced. The circuit connection bar may be directly electrically connected to the full-wave rectifier chip RECT, or may be electrically connected after placing the full-wave rectifier chip RECT on another substrate BR (preferably an insulating substrate). good.

In any case, the appearance of the composite first circuit component is that its main body is a thin plate of about 30×60×10 mm, and as shown in FIG. , and protrudes from the component body in a substantially orthogonal state. Here, the 17 circuit connection bars include a first group of four bars electrically connected to the AC input terminal AC+, a second group of four bars electrically connected to the AC input terminal AC-, and a pulsating current output terminal V+. It is divided into a third group of 4 electrically connected and a fourth group of 5 electrically connected to the pulsating current output terminal V−.

Each circuit connection bar in each group is in the shape of a round bar or flat plate, and its diameter Φ and plate width WD are about 1 mm (Φ=WD=about 0.6 to 1.5 mm) when viewed from the front. . In addition, the circuit connection bars in each group are aligned at a uniform pitch Pi of 2 mm or more (preferably about 2 to 3 mm), and the circuit connection bars in each group maintain the uniform pitch Pi. , are inserted from the front side of the power supply board 20 in a state substantially orthogonal to the power supply board 20, and are soldered to the circuit pattern lands corresponding to each group on the front and rear surfaces thereof.

A circuit pattern land is a conductor surface formed of copper foil or the like on a circuit board. In this embodiment, a material that does not cause any problem of power consumption even if a current of 1 A is passed through a conductor surface with a pattern width of 1 mm is used. It is selected to form a predetermined film thickness. The circuit pattern lands of each group are formed with a sufficient plane width not less than the maximum separation distance between the circuit connection bars belonging to each group.

Specifically, the first to third groups of circuit pattern lands are each formed to have a planar width exceeding 4×Pi corresponding to each of the four circuit connection bars, and the fourth group of circuit pattern lands are formed to have a planar width exceeding 5×Pi corresponding to the five circuit connection bars. Although not particularly limited, the circuit pattern lands of this embodiment each have a minimum width (4×Pi, 5×Pi) at the connection points with the circuit connection bar, and the other portions are formed with a pattern width equal to or larger than the minimum width. It is

Therefore, if Pi=2.5 mm, the circuit pattern lands of the first to third groups are each 4×Pi (10 mm) or more, and a steady current of 10 A or more is allowed. Become. Corresponding to such a configuration, the full-wave rectifier chip RECT of this embodiment functions with an output current of about 10A at maximum.

The pulsating current voltage V1 full-wave rectified by the full-wave rectification chip RECT (composite first circuit component) having the above configuration is supplied to the step-up power factor correction circuit. The power factor correction circuit is composed of a power factor correction component PFC and related circuit components. is illustrated. As shown, the power factor correction component PFC has a first input terminal Vin, a second input terminal Vin2, a negative voltage input terminal V−, a voltage output terminal Vout, a ground terminal GND, and a power supply voltage supply terminal Vcc. is configured with

FIG. 6(d) illustrates the appearance of the power factor correction component PFC, which is the composite second circuit component. The illustrated composite second circuit component has a thin plate-like main body of about 30×60×10 mm, and is completed as an integrated circuit component by being accommodated in the electromagnetic shield box SH shown in FIG. 6(e). . The electromagnetic box SH is formed of a rectangular conductor box of about 31 mm×65 mm×12 mm corresponding to the composite second circuit component. Then, the open surface BK formed in a gate shape, the flush closed surface FT, and the upper and side surfaces having a plate width of about 12 mm connecting the open surface BK and the closed surface FT form a substantially rectangular parallelepiped shape without a bottom surface. formed and fixed to the power supply board 20 .

The internal configuration of the power factor correction component PFC is as shown in FIG. 6(c). You can place it and complete it. In any case, as shown in FIG. 6(d), this composite second circuit component PFC also has a total of 16 circuit connection bars aligned in a line and protruding from the component body in a substantially orthogonal state. The 16 circuit connection bars include 4 first input terminal Vin groups, 4 negative voltage input terminal V-groups, 3 voltage output terminal Vout groups, and 3 ground terminal GND groups. there is

Also in the composite second circuit component, each group of circuit connection bars is in the shape of a round bar or flat plate, and its diameter Φ and plate width WD are about 1 mm (Φ=WD=0.6 ~1.5 mm). In addition, the circuit connection bars in each group are aligned at a uniform pitch Pi of 2 mm or more (preferably about 2 to 3 mm), and the circuit connection bars in each group maintain the uniform pitch Pi. , are inserted from the front side of the power supply board 20 in a state substantially orthogonal to the power supply board 20, and are soldered to the circuit pattern lands corresponding to each group on the front and rear surfaces thereof.

In the composite second circuit component as well, the circuit pattern lands are formed with a sufficient plane width that does not fall short of the maximum separation distance between the circuit connection bars belonging to each group, and a current of 1 A is applied to the conductor surface with a pattern width of 1 mm. A predetermined film thickness is formed by selecting a material that does not pose a problem of power loss even when the film is flowed. The circuit pattern land, for example, for the voltage output terminal Vout and the ground terminal GND, is formed with a planar width exceeding 3×Pi corresponding to each of the three circuit connection bars. In addition, the circuit pattern land has a minimum width (3×Pi) at the connecting portion with the circuit connection bar, and is formed with a pattern width substantially equal to or larger than the minimum width at the other portions.

Therefore, the circuit pattern land for the voltage output terminal Vout and the ground terminal GND is, for example, 3×Pi (7.5 mm) or more when Pi=2.5 mm, and a steady current of 7.5 A or more is permissible. will be Corresponding to such a configuration, the power factor correction component PFC of this embodiment functions at a maximum output current of about 7A.

Based on the above, the power factor correction component PFC will be further described including related circuit configurations. As shown in FIG. 6(c), the pulsating current output V1, which is the voltage across the pulsating current output terminals V+ and V- of the full-wave rectifier circuit RECT, is supplied to the smoothing capacitor C1 and the thermistor TH. However, the thermistor TH is connected in parallel with a switch circuit SW that is open only when the power is turned on. Normally, the thermistor TH does not function because the switch circuit SW is in the ON state.

A voltage (pulsating current output) V1 across the smoothing capacitor C1 is directly supplied to the second input terminal Vin2 and supplied to the first input terminal Vin via the choke coil L1. Also, the pulsating current output terminal V- of the full-wave rectifier circuit RECT is connected to the negative voltage input terminal V- of the power factor correction component PFC via the ON state switch circuit SW. Here, the electromagnetic shield box SH housing the power factor correction component PFC is arranged so that its closed surface FT faces the choke coil L1, and an eddy current corresponding to the high frequency magnetic field from the choke coil L1 flows. This reliably electromagnetically shields the power factor correction component PFC from high frequency magnetic fields.

A large-capacity smoothing capacitor C2 is connected between the output terminal Vout of the power factor correction component PFC and the ground terminal GND. Although not particularly limited, in the present embodiment, three cylindrical electrolytic capacitors C2 of about 10,000 μF are erected on the surface side of the power supply substrate 20 to achieve a capacitance of 30,000 μF. . The power factor correction circuit functions so that the voltage V2 across the smoothing capacitor C2 has an average value of about DC35V. A DC voltage of 12 V is supplied to the power supply voltage supply terminal Vcc to function the energization control circuit.

Integrated bypass diodes Db and Db (three-terminal composite diode element) are connected between the second input terminal Vin2 and the output terminal Vout. The bypass diodes Db, Db bypass the choke coil L1 and allow the smoothing capacitor C2 to absorb the inrush current when the power is turned on, thereby avoiding the reactor saturation of the choke coil L1 when the power is turned on, and the power factor correction circuit. It prevents the destruction of the constituent circuit parts.

Here, Schottky barrier diodes are preferably selected as the bypass diodes Db and Db from the conditions that a large current can flow instantaneously and that the forward voltage drop is low. The Schottky barrier diodes Db, Db of the example have a forward voltage drop of about 0.79 V at a forward current of 10 A (instantaneous power consumption is 7.9 W). It should be noted that the power factor correction circuit of the embodiment is a step-up type, and V1<V2 during normal operation, so it is desirable that the reverse current is small. Elements with a current of 30 μA or less are selected.

However, to continue normal operation, the junction temperature must of course be maintained below the upper limit. Therefore, in order to prevent element destruction under any operating conditions, the composite diode elements Db, Db of the embodiment are erected on the surface side of the power supply substrate 20 while holding the heat sink.

The power factor correction component PFC, to which the above components are connected, consists of N-type MOS transistors Q5 and Q6 that perform complementary ON/OFF operation at high speed, and ON operation when the power factor improvement operation is stopped. It is composed of a P-type MOS transistor Q7 and an energization control circuit that controls ON/OFF operations of the MOS transistors Q5, Q6 and Q7 to improve the power factor.

The energization control circuit compares the output voltage V2 (average value of about 35 V) with a reference voltage Vr of a predetermined level, and while the output voltage V2 is maintained below the reference voltage Vr, the voltage waveform and the current waveform peak , and the MOS transistors Q5 and Q6 are continuously ON/OFF controlled so as to form a current waveform similar to the voltage waveform. In this normal operation, the switch circuit S1 is controlled to be ON, and the switch circuits S2 and S3 are controlled to be OFF. Therefore, the gate terminal G of the P-type MOS transistor Q7 has the same potential as the source terminal S, and in this operating state, the input voltage V1<the output voltage V2, so the gate terminal G of the P-type MOS transistor Q7 is The drain terminal D becomes higher or lower potential and maintains the OFF state.

By the way, in amusement halls, AC voltage (24 V) is distributed from one power supply system to a large number of game machines, so the voltage level of the AC voltage temporarily changes according to the operating state of the surrounding game machines. may increase. In such a case, if a voltage V1 higher than the output voltage V2 of the power factor correction circuit is applied to the power factor correction circuit (V1>V2), the normal power factor correction operation cannot be continued. Therefore, in the energization control circuit of this embodiment, when the output voltage V2 becomes higher than the predetermined reference voltage Vr, both the MOS transistors Q5 and Q6 are turned off to stop the power factor improvement operation. In addition, while the switch circuit S1 is turned off, the switch circuits S2 and S3 are controlled to be turned on.

As a result, the gate terminal G of the MOS transistor Q7 becomes lower in potential than the drain terminal D, the P-type MOS transistor Q7 is turned on, bypasses the choke coil L1, and passes through the MOS transistor Q7 to the load side. distribution will continue. In this uncontrolled power distribution, the choke coil L1 is bypassed, no current flows through the body diode of the transistor Q7 or the body diode of the transistor Q6, and the composite diode elements Db, Db Since no electric current flows through the capacitor, wasteful power consumption can be reliably suppressed. After that, when the output voltage V2 returns to the predetermined reference voltage Vr or less, the power factor improvement operation is resumed.

As described above, in this embodiment, wasteful power consumption is eliminated by first reducing the reactive power to zero through the power factor correction operation. In addition, in the power factor correction component PFC of the embodiment, the MOS transistor Q6 is placed where a diode should be used, and the switching operation is complementarily performed with the MOS transistor Q5 (synchronous rectification). Power consumption is reduced.

Furthermore, in this embodiment, when the input voltage V1>the output voltage V2, the power distribution operation is continued without control. power consumption can be extremely reduced.

By the way, as explained above, the power factor correction circuit of this embodiment functions at a maximum output current of about 7A. Therefore, the power consumption of the choke coil L1 can reach a level that cannot be ignored. Therefore, in this embodiment, the choke coil L1 is of a toroidal core type (see FIG. 6(f)), and a predetermined inductance value (40 μH in the embodiment) is secured by winding a winding around the toroidal core the required number of times N. are doing.

The inductance value of this type of choke coil is L=μSN ² /L corresponding to the magnetic permeability μ of the core, the core cross-sectional area S, the average circumferential length L of the core, and the number of turns N, and the winding diameter (diameter) Φ has no effect on the inductance value. On the other hand, the resistance value of the winding is inversely proportional to the cross-sectional area (the square of the winding diameter Φ), and the thinner the winding, the higher the resistance value. Therefore, in this embodiment, a required inductance value is ensured by winding a wire with a diameter of 1 mm or more around the toroidal core.

In general, the larger the winding diameter Φ is, the more preferable it is to reduce the resistance value. Incidentally, in this embodiment, the internal resistance of the choke coil L1 with an inductance value of 40 μH is suppressed to 15 mΩ by setting the winding diameter Φ=1.2 mm. Therefore, the voltage drop at the time of energization of 7A is suppressed to about 0.1V, and wasteful power consumption is suppressed to about 0.7W.

Next, the voltage monitoring circuit WTCH that monitors the power factor correction output V2 (the average value of the pulsating current is about 35 V) of the power factor correction circuit will be described with reference to FIG. The voltage monitoring circuit WTCH includes voltage dividing resistors R1 and R2 that divide the power factor correction output V2 by about 1/10 to generate a monitoring voltage Vs, and a first resistor that receives the monitoring voltage Vs at a non-inverting voltage terminal (+). and second comparators CM1 and CM2, a transistor TRm that turns ON when the power factor correction output V2 drops to the first level, a transistor TRs that turns ON when the power factor correction output V2 drops to the second level, and a transistor TRm. , and output L level monitoring signals Wm5 and Ws5. and output transistors TR4 and TR5.

As shown in FIG. 4A, the supervisory signals Wm12 and Ws12 are supplied to the soft start terminals SS of the DC/DC converters CV12m and CV12s that generate DC12V, and the supervisory signals Wm5 and Ws5 are supplied to the DC/DC converter that generates DC5V. It is supplied to soft start terminals SS of converters CV5m and CV5s. Here, each DC/DC converter CV12m, CV12s, CV5m, CV5s does not start the DC conversion operation until the voltage of each soft start terminal SS reaches a predetermined value (H level) from 0 V (L level). (soft-start operation). After starting the DC conversion operation, if the supervisory signals Wm12, Ws12, Wm5, and Ws5 drop from the H level to the L level, the DC conversion operation is stopped.

Returning to FIG. 7 and continuing the description, the first comparator CM1 receives a first reference voltage Vr1 generated by a shunt regulator (TL431AIPK) or the like at its inverting input terminal (-), and the second comparator CM2 A second reference voltage Vr2 obtained by dividing the first reference voltage Vr1 is configured to be received at the inverting input terminal (-). Although not particularly limited, in this embodiment, the first reference voltage Vr1 is 2.5 V, and the second reference voltage Vr2 is set to 1.97 V based on the voltage dividing ratio of the voltage dividing resistors R3 and R4. . As described above, the monitoring voltage Vs is about V2/10, so the first reference voltage Vr1 is about V2/14 with respect to the power factor correction output V2, and the second reference voltage Vr2 is V2/10. It becomes about 17.7.

Since the first reference voltage Vr1 and the second reference voltage Vr2 are at the above levels, if the power factor correction output V2 is at a normal level (about 35 V), both comparators CM1 and CM2 are connected to the non-inverting input terminal (+ ) becomes higher than the voltage (=V2/14, V2/17.7) of the inverting input terminal (-), and H level signals are output from the comparators CM1 and CM2. . Therefore, the PNP transistors TRm and TRs both maintain the OFF state, and correspondingly, the NPN transistors TR2 to TR5 all maintain the OFF state.

Thus, if the power factor correction output V2 is at a normal level (approximately 35V), all the transistors TR2 to TR5 are in the OFF state, so the DC/DC converters CV12m, CV12s, CV5m, and CV5s stop operating. Instead, the DC conversion operation continues.

On the other hand, when an abnormality occurs in the power factor correction circuit for some reason and the power factor correction output V2 falls below the 25V level (first level), the monitoring voltage Vs (=V2/10) drops below 2.5V. Since it falls below, the output of the comparator CM1 changes from the H level to the L level, and the transistor TRm transitions to the ON state. As a result, the transistors TR2 and TR3 both transition to the ON state, the monitor signals Wm5 and Ws5 become L level, and the DC/DC converters CV5m and CV5s stop operating. When the DC/DC converters CV5m and CV5s stop operating, the distribution of DC5V to the payout control board 25 and the effect interface board 22 is stopped.

However, before the monitoring voltage Vs (=V2/10) falls below 2.5 V, the photocoupler PH of the power supply monitor MNT (FIG. 3(b)) is turned off, and the power supply abnormality signal ABN has already reached the abnormal level. (L). Therefore, the backup process is completed in the payout control board 25 and the main control board 21 when DC5V power distribution is stopped when the DC/DC converters CV5m and CV5s stop operating. The voltage level of 5V DC is maintained for a predetermined period of time by the electrolytic capacitors arranged on the respective control boards 21 and 25. Therefore, even if the backup processing is not completed when the power distribution of DC 5V is stopped, there is no problem in backing up. Processing can be terminated.

As described above, DC 5V is used as the power supply voltage for the payout control board 25 and the one-chip microcomputer of the main control board 21, and the power supply voltage for the logic elements mounted on each control board. Also, after the DC 5V is level-dropped by the DC/DC converter of the effect interface board 22, the level-dropped voltages of various levels are used as the power supply voltages of various computer circuits.

Therefore, when the distribution of DC 5V is stopped, the logic elements mounted on each control board stop operating, and the control operation such as the output operation of the control signal is stopped. In addition, the reset circuits RST1 and RST2 mounted on the payout control board 25 and the main control board 21 function and the reset signal changes to the L level, so that the payout control board 25 and the main control board 21 that have completed the backup process One-chip microcomputer stops control operation. This point is the same for the computer circuit (composite chip 50, voice processor 27, etc.) that was executing the game control operation, and immediately stops the game control operation.

As described above, in this embodiment, when the power factor correction output V2 falls below the 25V level, the DC/DC converters CV5m and CV5s first stop operating. At the power supply voltage level, the possibility that the game control operation is continued is avoided. Such an operation is normally executed when the power is turned off. However, in this embodiment, the above-described operation can be performed even when the AC voltage of 24 V is at a normal level and only the power factor correction circuit is in an abnormal state. Advantageously, the action is performed.

The timing at which the power factor correction output V2 falls below 25V has been described above, but when the power is cut off or when the power factor correction circuit malfunctions, the level of the power factor correction output V2 continues to drop, and eventually reaches 19.7V ( 2nd level). Then, since the monitoring voltage Vs (=V2/17.7) falls below 1.97 V, the output of the comparator CM2 changes from the H level to the L level, and the transistor TRs transitions to the ON state. Therefore, the transistors TR4 and TR5 both transition to the ON state, the monitoring signals Wm12 and Ws12 become L level, and the DC/DC converters CV12m and CV12s stop operating.

As described above, the DC 12V is used as the drive power supply for the LED lamps and motors controlled by each control board, and as the power supply voltage for the digital amplifiers. Distribution of 12V DC is stopped. However, at this timing, the control operations of the LED lamp, the effect motor, and the digital amplifier are already in a stopped state, and since no control signal is transmitted from the logic element, unnatural lamp effects and motor effects , and no abnormal noise is generated from the speaker.

As described above, in this embodiment, prior to stopping the power distribution to the controlled object such as the performance motor, the control source such as the one-chip microcomputer stops the control operation, so that the power supply can be cut off smoothly. Moreover, even when only the power factor correction circuit malfunctions, a similar smooth operation termination operation is realized.

Next, FIG. 8A is a circuit diagram showing the internal configuration of a synchronous rectification type DC/DC converter CV5s that receives the pulsating current output V2 (average value 35V) of the power factor correction circuit and generates a DC voltage of 5V. be. Although not particularly limited, the DC/DC converter CV5s of this embodiment is configured by connecting a converter IC element (monolithic IC) CHP and related circuit components on the power supply board 20 . While the choke coil L5 and the smoothing capacitor C6 are arranged on the front side of the power supply board 20, all other circuit components, including the converter IC element CHP without a heat sink, are arranged on the back side of the power supply board 20. are doing.

This converter IC element CHP includes an oscillation section OSC that oscillates a system clock signal CLK, a ramp generation section RaGEN that generates a sawtooth wave (ramp wave), and a start control section SS that realizes an appropriate soft start operation when the power is turned on. , an error amplifier EAP that outputs a differential voltage between the comparison reference voltage (0.7 V) and the feedback voltage VFB, a PWM comparator PWMC that outputs a PWM wave based on the output of the error amplifier EAP, and a power factor correction output V2. A constant voltage section RG that receives and generates a reference voltage of 10 V, a comparison voltage generation section RFG that receives a power factor correction output V2 and generates various comparison voltages, and an H driver HDRV that drives the upper external MOS transistor QH. , an L driver LDRV that drives the lower external MOS transistor QL, and a driver control section DrCTL that controls the operations of the drivers HDRV and LDRV.

Here, not only the lower MOS transistor QL but also the upper MOS transistor QH of the external MOS transistors QH and QL are formed of N-type MOSFETs, thereby reducing wasteful power consumption. That is, in general, an N-type MOS transistor is less expensive than a P-type MOS transistor and has a lower on-resistance, so according to the configuration of this embodiment, power supply efficiency can be improved.

In addition to the above-described soft start function, the converter IC element CHP also has an overcurrent protection function, a short circuit protection function, an overheat cutoff protection function, and an under voltage lock out (UVLO) function. Moreover, the slope of the ramp wave and the frequency Fsw of the system clock can be set.

Specifically, by connecting a capacitor Cs with an appropriate capacitance to the SS terminal, the start of operation of the converter is waited until the capacitor Cs is charged to a predetermined level, suppressing the inrush current and suppressing the overcurrent. Avoiding shoots. In addition, the SS terminal is supplied with a monitoring signal Ws5, which becomes L level in the event of an abnormality, from the voltage monitoring circuit WTCH. there is

Also, the upper limit current can be set based on the resistance value of the resistor connected to the ILIM terminal, and the slope of the ramp wave can be set based on the resistance value of the resistor connected between the KFF terminal and the BP5 terminal. there is In this embodiment, the frequency Fsw of the system clock signal CLK can be set by the resistance value of the resistor connected to the RT terminal. In this embodiment, the system clock CLK is Fsw=200 kHz.

Corresponding to such an internal configuration of the converter IC element CHP, the VIN terminal is supplied with the power factor correction output V2, and the BP10 terminal is connected to an appropriate capacitor so that the BP10 terminal can be set to an accurate DC10V. maintain. Further, by connecting the bootstrap capacitor Cbt between the BOOST terminal and the WS terminal, the voltage between the BOOST terminal and the WS terminal is 10-Vf≈9 V corresponding to the forward voltage Vf of the internal diode Din. maintained to some extent. This bootstrap capacitor Cbt is a component of a charge pump booster circuit for turning on the upper N-type MOS transistor QH.

The HDRV terminal of the converter IC element CHP is connected via an appropriate resistor to the gate terminal of the upper MOS transistor QH, and the LDRV terminal is connected via an appropriate resistor to the gate terminal of the lower MOS transistor QL. Connected to the gate terminal. The SW terminal is connected to the source terminal of the upper MOS transistor QH. The PGND terminal is connected to the source terminal of the lower MOS transistor QL. A power factor correction output V2 is supplied to the drain terminal of the upper MOS transistor QH, and the drain terminal of the lower MOS transistor QL is connected to the source terminal of the upper MOS transistor QH.

Corresponding to such a configuration, the drain terminal of the lower MOS transistor QL and the source terminal of the upper MOS transistor QH are both connected to the SW terminal and connected to one terminal of the choke coil L5. there is The other terminal of the choke coil L5 is connected to the ground potential PGND terminal via a capacitor C6.

The voltage across the capacitor C6 is appropriately divided by the voltage dividing resistors RV1 and RV2 and supplied as the feedback voltage VFB to the VFB terminal of the converter IC element CHP. Then, the MOS transistors QH and QL are turned ON/OFF with a duty ratio such that the feedback voltage VFB matches the reference voltage 0.7V, thereby generating a DC voltage of a predetermined level. In this embodiment, the resistance ratio of the voltage dividing resistors is set so that 5×Rv2/(RV1+RV2)=0.7, so the output voltage is DC5V.

In FIG. 8A, the charging current of the choke coil L5 when the MOS transistor QH is ON and the MOS transistor QL is OFF is indicated by a solid line arrow. , and the discharge current of the choke coil L5 are indicated by dashed arrows. Also, FIG. 8(c) shows the charging current, discharging current and average current Io of the choke coil L5. Since an RC snubber circuit is connected between the drain terminal and the source terminal of the lower MOS transistor QL, ringing at the ON/OFF operation transition is preferably absorbed.

The larger the inductance value of the choke coil L5 described above, the smaller the ripple current, but the larger the size. On the other hand, if the inductance is small, the ripple current increases, so the capacitor C6 needs to have a large capacitance, and the size of the capacitor C6 must be increased. Therefore, in this embodiment, the inductance value of the choke coil L5 is set to 30 μH and the capacitance of the electrolytic capacitor C6 is set to 700 μF based on the above conditions and the clock frequency Fsw. The electrolytic capacitor C<b>6 has a columnar shape and stands on the surface side of the power supply substrate 20 .

By the way, the inductance value required for the choke coil L5 is uniquely determined based on the magnetic permeability μ of the core, the cross-sectional area S of the core, the number of turns N of the coil, and the like. Specifically, when a toroidal core is used, the inductance value is N ² μS/L corresponding to the average diameter L of the toroidal core, the cross-sectional area S of the toroidal core, and the number of turns N. , when a cylindrical core is used, the inductance value per unit length ignoring leakage flux is μSN ² corresponding to the cross-sectional area S of the cylindrical core and the number of coil turns N per unit length (Fig. 10 (a)). That is, in any case, the inductance value is uniquely determined based on the configuration of the core (μ and S) and the number of turns N of the coil winding wound around the core.

Therefore, the necessary inductance value can be any value whether a toroidal core is used (see FIGS. 6(f) and 8(b)) or a cylindrical core is used (see FIG. 10(a)). You will be able to obtain However, since a large DC current Io steadily flows through the choke coil L5, even if the number of turns N is the same, the power loss varies greatly depending on the diameter of the winding. Therefore, in this embodiment, when a large current is not required, winding a winding with a diameter Φ<0.5 mm around the cylindrical core (compact configuration 1) reduces the size of the choke coil and reduces the manufacturing cost. (See FIG. 10(a)). On the other hand, when a large current is required, using a winding with a diameter Φ≧0.5 mm for the toroidal core (large configuration 2) reduces the power loss. Reduction is attempted (see FIGS. 6(f) and 8(b)).

When the small configuration 1 is adopted, the DC resistance of each choke coil is 30 mΩ or more (preferably 120 mΩ or less), and when the large configuration 2 is adopted, the DC resistance of each choke coil is less than 30 mΩ.

Based on the above design concept, in this embodiment, the DC/DC converters CV12m and CV5m for generating the DC voltage (12V, 5V) distributed toward the payout control board 25 via the first connector Main, In order to reduce the manufacturing cost, an asynchronous rectification method is adopted, and a choke coil having a compact configuration (1) shown in FIG. 10(a) is used. On the other hand, the DC/DC converters CV12s and CV5s that generate the DC voltage (12V, 5V) that is distributed to the presentation interface board 22 via the second connector Sub adopt a synchronous rectification method and consume power. Giving the highest priority to reducing the noise, the choke coils of the large configuration (2) shown in FIGS. 8(b) and 9(b) are used. It should be noted that the choke coil is erected on the surface side of the power supply substrate 20 regardless of which configuration is adopted. These points are the same for the choke coil L1 (FIG. 6(f)) used in the power factor correction circuit, which is a choke coil of the large configuration (2), which stands on the surface side of the power supply board 20. It is

Continuing the specific description, the choke coil L5 shown in FIG. 8(b) is configured by winding a wire with a wire diameter of 0.90 mm around a toroidal core based on the large configuration (2). The winding resistance in this case is about 20 mΩ at an inductance value of 30 μH, and power consumption can be effectively suppressed. In addition, since the synchronous rectification method is adopted and the MOS transistor QL is used, power consumption can be significantly reduced compared to the case where a rectifier diode is used at this location.

In this embodiment, the output of the DC/DC converter CV5s is not only the power supply voltage of the logic elements mounted on the production interface board 22 and the production control board 23, but also the power supply voltage of the voice processor 27 and the composite chip 50. Since the base voltage is (3.3V/1.5V/1.05V), the average current Io of the choke coil L5 is about 4.3A. In addition, in order to enrich the effect control, it is necessary to design a maximum average current of about 5A. extremely large.

Incidentally, if the winding diameter is halved, the winding resistance will be quadrupled, so if Io=5 A, the wasted power consumption of the choke coil L5 is 0.5 W (watts) in this embodiment. will further increase by 1.5 W (=5*5*20/1000*3). Also, if a rectifier diode is used instead of the MOS transistor QL, wasteful power consumption corresponding to the forward voltage drop Vf (≈1 V) and the average duty ratio of the PWM wave (τ≈5/35) 1×4.3×(1−τ)≈1×4.3×0.86=3.7W.

Next, FIG. 9(a) is a circuit diagram showing the internal configuration of a synchronous rectification type DC/DC converter CV12s that generates a DC voltage of 12V to be distributed to the presentation interface board 22. As shown in FIG. The basic configuration and operation contents are the same as those of the DC/DC converter CV5s shown in FIG. Considered special configuration is required.

First of all, the DC12V generated by the DC/DC converter CV12s not only drives a large number of LED lamps and production motors that make up the board-side member, but also digital It also serves as the power supply voltage for the amplifier. In addition, since the LED lamps and effect motors arranged on the front door members such as the glass door 6 and the front plate 7 are also driven via the third connector Aux, a driving current of about 13 A is required as a whole.

Therefore, in this embodiment, considering that the current flowing through the MOS transistors QH and QL is large, the necessary circuit components are not directly soldered to the power supply board 20, but are mounted on another board (circuit board or is an insulating substrate), the necessary circuit parts are attached, and the whole is resin-molded to complete a DC/DC converter for 12V. That is, the DC/DC converter CV12s is configured as a composite third circuit component CV12s in which the converter IC element CHP shown in FIG. 8A is integrated with related external components.

Thus, in this embodiment, since the converter IC element CHP and related external parts are arranged on a separate substrate and the whole is molded, it is not always necessary to connect the circuit parts with wiring patterns. Gone. In this composite third circuit component CV12s, components are connected to each other in the shortest possible manner by wiring cables of optimum thickness, and by reducing wiring resistance, wasteful power consumption is effectively suppressed. The composite third circuit component CV12s also has the same appearance as the composite first circuit component RECT and the composite second circuit component PFC, and is formed in a thin plate shape of about 40 mm×30 mm×8 mm, for example.

In addition, in order to realize electromagnetic shielding together with the heat radiation effect of the MOS transistors QH and QL, the composite third circuit component CV12s is an integrated circuit component accommodated in the conductive electromagnetic shield box SH shown in FIG. 9(d). As such, the use of a heat sink is made unnecessary. The electromagnetic shield box SH shown in FIG. 9(d) has the same configuration as that described with reference to FIG. 6(c), and is formed of a rectangular conductor box of approximately 31 mm×65 mm×12 mm. In order to ensure electromagnetic shielding, the blocking surface FT of the electromagnetic shield box SH is erected facing the choke coil L3. In addition, the electromagnetic shield box SH is connected to the ground line of the power supply board 20 in order to achieve an electrostatic shielding effect as well.

As shown in FIG. 9C, the composite third circuit component (DC/DC converter CV12s) has a total of 13 circuit connection bars aligned in a line and protruding from the component body in a substantially orthogonal state. The thirteen circuit connection bars include three input terminal IN groups, four output terminal OUT groups, and three ground terminal GND groups. The FB terminal is connected to the VREF terminal of the converter IC element CHP via a voltage dividing resistor RV1, and the Rref terminal and ON/OFF terminal are connected to the VFB terminal and SS terminal of the converter IC element CHP, respectively. Connected in a one-to-one relationship.

In the composite third circuit component, the circuit connection bars in each group are either round bars or flat plates, and their diameter Φ and plate width WD are about 1 mm (Φ=WD=0.6 ~1.5 mm). In addition, the circuit connection bars in each group are aligned at a uniform pitch Pi of 2 mm or more (preferably about 2 to 3 mm), and the circuit connection bars in each group maintain the uniform pitch Pi. , are inserted from the front side of the power supply board 20 in a state substantially orthogonal to the power supply board 20, and are soldered to the circuit pattern lands corresponding to each group on the front and rear surfaces thereof.

In the composite third circuit component as well, the circuit pattern lands are formed with a sufficient plane width that does not fall short of the maximum separation distance between the circuit connection bars belonging to each group, and a current of 1 A is applied to the conductor surface with a pattern width of 1 mm. A predetermined film thickness is formed by selecting a material that does not cause any problem of power loss even when the film is flown. For example, the circuit pattern land corresponding to the output terminal OUT group is formed with a planar width exceeding 4×Pi corresponding to four circuit connection bars. In addition, the circuit pattern land has a minimum width (4×Pi) at the connection point with the circuit connection bar, and is formed with a pattern width substantially equal to or larger than the minimum width at the other portions.

Therefore, the circuit pattern land corresponding to the output terminal OUT group is, for example, 4×Pi (10 mm) or more when Pi=2.5 mm, and a steady current of 10 A or more is sufficiently allowed. . The output current of the DC/DC converter CVs12 of this embodiment is, for example, about 13 A at maximum, and in this case it feels a little insufficient, but the maximum current flow time is at most 10 seconds. So it doesn't really matter.

The circuit operation is substantially the same as that of the DC/DC converter CV5s shown in FIG. CV12s are functioning. Note that the voltage dividing resistors RV1 and RV2 are defined to maintain the output voltage at 12 V, and in the circuit shown in FIG. , RV2 are set. Also, based on the internal clock frequency Fsw of the converter IC element CHP, etc., the inductance value of the choke coil L3 is set to 70 μH, and the electrostatic capacitance of the electrolytic capacitor C4 is set to 1400 μF. Note that the capacitance of 1400 μF is realized by erecting two cylindrical electrolytic capacitors of 700 μF on the surface side of the power supply substrate 20 .

By the way, the output of the DC/DC converter (composite third circuit component) CV12s becomes a power source for driving a large number of high-brightness LEDs via the second connector Sub and the third connector Aux. drive voltage. When all the performance motors are operated simultaneously, the consumption current increases to, for example, 14 A or more, but this is too much power consumption and may exceed the capacity of the power distribution system of the game hall.

Therefore, in this embodiment, by appropriately allocating the performance timing of each performance motor, etc., the performance contents of the movable performance and the lamp performance are designed so as not to exceed the limit current I _max (for example, 13 A) even at the maximum time. Also, the maximum value I _m2 of the current I _S2 supplied from the second connector Sub and the maximum value I _m3 of the current I _A3 supplied from the third connector Aux are defined as I _m2 =8 A and I _m3 =6 A, respectively. In addition, the effect is designed so that the total current I _S2 +I _A3 supplied from the DC12V terminals of the second connector Sub and the third connector Aux does not exceed the limit current I _max in any operation. That is, I _S2 <I _m2 (=for example, 8 A) and I _A3 <I _m3 (=for example, 6 A), and I _S2 +I _A3 <I _max (=for example, 13 A) It stipulates the content of the production.

Even if the current distribution is suppressed as described above, the DC/DC converter CV12s must output a maximum of 13 A, so wasteful power consumption in the choke coil L3 becomes a problem. Therefore, as shown in FIG. 9(b), a thick wire with a diameter of about 1.0 mm is wound around the toroidal core the required number of times to achieve an inductance value of about 70 μH (large configuration (2)). . By using a large-diameter winding, the resistance value can be suppressed to about 25 mΩ, and power loss is suppressed to about 4 W when the limit current I _max (=13 A) flows. The DC/DC converter CV12s of the embodiment employs a synchronous rectification method. , the wasteful power consumption at the time of distribution of the limit current I _max reaches 1×13×(1−τ)≈1×13×0.66=8.5W, where Vf=1.0V.

Next, an asynchronous rectification type DC/DC converter will be described with reference to FIG. FIG. 10(b) shows a DC/DC converter CV12m that drops the power factor correction output V2=35V to output DC12V, and FIG. 10(c) shows the circuit configuration of the DC/DC converter CV5m that outputs DC5V. showing. As shown in FIG. 4, the output (12V/5V) of the DC/DC converter CV12m and the DC/DC converter CV5m is first distributed to the payout control unit 25 via the first connector Mian, and then the payout control Power is distributed from the unit 25 to the main control board 21 .

The 5V DC is used as the power supply voltage for the logic elements of the control boards 25 and 21 and for the one-chip microcomputer, but a total current of about 0.5A is sufficient for the 5V DC lines. On the other hand, DC 12V is used as a driving voltage for a payout motor, a solenoid for opening and closing a variable winning device, etc., but since it does not drive that many, about 1A is sufficient.

Therefore, in this embodiment, in consideration of the above points, an asynchronous rectification type DC/DC converter is adopted in order to suppress the manufacturing cost and reduce the size of the circuit board. Further, as shown in FIGS. 10(b) and 10(c), both DC/DC converters CV12m and CV5m are configured using a converter IC element SRG (step-down switching regulator) shown in FIG. 10(d). It is Note that the converter IC element SRG is classified as a monolithic IC.

The voltage dividing ratio of the voltage dividing resistors RA1 and RA2 of the DC/DC converter CV12m that outputs DC12V and the voltage dividing ratio of the voltage dividing resistors RB1 and RB2 of the DC/DC converter CV12m that outputs DC5V are different from each output voltage level ( 12V/5V). Specifically, both 12×RA2/(RA1+RA2) and 5×RB2/(RB1+RB2) are set to match the comparison reference voltage ReV of the converter IC element SRG.

As shown in FIG. 10(d), the converter IC element SRG includes a power supply section PReg that generates voltages for each section based on the voltage received at the IN terminal, and a soft start operation and an emergency stop operation based on the control signal received at the SS terminal. A startup control unit Soft & ON/OFF, an overcurrent protection unit Overcurrent Protection, a heating protection unit Thermal Protection, an oscillation unit OSC that oscillates a pulse wave of about 300 KHz, and a reset unit Rset that detects power-on. , an error amplification unit ErAmp that compares the detected voltage received at the ADJ terminal with the comparison voltage ReV and outputs an error voltage; a PWM comparator COMP that outputs a PWM wave based on the output of the oscillator OSC and the error voltage; and a drive control section Latch & Driver for controlling ON/OFF of the output transistor TRsw based on the control signal.

Both DC/DC converters CV12m and CV5m are of the asynchronous rectification type, and choke coils L2/L4 and smoothing capacitors C3/C5 are connected in series between the SW terminal and the GND terminal, and a rectifier diode Dcv is connected. ing. As indicated by the solid line in FIG. 10(b), when the output transistor TRsw is ON, the coil charging current flows through the path of choke coil L2→smoothing capacitor C3→ground. Further, as indicated by the dashed line in FIG. 10B, when the output transistor TRsw is turned off, a coil discharge current flows through the path of choke coil L2→smoothing capacitor C3→rectifier diode Dcv.

In this way, the coil discharge current flows through the rectifier diode with a forward voltage Vf of about 0.7 to 1.0 V. Therefore, corresponding to the average coil current Io and the average duty ratio τ of the PWM wave, the power consumption is Io×Vf×(1−τ). However, if the output current of the DC/DC converter CV12m is 2A and the output current of the DC/DC converter CV5m is 1A, the power consumption will be 2×1×(1-12/35 )=1.3 W and 1.times.1.times.(1-5/35)=0.86 W, which is not so much, and there is no particular problem in adopting the asynchronous rectification method.

However, there is a risk of thermal runaway of the output transistor TRsw due to heat generated by the current (2A/1A) flowing through the output transistor TRsw. In addition, there is a risk that the overcurrent protection unit Overcurrent Protection will function and the DC conversion operation will be stopped in an emergency. Therefore, in this embodiment, the above problem is prevented by attaching the required heat sink to each converter IC element SRG. Further, the converter IC elements forming the DC/DC converters CV12m and CV5m are erected on the surface side of the power supply board 20 while holding the heat sink.

As described above, in the case of the embodiment, the total current of the DC5V line is about 0.5A, and the total current of the DC12V line is about 1A. However, different models may have different numbers of variable prize winning openings and game ball guide devices arranged on the game board surface. Thus, the DC/DC converter CV12m requires a current upper limit of about 2A, and the DC/DC converter CV5m requires a current upper limit of about 1A.

However, with this level of current upper limit, the power loss in the choke coils L2/L4 is not a problem, as will be explained below. A necessary inductance value is realized by winding (compact configuration (1) in FIG. 10(a)). In the compact configuration (1), the central core is surrounded by a cylindrical outer core in order to minimize leakage flux. When adopting such a configuration, ignoring leakage flux, the inductance value per unit length is N ² μS corresponding to the cross-sectional area S of the central core, the magnetic permeability μ of the core, and the number of turns N per unit length. Become.

To explain the compact configuration (1) of this embodiment in detail, the choke coil L2 used in the DC/DC converter CV12m that generates 12V DC uses a winding with a diameter of about 0.3mm to achieve an inductance value of 45μH. However, the winding resistance was about 90 mΩ. In this embodiment, since the current upper limit value of the DC12V line is set to 2A, the power loss in the choke coil L2 is about 0.36W, which poses no particular problem. The smoothing capacitor C<b>3 is specifically a cylindrical electrolytic capacitor of 700 μF, and is erected on the surface side of the power supply substrate 20 .

On the other hand, the choke coil L4 used in the DC/DC converter CV5m that generates DC5V realized an inductance value of 20µH by using a winding with a diameter of about 0.4mm, but the winding resistance was about 40mΩ. In this embodiment, the current upper limit of the DC5V line is set to 1A, so the power loss in the choke coil L4 is about 0.04W, which poses no problem. The smoothing capacitor C<b>5 is specifically a cylindrical electrolytic capacitor of 700 μF, and is erected on the surface side of the power supply substrate 20 .

The circuit configuration of the power supply board 20 has been described in detail above. Surface-mounted components are placed on the back side for surface-mounting. Here, the surface-mounted products include Zener diodes and rectifier diodes. In this embodiment, all Zener diodes and rectifier diodes (excluding the composite first circuit component RECT) are mounted on the back side of the power supply substrate 20. is surface-mounted.

FIG. 11 illustrates the back side of the power supply board 20, and shows each part circuit mainly composed of surface-mounted components. First, a thermistor circuit composed of a thermistor TH and a switch circuit SW that bypasses the thermistor is arranged on the back surface of the power supply substrate 20 . Further, the voltage monitoring circuit WTCH is composed only of mounted parts, and all the parts are surface-mounted on the back surface of the power supply board.

Next, the energization cutoff circuit CUT, except for the film capacitor Cbr, the current limiting resistor R, and the electrolytic capacitor Crec, is a surface-mounted product, and is arranged on the back surface of the power supply substrate 20 . On the other hand, the film capacitor Cbr, the current limiting resistor R, and the electrolytic capacitor Crec are inserted and mounted on the surface side of the power supply board 20 close to the arrangement position of the surface-mounted components that constitute the energization cutoff circuit CUT.

Similarly, the synchronous rectification type DC/DC converter CV 5 s is composed of surface-mounted components except for the choke coil L5 and the electrolytic capacitor C6 which are inserted and mounted on the surface side of the power supply board 20. Components are surface-mounted on the back surface of the power supply board 20 . The asynchronous rectification type DC/DC converters CV12m and CV5m are also composed of surface-mounted components except for the choke coils L2/L4 and the electrolytic capacitors C3/C5 inserted and mounted on the surface side of the power supply board 20. All surface-mounted components are surface-mounted on the back surface of the power supply board 20 .

By the way, pattern lands having a pattern width corresponding to the value of the current flowing therethrough are formed vertically and horizontally on the front and back sides of the power supply board 20 . As described above, in this embodiment, even if a current of 1 A flows through a conductor surface with a pattern width of 1 mm, power loss does not pose a problem at all. However, in order to reduce wasteful power consumption, it is also necessary to reduce the contact resistance in the first connector Main, the second connector Sub, and the third connector Aux, and the power loss in the feed line.

Therefore, in this embodiment, the connector terminals, the connector terminals, and the wiring cables connected to the connector terminals each have a resistance value that does not pose a problem of power loss even if a current of about 3 A flows therethrough. Further, when a large current exceeding 3 A is supplied, the supply is shared by a plurality of connector terminals, and specific connector terminals are connected in parallel to a common pattern land.

Each connector will be described below. The connector terminals of the first and second connectors Main and Sub are arranged in two rows as shown in FIG. 12(a), and the connector terminals of the third connector Aux are arranged in one row. However, in either case, the arrangement pitch Pi of the connector terminals is set to about 2.0 mm in the lateral direction of the drawing.

For the sake of convenience, the connector terminals are numbered serially below. For the first connector Main and the second connector Sub, the odd-numbered and even-numbered connector terminals are separated from the adjacent numbered connector terminals by about 2.0 mm. They are inserted and mounted from the front side of the power supply board 20 in a state in which they are arranged in a row at the same arrangement pitch Pi. Six connector terminals of the third connector Aux are also inserted and mounted from the surface side of the power supply substrate 20 in a state of being aligned in a row at the arrangement pitch Pi.

First, describing the first connector Main, as described above, DC5V/DC12V/DC35V is distributed to the payout control board 25 via the first connector Main. In this embodiment, based on the configuration of the DC/DC converters CV5m and CV12m and the number of LED lamps and solenoids, a maximum current of about 2 A flows in the DC5V line and a maximum current of about 1A flows in the DC12V line. There is In addition, since the DC35V line is used for the firing solenoid and the ball feed solenoid, a maximum of about 1A flows.

Therefore, in consideration of the above-mentioned current amount, in order to distribute the power with a sufficient margin, the voltage of each level is applied to each of two connector terminals selected from adjacent even-numbered terminals and two distribution cables corresponding to these terminals. is distributed in Although one connector terminal is sufficient for each voltage level, by selecting a pair of adjacent connector terminals (total width of about 3 mm between terminals), the pattern width of the corresponding circuit pattern land is matched. be able to. In addition, since transmission loss decreases as the number of used cables increases, it is preferable to use as many connector terminals and wiring cables as possible.

From this point of view, the number of connector terminals equal to or greater than the total number of power distribution lines of each voltage level (5/12/35) is used as the ground line. Specifically, as shown in FIG. 12B, 8 connector terminals (ground terminals), which are 2×3=6 or more, are connected to the ground line (circuit pattern land) of the power supply substrate 20. ing.

Next, the second connector Sub will be described. In the present embodiment, maximum currents of 5 A/13 A/4 A are planned for the 5 V DC/12 V DC/35 V DC power distribution lines passing through the second connector Sub. Therefore, in order to distribute power with a sufficient margin, the voltage of each level is distributed by a plurality of connector terminals selected from adjacent even-numbered terminals or odd-numbered terminals and a plurality of wiring cables corresponding to these terminals. The 35V DC is distributed via the performance interface board 22 and serves as a drive power source for an electromagnetic solenoid that reciprocates the movable object.

Specifically, the DC5V power distribution line is composed of three connector terminals, Nos. 3, 5, and 7, and their corresponding wiring cables, while the DC12V power distribution line is composed of Nos. 8 and 10. , 12, and 14, and wiring cables corresponding to these terminals. The three connector terminals forming the DC5V power distribution line are all odd-numbered and adjacent to each other (there is no other connector terminal interposed). The overall width of the three connector terminals is about 5 mm, and they are connected to one corresponding circuit pattern land.

The same applies to the four connector terminals constituting the 12 VDC power distribution line, all of which are even-numbered and adjacent to each other (no other connector terminals intervene). The overall width of the four connector terminals is about 7 mm, and they are connected to one corresponding circuit pattern land. The two connector terminals forming the 35V DC line are adjacent to each other as odd-numbered terminals (no other connector terminal intervenes), and are connected to one corresponding circuit pattern land.

Corresponding to the above configuration, more connector terminals than the total number of power distribution lines of each voltage level (5/12/35) are used as ground lines. Specifically, as shown in FIG. 12C, the same 10 connector terminals (ground terminals) of 3+5+2=10 or more are connected to the ground line of the power supply substrate 20 .

On the other hand, since the third connector Aux is not arranged in two rows, three of Nos. 1 to 3 are DC12V power distribution lines and three of Nos. 4 to 6 are ground lines. As described above, in this embodiment, in order to distribute power with a sufficient margin, each of the 5V DC and 12V DC power distribution lines passing through the first connector Main is realized using two or more connector terminals. Each of the 5V DC and 12V DC power distribution lines passing through the Sub is implemented using three or more connector terminals. Also, the number of ground terminals is equal to or greater than the total number of connector terminals constituting the power distribution line (including the same number). In other words, the number of ground terminals is equal to or greater than half of the total number of connector terminals of each connector.

Since the power supply board 20 has been described in detail above, returning to FIG. 3A, another configuration of the gaming machine GM will be described. As shown in FIG. 3A, the effect interface board 22 is equipped with a sound circuit SND such as a sound processor 27, and the effect control board 23 is equipped with computer circuits such as a VDP circuit 52 and a built-in CPU circuit 51. A combined chip 50 is mounted. Hereinafter, the built-in CPU circuit may be abbreviated as a CPU circuit.

The performance interface board 22 is equipped with reset circuits RST3 and RST4 for detecting an increase in the power supply voltage and generating various reset signals RT3 and RT4 when the power is turned on. First, the reset circuit RST3 generates a reset signal RT3 based on the DC voltages of 12V and 5V distributed from the power supply board 20. FIG. The reset signal RT3 resets only the voice memory 28 and is transmitted to the effect control board 23 as it is.

As shown in FIG. 13(a), the reset signal RT3 transmitted to the effect control board 23 is AND-operated with the output of the WDT (Watch Dog Timer) circuit 58 in the AND gate G1, and is output to the CPU circuit as the system reset signal SYS. 51 and the VDP circuit 52 are reset (see FIGS. 13(a) and 13(d)).

After the power is turned on, the reset signal RT3 generated by the reset circuit RST3 maintains the L level for a predetermined time as a power reset signal, and then rises to the H level. However, if one or more of the DC voltage of 12 V or DC voltage of 5 V subsequently drops (usually when power is cut off), the system reset signal SYS also drops to L level in response to the level drop of the reset signal RT3. As a result, the CPU circuit 51 and the VDP circuit 52 of the effect control board 23 are put into a non-operating state.

Since this system reset signal SYS also changes based on the output of the WDT circuit 58 (which is normally H level), the output of the WDT circuit 58 may change when the reset signal RT3=H due to program runaway or the like. In response to the drop to L level, the system reset signal SYS also changes to L level to abnormally reset the CPU circuit 51 and VDP circuit 52 (see FIG. 13(d)).

On the other hand, the reset circuit RST4 generates a reset signal RT4 based on 3.3V generated by dropping the 5V distributed from the power supply substrate 20 . This reset signal RT4 resets the power of the audio processor 27 as a power reset signal when the power is turned on.

As illustrated, the reset circuit RST4 is also supplied with the system reset signal SYS sent back from the performance control board 23, so that when the CPU circuit 51 or the VDP circuit 52 is abnormally reset, the system is synchronized with the abnormal reset of these circuits. Then, the audio processor 27 is also abnormally reset. As a result, the sound effect returns to the initial state together with the image effect and the lamp effect, and there is no possibility that the unnatural sound effect will continue.

Next, reset circuits RST1 and RST2 are mounted on the payout control board 25 as the frame-side member GM1 and the main control unit 21 as the board-side member GM2, respectively. A computer circuit is configured to be power reset.

Thus, in this embodiment, the reset circuits RST1 to RST4 are arranged in the main control section 21, the payout control section 25, and the effect interface board 22, respectively, and the system reset signal SYS is generated between the circuit boards. never transmitted. That is, since there is no wiring cable for transmitting the system reset signal SYS, the risk of abnormal resetting of the computer circuit due to noise superimposed on the wiring cable is eliminated.

However, the reset circuits RST1 and RST2 provided in the main control unit 21 and the payout control unit 25 each incorporate a watchdog timer, and do not receive regular clear pulses from the CPUs of the control units 21 and 25. If so, each CPU is forced to reset.

Further, the main control unit 21 is provided with an initialization switch SW that can be operated by a staff member. It is configured. This RAM clear signal CLR is transmitted to the one-chip microcomputers of the main control unit 21 and the payout control unit 25, and determines whether or not to initialize the entire area of the built-in RAM of the one-chip microcomputers of the control units 21 and 25. ing.

In addition, as described above, the one-chip microcomputer of the main control unit 21 and the payout control unit 25 receives the power failure signal ABN from the power supply monitor MNT arranged in the payout control unit 25, thereby to initiate the necessary termination processing.

As shown in FIG. 3A, the main control unit 21 receives, from the payout control unit 25, a winning ball count signal indicating the payout operation of game balls, a status signal CON related to an abnormality in the payout operation, and an operation start signal BGN. receiving. The status signal CON includes, for example, a supply shortage signal, a dispensation shortage error signal, and a lower tray full signal. The operation start signal BGN is a signal that notifies the main control unit 21 that the initial operation of the payout control unit 25 has been completed after the power is turned on.

In addition, the main control unit 21 receives switch signals from detection switches built into the winning holes 16 to 18 on the game board, and drives solenoids such as electric tulips. Solenoids and detection switches are configured to operate with the power supply voltage VB (12 V) distributed from the main control unit 21 . In addition, each switch signal indicating the winning state to the symbol start port 15 is converted into a switch signal of TTL level or CMOS level by an interface IC that operates with power supply voltage VB (12V) and power supply voltage Vcc (5V). After that, it is transmitted to the main control unit 21 .

As described above, the effect interface board 22 receives DC voltages (5V, 12V, 35V) of various levels from the power supply board 20 via the central connection connector C2 (FIGS. 3A and 3B). 13(a)). A DC voltage of 12V is used as a power supply voltage for the digital amplifier 29 and as a drive voltage for LED lamps and the like. In addition, the DC voltage of 35V is used as a drive voltage for a solenoid that is distributed to appropriate places in the game frame and reciprocates the movable object.

On the other hand, the DC voltage of 5V is supplied as a power supply voltage for circuit elements in various locations on the production interface board 22, and is also supplied to two DC/DC converters DC1 and DC2 to generate 3.3V and 1.0V ( See FIG. 13(a)). The generated DC voltages of 3.3 V and 1.0 V are supplied to the audio processor 27 as power supply voltages for I/O (input/output) and chip core, respectively. Also, the DC voltage of 3.3 V is the base voltage of the power reset signal RT4 generated by the reset circuit RST4.

The DC voltage of 5V distributed to the effect interface board 22 is distributed to the effect control board 23 together with 3.3V generated by the DC/DC converter DC1. Then, the DC voltage of 3.3V distributed to the performance control board 23 is supplied to the composite chip 50, the PROM 53 and the CGROM 55 as a power supply voltage.

As shown in FIG. 13(a), two DC/DC converters DC3 and DC4 are arranged on the effect control board 23, and 1.5V and 1.05V based on the DC voltage 5V supplied to each. is generating Here, the DC voltage of 1.05 V is the power supply voltage for the chip core of the composite chip 50 , and the DC voltage of 1.5 V is the power supply voltage for I/O (input/output) with the DRAM 54 . Therefore, the DC voltage of 1.5 V is also supplied to the DRAM 54 as a power supply voltage.

As shown in FIG. 3( a ), the effect interface board 22 receives the control command CMD and the strobe signal STB from the main control section 21 and transfers them to the effect control board 23 . More specifically, as shown in FIG. 13(a), the control command CMD and strobe signal STB are transferred to the composite chip 50 (CPU circuit 51) of the effect control board 23 via the input buffer 40. . Here, the strobe signal STB is the received interrupt signal IRQ_CMD, and the effect control CPU 63 acquires the control command CMD based on the interrupt processing program (interrupt handler) started upon receiving the received interrupt signal IRQ_CMD.

As shown in FIG. 13(a), the input buffer 44 of the effect interface board 22 receives the switch signals of the chance button 11 and volume switch VLSW from the frame relay board 36, and outputs each switch signal to the CPU circuit 51 of the effect control board 23. is transmitting to Specifically, the 3-bit length of the encoder output indicating the contact position (0 to 7) of the volume switch VLSW and the 1-bit length indicating the ON/OFF state of the chance button 11 are transmitted to the CPU circuit 51 .

The effect interface board 22 is connected to a lamp drive board 30 and a motor/lamp drive board 31 , and is also connected to a motor/lamp drive board 37 via a frame relay board 36 . As shown, an output buffer 42 is arranged corresponding to the lamp driving board 30 , and an input buffer 43 a and an output buffer 43 b are arranged corresponding to the motor/lamp driving board 31 . Note that in FIG. 4A, the input buffer 43a and the output buffer 43b are collectively referred to as an input/output buffer 43 for the sake of convenience. The input buffer 43a receives the outputs SN0 to SNn of the origin sensors for grasping the current positions of the characters as movable effects (rotational positions of the effect motors M1 to Mn), and transmits the outputs to the CPU circuit 51 of the effect control board 23. there is

The lamp driving board 30, the motor/lamp driving board 31, and the motor/lamp driving board 37 are equipped with the same kind of driver ICs, and the effect interface board 22 receives the serial signal from the effect control board 23, It is transferred to each driver IC. Specifically, the serial signals are a lamp (motor) drive signal SDATA and a clock signal CK. , the performance motors M1 to Mn perform a role performance.

In the case of this embodiment, the lamp effect is executed by the three lamp groups CH0 to CH2, and the motor/lamp drive board 37 outputs the lamp drive signal SDATA0 of CH0 via the frame relay board 36 as a clock. It is received in synchronization with the signal CK0. A series of lamp drive signals SDATA0 transmitted as a serial signal are output from the driver IC to the lamp group CH0 at the timing when the operation control signal ENABLE0 changes to the active level, thereby updating the lighting state all at once.

The above points also apply to the lamp drive board 30. The driver IC of the lamp drive board 30 receives the lamp drive signal SDATA1 of the lamp group CH1 in synchronization with the clock signal CK1, and the operation control signal ENABLE1 is at the active level. , the lighting state of the lamp group CH1 is updated all at once.

On the other hand, the driver IC mounted on the motor/lamp drive board 31 receives the lamp drive signal transmitted in clock synchronization to drive the lamp group CH2, and receives the motor drive signal transmitted in clock synchronization. , drives a group of effect motors M1 to Mn, which are composed of a plurality of stepping motors. The lamp driving signal and the motor driving signal are a series of serial signals SDATA2, which are serially transmitted in synchronism with the clock signal CK1. , the driving states of the lamp group CH2 and the motor groups M1 to Mn are updated.

Next, the audio circuit SND will be explained. As shown in FIG. 13(a), the effect interface board 22 includes a voice processor (sound synthesis circuit) 27 for reproducing voice signals based on instructions received from the CPU circuit 51 (effect control CPU 63) of the effect control board 23. , an audio memory 28 for storing compressed audio data, which is the original data of the audio signal to be reproduced, and a digital amplifier 29 for receiving the audio signal output from the audio processor 27 are mounted.

The voice processor 27 includes a WDT circuit that automatically resets the set value of the internal circuit to a default value (initial value) when the internal circuit malfunctions, and a voice control register SRG. Then, the audio processor 27 accesses the audio memory 28 based on the operation parameters (set values by the audio commands) received from the effect control CPU 63 to the audio control register SRG, and reproduces and outputs the necessary audio signals. .

As shown in FIG. 13A, the audio processor 27 and the audio memory 28 are connected by a 26-bit audio address bus and a 16-bit audio data bus. Therefore, the audio memory 28 can store data of 1 Gbit (=2 ²⁶ *16).

The voice control register SRG is divided into register banks 1 to 6, which are specified by register numbers 00H to FFH, respectively. Therefore, the predetermined setting operation is realized by specifying the register bank and then writing the operation parameter of 1 byte length to the voice control register SRG of the predetermined register number (1 byte length) by the effect control CPU 63. be.

In the case of this embodiment, the register numbers (00H to FFH) of the voice control register SRG correspond to the address space CS3 of the effect control CPU 63. For example, the voice control register SRG of the register number XXH is set to the operating parameter YYH. In this case, the effect control CPU 63 writes XXH to the zero address of the address space CS3, and then writes YYH to the first address. That is, the effect control CPU 63 writes XXH and YYH to the data bus in this order. In this specification, the subscript H and the prefixes 0X/0x indicate that the numerical values are represented in hexadecimal notation.

Further, in this specification, the address spaces CS0 to CS7 refer to external memories for the CPU circuit 51 that can respectively define the memory type including the presence or absence of volatility and the data bus width (8/16/32 bits). means (excluding internal memory). These address spaces CS0-CS7 are selected by different chip select signals CS0-CS7, and are configured so that the READ/WRITE control signals that function during READ/WRITE access can be optimized according to the memory type. Note that this setting operation is executed for the bus state controller 66 .

FIG. 13(e) illustrates the setting operation to the voice register SRG by the effect control CPU 63, and shows the contents of the 2-bit length address bus A1-A0 and the 1-byte length data bus D7-D0. there is In this embodiment, the chip select signal CS3 is set at power-on so as to automatically become active when accessing the address space CS3, which will be described later with reference to FIGS. 15 and 21. FIG.

In any case, in the case of this embodiment, the compressed audio data stored in the audio memory 28 is phrase compressed data specified by a 13-bit length phrase number NUM (000H to 1FFFH), and a series of background data. A maximum of 8192 types (=2 ¹³ ) of one piece of music (BGM), a group of dramatic sounds (announcement sounds), etc. are stored in association with the phrase number NUM. This phrase number NUM is specified by a set value (operating parameter) of a voice command transmitted from the effect control CPU 63 to the voice control register SRG of the voice processor 27 .

As described above, the audio memory 28 having the above configuration is power reset by the reset signal RT3, and the audio processor 27 is power reset by the reset signal RT4. As shown in FIG. 13(c), the reset signal RT4 rises to H level after a predetermined assertion period ASRT (L level section) after power-on. function automatically to perform initialization sequence processing. This initialization sequence process is an internal operation that is executed according to a predetermined procedure, and the effect control CPU 63 cannot access the sound register SRG during the operation of the initialization sequence process.

When the initialization sequence processing as an internal operation is completed, the interrupt signal IRQ_SND to the CPU circuit 51 changes to L level, and the CPU circuit 51 (effect control CPU 63) executes the interrupt processing program based on the interrupt signal IRQ_SND. Then, the interrupt signal IRQ_SND is returned to the H level based on a predetermined instruction, the details of which will be described later with reference to FIG. 23(c).

As shown in FIG. 13(a), the data bus and address bus of the CPU circuit 51 of the effect control section 23 extend to a clock circuit (real time clock) 38 and effect data memory 39 mounted on the liquid crystal interface board 24. I'm listening. The clock circuit 38 is connected to the lower 4 bits of the address bus of the CPU circuit 51 and the lower 4 bits of the data bus. (having an address value) can be accessed arbitrarily.

The effect data memory 39 is a memory element SRAM (Static Random Access Memory) that can be accessed at high speed, and is connected to the 16-bit address bus of the CPU circuit 51 and the lower 16-bit data bus. In the state where the chips are selected in , game performance information and other information stored in the SRAM (performance data memory) 39 are appropriately R/W-accessed from the CPU circuit 51 . In the address space CS4 selected by the chip select signal CS4, since addresses 0 to 15 are assigned to the clock circuit 38, the SRAM 39 does not use them.

The clock circuit 38 and the performance data memory 39 are driven by a secondary battery (not shown), and this secondary battery is appropriately charged by the power supply voltage from the power supply board 20 during game operation. Therefore, even after the power is turned off, the timekeeping operation of the clock circuit 38 is continued, and the game performance information stored in the effect data memory 39 is permanently stored (imparted non-volatility). The clock circuit (RTC) 38 is configured to output an interrupt signal IRQ_RTC to the CPU circuit 51 (RTC interrupt). The RTC interrupt includes an alarm interrupt that can specify the date, day of the week, hour, minute, and second, and a timer interrupt that is activated after a predetermined time has elapsed. Uses alarm interrupts to update game performance information.

As shown on the right side of FIG. 13(a), the effect control board 23 includes a composite chip 50 containing a CPU circuit 51 and a VDP circuit 52, a control memory (PROM) 53 for storing a control program for the CPU circuit 51, A DRAM (Dynamic Random Access Memory) 54 capable of accessing a large amount of data at high speed, and a CGROM 55 storing a large amount of CG data required for control of effects are installed.

As will be described later with reference to FIG. 16, the control memory (PROM) 53 is located in the address space CS0 selected by the chip select signal CS0 in this embodiment. A DRAM (Dynamic Random Access Memory) 54 composed of DDR (Double-Data-Rate 3) is positioned in an address space CS5 selected by a chip select signal CS5.

FIG. 14(a) is a circuit block diagram illustrating the composite chip 50 that constitutes the effect control section 23, including related circuit elements. As shown, the composite chip 50 of the embodiment includes a CPU circuit 51 that issues a display list DL at predetermined time intervals, and a CPU circuit 51 that generates image data based on the issued display list DL to drive the display devices DS1 and DS2. A VDP circuit 52 is built in. The CPU circuit 51 and the VDP circuit 52 are connected through a CPUIF circuit 56 that relays transmission/reception data between them.

Although the VDP circuit 52 incorporates an audio circuit SND that exhibits functions equivalent to those of the audio processor 27, the embodiment described below does not utilize the audio circuit SND. However, if the audio circuit SND built in the VDP circuit 52 is used, the arrangement of the audio memory 28 and the audio processor 27 becomes unnecessary.

First, the CPU circuit 51 receives the oscillation output (for example, 100/3 MHz) of the oscillator OSC1 at the HCLKI terminal and multiplies the frequency (for example, by 8) to obtain a CPU operating clock of about 266.7 MHz. Here, the oscillator OSC1 is configured to output a spread spectrum wave, thereby taking measures against EMI (Electromagnetic Interference) for preventing radio interference/electromagnetic interference.

On the other hand, the VDP circuit 52 receives the oscillation output (for example, 40 MHz) of the oscillator OSC2 at the PLLREF terminal, and after appropriately multiplying the frequency by a PLL (Phase Locked Loop) circuit, the system clock of the VDP circuit 52 and the display device It is used as a display clock (dot clock, etc.) and a DDR clock for the external DRAM 54 . That is, the output of oscillator OSC2 functions as a reference clock for the entire VDP circuit 52. FIG. Note that the frequency multiplication ratio of the PLL circuit is defined by a set value to a predetermined setting terminal.

Therefore, in consideration of the importance of this reference clock, in this embodiment, the oscillator OSC2 is operated at the same power supply voltage of 3.3 V as the VDP circuit 52, and the output enable terminal OE is at H level (=3.3 V). It is configured to oscillate and output the reference clock on the condition that there is. In the unlikely event that the power supply voltage 3.3V falls below a predetermined level, since normal performance operations cannot be expected thereafter, a non-maskable interrupt (NMI) is generated.

Also, the composite chip 50 is provided with an HBTSL terminal, and based on the logic level of the HBTSL terminal, whether a boot program (initial setting program) to be executed after power-on (CPU reset) is stored in the CGROM 55 (HBTSL =H) or stored in other memory (HBTSL =L). As shown in the figure, in this embodiment, HBTSL is set to L level, and address zero in the address space CS0 of the effect control CPU 63 is assigned outside the CGROM. assigned to.

On the other hand, when the HBTSL terminal is set to H level (see the broken line), zero address in the address space CS0 of the effect control CPU 63 is assigned to the CGROM 55 . In this case, the memory type and bus width (64/32/16 bits) of the CGROM 55 are specified based on the input values to the HBTBWD terminal of 2-bit length and the HBTRSL terminal of 4-bit length, respectively.

Next, the CPUIF circuit 56 that relays transmission/reception data between the CPU circuit 51 and the VDP circuit 52 will be described. As shown in FIG. 14A, the CPUIF circuit 56 includes a control memory (PROM) 53 for nonvolatilely storing control programs and necessary control data, and a work memory (RAM) 57 having a storage capacity of about 2 Mbytes. , and are configured to be accessible from the CPU circuit 51 . As described above, the control memory (PROM) 53 is positioned in the address space CS0 selected by the chip select signal CS0, and the work memory (RAM) 57 is positioned in the address space CS6 selected by the chip select signal CS6. It is

The work memory (RAM) 57 reserves a DL buffer BUF for temporarily storing a display list DL containing a series of instruction commands specifying one frame of each of the display devices DS1 and DS2. In the case of this embodiment, the series of instruction commands include a texture load command such as a TXLOAD command for reading and decoding image materials (textures) from the CGROM 55, and a VRAM area (index texture setting commands such as the SETINDEX command, which has functions such as specifying the space) in advance, and primitive drawing commands such as the SPRITE command for placing the decoded (expanded) image material at a predetermined position in the virtual drawing space. , environment setting commands such as the SETDAVR command and SETDAVF command for specifying the drawing area to be actually drawn on the display device among the images drawn in the virtual drawing space by the drawing commands, and the index table IDXTBL for managing the index space. includes an index table control command (WRIDXTBL) for

Note that FIG. 18C shows a virtual drawing space (±8192 in the horizontal X direction: ±8192 in the vertical Y direction), a drawing area that can be arbitrarily set in the virtual drawing space, and outputs to the display devices DS1 and DS2. The relationship between the actual drawing areas in the frame buffers FBa and FBb that temporarily store the image data to be processed is shown.

Next, the CPU circuit 51 is a circuit having performance equivalent to that of a general-purpose one-chip microcomputer. A watchdog timer (WDT) that forcibly resets the CPU, a built-in RAM 59 that has a storage capacity of about 16 kbytes and is used as a work area for the CPU, and a DMAC (Direct Memory Access) that realizes data transfer without going through the CPU 63 Controller) 60, a serial input/output port (SIO) 61 having a plurality of input ports Si and output ports So, a parallel input/output port (PIO) 62 having a plurality of input ports Pi and output ports Po, and It includes an operation control register REG in which set values are set to control the operation. However, in this embodiment in which the external WDT circuit 58 is provided, the watchdog timer (WDT) built in the CPU circuit 51 is not utilized.

In this specification, for the sake of convenience, the term input/output port is used, but in the effect control unit 23, the input/output port includes an input port and an output port that operate independently. This point also applies to the input/output circuit 64p and the input/output circuit 64s described below.

The parallel input/output port 62 is connected to an external device (effect interface board 22) through an input/output circuit 64p. It receives the switch signal of the button 11, the control command CMD, and the interrupt signal STB. A 3-bit encoder output and a 1-bit switch signal are supplied to a parallel input/output port (PIO) 62 via an input/output circuit 64p.

Similarly, the received control command CMD is supplied to the parallel input/output port (PIO) 62 via the input/output circuit 64p. Further, the strobe signal STB is supplied to the interrupt terminal of the effect control CPU 63 via the input/output circuit 64p, thereby activating the reception interrupt process. Therefore, the effect control CPU 63, which grasps the control command CMD based on the reception interrupt process, controls the sound effect, the lamp effect, the motor effect, and the image effect corresponding to the control command CMD through the effect lottery and the like in a unified manner. will do.

Although not particularly limited, in this embodiment, the SMC (Serial Management Controller) 78 of the VDP circuit 52 is used for the lamp effect and the motor effect. The SMC unit 78 is a composite controller containing an LED controller and a motor controller, and is configured to output a serial signal in clock synchronization. Also, the motor controller is configured to output a latch pulse at an arbitrary timing based on a value set in a predetermined control register 70, and is configured to input a serial signal in a clock synchronous manner.

Therefore, in this embodiment, while the motor drive signal and the LED drive signal are output from the SMC unit 78 in synchronization with the clock signal, the latch pulse is output as the operation control signal ENABLE at an appropriate timing. . Further, the origin sensor signals SN0 to SNn from the performance motor groups M1 to Mn are serially input in a clock synchronous manner.

As described with reference to FIG. 13(a), the clock signals CK0-CK2, the drive signals SDATA0-SDATA2, and the operation control signals ENABLE0-ENABLE2 pass through the output buffers 41-43 to the predetermined drive substrates 30, 31, . 37. Further, the origin sensor signals SN0 to SNn are serially input to the SMC section 78 from the motor/lamp driving board 31 via the input/output buffer 43. FIG.

However, it is not essential to use the SMC unit 78 in this embodiment. That is, since the CPU circuit 51 has a built-in general-purpose serial input/output port SIO61, it is also possible to use these ports to execute lamp effects and motor effects.

14(a), in which the clock signals CK0 to CK2, CK2, Drive signals SDATA0 to SDATA2 are output, and operation control signals ENABLE0 to ENABLE2 are output via the input/output circuit 64p. For convenience, they are expressed as input/output ports and input/output circuits, but what actually functions are output ports and output circuits.

Here, the serial output port SO is configured with a built-in 16-stage FIFO register. Then, the DMAC circuit 60 is activated upon receiving an operation start instruction (see FIG. 26(b) ST18) from the effect control CPU 63, and from the lamp/motor drive table (see FIG. 26(b)), the necessary drive data is sequentially and DMA transferred to the FIFO register of the serial output port SO. The drive data stored in the FIFO register are serially output from the serial output port SO in clock synchronization. The DMAC circuit has a plurality of (for example, 7) DMA channels. The third DMA channel with lower priority is used for DMA transfer of the lamp drive data, and the first DMA channel with the highest priority is used to drive the motor. It is configured to DMA transfer data.

The operation control register REG built in the CPU circuit 51 is an 8-bit, 16-bit, or 32-bit length register with a register number (address value) after 0xFF400000. (see FIG. 16). Therefore, there is a possibility that an irrational value is set in the operation control register REG due to the influence of noise or the like.

However, for example, the composite chip 50 can be abnormally reset by intentionally executing an infinite loop process to activate the external WDT circuit 58 . In this case, the value of the operation control register REG is returned to the same default value (initial value) as after power-on, and the value of the VDP register RGij of the VDP circuit 52 is also returned to the default value (initial value). This eliminates the abnormal state.

FIG. 13(b) is a circuit configuration related to this reset operation, and is a drawing for explaining a reset mechanism that is characteristic of this embodiment. In this specification, the VDP register denoted as RGij is not the operation control register REG built in the CPU circuit 51, but any one of the control register group 70 (see FIG. 16) that controls the internal operation of the VDP circuit 52. means Also, the system control circuit 520 shown in FIG. 13(b) means an internal control circuit of the VDP circuit 52 that functions based on the set value of the VDP register RGij (one of the control registers 70 of FIG. 16). (See FIG. 14(a)). The VDP register RGij is positioned in the address space CS7 selected by the chip select signal CS7 in the address map of the effect control CPU63.

Based on the above, the reset mechanism will be described. As shown in FIG. is configured to be resettable. However, in this embodiment, the built-in WDT is not activated as indicated by the dashed line, so the input terminal and the output terminal of the OR gate G2 are directly connected.

In any case, a pattern check circuit CHK is provided between the CPU circuit 51 and the VDP circuit 52, and the pattern check circuit CHK receives from the parallel input/output port (PIO) 62 a predetermined keyword string (a code string for resetting). ), the reset signal RST is output.

The internal circuit of the composite chip 50 is divided into three parts: (1) the CPU circuit 51, (2) the display circuit 74 of the VDP circuit 52, and (3) the circuits other than the display circuit of the VDP circuit 52. It is configured to receive reset signals of the first to third reset paths from gates G2 to G4.

First, the OR gate G2 whose input/output terminals are directly connected is related to the first reset path, and is configured to system-reset the entire CPU circuit 51 based on the system reset signal SYS bar. Also, the OR gate G3 is related to the second reset path, and receives the system reset signal SYS bar and the reset signal RST from the pattern check circuit CHK, and can reset the entire VDP circuit 52 based on the OR logic. is configured to

This second reset path is used not only for the power reset operation when the power is turned on, but also for the effect control CPU 63 that detects a predetermined abnormality to abnormally reset the entire VDP circuit 52 to return it to its initial state. Specifically, when it is determined that a serious abnormality has occurred based on a predetermined status register RGij that indicates the internal operation of the VDP circuit 52, the reset signal RST is generated from the pattern check circuit CHK. , the entire VDP circuit 52 is abnormally reset. The display circuit 74 is abnormally reset in the second reset path→the third reset path via the OR gate G4.

On the other hand, the internal circuits built in the VDP circuit 52 are configured to be able to be reset individually when necessary through the fourth reset path. The individually resettable internal circuits include an index table IDXTBL, a data transfer circuit 72, a preloader 73, a display circuit 74, a drawing circuit 76, an SMC circuit 78, and an audio circuit SND shown in FIG. An ICM circuit shown at 19 is included.

A method for realizing individual reset operations is as described in the lower part of FIG. Thus, it is reset through the fourth reset path 4A→the third reset path.

Each internal circuit (72, 73, 74, 76, SND, . After writing, (2) a predetermined VDP register RGij (system command register) is reset individually by writing a second reset value (fourth reset path 4B). Although not used in this embodiment, the audio circuit SND can be reset not only by the fourth reset path 4B, but also by writing a reset value to a predetermined VDP register (circuit setting command register). 4 reset path 4C).

Since this embodiment has the above-described configuration, not only does the entire VDP circuit 52 automatically return to the initial state when the power is turned on or when the program runs out of control, but each part is returned to the initial state as necessary to prevent an abnormal situation from occurring. recovery can be achieved. For example, when the drawing circuit 76 is frozen without READ/WRITE access to the built-in VRAM 71 for a certain period of time, the drawing circuit 76 is individually initialized via the fourth reset path 4B (Fig. 26(d) ST16a reference). The same applies to the preloader 73 and the data transfer circuit 72. In the event of a predetermined abnormality, the preloader 73 is initialized via the fourth reset path 4B (see ST27 in FIG. 25), and the preloader 73 is initialized via the fourth reset path 4B. Then, the data transfer circuit 72 is initialized (see ST27 in FIG. 20 and FIG. 25).

In addition, regarding the display circuit 74, when the display timing of every 1/60th of a second continues underrun (underrun), in which display data cannot be generated in time, the fourth reset path 4A or the fourth reset path 4B is switched. The display circuit 74 is individually initialized via this (see ST10c in FIG. 26).

The reset mechanism that is characteristic of this embodiment has been described above. The setting value of returns to the same default value after power-on.

Next, returning to the internal configuration of the CPU circuit 51, the description of the characteristic circuit configuration will be continued. FIG. 15 is a block diagram showing in some detail the internal configuration of the CPU circuit 51. As shown in FIG. The CPU circuit 51 includes many characteristic circuits in addition to the built-in RAM 59, DMAC circuit 60, SIO 61, PIO 62, and WDT described above.

First, CPU circuit 51 implements the Harvard architecture by having separate CPU fetch buses for instructions and CPU memory access buses for data. Therefore, the fetch operation in which the CPU core (rendering control CPU) 63 reads an instruction from the memory and the memory access operation do not conflict with each other, and high-speed processing is realized by continuing the fetch operation.

Further, the CPU core 63 is configured with a plurality of (for example, 15) register banks RB0 to RB14, and is configured to select whether or not to use them. In an operating state in which the use of the register bank RBi is permitted, at the start of interrupt processing, the register values (each 32-bit length) of the internal registers of the CPU (eg, 19 registers) are automatically saved in the empty register bank RBi. be done.

Further, when a predetermined return instruction is executed at the end of interrupt processing, for example, 19 pieces of saved data are automatically restored to the corresponding built-in registers. Therefore, it is not necessary to execute the PUSH instruction 19 times at the start of interrupt processing and the POP instruction 19 times at the end of interrupt processing as in a normal configuration, and high-speed processing is realized.

Further, the CPU circuit 51 of the embodiment realizes a Harvard cache operation by providing an instruction cache memory 67, an operand cache memory 89, and a cache controller 69, and when accessing the same address, cached By using this data, we are aiming to further speed up program processing. By providing the bus bridge 65, the controller for the peripheral bus (1), the controller for the peripheral bus (2), and the controller for the peripheral bus (3), the internal bus and the peripheral bus (1) are provided. ), peripheral bus (2), and peripheral bus (3) are connected as appropriate.

Next, in the circuit configuration of FIG. 15, the bus state controller 66 operates based on appropriate set values in the operation control register REG to perform memory READ operations with various memory devices connected to the CPU circuit 51 and memory read operations. This is the part that optimizes WRITE operations. The memory READ operation and memory WRITE operation are executed, for example, at the operation timings illustrated in FIG. The operation timing of the WRITE data written to the WRITE data bus (32 bits) and the control signals such as chip select signals CS0 to CS7 correspond to the characteristics of each memory device based on the values set in the operation control register REG. Defined as appropriate.

Since the READ data bus and the WRITE data bus are provided separately, high-speed operation is realized by the Harvard architecture described above. In this specification, the address bus (28 Bit), READ data bus (32 Bit), and WRITE data bus (32 Bit) are referred to as the internal bus, peripheral bus (1) to peripheral bus (3), etc. shown in FIG. In order to distinguish it from the external bus, it may be generically called an external bus.

FIG. 16 shows the address spaces CS0-CS7 selected by the chip select signals CS0-CS7, and shows the address map for the effect control CPU 63 accessed via the bus state controller 66. FIG. . First, each of the address spaces CS0 to CS7 is defined to have a maximum of 64 Mbytes (=0x4000000H=67108864).

As described above, the address spaces CS0 to CS7 mean external memories for the CPU circuit 51, which can define the memory type including the presence or absence of volatility, and the data bus width (8/16/32 bits). do. In this embodiment, as shown in FIGS. 15B and 16, the control memory (PROM) 53 has an address space CS0, the audio control register SRG of the audio processor 27 has an address space CS3, the internal registers of the clock circuit 38 and The SRAM 39 is positioned in the address space CS4, the external DRAM (DDR) 54 is positioned in the address space CS5, the work memory 57 is positioned in the address space CS6, and the VDP register RGij is positioned in the address space CS7. A description of the address spaces CS1 and CS2 will be omitted.

By the way, as can be seen from FIG. 16, the address spaces CS0 to CS7 are secured not only at address values 0x00000000 to 0x1FFFFFFF (cache valid space) but also at address values 0x20000000 to 0x3FFFFFFF (cache invalid space). When the address bit A29=1, the cache is invalidated according to the internal operation of the CPU circuit 51, while when the address bit A29=0, the cache is validated. It is designed to

Therefore, in this embodiment, even if the value of bit A29 is either 1 or 0 in all 32-bit address information (bits A31 to A0), the remaining 31 bits (bits A31 to A30 and bits A28 to A0) If the values are the same, they point to the same location in the same memory. For example, the same data is read from the zero address of the work memory 57 even if the address 0x18000000 is read-accessed and the address 0x38000000 is read-accessed. When the address 0x18000000 is read-accessed, the read data is stored in the cache, and FIG. 15(b) illustrates the cache valid/invalid access operation.

However, it is also possible to invalidate the cache operation of the instruction cache and/or the operand cache based on the value set in the predetermined operation control register REG. However, in this embodiment, after the power is turned on, the cache operations of the instruction cache and the operand cache are validated, and the cache invalidation space is accessed as necessary to invalidate the cache operations.

Continuing the description of the memory map in FIG. 16, from 0x40000000 onwards is an internal memory space where the bus state controller 66 does not function, and addresses 0xF0000000 to 0xFF3FFFFF are assigned to the cache address array space. Addresses 0xFF400000 to 0xFFF7FFFF and 0xFFFC0000 to 0xFFFFFFFF are assigned to built-in peripheral modules, specifically, to the operation control register REG of the CPU circuit. The address range of the internal RAM 59 is 0xFFF80000 to 0xFFFBFFFF.

Continuing the description of the internal configuration of the CPU circuit 51, the compare match timer CMT and the multi-function timer unit MTU count external signals supplied to the CPU circuit 51, or count by multiplying or dividing the internal clock. This is a circuit that counts clocks and generates an interrupt signal or the like when the counted result reaches a predetermined value. Although not particularly limited, this embodiment utilizes the multifunction timer unit MTU to generate a 1 ms interrupt signal and a 20 μS interrupt signal.

Next, the interrupt controller INTC receives internal interrupts from the VDP circuit 52, the DMAC circuit 60, the multi-function timer unit MTU, etc., and external interrupts such as IRQ_CMD, IRQ_SND, IRQ_RCT, etc., and based on a predetermined priority. It is a circuit that activates interrupt processing (interrupt handler). IRQ_CMD is a command reception interrupt signal for receiving the control command CMD, IRQ_SND is a termination interrupt signal indicating that the voice processor 27 has completed the initialization sequence, and IRQ_RCT is an alarm interrupt signal.

In this embodiment, the command reception interrupt IRQ_CMD has the highest level of interrupt priority. The order is IRQ_RCT (see FIG. 23(d)). All of these are maskable interrupts, and the unmaskable interrupt NMI is output to the effect control CPU 63 when the reference clock is not output from the oscillator OSC2, as described above.

In any interrupt process, the register values (32-bit length each) of a plurality of built-in registers of the CPU are automatically saved in any one of the empty register banks RBi. Then, when a predetermined restore instruction is executed at the end of interrupt processing, the saved data is automatically restored to the corresponding built-in register.

Next, the DMAC circuit 60 will be described. The DMAC circuit 60 of the embodiment transfers from the transfer source (Source) to the transfer destination (Destination) in a predetermined DMA transfer mode for each predetermined data transfer unit based on the set value in the predetermined operation control register REG. In addition, it is a circuit that repeats data transfer a predetermined number of times. A plurality of channels of DMAC0 to DMACn having the same internal configuration are prepared and can operate in parallel. However, the priority is determined (channel 0 > . . . > channel n), and during parallel operation in the channel arbitration operation mode, the operation of DMACi with a higher priority is prioritized by channel arbitration at predetermined timing.

As for the utilization of the DMAC circuit 60, for example, in the embodiment in which the serial output port SO functions (see the dashed line part in FIG. (head value of transfer source address), address of input register of serial output port SO (fixed value of transfer destination address), data transfer unit (8 bits), and number of transfers are specified. Then, the DMAC circuit 60, which has received the operation start instruction from the predetermined operation control register REG, DMA-transfers the driving data to the predetermined transfer destination address while updating the transfer source address. Then, when all DMA transfers are completed, a DMAC interrupt (operation end interrupt) is generated.

This point is substantially the same in the case of the embodiment in which the DMAC circuit 60 issues the display list DL (FIGS. 21 and 25(c)). That is, the effect control CPU 63 stores the head address of the transfer source (DL buffer BUF), the address of the transfer destination (transfer port TR_PORT), the DMA transfer mode, and the data transfer unit in a predetermined operation control register REG of the CPU circuit 51. Then, the number of transfers and other conditions are set. Note that these points will be discussed further below with respect to FIG.

By the way, in general, DMA transfer modes include a cycle steal transfer mode in which DMA operations do not occupy the memory bus, such as releasing the bus control right in the middle of a unit operation (R operation/W operation) of DMA transfer, and a cycle steal transfer mode in which DMA operations do not occupy the memory bus. Burst transfer (pipeline transfer) mode in which the bus control right is not released until the specified number of transfers is completed, such as continuous operation or W operation, and while DMA transfer requests (demands) received from other devices are active A demand transfer mode that continues the DMA operation can be considered. However, the DMAC circuit 60 of this embodiment functions in a cycle steal transfer mode in which at least one cycle of memory release period is provided between read access activation (R operation) and write access activation (W operation) during DMA transfer. By doing so, the operation of the effect control CPU 63 is prevented from being hindered.

FIG. 17 is a diagram for explaining the cycle steal transfer operation (a1) and the pipeline transfer (a2). As shown in FIG. 17(a1), the DMAC circuit 60 functioning in the cycle steal transfer mode operates with at least one cycle between read access activation (R) and write access activation (W) of one data transfer. In this empty cycle, the effect control CPU 63 can use the bus. As is clear from the comparison between FIGS. 17(a1) and 17(a2), in pipeline transfer, the bus is not released to the CPU until one cycle (one-operand transfer) is completed. In the transfer mode, the bus is released to the CPU for each read access, so the operation of the CPU is not greatly delayed.

Then, for example, when the display list DL is issued to the VDP circuit 52, in an embodiment using the DMAC circuit 60, the data transfer unit (1 operand) of one cycle is set to 32×2 bits, and the display list DL is stored. While appropriately increasing the source address of the built-in RAM 59 (+8 for each 1-operand transfer), the DMA transfer operation is performed for the transfer port register TR_PORT (see FIG. 19) of the data transfer circuit 72 specified by the fixed address. running

As will be described later, in the embodiment, by adding the required number of NOP (no operation) commands to the display list DL, the overall data size is set to a fixed value (for example, 4×64=256 bytes, or its integer 32 bits×2 times of one operand transfer is repeated 32 times (or an integer multiple thereof) to complete the issue of the display list DL. Note that execution of the NOP command by the drawing circuit 76 does not, in fact, cause any change.

Further, when classifying operation modes with respect to DMA transfer conditions, generally, single operand transfer (see FIG. 17(b1)), continuous operand transfer (see FIG. 17(b2)), and non-stop transfer (see FIG. 17(b3) See).

Here, the single-operand transfer is the point in time when the byte count, which counts the number of transfer bytes, becomes zero after repeating the transfer of one operand each time a DMA transfer request is given, as shown in FIG. 17(b1). and means the mode of operation in which a DMA interrupt request occurs. Next, continuous operand transfer means an operation mode in which DMA transfer is repeated until the byte count becomes zero with one DMA request, as shown in FIG. 17(b2).

In these continuous operand transfers (b2) and single operand transfers (b1), channel arbitration is performed each time a single operand transfer is completed. transfer continues (channel arbitration mode of operation). Therefore, in this embodiment, the single operand transfer method is adopted for issuing the display list DL to the VDP circuit and for DMA transfer of lamp drive data and motor drive data. During parallel operation, the DMACi of the optimum channel is used so as to achieve channel arbitration with the priority of, for example, motor data>display list DL>lamp data.

On the other hand, non-stop transfer is an operation mode in which channel arbitration is not executed, and as shown in FIG. be In this embodiment, in the memory section initialization process (SP8 in FIG. 21) at power-on, programs and data are DMA-transferred by non-stop transfer.

The CPU circuit 51 has been described above. Next, the VDP circuit 52 will be described. , a main display device DS1, and a sub display device DS2 are connected. The DRAM 54 is preferably composed of DDR3 (Double-Data-Rate3 SDRAM).

Although not particularly limited, in this embodiment, the CGROM 55 is composed of a flash SSD (solid state drive) composed of a NAND flash memory with a storage capacity of about 62 Gbits. is configured to obtain Therefore, the problem of skew (difference in transmission speed for each bit data) that inevitably occurs in parallel transmission is resolved, and extremely high-speed transmission operation becomes possible. Although not particularly limited, in this embodiment, the CGROM 55 is accessed at high speed by the HSS (High Speed Serial) system conforming to SerialATA.

Regardless of whether or not the HSS method conforming to SerialATA is adopted, the NAND type flash memory is mechanically more stable than the hard disk and is capable of high-speed access. Compared with DRAM and SRAM (Static Random Access Memory), there is a problem in random accessibility. Therefore, in this embodiment, a group of compressed data (CG data) is preloaded into the DRAM 54 prior to the drawing operation, thereby realizing smooth random access of the CG data during the drawing operation. ing. Incidentally, the access speed decreases in the order of built-in VRAM>external DRAM>CGROM.

More specifically, the VDP circuit 52 includes a control register group 70 in which various operating parameters that define the operation of the VDP (Video Display Processor) can be set by an effect control CPU 63, and image data to be displayed on the display devices DS1 and DS2. A built-in VRAM (video RAM) 71 of about 48 Mbytes used at the time of generation, a data transfer circuit 72 that executes data transmission/reception between each part inside the chip and data transmission/reception with the outside of the chip, and the built-in VRAM 71 have Source and Destination. An index table IDXTBL capable of specifying address information, a preloader 73 capable of executing a preload operation for READ access to the CGROM 55 prior to the drawing operation, and a graphics decoder for decoding (decoding/decompressing/decompressing) compressed data read from the CGROM 55. (GDEC) 75, a rendering circuit 76 for generating image data for one frame of each of the display devices DS1 and DS2 by appropriately combining still image data and moving image data after decoding (expanding), and operation of the rendering circuit 76. A geometry engine 77 that generates a stereoscopic image by appropriate coordinate transformation, and a three-system system that reads image data from the frame buffers FBa and FBb generated by the drawing circuit 76 and executes appropriate image processing in parallel. (A/B/C) display circuits 74A to 74C, an output selection unit 79 that appropriately selects and outputs the outputs of the three-system (A/B/C) display circuits 74, and an image output by the output selection unit 79 LVDS section 80 for converting data into LVDS signals, SMC section 78 capable of transmitting and receiving serial data, CPUIF section 81 for relaying data transmission and reception with CPUIF circuit 56, and CG bus IF section 82 for relaying data reception from CGROM 55. , a DRAMIF section 83 for relaying data transmission/reception with the external DRAM 54 , and a VRAMIF section 84 for relaying data transmission/reception with the built-in VRAM 71 . An audio circuit SND is also incorporated.

FIG. 14B shows the relationship between the CPUIF section 81, the CG bus IF section 82, the DRAMIF section 83, the VRAMIF section 84, the control register group 70, the CGROM 55, the DRAM 54, and the built-in VRAM 71. FIG. As shown, the CG data acquired from the CGROM 55 is transferred to the preload area of the external DRAM 54 via the data transfer circuit 72 and the DRAM IF unit 83 as preload data, for example.

However, the above-described preload operation is not an essential operation, and the data transfer destination is not limited to the external DRAM 54, and may be the built-in VRAM 71 as well. Therefore, for example, in an embodiment in which no preload operation is performed, the CG data is transferred to the built-in VRAM 71 via the data transfer circuit 72 and VRAMIF section 84 (FIG. 14(b)).

By the way, in this embodiment, the built-in VRAM 71 stores the image data specifying the expansion area of the compressed data read from the CGROM 55 and the ARGB information (32 bits=8×4) of each of W×H display pixels of the display device. A frame buffer area to store the depth information of each display pixel and a Z buffer area to store the depth information of each display pixel are required. In the ARGB information, A means 8-bit α-plane data, and RGB means 8-bit data of three primary colors.

Here, each area of the built-in VRAM 71 is indirectly accessed based on various instruction commands (textures, sprites, etc. described above) described in the display list DL by the effect control CPU 63, but the READ/WRITE access , it is troublesome to specify the destination address and the source address of the built-in VRAM 71 one by one. Therefore, in this embodiment, in the initial processing after resetting the CPU, a one-dimensional or two-dimensional logical address space (hereinafter referred to as an index space) required for the drawing operation is secured, and an index number is assigned to each index space. allows access based on the index number.

Specifically, after resetting the CPU, the built-in VRAM 71 is roughly divided into three types of memory areas, and the necessary number of index spaces are secured in each memory area. By constructing an index table IDXTBL (see FIG. 18A) that stores the index space and the index number in association with each other, subsequent operations based on the index number are realized.

This index space needs to be (1) added after initial processing, and conversely (2) freed. Therefore, when the addition/release effect control CPU 63 operates, a flag that can determine whether or not it is the timing at which the addition/release processing can be performed, and whether or not the processing such as addition/release has actually been completed. A region FG is provided in the index table IDXTBL. The built-in VRAM 71 is roughly divided into three types of memory areas: two AAC areas (a1, a2), a page area (b), and an arbitrary area (c). The index table IDXTBL is divided into three corresponding to (a1,a2)(b)(c) (FIG. 18(a)). As shown in the figure, in this embodiment, the first AAC area (a1) and the second AAC area (a2) are secured as the AAC area (a). But it's okay. In the following description, the first and second AAC areas (a1, a2) may be collectively referred to as the AAC area (a).

In this embodiment, the built-in VRAM 71 comprises (a) an AAC area having an index space and its index number automatically assigned by internal processing and having a memory cache function, and (b) a two-dimensional space of, for example, 4096 bits×128 lines. The unit space is divided into a page area in which an index space can be secured within the range of integral multiples thereof, and (c) an arbitrary area in which the start address (space start address) STx and horizontal size Hx can be set arbitrarily. (See FIG. 18(b)). However, in order to facilitate the internal operation of the VDP circuit 52, the space head address STx of the index space arbitrarily set in the arbitrary area (c) has 0 in the lower 11 bits, and has a predetermined number of bits (2048 bits=256 bytes). Must be in units.

After resetting the CPU, the maximum value of the address space required for each area and the top address of the area (lower 11 bits=0) are defined, and the AAC area (a1), the second AAC area (a2), and the page area ( b) is secured, and the remaining memory area becomes the arbitrary area (c). In order to facilitate the internal operation of the VDP circuit 52, the maximum value of the address space of the AAC area is defined in units of 2048 bits, and the maximum value of the address space of the page area is an integer multiple of the unit space of 4096 bits×128 lines. It is said that

Next, the necessary number of index spaces are set in each of the areas (a1, a2), (b), and (c) thus secured. When the arbitrary area (c) is used, the horizontal size Hx of the index space that handles two-dimensional data can be arbitrarily set as a multiple of 256 bits in order to facilitate the internal operation of the VDP circuit 52. Its vertical size is a fixed value (eg, 2048 lines).

In any case, the first and second AAC areas (a1, a2) are automatically given an index space and an index number by the VDP circuit 52. Therefore, for example, the SETINDEX command, which is a texture setting command, If the AAC area (a) is specified as the decoding destination, the TXLOAD (texture load) command for reading CG data from the CGROM 55 only needs to specify the source address of the CGROM 55 and the horizontal and vertical sizes after expansion (decoding). It will be. Therefore, in the present embodiment, still images (textures) such as characters that temporarily appear in advance notice effects and I-stream moving images are decoded to the AAC area (a).

Since this AAC area (a) is provided with a memory cache function, for example, when the same texture in the CGROM 55 is read out to the AAC area (a) a plurality of times, from the second time onwards: The decoded data cached in the AAC area (a) can be utilized, and unnecessary READ access and decoding processing can be suppressed. However, when the AAC area (a) is used up, the old data is automatically destroyed. Only specific textures that are used repeatedly are acquired in the second AAC area (a2).

Examples of repeatedly used textures include a character that appears repeatedly during a predetermined advance notice effect, and a background image when the background screen is composed of a still image. In such a case, set the decoding destination to the second AAC area (a2) with the SETINDEX command of the texture setting commands, and decode the textures such as characters and background images to the second AAC area (a2) with the TXLOAD command. After that, the decoding result is protected by not using the second AAC area (a2).

After that, after specifying the decoding destination to the second AAC area (a2) with the SETINDEX command, executing the same TXLOAD command to reacquire the acquired texture will cause a cache hit for the acquired texture. , READ access to the CGROM 55 and the time required for the decoding process can be eliminated. As will be described later, such a cache hit function is exhibited even in preload data prefetched in the preload area. It is significant that the cache hit in the area is the decompressed data after decoding.

By the way, the term "texture" generally refers to the texture and feel of the surface of an object. , is used as a concept including not only image data to be pasted on drawing primitives such as triangles and squares, but also image data after decoding. When image data is to be copied (hereinafter referred to as movement for convenience) within the built-in VRAM 71, the original image data is set as a texture by the SETINDEX command of the texture setting commands, and then the SPRITE command is executed. will be executed.

By executing the sprite command, the Source image data of the movement source is formally drawn in the virtual drawing space shown in FIG. 18(c). If the correspondence relationship between the area and the index space that becomes the frame buffer is set in advance by environment setting commands (SETDAVR, SETDAVF) and texture setting commands (SETINDEX), for example, the sprite command can be used to access the virtual drawing space. By drawing, the Source image data of the movement source is drawn in a predetermined index space (frame buffer) (see FIG. 18(c)).

In any case, in this embodiment, the built-in VRAM 71 is roughly divided into an AAC area (a1, a2), a page area (b) and an arbitrary area (c), each of which has an appropriate number of index spaces. and each index space is specified by an independent index number for each region (a)(b)(c). The index number is, for example, 1 byte long, and the page area (b) (excluding the AAC area (a) automatically assigned by the internal circuit) and the arbitrary area (c) are rendered in the range of 0 to 255. The control CPU 63 can freely assign index numbers.

Therefore, in this embodiment, as shown in FIG. 18(a), a pair of frame buffers FBa are secured in an arbitrary area (c) for the display device DS1, and index numbers 255, 254 is given. That is, an index space 255 and an index space 254 that are toggled to be used are secured as the frame buffer FBa for the main display device DS1. Although not particularly limited, the index spaces 255 and 254 have a horizontal size of 1280 corresponding to the number of pixels in the horizontal direction of the display device DS1. Since each pixel is specified by 32-bit ARGB information, the horizontal size 1280 means 32×1280=40960 bits (a multiple of 256 bits).

For the display device DS2, another pair of frame buffers FBb are secured in the arbitrary area (c), and index numbers 252 and 251 are assigned to both of the double buffer structures. That is, the index space 252 and the index space 251 are secured as the frame buffer FBb for the sub display device DS2. The index spaces 252 and 251 have a horizontal size of 480 corresponding to the number of pixels in the horizontal direction of the display device DS2. Also in this case, each pixel is specified by 32 bits of ARGB information, so the horizontal size 480 means 32×480=15360 bits (a multiple of 256 bits).

The reason why the frame buffers FBa and FBb are secured in the arbitrary area (c) is that the arbitrary horizontal size can be set in the arbitrary area (c) as a multiple of 32 bytes (= 256 bits = 8 pixels). This is because, as described above, by matching the number of horizontal pixels of the display devices DS1 and DS2, no waste occurs in the reserved area. On the other hand, in the page area (b), only horizontal/vertical sizes that are integral multiples of the unit space of 128 pixels×128 lines can be set.

However, the vertical size of the two-dimensional index space secured in the arbitrary area (c) is a fixed value (for example, 2048 lines). Therefore, in the frame buffer FBa, only the area of horizontal size 1280×vertical size 1024 is the valid data area for the main display device DS1. This point is the same for the sub-display device DS2, and in the frame buffer FBb, only the area of horizontal size 480×vertical size 800 is the valid data area for the sub-display device DS2 (FIG. 18(c), FIG. 26(e)).

The above points will be further described later, but in any case, the frame buffers FBa and FBb are alternately used as the drawing areas for the drawing circuit 76, and the double buffers (255/254, 252/251) are alternately used. Each double buffer (255/254, 252/251) is alternately used as a display area for the display circuits 74A, 74B. In this embodiment, since the Z-buffer for storing the depth information of the display pixels is not used, a missing number (253) occurs. Index spaces 253 and 250 provide Z-buffers for display devices DS1 and DS2.

Also, in this embodiment, when an additional index space (memory area) is to be secured in the optional area (c) in which the frame buffers FBa and FBb are secured, an index number starting from 0 is given. . Although it is not limited in any way, in this embodiment, as a work area for the notice effect, in which a effect image composed of a character or other still image is made to appear in a part of the display screen in an appropriate rotational posture as necessary, An index space (0) is secured in the arbitrary area (c).

However, the use of a work area is not essential, and an index space as a work area may be secured in the page area (b) instead of the arbitrary area (c). If the page area (b) is used, it is possible to secure an index space with dimensions that are multiples of a square unit space of horizontal size 128 (=4096 bits)×vertical size 128, so it is suitable for handling small-sized effect images.

By the way, in this embodiment, the background image is composed of moving images, and the image effect is realized almost exclusively by moving images. In particular, a large number (usually 10 or more) moving images are drawn at the same time during the variable presentation. Each of these moving images is stored in the CGROM 55 in a compressed state as a series of moving image frames. and Here, an I frame (Intra coded frame) means a frame in which an input image is directly compressed independently of other screens. On the other hand, a P-frame (Predictive coded frame) means a frame for which forward predictive coding is performed, and requires an I-frame or P-frame positioned in the past in terms of time.

Therefore, in this embodiment, the IP stream moving image is developed in the page area (b) instead of the AAC area (a) where there is a concern that the old data will be destroyed. That is, a number of index spaces (IDX ₀ to IDX _N ) are secured in the page area (b) that can secure index spaces of multiple dimensions of horizontal size 128×vertical size 128, and a series of video frames are The same index space IDXi corresponding to MVi is always used for decoding. That is, the moving picture MV1 is developed in the index space IDX1, the moving picture MV2 is developed in the index space IDX2, and similarly, the moving picture MVi is developed in the index space IDXi.

More specifically, the moving picture MVi is specified in advance by the SETINDEX command that "the decoding destination of the IP stream moving picture MVi is the index space (i) of the index number i in the page area (b)". A TXLOAD command is executed to acquire one moving image frame of the IP stream moving image MVi.

Then, one moving image frame (either of a series of moving image frames) on the CGROM 55 specified by the TXLOAD command is first acquired in the AAC area (a), and then automatically activated by the GDEC (graphics decoder) 75. , one frame of the acquired moving image is decoded and developed in the index space (i) of the page area (b).

On the other hand, in this embodiment, I-stream moving pictures are handled in the same way as still pictures. Run the TXLOAD command. As a result, the moving image frame is acquired in the first AAC area (a1), and then the automatically started GDEC 75 develops the decoded data in the first ACC area (a1). As explained above, the index space for the AAC area (a) is automatically generated, so there is no need to specify the index number. Note that the expansion volume required for the index space, that is, the horizontal size and vertical size of the decoded texture (video frame), is TXLOAD regardless of whether the expansion destination is the AAC area (a) or the page area (b). Identified by command.

By the way, IP stream moving images MVi and I stream moving images MVj are generally composed of N moving image frames (I frames and P frames). Therefore, the TXLOAD command specifies, for example, the source address of the CGROM 55 in which the k-th (1≤k≤N) video frame is stored and the horizontal/vertical size after development. Although not limited in any way, in an embodiment in which still pictures are hardly used, most of the 48 Mbyte address space (about 30 Mbytes) of the built-in VRAM 71 is allocated to the page area (b). In an embodiment in which still images are hardly used, only the first AAC area (a1) is secured as the AAC area, the second AAC area (a2) is not secured, and the cache hit function of the AAC area is used. do not use either.

It is also conceivable to provide a dedicated GDEC (graphics decoder) circuit in order to speed up the decoding process of compressed video data. If a dedicated GDEC circuit is incorporated in the VDP circuit 52, it is sufficient to instruct the GDEC circuit of the head address of the compressed moving image data in the decoding process of the compressed moving image data composed of N compressed moving image frames. It is no longer necessary to specify the start address for each of the N compressed video frames.

However, incorporating a plurality of such dedicated GDEC circuits for each compression algorithm further complicates the internal configuration of the VDP circuit 52 . Therefore, in this embodiment, software GDEC is used, and decoding processing is realized by software processing corresponding to each compression algorithm for data such as IP stream moving images, I stream moving images, still images, and other α values. The processing time difference between the hardware processing and the software processing does not matter so much, and the processing time that matters is mainly the access (READ) time from the CGROM 55 .

Next, returning to FIG. 14A, the data transfer circuit 72 uses the resources (storage media) inside the VDP circuit and the external storage media as transfer source ports or transfer destination ports. This is a circuit that performs data transfer operations in a DMA (Direct Memory Access) manner. FIG. 19 is a block diagram showing the internal configuration of this data transfer circuit 72 together with related circuit configurations.

As shown in FIG. 19, the data transfer circuit 72 is configured to transmit/receive data to/from the CGROM 55, DRAM 54, and built-in VRAM 71 via an integrated connection bus ICM having a router function. The CGROM 55 and DRAM 54 are accessed via the CG bus IF section 82 and the DMAM IF section 83 .

On the other hand, the CPU circuit 51 issues the display list DL to the drawing circuit 76 and the preloader 73 via the transfer port register TR_PORT incorporated in the data transfer circuit 72 . The CPU circuit 51 and the data transfer circuit 72 are bi-directionally connected. When the display list DL is issued, the transfer port register TR_PORT is used as a data write port for receiving one unit of data constituting the display list DL. Function. The write unit (one unit data length) of the transfer port register TR_PORT is 32 bits corresponding to the FIFO structure of the CPU bus control section 72d.

As shown, the effect control CPU 63 can WRITE access the transfer port register TR_PORT via the CPUIF unit 81, while the DMAC circuit 60 directly accesses the transfer port register TR_PORT when utilizing the DMAC circuit 60. WRITE access. A series of instruction commands written in the transfer port register TR_PORT (that is, a series of instruction commands forming the display list DL) are processed in 32-bit units by a CPU bus containing a FIFO buffer with a FIFO structure (32 bits x 130 stages). It is configured to be automatically stored in the control unit 72d.

In addition, the data transfer circuit 72 executes data transmission/reception operations on the transmission paths of three channels ChA to ChC, and has a FIFO buffer of a FIFO structure (64 bits×N stages) ChA control circuit 72a (N=130 stages), a ChB control circuit 72b (N=1026 stages), and a ChC control circuit 72c (N=130 stages).

Then, the instruction command string (display list DL) accumulated in the CPU bus control unit 72d is sent to the drawing circuit 76 or It is transferred to the preloader 73 . As indicated by the arrow, the display list DL is transferred from the CPU bus control section 72d to the drawing circuit 76 via the FIFO buffer of the ChB control circuit 72b, and transferred to the preloader 73 via the FIFO buffer of the ChC control circuit 72c. configured to be

In this embodiment, the ChB control circuit 72b and the ChC control circuit 72b are specialized for the transfer operation of the display list DL. 72b or ChC control circuit 72c, respectively, to the drawing circuit 76 or the display list analyzer of the preloader 73 as part of the display list DL.

The drawing circuit 76 then starts a drawing operation based on the transferred display list DL. On the other hand, the preloader 73 performs necessary preload operations based on the transferred display list DL. The CG data in the CGROM 55 is read ahead into the preload area secured in the DRAM 54 by the preload operation, and a display list DL (hereinafter referred to as a rewrite list DL') in which the texture source address is changed in relation to the TXLOAD command is secured in the DRAM 54. stored in the DL buffer area BUF'.

On the other hand, a ChA control circuit 72a and a connection bus access arbitration circuit 72e function for data transfer between storage media such as the CGROM 55, the DRAM 54, and the built-in VRAM 71. FIG. In addition, the IDXTBL access arbitration circuit 72f functions when accessing the built-in VRAM 71 that requires the address information of the index table IDXTBL. Specifically, the ChA control circuit 72a, for example, (a) transfers the compressed data of the CGROM 55 to the built-in VRAM 71, or (b) preloads (prefetches) the compressed data of the CGROM 55 and transfers it to the external DRAM 54. and (c) transferring pre-read data in the preload area to the built-in VRAM 71 .

Here, the ChA control circuit 72a is configured to be able to operate in parallel with the ChB control circuit 72b and the ChC control circuit 72c. 26, PT11 in FIG. 23) and the transfer operation of the rewrite list DL' (PT10 in FIG. 23). In addition, the ChB control circuit 72b and the ChC control circuit 72c can also be executed simultaneously. For example, the processing of step PT10 in FIG. can be executed by However, since there is only one transfer port register TR_PORT, at the timing when one of the transfer port registers TR_PORT is being used by one of them (72b/72c), the other (72c/72b) can access the transfer port register TR_PORT. can't.

During operation of the ChA control circuit 72a, the connection bus access arbitration circuit 72e arbitrates data transmission with each storage element (CGROM 55, DRAM 54) via the integrated connection bus ICM. On the other hand, the IDXTBL access arbitration circuit 72f arbitrates data communication with the built-in VRAM 71 by controlling the ChA control circuit 72a based on the index table IDXTBL. In the embodiment in which the preloader 73 functions, the rewrite list DL' stored in the DL buffer area BUF' of the DRAM 54 is transferred to the drawing circuit 76 via the connection bus access arbitration circuit 72e and the ChB control circuit 72b. (See FIG. 24(b)).

As described above, the data transfer circuit 72 of this embodiment has a data transfer source arbitrarily selected from various storage resources and a data transfer destination arbitrarily selected from various storage resources. It provides high-speed data transfer between As can be seen from FIG. 19, the storage resources on which the data transfer circuit 72 functions include not only the built-in VRAM 71 but also external devices via the CPUIF section 56, CG bus IF section 82, and DRAMIF section 83. FIG.

And, like the amount of data to be acquired from the CGROM 55 at one time (memory sequential READ), the amount of data transfer with an external device in which the ChA control circuit 72a functions is the display in which the ChB control circuit 72b and the ChC control circuit 72c function. The list DL is huge compared to the case of the list DL, and the amount of data transfer is greatly different from each other.

Here, it is conceivable that the unit data amount and the total transfer data amount can be finely set for these various types of data transfer. inhibited. Therefore, in the present embodiment, the minimum data amount Dmin for data transfer is uniquely defined, and the total transfer data amount is limited to an integral multiple of the minimum data amount DTmin, thereby achieving high-speed and smooth data transfer operations. Realized. Although not particularly limited, in the data transfer circuit 72 of the embodiment, the minimum data amount Dmin (unit data amount) is set to 256 bytes, and the total transfer data amount is limited to integral multiples of this.

Therefore, the instruction command string of the display list DL accumulated in the FIFO buffer of the CPU bus control section 72d for each 32 bits is transferred to the ChB control circuit 72b and the ChC control circuit 72b at the timing when the total amount reaches the minimum data amount Dmin. and stored in each FIFO buffer.

The display list DL consists of a series of instruction commands. In this embodiment, the command length of the display list DL is an integer N times 32 bits corresponding to the write unit (32 bits) of the transfer port register TR_PORT. It is composed only of (N>0) instruction commands. Therefore, the drawing circuit 76 and the preloader 73 that receive the instruction command of the display list DL via the data transfer circuit 72 can quickly and smoothly start command analysis processing (DL analyze). It should be noted that the command length of 32-bit integer N times does not necessarily mean that all of them are significant bits, but that it is 32-bit integer N times including non-significant bits (Don't care bits).

Next, the preloader 73 will be explained. As outlined above, the preloader 73 interprets the display list DL transferred from the data transfer circuit 72 (ChC control circuit 72b), and preloads the CG data on the CGROM 55 referenced by the TXLOAD command into the DRAM 54. It is a circuit that transfers to the preload area of . In addition, the preloader 73 stores in the DL buffer BUF' of the DRAM 54 the rewrite list DL' in which the reference destination of the CG data is rewritten to the address after transfer in relation to this TXLOAD command. Note that the DL buffer BUF' and the preload area are secured in advance during the initial processing after CPU reset (ST3 in FIG. 26).

The rewrite list DL' is transferred to the display list analyzer (DL Analyzer) of the drawing circuit 76 via the connection bus access arbitration circuit 72e of the data transfer circuit 72 and the ChB control circuit 72b when the drawing operation of the drawing circuit 76 is started. ). The drawing circuit 76 then executes the drawing operation based on the rewrite list DL'. Therefore, based on the TXLOAD command or the like, CG data that should originally be obtained from the CGROM 55 is obtained from the preload area of the DRAM 54 as preload data preloaded in the preload area. In this case, the preload data can be used repeatedly as long as it is not overwritten, and the preload data hit in the preload area is reused repeatedly.

In this embodiment, since the preload area is set in the external DRAM 54 having a sufficient storage capacity, the above cache hit function works effectively. Also, since the external DRAM 54 has a large storage capacity, it is possible to preload multiple frames of CG data at once, for example. That is, regarding the operation period of the preloader 73, the operation period of a series of preload operations including the read-ahead operation of the CG data is appropriately set within the range of integral multiples of the operation period δ during the intermittent operation of the VDP circuit 52. Multiple preloading is realized with

However, in the following description, for the sake of convenience, an embodiment without multiple preloading will be described, so the preloader 73 of the embodiment completes the preloading operation for one frame during one operation period (.delta.). As will be described later with reference to FIG. 26, in this embodiment, the operation cycle δ of the VDP circuit 52 during intermittent operation is 1/30 second, which is twice the cycle of the vertical synchronization signal of the display device DS1.

Next, the drawing circuit 76 sequentially analyzes the instruction command strings of the display list DL and the rewrite list DL' transferred via the data transfer circuit 72, and cooperates with the graphics decoder 75, the geometry engine 77, and the like. This is a circuit for drawing an image of one frame of each of the display devices DS1 and DS2 in a frame buffer formed in the VRAM 71. FIG.

As described above, in the embodiment in which the preloader 73 functions, the reference destination of the CG data of the rewrite list DL' is not the CGROM 55 but the preload area set in the DRAM 54. FIG. Therefore, sequential access to CG data that occurs during execution of drawing by the drawing circuit 76 can be executed quickly, and high-resolution moving images with rapid motion can be drawn without problems. In other words, according to this embodiment, it is possible to use an inexpensive SATA module as the CGROM 55 and execute complex and advanced image effects.

By the way, regardless of whether the preloader 73 is activated or not, the drawing circuit 76 cannot detect any garbled data when the display list DL or the rewrite list DL' is transferred. In addition, it is possible that the drawing circuit 76 freezes due to noise or the like, and the READ/WRITE access to the built-in VRAM 71 stops abnormally. Therefore, in this embodiment, when the drawing circuit 76 detects an irrational instruction command (analyze-disabled bit arrangement) or when there is no READ/WRITE access to the built-in VRAM 71 for a certain period of time, a drawing abnormal interrupt (drawing error interrupt is enabled). This point will be described later with reference to FIG. 26(d).

Next, as described with reference to FIG. 18, the frame buffer FB secured in the arbitrary area (c) of the VRAM 71 is a double buffer divided into a drawing area and a readout area, and the two areas are alternately switched between uses. to use. In this embodiment, since two display devices DS1 and DS2 are connected, two sections of frame buffers FBa/FBb are secured as shown in FIG. Therefore, the drawing circuit 76 draws the image data for one frame in the drawing area (writing area) of the frame buffer FBa for the display device DS1, and draws the drawing area (writing area) of the frame buffer FBa for the display device DS2. Then, one frame of image data is drawn. Note that when image data is written in the drawing area, the display circuit 74 reads the image data in the other read area (display area) and outputs it to each of the display devices DS1 and DS2.

The display circuit 74 is a circuit that reads the image data in the frame buffers FBa and FBb, performs final image processing, and outputs the data (see FIG. 20). Final image processing includes, for example, scaler scaling processing for enlarging/reducing the image, subtle color correction processing, and dithering processing for minimizing the quantization error of the entire image. Digital RGB signals (total of 24 bits) that have undergone these image processes are output together with the horizontal synchronizing signal and the vertical synchronizing signal. As shown in FIG. 20, this embodiment is provided with three systems of display circuits A/B/C that execute the above operations in parallel, and each display circuit 74A to 74C has a corresponding frame buffer. The image data of FBa/FBb/FBc are read out and the final image processing described above is executed. However, since there are two display devices in this embodiment, the frame buffer FBc is not secured and the display circuit 74C does not function.

In relation to this operation, the output selection section 79 of this embodiment transmits the output signal of the display circuit 74A to the LVDS section 80a, and transmits the output signal of the display circuit 74B to the LVDS section 80b (Fig. 20). Then, the LVDS unit 80a converts the image data (24-bit digital RGB signals in total) into LVDS signals, adds a pair for transmitting a clock signal, and outputs all five pairs of differential signals to the main display device DS1. ing. The main display device DS1 incorporates an LVDS signal conversion/reception unit RV, which restores the RGB signals from the LVDS signals and displays an image corresponding to the output of the display circuit 74A.

In this regard, the LVDS section 80b is the same. For a total of 24 bits of each 8-bit digital RGB signal, a pair for transmitting a clock signal is added, and all five pairs of differential signals are output to the conversion receiving section RV. The display device DS2 realizes image display by a total of 24-bit RGB signals received from the conversion receiving unit RV. Therefore, the sub display device DS2 and the main display device DS1 have a resolution of ²⁸ * ²⁸ * ²⁸ .

Note that the LVDS signal is not necessarily required. For example, when the transmission distance is short, the digital RGB signal is directly transmitted to the display device via the digital RGB section 80c. converts a digital RGB signal into a V-By-one (registered trademark) signal in a conversion transmitting section TR', transmits the V-By-one (registered trademark) signal to a conversion receiving section RV', and converts it back to a digital RGB signal in a conversion receiving section RV'. is also suitable. Although the dashed lines in FIG. 20 indicate this mode of operation, the above operation is possible for any of the output signals of the display circuits 74A to 74C by appropriately setting the operation of the output selection section 79. becomes.

By the way, in the case of this embodiment, each of the display circuits 74A to 74B is provided with underrun counters URCNTa to URCNTc for counting Underrun abnormalities in which the generation of display data is not in time with respect to the display timing (see FIG. 20). reference). The counter values of the underrun counters URCNTa to URCNTc are automatically added for each VBLANK when an underrun abnormality occurs.

Next, the SMC section 78 (Serial Management Controller) is a composite controller containing an LED controller and a Motor controller. Then, it outputs an LED drive signal and a motor drive signal in synchronization with the clock signal to the LED/Motor driver (driver IC with a built-in shift register) mounted on the external board, while outputting the latch pulse at an appropriate timing. configured for output.

Regarding the internal circuit and its operation of the VDP circuit 52 described above, the operation contents to be executed by the internal circuit are defined by the operation parameters (set values) set in the control register group 70 by the effect control CPU 63, and the execution of the VDP circuit 52 The state can be specified by reading the operation status value of the control register group 70 . The control register group 70 means a large number of VDP registers RGij mapped in an address space (0 to FFFFFH) of about 1 Mbyte on the memory map of the effect control CPU 63. WRITE (setting) operation of operation parameters and READ operation of operation status values are executed (see FIG. 14(b)).

The control register group 70 (VDP register RGij) includes "system control registers" in which initial setting values related to system operations such as interrupt operations are written, and the AAC area (a) and page area (b) in the built-in VRAM. , an "index table register" relating to building or changing the index table IDXTBL, and a "data transfer a "GDEC register" for specifying the execution status of the graphics decoder 75; a "drawing register" in which instruction commands and setting values relating to the drawing circuit 76 are written; and setting values relating to the operation of the preloader 73 are written. A "preloader register", a "display register" in which setting values relating to the operation of the display circuit 74 are written, an "LED control register" in which setting values relating to the LED controller (SMC unit 78) are written, a motor controller (SMC 78), and a "sound control register SRG" into which settings for the audio circuit SND are written. However, in this embodiment, the audio circuit SND is not utilized.

In any event, in the following description, one or a plurality of registers RGij included in the control register group 70 may be referred to by the individual names described above, or may be generically referred to as VDP registers RGij. The effect control CPU 63 controls the internal operation of the VDP circuit 52 by writing an appropriate set value to a predetermined VDP register RGij. Specifically, the effect control CPU 63 realizes a predetermined image effect based on the display list DL updated at appropriate time intervals and the set value in the predetermined VDP register RGij. In this embodiment, since the effect control CPU 63 is in charge of the lamp effect and the motor effect, the VDP register RGij also includes an LED control register and a motor control register.

Next, a unified effect control operation for image effect, sound effect, motor effect, and lamp effect realized by the composite chip 50 incorporating the CPU circuit 51 and the VDP circuit 52 will be described.

In the case of this embodiment, the operation of the composite chip 50 is started by a power-on reset operation (see FIG. 21A) due to power-on or an abnormal reset, and an initial setting process (SP1 to SP1) by an initial setting program (boot program) Pinit. Through SP9), it is configured to shift to the main control process (SP10) by the effect control program Main and the interrupt processing program (vector handler) Vopt. As for the main control processing, FIG. 23(a) describes the processing contents of the introductory part, and FIG. 26(a) describes the processing contents of the main body part. The processing of step SP27 in FIG. 23 includes the processing of steps ST1 to ST3 in FIG. 26(a).

Based on the above, the power-on reset operation will be described with reference to FIG. 21(a). When the system reset signal SYS maintains the L level for a predetermined period (assertion period) such as when power is turned on, all the operation control registers REG and all the VDP registers RGij are automatically set to predetermined default values. Then, after that, when the system reset signal SYS changes to H level (negate level), in this embodiment, first, 32-bit data from the head address of the address space CS0 is set in the program counter PC of the effect control CPU 63, The following 32-bit data is configured to be set in the stack pointer SP. Note that in FIGS. 16 and 22(c), the head area of the memory that stores the initial values of the program counter PC and stack pointer SP is called a vector table VECT.

As shown in FIG. 21(b), the vector table VECT stores vector numbers identifying priority levels, interrupt factors, etc., and address information in association with each other. The smaller the vector number, the higher the priority. For example, vector number 11 is a non-maskable interrupt (NMI), and the start address of the interrupt processing program executed at the time of the NMI interrupt is stored as address information. It is A vector number 64 is an internal interrupt (VDP_IRQ0) from the VDP, and as address information, the start address of the interrupt processing program executed at the time of the VDP_IRQ0 interrupt is stored.

Since the interrupt priority is as shown in FIG. 23(d), the control command reception interrupt IRQ_CMD, the 20 μS timer interrupt, and the 1 mS timer interrupt are shown in the columns of the vector numbers smaller than vector number 64. Each head address is stored. On the other hand, in columns of vector numbers larger than vector number 64, start addresses of interrupt processing programs (IRQ_SND, IRQ_RTC, etc.) having lower priority than VDP_IRQ1 are stored.

In the vector table VECT, vector numbers 0 and 1 define setting values that should be automatically set to the program counter and stack pointer of the CPU at power-on reset. As shown in FIG. 21(b), in this embodiment, 4-byte data "****" is set in the program counter PC as an internal operation at the time of power-on reset (reset assertion period), and 4-byte data " ++++" is set to the stack pointer SP. "****" is the top address value of the initial setting program Pinit (SP1 to SP9 in FIG. 21) nonvolatilely stored in the address space CS0, and "++++" is reserved in the built-in RAM 59. It is also the address value of the top or end of the stack area that functions in the LIFO (Last-In First-Out) method.

In this embodiment, since the register bank RBi is effectively utilized, the stack area is not consumed during interrupt processing, and a large memory capacity is not required. That is, in this embodiment, the stack area is exclusively used for function processing and subroutine processing.

As a result of the above operations, the effect control CPU 63 then executes the initial setting program Pinit described after the address value "****". However, the memory READ operation of the address space CS0 is executed based on the default value (initial value) of the operation control register REG that defines the operation of the bus state controller 66 (FIG. 15). The initial value of this operation control register REG is a value that is automatically set during the reset assert period (the period shown in FIG. 4(d) in which the system reset signal SYS maintains the L level). The slowest READ access operation (default access operation) is set so that READ access can be performed without problems even when configured with memory devices.

Therefore, in order to change this default access operation to the optimum access operation, first, an optimum value is set in a predetermined operation control register REG that defines the operation of the bus state controller 66 (FIG. 15) with respect to the address space CS0 ( SP1). That is, the initial setting program Pinit (SP1 to SP9), the production control program MainB (SP10), the memory READ operation when accessing the PROM53 storing constant data, etc., in order to optimize according to the memory device, the bus width and In addition to setting the presence or absence of page access, the chip select signal CS0, the READ control signal, the WRITE control signal, and other operation timings are optimally set (see FIG. 27).

As a result of the above settings, the processing after step SP2 is executed by optimally memory READing the program stored in the address space CS0. Therefore, next, the performance control CPU 63 performs predetermined operation control that defines the operation of the bus state controller 66 (FIG. 15) for the VDP register RGij in order to optimize the READ/WRITE access operation when accessing the VDP register RGij. An optimum value is set in the register REG (SP2).

As described above, in this embodiment, the VDP register RGij is positioned in the address space CS7 of the effect control CPU 63. Therefore, a predetermined operation timing of the chip select signal CS7 and other control signals is optimally set. A predetermined value is written in the operation control register REG.

Subsequently, the register value of a specific VDP register RGij is read, and it is determined whether or not the value is a predetermined value (device code) (SP3). This is confirmation determination that the system clock of the VDP circuit 52 has stabilized. That is, the VDP circuit 52 operates based on the oscillation output of the oscillator OSC2 supplied to the PLLREF terminal. It is a judgment whether or not it is possible to accept it.

Then, if it can be confirmed that the system clock has stabilized by the device code reading process (SP3), the normal operation of the VDP circuit 52 can be expected thereafter, so the setting process for the predetermined VDP register RGij is executed (SP4 ~SP6). Specifically, first, the endian setting (big/little) when accessing the VDP register RGij from the effect control CPU 63 and the data bus width are set (SP4).

In this embodiment, the most significant bit of the setting value is set to big endian to be stored in the most significant bit of the VDP register RGij, and the data 32 bus width is set to 32 bits. If the values are the same as the default values, these setting processes can be omitted (the same applies to the following processes).

Next, for the internal interrupts (VDP_IRQ0, VDP_IRQ1, VDP_IRQ2, VDP_IRQ3) from the VDP circuit to the CPU circuit, the interrupt significance level (H/L) is set, and the clock signal ( DDR (DRAM 54) is set to function (SP4). As described with reference to FIG. 14A, the reference clock of the oscillator OSC2 is supplied to the PLLREF terminal.

Subsequently, address spaces CS1 to CS6 are defined to implement the memory map shown in FIG. 16 (SP5). As described above, the address space CS3 is assigned to the internal registers of the audio processor 27, the address space CS4 is assigned to the internal registers of the RTC 38 and the address space of the SRAM 39, and the address space CS5 is assigned to the external DRAM (DDR). 54, and the address space CS6 is assigned to the work memory 57 of the built-in CPU.

Since it is fixedly defined that the VDP register RGij is assigned to the address space CS7, definition processing of the address space CS7 is unnecessary. Further, the address space CS0 is preliminarily defined to be located at the address 0x000000000 or later in the memory map of the CPU circuit 51. Based on this definition, the address space CS0 is secured in the CGROM 55 or other memory. The H/L level of the HBTSL terminal determines whether it is applied to the device.

As described above, in this embodiment, the HBTSL terminal=L, indicating that the address space CS0 is defined in addition to the CGROM 55. FIG. Since the specific bus width of the control memory 53 other than the CGROM 55 and the optimum access operation have already been set in step SP1, the processing of step SP5 is unnecessary for the address space CS0 as well.

Subsequently, for the address spaces CS1 to CS6 defined in the process of step SP5, a predetermined value is written in a predetermined operation control register REG regarding the bus width and presence/absence of page access when accessing each address space CSi (SP6 ). Also, in order to optimally set the chip select signal CSi and others, a predetermined value is written in a predetermined operation control register REG (SP6). These processes are the same as the processes of steps SP1 and SP2. By writing to the operation control register that defines the operation of the bus state controller 66 (FIG. 15), the chip select signal CSi, READ control signal, WRITE Control signals and other operation timings are optimally set.

Subsequently, the abnormal reset is avoided by outputting a clear signal to the WDT circuit 58 (SP7). This is in consideration of the fact that the WDT circuit 58 automatically starts operating after the power is turned on, and after that, the same processing is repeatedly executed. The processing of step SP9 is stored in the control memory 53 as a subroutine SP7, but until the end of step SP9, the subroutine SP7 of the control memory 53 is called. Another transferred subroutine SP7' is called and executed.

Subsequently, among the programs and data stored in the address space CS0, the vector handler Vopt (interrupt processing program) shown in FIGS. The variable D with an initial value and the constant data C are transferred to the external DRAM 54 and internal RAM 59 (SP8). The variable D with an initial value means initial value data stored in a predetermined variable area. This memory section initialization process (SP8) is a process of transferring programs and data in order to speed up the effect control process, and is a process of avoiding access to the ROM, which is inferior in access speed.

Then, a setting is made to indicate that the register bank RBi is to be used (SP9). Therefore, after that, the register banks RB0 to RB14 function during interrupt processing, which speeds up the interrupt processing and reduces the consumption of the stack area.

The above processing is realized by executing the "initial setting program Pinit" stored in the control memory 53, which is the address space CS0 (see FIG. 22(c)). After the execution of the initial setting program Pinit is finished, the main control process by the effect control program Main is executed (SP10). Here, execution of the main control process means execution of the "effect control program Main" transferred from the control memory 53 to the external DRAM 54 by the transfer process of step SP8 (see FIG. 21(b)).

The specific contents of the main control process (effect control program Main) will be described with reference to FIG. 23(a) and FIG. 26(a). will be explained. As shown in FIG. 22(a), in the memory section initialization process (SP8), first, the DMACs of a plurality of channels are initialized to stop operation. It should be noted that this process is merely a formal process just in case.

When the above processing is completed, the DMACi of the predetermined channel is activated, and the vector handler Vopt (interrupt processing program) stored in the control memory 53 is transferred to the internal RAM 59 by a non-stop transfer method (see FIG. 17(b3)). DMA transfer. In this embodiment, since the interrupt processing program Vopt is transferred to the built-in RAM 59, even when the external DRAM 54 malfunctions, an appropriate abnormality handling process can be performed.

Subsequent processing is also the same, and is executed by a non-stop transfer method using the DMACi of a predetermined channel, and the error recovery processing program Piram is DMA-transferred to the built-in RAM 59 (SP62). In this embodiment, since the error recovery processing program Piram is transferred to the built-in RAM 59, the peripheral circuits can be reliably reset in the error recovery processing. For example, if the error recovery processing program Piram is transferred to, for example, the external DRAM 54 other than the internal RAM 59, the external DRAM 54 cannot be reset during the error recovery processing.

Next, the effect control program Main is DMA-transferred to the external DRAM 54 (SP63), and the constant data C is DMA-transferred to the external DRAM 54 (SP64). The constant data includes lottery data to be used for effect lottery, and lamp drive data and motor drive data in various drive data tables shown in FIG. 26(b). Also, the variable D having an initial value is DMA-transferred to the external DRAM 54 (SP65).

Finally, the clear data is written to the beginning of the variable area B of the external DRAM (SP66). Assuming that this head address is ADb, in the subsequent DMA transfer processing, after initializing the transfer source address as ADb and the transfer destination address as ADb+1, each address value ADb, ADb+1 is incremented and this clear data is diffused, the variable area B is cleared (SP67).

The processes of steps SP61 to SP66 and step SP67 described above are all similar operations, as shown in FIG. 22(b). That is, first, regarding the DMACi of a predetermined channel, the DMA transfer conditions are (1) cycle steal transfer mode, (2) non-stop transfer method, and (3) update the address values of Source and Destination by increments. SP68).

Next, the initial values of the source address of the transfer source and the destination address of the transfer destination are set (SP69), the transfer size is set, interrupts are disabled (SP70), and the DMA transfer operation is started (SP71). ). Note that the settings in steps SP68 to SP71 are all realized by a setting operation to a predetermined operation control register REG.

In the initialization processing of this memory section, interrupts for the end of DMA transfer are disabled (SP70). and waits for the end of the DMA transfer (SP72). However, considering the processing time until the end of the operation, the clear signal is repeatedly output to the WDT circuit 58 (SP73). At the end of the DMA transfer, the DMACi is set to stop based on the setting operation to the predetermined operation control register REG.

Next, the operation contents of the main control process will be described with reference to FIGS. 23 to 26. FIG. As described above, for the main control process, FIG. 23(a) describes the processing contents of the introduction part (SP20 to SP27), and the processing contents of the main part (ST4 to ST14) are shown in FIG. a). The processing of step SP27 in FIG. 23 includes the processing of steps ST1 to ST3 in FIG. 26(a).

As shown in FIG. 23(a), in the main control process (introductory part), first, the bus width and type of ROM device of the CGROM 55 are specified (SP20). Specifically, as shown in FIG. 24(a), a predetermined VDP register RGij (for example, CG bus Status register) specifying the operating state of the CG bus that controls the interface with the CGROM 55 is read-accessed (SP80 ), it is determined whether or not the CG bus can be set for operation (SP81).

Here, if the value of the CG bus Status register is 1, it means that the internal circuit of the CG bus is in the process of resetting, meaning that the set value to the VDP register RGij cannot be accepted. Therefore, after confirming that the value of the CG bus Status register has changed from 1 to 0 (SP81), ( Operation parameters such as 1) enable/disable of each device section SPAi, (2) ROM device type, and (3) data bus width are set in a predetermined VDP register RGij (SP82).

As shown in FIG. 23(a), in this embodiment, the CGROM 55 can be divided into a plurality of areas (device sections). can be selected. As memory devices, for example, (1) SATA module (AHSI/F) adopted in this embodiment, (2) memory element adopting parallel I/F (Interface) type, (3) sequential I/F type adopting It is roughly classified into memory devices and the like, and for each of the roughly classified memory devices, the memory device can be specifically selected and the data bus width can be arbitrarily defined.

Next, predetermined operation parameters are set in predetermined VDP registers RGij in order to optimize memory READ operations with memory devices selected for each device section (SPA0 to SPAn) (SP83). The operation parameters include set values that define the operation timings of the chip select signal and other control signals (such as the READ control signal). Also, when a memory element adopting the sequential I/F format is selected, the output timing of the address latch, the number of read clocks, etc. are also specified in order to realize the operation shown in FIG. 24(b).

Therefore, the CGROM 55 can be configured by combining different types of memory devices. However, in this embodiment, the CGROM 55 is configured using only SATA modules, only the device section (SPA0) is enabled, and the other device sections (SPA1 to SPAn) are disabled.

In any case, when the setting processing of steps SP82 and SP83 is completed, a predetermined value is written in a predetermined VDP register RGij in order to make the setting processing effective (SP84). This is in consideration of the fact that it takes a certain amount of time for the internal circuits of the CG bus to operate in response to the setting processing of steps SP82 and SP83. (see SP80) becomes 0.

Therefore, after that, the CG bus Status register is repeatedly read-accessed (SP85), and the process is finished after confirming that the value of the Status register returns from 1 to 0 (SP86). It should be noted that the process of step SP66 may be ended when the value of the Status register does not return from 1 to 0 regardless of the number of determinations made a predetermined number of times. However, in that case, since the game process starts in a state in which the CGROM cannot be normally accessed, the WDT circuit 58 is activated at some timing after that, and the composite chip 50 enters an abnormal reset state. In this case, the power-on reset operation is executed again.

On the other hand, after the process of step SP20 in FIG. 23 is normally executed, internal circuits of the CPU circuit 51, such as the interrupt controller INTC, the DMAC circuit 60, and the multifunction timer unit MTU, are individually initialized by software processing. (SP21).

Next, for the multi-function timer unit MTU, after starting a predetermined timer measurement operation (SP22), the internal interrupt and the internal interrupt are set to an interrupt enabled state by writing a permission setting value to a predetermined operation control register REG. (SP23).

As a result, after that, various interrupts shown in FIG. 23(d) can occur. Normally, at this timing, the audio processor 27 has finished its initialization sequence, so the end interrupt signal IRQ_SND should have fallen to the L level as shown in FIG. 4(c). Therefore, the interrupt processing shown in FIG. 23(c) is started, and the effect control CPU 63 initializes the error flag ERR to 1, and READ-accesses the address space CS3 (SP30), and the predetermined sound of the sound processor 27 The value of the register SRG is obtained and it is determined whether the initialization sequence has ended normally (SP31).

If the initialization sequence is not completed normally, the effect control CPU 63 writes a reset command to a predetermined voice register SRG of the voice processor 27 (SP32), and is initialized to 1. set the error flag ERR to 2 (SP33). This error flag ERR defines whether or not to execute the speech processor initialization process (SP26), and the error flag ERR=1 is the execution condition of step SP26.

On the other hand, in response to receiving the reset command, the audio processor 27 restarts the initialization sequence with the end interrupt signal IRQ_SND=H level. Lower to L level. As a result, the process of FIG. 23(c) is re-executed.

The above describes an exceptional case in which the initialization sequence is not normally completed, but normally, following step SP31, the process of step SP32 is executed, and the effect control CPU 63 stores a predetermined sound register SRG, By writing a predetermined value, the termination interrupt signal IRQ_SND is returned from L level to H level (SP34).

Finally, by writing a predetermined value to a predetermined voice register SRG, READ/WRITE access to all voice registers SRG is permitted (SP35). As a result of this processing, necessary setting processing can be executed in the subsequent voice processor initialization processing (SP26).

An example of the Maskable Interrupt corresponding to the interrupt permission setting in step SP23 has been described above, but a non-maskable interrupt based on the oscillation stop of the oscillator OSC2 can be activated at any timing. As described above, the operating clocks of the circuits other than the built-in CPU (performance control CPU 63) are generated by frequency-multiplying the output clock of the oscillator OSC2 by PLL (Phase Locked Loop), and the oscillation of the oscillator OSC2 is stopped. If so, normal operation of the VDP circuit 52 after that is impossible.

On the other hand, the operation clock of the effect control CPU 63 is generated by multiplying the output clock of the oscillator OSC1 by the PLL, and the program processing can be continued. Moreover, the interrupt processing program is stored in the built-in RAM 59 . Therefore, the effect control CPU 63 notifies the occurrence of the abnormal situation by sound or lamp (SP28), and continues outputting the clear signal to the WDT circuit 58 (SP29). The anomaly notification is, for example, a voice notification saying, "An abnormal situation has occurred. Please contact the person in charge as soon as possible." The reason why the clear signal is continuously output to the WDT circuit 58 is to avoid an abnormal reset operation. That is, in the event of a serious abnormality in which the oscillator OSC1 stops operating, even if the abnormality reset process is repeated, the device cannot be expected to return to normal.

23(b) and 23(c) have been described above, the description will be continued by returning to FIG. 23(a). At step SP24, in order to protect the program area of the external DRAM, the required area is set to be write-inhibited. Next, the clock circuit 38, which is battery-powered when the power is cut off, is checked for normal operation when the power is turned off, and the alarm interrupt is set again just in case (SP25).

Then, under the condition that the error flag ERR=1, the necessary set values are written into the built-in register (sound register SRG) of the sound processor 27 to execute initialization processing (SP26). When the error flag ERR=0, the process waits for a predetermined time until the error flag ERR=1, but when the limit time is exceeded, the WDT circuit 58 is activated to shift to infinite loop processing.

Next, the VDP circuit 52 is initialized by writing necessary set values to the VDP register RGij (SP27). The processing of step SP27 includes the processing of ST1 to ST3 of FIG.

Although the embodiment in which the termination interrupt signal IRQ_SND is received from the audio processor has been described above, it is also preferable to omit the interrupt processing in FIG. 23(c). FIG. 25 shows a modified embodiment, in which a 1 ms timer interrupt signal generated by the multifunction timer unit MTU is used instead of the end interrupt signal IRQ_SND.

FIG. 25 illustrates part of the 1ms timer interrupt processing, and realizes four stages of operation based on the value (0/1/2/3) of the operation management flag FLG whose initial state is zero. are doing. The IRQ_SND output terminal of the audio processor 27 is in an open state, and the IRQ_SND input terminal of the CPU circuit 51 is fixed at H level.

In the 1mS timer interrupt processing, first, when it is determined that the operation management flag FLG=0 in the processing of step SP42, it is confirmed that the initialization sequence of the audio processor 27 has been completed normally (SP43). If the operation has been completed normally, the interrupt signal (IRQ_SND) is cleared by writing a predetermined value to a predetermined voice register SRG (SP46), and the operation management flag FLG is set to 1 (SP47). The processing of steps SP43 and SP46 is the same as the processing of steps SP31 and SP34 in FIG. 23(c).

On the other hand, if the initialization sequence has not ended normally, the voice processor 27 is caused to start the initialization sequence by writing a reset command to a predetermined voice register SRG (SP44), and the operation management flag FLG is set to zero. Return (SP45). The processing of step SP44 corresponds to the processing of step SP32 in FIG. 23(c).

Normally, after the processing of step SP47, the operation control flag FLG=1, so in the next 1 ms timer interrupt, writing a predetermined value to a predetermined voice register permits access to all voice registers (SP48). ), and the operation control flag FLG is set to 2 (SP49). The processing of step SP48 corresponds to the processing of step SP35 in FIG. 23(c).

Next, in the 1 ms timer interrupt with the operation control flag FLG=2, as in the case of step SP26 in FIG. Initialization processing is executed (SP50), and the operation management flag FLG is set to 3.

The operation management flag FLG=3 means a normal voice control state, and by setting necessary operation parameters in the necessary voice register SRG, the voice control is advanced (SP52).

As described above, the normal end of the initialization sequence of the audio processor 27 is confirmed by the interrupt processing caused by the interrupt signal (IRQ_SND) (SP31 in FIG. 23(c)) and by the 1 ms timer interrupt processing (FIG. 25). SP43) of the method has been described, but the method is not limited to these methods in any way. For example, as part of the processing of step SP26 in FIG. 23, it is also preferable to determine whether the initialization sequence of the audio processor 27 has been completed normally.

Since the introduction part of the main control process (SP20 to SP27 in FIG. 23) has been described above, the operation of the main part of the main control process will be described below with reference to FIG. As shown in FIG. 26, the operation of the effect control CPU 63 is the main control process (a), the timer interrupt process (b) that starts every 1 ms, and the reception interrupt process (not shown) that starts in response to the control command CMD. , VBLANK interrupt processing (c) that is activated by receiving the VBLANK signal generated at the start timing of the V blank (vertical blanking interval) of the display device DS1, and drawing abnormal interrupt processing ( d) and Note that the description of the 20 μs interrupt processing is omitted.

In the reception interrupt process, the control command CMD received from the main control section 21 is stored in a predetermined reception buffer so that it can be referred to in the main control process (ST13), and the process ends. In addition, in the VBLANK interrupt processing (FIG. 26(b)), the interrupt counter VCNT is incremented (ST15) for each VBLANK interrupt, and at the start timing of the main control processing, 1/30 second is calculated based on the value of the interrupt counter VCNT. After grasping the operation start timing, the interrupt counter VCNT is cleared to zero (ST4).

On the other hand, as shown in FIG. 26(b), the timer interrupt processing includes progress processing (ST18) for ramp effects and motor effects, and sensor signal acquisition processing for acquiring origin sensor signals SN0 to SNn signals, chance button signals, and the like. (ST19). The lamp effect and the motor effect are controlled based on the effect scenario that centrally manages all the effect operations, and when the effect start time managed by the effect counter EN is reached, the motor drive table and the motor drive table are changed in the effect scenario update process (ST11). A lamp drive table is specified.

After that, the motor effect progresses based on the specified motor drive table, and the lamp effect progresses based on the specified motor drive table. As explained above, in some embodiments, the DMAC circuit (first and second DMA channels) 60 functions during the operation of step ST18. Note that the motor effect progresses every 1 ms, but the ramp effect progresses at an appropriate timing longer than 1 ms.

On the other hand, as shown in FIG. 26(d), in the abnormal drawing interrupt process, the status register RGij indicating the operating state of the drawing circuit 76 is read-accessed to identify the cause of the interrupt. Specifically, (1) the abnormal drawing interrupt due to the detection of an abnormal instruction command (bit garbled) or (2) the abnormal drawing interrupt due to the abnormal operation (freeze) of the drawing circuit 76 is specified (ST16a). If the abnormal drawing interrupt is detected based on the detection of an abnormal instruction command, the drawing circuit 76 is initialized by writing a predetermined value to a predetermined system control register RGij (ST16b). This operation is nothing but the individual reset operation of the reset path 4B shown in FIG. 13(b).

Next, after confirming the normal completion of the individual reset operation with a predetermined status register RGij, a group of operation parameters that define the operation of the drawing circuit 76 are reset to the predetermined drawing register RGij, and the process ends (ST16c). . After adjusting the stack area for storing the return address (clearing process for erasing the return address after the interrupt processing), the process proceeds to step ST13 (ST16c).

On the other hand, in the case of an abnormal drawing interrupt due to an abnormal operation of the drawing circuit 76, the WDT circuit 58 is activated and the entire composite chip 50 is reset by shifting to infinite loop processing (ST16d). If it is not desired to reset the CPU circuit 51, a predetermined keyword string may be output to the pattern check circuit CHK, and only the VDP circuit 52 may be reset by the reset signal RST (see FIG. 13(b)). . In this case, after confirming the normal completion of the reset operation of the VDP circuit 52, the processing of steps ST4 and ST13 is performed. In order to avoid reading the control command CMD as much as possible, it is better to proceed from step ST4 to step ST13, including other cases.

When the entire composite chip 50 is reset, the presentation up to that point disappears and the presentation control is completely returned to the initial state (power-on state), but when only the VDP circuit 52 is reset, the reset operation of the VDP circuit 52 Although a predetermined standby time occurs until is completed, a series of effect control can be continued. In addition, since the effect control CPU 63 controls the image effect, the lamp effect, and the sound effect in a unified manner, there is no unnatural deviation in each effect.

Next, the main control process (a) will be described for an embodiment in which the preloader does not function. As shown in FIG. 26(a), the main control process consists of an introduction initial process (ST1 to ST3) executed after the CPU is reset, and then a regular process (ST4 to ST14) repeatedly executed every 1/30th of a second. classified into Note that the initial processing (ST1 to ST3) is part of the introductory part of the main control processing, and the regular processing means the body of the main control processing.

Since the steady process is started at the timing when the interrupt counter VCNT becomes VCNT≧2 (ST4), the operation period δ of the steady process is 1/30 seconds. This operating cycle δ is nothing but the substantial operating cycle δ of the VDP circuit 52 that operates intermittently under the control of the effect control CPU 63 . The reason why the judgment condition is set to VCNT≧2 is to take into account the possibility that the steady process (ST4 to ST14) is abnormally prolonged and the timing of VCNT=2 is missed. is designed so that it does not occur.

Continuing the description of the main control process (FIG. 26(a)) based on the above, in the present embodiment, in the initial process, the built-in VRAM 71 with a storage capacity of 48 Mbytes is used as the ACC area (a) having an appropriate storage capacity. , a page area (b) and an arbitrary area (c) (ST1). Specifically, for the ACC area (a1, a2) and the page area (b), the head address of each area and the required total data size are set in a predetermined index table register RGij (ST1). Then, the reserved ACC area (a1, a2) and the remaining area not included in the page area (b) become the arbitrary area (c).

Here, the lower 11 bits of the area start addresses of the first and second ACC areas (a1, a2) and the page area (b) must be 0, but they can be arbitrarily selected in units of 2048 bits. (1 address = 1 byte, selection for each 256 addresses). Also, the total data size is arbitrarily selected within the range of integral multiples of the unit size. Although not particularly limited, the unit size of the ACC area (a) is 2048 bits, and the unit size of the page area (b) is 512 kbits.

Thus, in this embodiment, certain conditions are set for setting the ACC area (a1, a2) and the page area (b). This is for the purpose of facilitating the internal operation of the VDP circuit 52 while eliminating the area. In other words, if the storage capacity of the built-in VRAM 71 is recklessly increased, there is concern that the manufacturing cost will rise and the chip area will increase. This is because the processing time for VRAM access cannot be shortened due to complication. It is for the same reason that certain restrictions are placed on securing the index space described below.

Continuing the explanation based on the above, following the processing of step ST1, necessary index spaces IDXi are secured for the page area (b) and the arbitrary area (c) (ST2). Specifically, by setting necessary information in a predetermined index table register RGij, an index space IDXi for each area (b) and (c) is secured.

For example, when an index space IDXi is provided in the page area (b), multiple information of an arbitrary horizontal size Hx and an arbitrary vertical size Wx (vertical and horizontal multiple information for the unit space) ) is set in a predetermined index table register RGij (ST2).

As described above, the index space IDXi of the page area (b) has a horizontal size of 128×vertical size of 128 lines as a unit space, and one pixel is specified by 32-bit information. Based on the setting of the size Wx, an index space IDXi of data size (bit length)=32×128×Hx×128×Wx is secured. The head address (space head address) of the index space IDXi in the page area (b) is automatically assigned internally.

When the index space IDXi is provided in the arbitrary area (c), an arbitrary start address (space start address) STx and information on multiples of an arbitrary horizontal size Hx corresponding to an arbitrary index number i are specified. is set in the index table register RGij (ST2). Arbitrary means that the horizontal size Hx is arbitrarily determined in units of 256 bits, the lower 11 bits of the start address STx are 0, and is arbitrarily determined in units of 2048 bits. As described above, the vertical size of the arbitrary area is fixed to 2048 lines, so based on the setting of the horizontal size Hx, after the start address STx, the data size (bit length) = 2048 × Hx index A space has been secured.

Specifically, as the frame buffer FBa of the main display device DS1, a pair of index spaces each having a horizontal size of 1280×vertical lines of 2048 are set in one or a plurality of predetermined index table registers RGij, each specifying an index number. , as the frame buffer FBb of the sub-display device DS2, a pair of index spaces of horizontal size 480×vertical lines 2048 are set in one or more predetermined index table registers RGij, each specifying an index number. If the number of horizontal pixels of the display device does not match the integer multiple of 256 bits/32 bits, the horizontal size of each index space should be larger than the number of horizontal pixels of the display device and 256/32=8 , to minimize wasted memory space.

As described above, the necessary number of index spaces IDXi are generated by setting the necessary size information and address information in the predetermined index table registers RGij for the page area (b) and the arbitrary area (c). (ST2). In response to this setting process (ST2), an index table IDXTBL for specifying the address information and size information of each index space IDXi is automatically constructed. As shown in FIG. 18(a), the index table IDXTBL stores the start address of each index space IDXi together with other necessary information. ) is referred to when acquiring data from (see FIG. 19). The index space IDXi of the AAC area (a) is automatically generated when necessary and is automatically deleted, so the setting process of step ST2 is unnecessary.

As shown in FIGS. 18(a) and 18(b), a pair of frame buffers FBa and FBb are secured in the arbitrary area (c), and index numbers are assigned to each pair. In an embodiment that does not use the Z-buffer, a pair of index spaces 255 and 254 assigned index numbers 255 and 254 are reserved as the frame buffer FBa. A pair of index spaces 252 and 251 to which index numbers 252 and 251 are assigned are secured as the frame buffer FBb. In this embodiment, a work area with index number 0 (index space 0) is also secured in the arbitrary area (c).

Also, in this embodiment, the necessary number of index spaces IDXi for decoding IP stream moving images are secured in the page area (a), and the index number i is assigned. However, initially, only the index space IDX ₀ for the background moving image (IP stream moving image) is reserved. Then, according to the necessity of the image effect (fluctuation effect and advance notice effect), the index space IDXj of the page area (a) is increased based on the setting process to the index table register RGij and the instruction command of the display list DL, After that, when it becomes unnecessary, the index space IDXj is released. That is, FIG. 18(a) shows the index table IDXTBL during steady operation.

The index space of the ACC area (a) is automatically generated when necessary based on the instruction command described in the display list DL. and other necessary information are automatically set. In this embodiment, this AAC area (a) is used as a decoding area for textures such as still images.

The above operation of securing the index space is realized mainly by setting the index table register RGij included in the control register group 70. Following the processing of steps ST1 and ST2, another VDP register RGij is set to: The steady operation (intermittent operation) of the VDP circuit 52 is made possible by executing the necessary setting operation.

For example, by writing predetermined operation parameters (the number of lines and the number of pixels) in a predetermined display register RGij that defines the operation of the display circuit 74, the number of display lines and the number of horizontal pixels are set for each of the display devices DS1 and SD2. (SS30). As a result, in each of the frame buffers FBa and FBb, the vertical and horizontal dimensions of the valid data area (broken line portion in FIG. 26(e)) to be read-accessed by the display circuit 74 are specified.

Next, a predetermined operation parameter (address value) is written in a predetermined display register RGij to specify the vertical display start position and horizontal display start position for each of the frame buffers FBa and FBb (SS31). As a result, the effective data area whose vertical and horizontal dimensions are specified in the process of step SS30 is determined on the frame buffers FBa and FBb. Here, the vertical display start position and the horizontal display start position are relative address values in each index space, and the display start position is (0, 0) in the example shown in FIG. 26(e).

Subsequently, the display register RGij (DSPAINDEX) relating to the display circuit 74A driving the main display device DS1 and the display register RGij (DSPBINDEX) relating to the display circuit 74B driving the sub-display device DS2 are respectively filled with "display area (0)". and "display area (1)" are set to define each display area (SS32).

Here, the "display area" means an index space (frame buffers FBa, FBb) from which image data should be read in order for the display circuits 74A, 74B to drive the display devices DS1, DS2. means either one of the double buffers in the frame buffers FBa and FBb. However, the display circuits 74A and 74B actually read the image data only in the "effective data area" specified in steps SS30 to SS31 in the display area (0) or the display area (1).

Although not limited in any way, in this embodiment, for the frame buffer FBa, the index space 254 of the index number 254 in the VRAM arbitrary area (c) is defined as "display area (0)", and the index number in the VRAM arbitrary area (c) 255 index space 255 is defined as "display area (1)" (SS32).

As for the frame buffer FBb, the index space 251 of the index number 251 in the VRAM arbitrary area (c) is designated as "display area (0)", and the index space 252 of the index number 252 in the VRAM arbitrary area (c) is designated as "display area ( 1)” (SS32). It should be noted that defining the "display area" in the initial processing (SS3) is not particularly limited. You can switch.

In this embodiment, after the above initial processing (SS30 to SS32) is completed, next, the set value of the predetermined system control register RGij is set to the first type prohibition setting so as not to be changed by the influence of noise or the like. A predetermined prohibition value is set in the register RGij (first prohibition setting SS33).

Here, the setting values for which future writing is prohibited include (1) setting values related to the display clocks of the display devices DS1 and DS2, (2) setting values related to the sampling clock of the LVDS, and (3) selection of the output selection circuit 79. (4) a synchronous relationship between the plurality of display circuits DS1 and DS2 (that the display circuit 74B is subordinate to the operation cycle of the display circuit 74A); Although there is software processing for canceling the first prohibition setting, it is not used in this embodiment. However, it is also suitable to use it as needed.

Next, by setting a predetermined prohibition value in the type 2 prohibition setting register RGij, the VDP register RGij of the initial setting system is write-prohibited (second prohibition setting SS34). Here, the prohibited registers include the VDP registers RGij related to steps SS30 to SS32.

On the other hand, by setting a predetermined prohibition value in the third type of prohibition setting register RGij, it is possible to prohibit many VDP registers, including the VDP registers related to the setting process of steps ST1 to ST3 (see the 3 prohibition setting). However, it is not used in principle in this embodiment. In any case, the second prohibition setting and the third prohibition setting can be arbitrarily released by writing a release value to a predetermined release register RGij, and the set value can be changed during steady operation. is also possible.

The initial setting processing of steps ST1 to ST3 described above is executed based on the initial value setting table SETTABLE (see FIG. 31) that associates the register address value of the VDP register RGij with the setting value of the register RGij. be done. Since the initial setting process has been described above, next, before describing the steady process (ST4 to ST14), the steady operation (intermittent operation) of the VDP circuit 52 controlled by the effect control CPU 63 is shown in FIGS. A schematic description will be given based on FIG. 26(b).

The intermittent operation of the VDP circuit 52 is as shown in FIGS. 26 and 26. In an embodiment in which the preloader 73 is not used, the display list DLi completed by the effect control CPU 63 is as shown in FIG. In the operation cycle (T1), the drawing circuit 76 is issued, and the drawing circuit 76 completes the image data in the frame buffers FBa and FBb by the drawing operation based on the display list DLi. Then, the image data completed in the frame buffers FBa and FBb are output by the display circuit 74 to the display devices DS1 and DS2 in the next operation period T1+.delta. , becomes a display screen that the player perceives.

On the other hand, in the embodiment using preloader 73, as shown in FIG. , interprets the display list DLi, performs the necessary look-ahead operations, and rewrites a portion of the display list DLi to complete the rewrite list DL'. The pre-read CG data and rewrite list DL' are stored in appropriate locations in the DRAM 54. FIG.

Next, the drawing circuit 76 acquires the rewrite list DL' from the DRAM 54 in the next operation period (T1+.delta.), and completes the image data in the frame buffers FBa and FBb by the drawing operation based on the rewrite list DL'. . Then, the image data completed in the frame buffers FBa and FBb are output by the display circuit 74 to the display devices DS1 and DS2 in the next operation cycle (T1+2δ), thereby enabling subsequent drawing of the display devices DS1 and DS2. Based on the action, it becomes a display screen that the player perceives.

The intermittent operation of the VDP circuit 52 has been briefly described above, but in order to realize the above-described intermittent operation, the effect control CPU 63 repeatedly refers to the value of the interrupt counter VCNT after the initial processing (ST1 to ST3). , until the operation start timing is reached, and when the operation start timing (V blank start timing of one skip) is reached, the interrupt counter VCNT is cleared to zero (ST4).

After that, steady operation is started. In this embodiment, first, it is determined whether or not an operation start condition for starting steady operation is satisfied (ST5). This determination timing is the start timing of the vertical blanking period (VBLANK) of the display device DS1. The display timing of the display device DS2 is set at the initial setting (ST3) so as to follow the display timing of the display device DS1.

Since the operation start condition determined by the start timing of the vertical blanking interval (VBLANK) differs depending on whether the preloader 73 is used or not, an embodiment (FIG. 26) in which the preloader 73 is not used will be described first. In this case, the circuit configuration and program are originally designed so that the internal operation of the VDP proceeds as shown in the time chart of FIG. 26(a). That is, based on the display list DL1 completed in the operating cycle (T1), the drawing circuit 76 should finish the drawing operation during the operating cycle (T1 to T1+δ). However, for example, like the display list DL3 completed in the operation cycle (T1+2δ) of FIG. In addition, regarding the display circuit 74, there is a possibility that an underrun abnormality has occurred in which display data is not generated in time with respect to the display timing.

The determination process of step ST5 takes this situation into consideration, and the effect control CPU 63 accesses the status register RGij (a kind of the control register group 70) indicating the operation state of the drawing circuit 76, and at the timing of step ST5, The drawing circuit 76 determines whether or not necessary operations have been completed, and whether or not there is an Underrun abnormality. The presence or absence of Underrun abnormality is determined based on underrun counters URCNTa to URCNTc. Also, in an embodiment in which the preloader 73 is not used, for example, at timing T1+.delta. in FIG. to confirm.

Then, if the operation start condition is not satisfied (abnormal/unsuitable), the abnormality flag ER that counts the number of abnormalities is incremented, and steps ST6 to ST8 are skipped. The abnormality flag ER is determined in the processing of steps ST9 and ST10 together with other serious abnormality flags ABN. On the premise that the serious abnormality flag ABN is in a reset state, if the number of consecutive abnormalities is not large (ER≤2), Effect command analysis processing is executed in the same manner as in the normal state (ST13).

In the case of an underrun abnormality, steps ST6 to ST8 are similarly skipped. Then, by writing a predetermined clear value to a predetermined system control register RGij, the display clock (frequency) and the display circuit 74 are initialized (ST10c). After confirming the normal completion of this initialization process, the frequency of the display clock and the values of the group of system control registers RGij that define the operation of the display circuit 74 are reset to specified values (ST10c), Effect command analysis processing is executed (ST13).

In the effect command analysis process (ST13), it is determined whether or not the control command CMD is received from the main control board 21. If the control command CMD is received, the control command CMD is analyzed and necessary processing is executed. (ST13). Here, the necessary processing includes start preparation processing for a new variable performance based on the control command CMD instructing the start of the variable performance, and error notification start processing based on the control command CMD indicating the occurrence of an error. Subsequently, a clear pulse is output to the WDT circuit (ST14), and the process returns to step ST4.

In the above, the case where the minor underrun abnormality or the operation start condition is not met and the abnormality flag ER is ER≤2 has been described. In such a case, the display circuit 74 Toggling the display area read by (ST6) and display list creation processing (ST7) are skipped, and the production scenario does not progress (see ST8 to ST12). This is to prevent output of image data in the frame buffers FBa and FBb that are incomplete. Therefore, the image effect does not proceed, and frame drop occurs in which the original screen (screen based on DL2) is redisplayed.

Here, in order to avoid dropping frames, a configuration of waiting until an operation start condition is satisfied is also conceivable. However, there are many control processes (ST6 to ST12) to be executed by the effect control CPU 63, and it is necessary to secure the processing time for each. there is

However, even if a frame drop occurs, the progress of the image rendering will only be delayed by about 1/30 to 2/30 of a second compared to the ramp rendering and motor rendering progressing by the interrupt processing (FIG. 26(b)). Yes, and the player is unaware of this. Moreover, when a frame is dropped, the effect scenario process (ST11) including the process of updating the effect counter EN and the sound progress process (ST12) are also skipped, so that the ready-to-win effect, the advance notice effect, and the accessory that are started after that are skipped. In the production, there is no possibility that the start timing of the image production, sound production, lamp production, motor production, etc. is shifted.

That is, in the production scenario, the start timing of image production, sound production, lamp production, and motor production and the content of production to be executed thereafter are centrally managed. Since the timing is controlled, the synchronization of various effects will not be lost. For example, when there is an effect operation that combines an explosion sound, an explosion image, a character object movement, and a lamp flash operation, each of the above effect operations is correctly started in synchronization even after a frame drop occurs. be.

In the above, the case of a relatively minor abnormality has been explained. After the determination, an infinite loop state is established (ST10b). As a result, the timing operation of the WDT circuit 58 progresses, the composite chip 50 including the effect control CPU 63 is abnormally reset, and then the initial processing (ST1 to ST3) is re-executed, thereby preventing the occurrence of an abnormal situation. It is hoped that the root cause will be eliminated.

Since this reset operation is executed by activating the WDT circuit 58, the entire composite chip 50 including the CPU circuit 51 is reset (FIG. 13(b)). Therefore, in order to avoid resetting the CPU circuit 51, the effect control CPU 63 outputs a predetermined keyword string (for example, three pieces of 1-byte data) to the pattern check circuit CHK, and outputs the reset signal RST to the VDP circuit 52. is also suitable. Also in this case, after confirming the normal completion of the reset operation of the VDP circuit 52 (ST101), the processing of steps ST4 and ST13 is performed.

In any event, since the sound circuit SND is also abnormally reset at the time of this abnormality, the image effect, sound effect, lamp effect, and motor effect all return to their initial states. However, since these reset operations have no effect on the main control unit 21 and the payout control unit 25, there is no danger of disappearance of the big win state or disappearance of prize balls.

Abnormalities have been described above, but in reality, the abnormalities described above rarely occur, even if they are minor. Based on this, the "display areas" of the frame buffers FBa and FBb for storing the image data to be read by the display circuit 74A and the display circuit 74B are toggled (ST6). As described above, "display area (0)" and "display area (1)" are defined in advance in the initial processing (ST3). 'display area' specifies which of display area (0)/display area (1).

By executing step ST6, the display circuit 74A alternately outputs image data from the index space 254 (display area (0)) and the index space 255 (display area (1)) at each operation cycle δ. The data is read out to drive the display device DS1. Similarly, the display circuit 74B alternately reads image data from the index space 251 (display area (0)) and the index space 252 (display area (1)) every operation cycle δ, and displays the sub display device DS2. will drive. As described above, the display circuit 74 actually performs READ access only to the effective data area in the display area (0)/display area (1).

In any case, in this embodiment, since the "display area" is switched for each operation cycle, the display circuits 74A and 74B display the image data completed by the drawing circuit 76 in the immediately preceding operation cycle on the display devices DS1 and DS2. will start the output process to However, since the process of step ST5 is started at the start of the vertical blanking period (V blank) of the main display device DS1, the image data output process actually starts after the vertical blanking period is completed. will be In FIG. 26(a), the arrows shown in the display circuit column indicate the operation cycle of this output process.

When the processing of step ST6 having the above significance is completed, the effect control CPU 63 subsequently completes the display list DL specifying the image data to be output to the display device by the display circuit 74 in the next operation cycle. (ST7). Although not particularly limited, in this embodiment, a list buffer area (DL buffer BUF) of the RAM 59 is secured and the display list DL is completed there (see FIG. 19).

The display list DL is configured by listing a series of instruction commands in an appropriate order, and is configured to end with an EODL (End Of DL) command. In this embodiment, in order to realize smooth operation of the data transfer circuit 72, the drawing circuit 76, and the preloader 73, all the instruction commands including the EODL command are set to an integer N times the command length of 32 bits (N>0). It is limited to only instruction commands for As described above, an instruction command composed of 32-bit integer N times may include a Don't care bit.

In this way, the display list DL of the embodiment is composed only of instruction commands whose command length is an integer N times 32 bits (N>0), so the data volume value (total data amount) of the entire display list DL is It is always an integral multiple of the minimum command length unit (32 bits=4 bytes). Furthermore, in this embodiment, considering the minimum data amount Dmin of the data transfer circuit 72, the data volume value of the display list DL is set to an integer multiple (1 or more) of the minimum data amount Dmin and Adjusted to be an integral multiple of the minimum unit (4 bytes). For example, if Dmin=256 bytes, the data volume value of the display list DL is adjusted to any value of 256 bytes, 512 bytes, and so on.

Here, depending on the complexity of the content of the presentation, it is also suitable to adjust to 256 bytes or 512 bytes as appropriate. The data volume value of the display list DL is always adjusted to 256 bytes in consideration of not executing such complicated image effects.

However, this method is not limited in any way, and if the number of display devices is three or more, or if the game machine executes complicated image effects including the sub-display device DS2, it is adjusted to 512 bytes or 768 bytes. be done. In addition, the data volume value of the display list DL is adjusted to 256 bytes at the time of normal rendering, and the data volume value of the display list DL is adjusted to 512 bytes or 768 bytes only when executing a special rendering. is also preferred.

However, in the case of this embodiment, the data volume value of the display list DL is adjusted to a predetermined byte length (256 bytes) in each operation cycle δ. As an adjustment method, after the 32-bit length EODL command, a simple method (A) that fills the missing area with a 32-bit length NOP (No Operation) command, or after filling the missing area with a 32-bit length NOP command , and finally a standard method (B) that describes a 32-bit long EODL command. The data volume value (total amount of data) of the display list DL is terminated by the EODL command without any adjustment, and dummy data is additionally transferred during the operation of the data transfer circuit 72 to obtain an integral multiple of the minimum data amount Dmin. A non-adjustment method (C) that secures the transfer amount of is also conceivable.

Here, when adopting the standard method (B), first, the command counter CNT is initialized to a specified value (64-1 corresponding to 256 bytes), and every time a significant instruction command is written to the DL buffer area BUF Another possible method is to decrement the command counter CNT as appropriate, write a NOP command until the command counter CNT becomes zero, and write an EODL command at the end after writing a series of significant instruction commands. In the case of this embodiment, the instruction command is limited to a command length N times an integer of 32 bits (N>0). Subtraction processing corresponding to N is performed.

On the other hand, when the simplified method (A) is adopted, when creating the display list DL, it is sufficient to first fill the entire list buffer area (DL buffer BUF) with NOP commands. seems to be excellent. Also, from the viewpoint of simplicity, the no-adjustment method (C) seems to be superior. However, in this embodiment, the standard method (B) is basically adopted, and the actual amount of data from the top of the display list DL to the EODL command, that is, the amount of data up to the EODL command is always transferred to the data transfer circuit 72. is adjusted to be an integer multiple of the minimum data amount Dmin.

This takes into consideration an embodiment that utilizes the preloader 73. If the simple method (A) or non-adjustment method (C) is adopted, the amount of actual data in the display list DL up to the EODL command will be random. This is because a problem occurs when the rewrite list DL′ rewritten by the preloader 73 is transferred to the DRAM 54 or when the rewrite list DL′ is transferred from the DRAM 54 to the drawing circuit 76 . The ChA control circuit 72a of the data transfer circuit 72 functions when the rewrite list DL' is transferred to the DRAM 54, and the ChB control circuit 72b functions when the rewrite list DL' is transferred to the drawing circuit 76 (FIG. 24). ), in either case, only the rewrite list DL' up to the EODL command is transferred.

The advantages of the standard method (B) for adjusting the data volume values of the display list DL have been described above. Therefore, the use of the simplified method (A) and the no-adjustment method (C) is not prohibited at all.

However, in the following explanation, the details of the display list DL will be explained based on FIG. 28 on the premise that the standard method (B) is adopted in principle regardless of whether or not the preloader 73 is used.

Although not particularly limited, in this embodiment, the display list DL first describes an instruction command string (L11 to L16) for the main display device DS1, and then writes an instruction command string (L17 to L20) for the sub display device DS2. I am trying to describe it. Also, the standard method (B) is adopted to adjust the data volume value of the display list DL to a fixed length (256 bytes). Incidentally, FIG. 28 actually shows the procedure by which the effect control CPU 63 writes the instruction command in the list buffer area of the RAM 59 and the operation of the drawing circuit 76 based on the display list DL.

As shown in FIG. 28, at the top of the display list DL, an environment setting instruction command (SETDAVR) is written to set the upper left base point address (X, Y) on the index space IDX for the frame buffer FBa of the display device DS1. Define (L11). As described with reference to FIG. 18(a), in this embodiment, a pair of frame buffers FBa are secured in the arbitrary area (c) for the display device DS1. Usually, by setting the base point address (X, Y)=(0, 0) corresponding to the effective data area for the display circuit 74, the frame buffer FBa is used by the drawing circuit 76 from the head position. .

In FIG. 18(c), the actual drawing area on the lower left side is indicated by L11. 0) means specified starting from position. However, the vertical and horizontal dimensions of the actual drawing area and the index number that specifically specifies the actual drawing area are not yet determined, and are determined by an instruction command (SETINDEX) L13, which will be described later. The instruction command L11 also designates whether or not to use the Z-buffer.

Next, the upper left base point coordinates (Xs, Ys) and the lower right diagonal point coordinates (Xe, Ye) are set in the virtual drawing space by the instruction command (SETDAVF) of the environment setting system, and the W x H dimension is set. is defined (L12). Here, the virtual drawing space is a virtual two-dimensional space of ±8192 in the X direction and ±8192 in the Y direction that can be drawn by a drawing instruction command (such as a sprite command) (see FIG. 18(c)). .

By means of this instruction command L12 (SETDAVF), the virtual drawing space is divided into a drawing area in which drawing contents are actually reflected on the display device DS1 and other non-drawing areas. The instruction command L12 (SETDAVF) associates the actual drawing area whose starting position (base point address) is defined by the instruction command L11 with the drawing area in the virtual drawing space.

In other words, the instruction command L12 defines a W×H real drawing area starting from the base point address corresponding to the drawing area in the virtual drawing space in the frame buffer FBa (the index space is undecided). It will be. Therefore, the drawing area specified by the instruction command L12 must be equal to or smaller than the horizontal size of the frame buffer FBa. Normally, the drawing area and the actual drawing area are defined to have the same dimensions as the effective data area for the display circuit 74 (FIG. 26(e)).

After the drawing circuit 76 executes the instruction commands L11 and L12, of the drawing contents drawn in the virtual drawing space, only those included in the drawing area are reflected in the actual drawing area of the frame buffer FBa. become. Therefore, the drawn contents of the part protruding from the drawing area and the part described as the work area in FIG. 18C are not directly reflected in the frame buffer. Note that when a work area is secured in the virtual drawing space, a non-drawing area in the virtual drawing space is used.

Next, in the current operation cycle, the drawing circuit 76 defines where the content to be drawn should be drawn based on the display list DL to be completed (L13). Specifically, for the frame buffer FBa of the double-buffered display device DS1, an index space IDX that serves as a "writing area" for drawing content based on the current display list DL is identified (L13). Specifically, the SETINDEX command, which is a command of the texture setting system, requires that (1) the frame buffer FBa is secured in an arbitrary area, and (2) an arbitrary index space IDX _N serving as a "write area" is set. An index number N on the region is specified.

For example, when N=255 is specified by this instruction command L13, the actual drawing area corresponding to the drawing area defined in the virtual drawing space is specifically would have been defined to be index space IDX ₂₅₅ .

In the case of this embodiment, the index number of the frame buffer FBa is 255 or 254 (FIG. 18(a)), and one of them is designated by switching in a toggle manner (L13). This index number is the index number other than the display area (0)/(1) specified in step ST6 of the main control process. For example, when the display area (0) is specified for the display circuit 74 in the process of step ST6, the display area (1) becomes the “writing area” for the drawing circuit 76. FIG.

As described above, after the correspondence relationship between the actual drawing area (W×H logical space) and the drawing area (W×H virtual space) is generally defined by the instruction command L11 and the instruction command L12, The instruction command L13 (SETINDEX) specifically specifying the index space IDX associates the W×H virtual space with the W×H logical space in the specific index space IDX.

In other words, the contents to be virtually drawn in the W×H virtual space based on a series of instruction commands from now on will be the internal VDP that defines the correspondence relationship between the virtual space and the internal VRAM 71 real addresses. Based on the conversion table, it becomes the image data of the built-in VRAM 71 (frame buffer). Subsequently, an instruction command for executing a frame buffer clear process for filling the specified index space IDX with black, for example, is described as a "write area" (L14, L15). This is nothing but erasing processing of the image data written in the frame buffer FBa two operation periods before.

Specifically, the SETFCOLOR command, which is a type of environment setting command, is used to select, for example, black color, and the RECTANGLE command, which is a primitive drawing command, is used to specify that the rectangular area should be filled. In the RECTANGLE command, the XY coordinates of the upper left end point and the lower right end point of the drawing area set in the virtual drawing space (virtual space corresponding to the frame buffer FBa) are specified (see FIG. 18(c)). .

With the above processing, the rendering preparation processing is completed. Next, instruction commands for rendering appropriate textures such as still images and one frame of moving images in the virtual rendering space are listed. Typically, first, the index space IDX to which the texture is to be developed is specified by the SETINDEX command of the texture setting system, and then the TXLOAD command, which is the instruction command of the texture load system, is written, and the predetermined Textures are described in the display list DL so as to be developed in a predetermined index space IDX.

As described above, in this embodiment, the background moving image is composed of IP stream moving images. Therefore, for example, the index space IDX in which the background video should be developed is specified as the index space IDX ₀ of the page area (b) by the SETINDEX command of the texture setting system, and then the TXLOAD command of the texture load system is described. do. In the TXLOAD command, it is necessary to specify the start address of the CGROM 55 (texture source address) and the data size after expansion (horizontal×vertical) for the video frame to be loaded this time.

When the TXLOAD command is executed in the VDP circuit 52, one moving image frame (texture) of the background moving image is first captured in the AAC area (a), and then transferred to the page area ( b) is expanded in index space IDX ₀ . Next, this one animation frame will be drawn in the virtual drawing space. In this case, the SETINDEX command (texture setting system) may be used to set "the index space IDX ₀ of the page area (b) is the texture to be processed later", but the If you do, you can omit this SETINDEX command.

In any case, in a state where "the index space IDX ₀ of the page area (b) is the texture to be processed later" is specified, next, parameters for alpha blend processing are set, and so on. Write an instruction command for an appropriate inter-rendering operation system. Note that the α-blending process relates to a transparent/semi-transparent process between an image already written in the drawing area (frame buffer FBa) and an image to be overwritten from now on. Therefore, like the moving image frame of the background moving image, in the drawing operation of the first frame, it is not necessary to use the instruction command of the inter-drawing arithmetic system.

Next, by using the sprite command, which is a primitive drawing system instruction command, "the texture of the index space IDX ₀ of the page area (b) (one video frame of the background video)" is placed in the appropriate place (rectangular destination area) in the virtual drawing space. Describe the sprite command to draw in. For the sprite command, it is necessary to specify the upper left corner point and the lower right corner point of the destination area of the virtual drawing space.

This destination area is the whole or part of the drawing area (virtual space defined on the virtual drawing space) previously associated with the actual drawing area (FBa) by the instruction commands L11 and L12. However, since the background moving image is usually drawn on the entire display screen, the destination area in such a case is the entire drawing area or more. Note that the case where the Destination area is larger than the entire rendering area is, for example, the case where the background moving image is zoomed up.

With the above processing, the drawing of the moving image frame of the background moving image is completed. The display list DL is configured to draw various textures superimposed on the background moving image. As described above, a large number of moving images are required during the variable rendering. The command (NEWPIX) will be described.

For example, regarding the second IP stream video, after allocating an additional index space IDX ₁ in the page area (b) with the NEWPIX command, this index space IDX ₁ is specified (SETINDEX), and the second Instruct the development of one frame of the video (TXLOAD), and place the developed texture in the appropriate place in the drawing area (SPRITE). Normally, the Destination area in this case will be part of the drawing area.

Afterward, the same is true. After securing the index space IDX _k one after another with the NEWPIX command, if a plurality of IP streams are drawn in the drawing area while executing appropriate α-blending processing, the drawing contents in the drawing area will be , is sequentially stored as image data in the frame buffer FBa, which is the actual drawing area. When a plurality of N IP stream moving images are rendered, a plurality of N index spaces are functioning in the page area (b).

Then, when a series of variable effects is completed, the DELPIX command is used to release the index space IDX that is deemed unnecessary among the many index spaces IDX ₁ to _IDXk secured in the page area (b). The unnecessary index space IDX should be deleted.

When drawing a still image or an I-stream video, use the SETINDEX command to specify that these textures are to be decoded in the AAC area (a), and then execute the TXLOAD command to load the AAC area. The texture acquired in (a) is then developed in the ACC area (a) by the automatically activated GDEC 75 . Then, the developed texture can be drawn in the proper place of the drawing area by the sprite command. The first AAC area (a1) or the second AAC area (a2) is used depending on whether or not the cache hit function is used.

In the explanation so far, each texture is directly drawn in the drawing area of the main display device DS1, but the operation is not necessarily limited to this. For example, if an appropriate drawing area is provided so as not to overlap the drawing area already reserved for the display device DS1 (FIG. 18(c)), and this drawing area is associated with the work area of the built-in VRAM 71, an intermediate drawing area can be obtained. A suitable drawing area can be constructed to complete an appropriate effect image. Here, the reason why the drawing area for the display device DS1 does not overlap is that the later association setting is prioritized for the overlapping area, and the drawing contents for that area are not reflected in the frame buffer FBa.

As shown in FIG. 18(c), the working area of this embodiment is the index space IDX ₀ in the arbitrary area (c). Then, at the performance timing using this work area, an instruction command for associating the rendering area for the effect image (see FIG. 18(c)) with the work area (actual rendering area of index space IDX ₀ ) is issued first. Note the columns (SETDAVR, SETDAVF, SETINDEX). As shown in FIG. 18(c), the rendering area for the effect image is secured in an area that is not included in the rendering area for the main display device DS1.

After that, it is sufficient to list instruction commands similar to the instruction command string L16 regarding the frame buffer FBa to complete an appropriate effect image in the index space _IDX0 . In the case of this embodiment, since the effect image is composed of a still image, an instruction command ₍ SETINDEX) is written so that the decoded data is developed in the first AAC area (a1). A primitive drawing system instruction command (SPRITE) with a suitable place in the drawing area as the Destination is used. It should be noted that such an operation is repeated once or multiple times according to the content of the effect.

Then, after the index space IDX ₀ in which the effect image is completed is positioned as a texture (SETINDEX), the effect image (texture) of the index space IDX ₀ is drawn in the proper place of the drawing area of the DS1 for the main display device by the sprite command. do it. In such a case, it is conceivable to decompose the effect image in the index space IDX ₀ into triangular drawing primitives, rotate them to an appropriate angle, and then draw them in the drawing area. Note that the texture rotation angle is associated with, for example, the reliability of the advance notice effect.

The instruction command sequence (L11 to L16) for completing one frame of the main display device DS1 has been described above. It is the same. That is, the starting XY coordinates of the frame buffer FBb are specified, (L17) is defined (usually X=0, Y=0), and the sub-display device DS2 is displayed in the virtual drawing space shown in FIG. 18(c). A drawing area is defined (L18).

By the way, in this embodiment, after the generation of the image data for the main display device DS1 is completed, the process shifts to the generation processing for the sub display device DS2. You can freely set the drawing area without any problem even if it overlaps with the drawing area of . Therefore, when developing a display list DL generation program, for example, when pasting an appropriate texture to a newly set drawing area with the SPRITE command, the setting of the operation parameter (Destination area) of the SPRITE command, etc. It can be standardized to some extent.

After the definition of such an arbitrary drawing area is completed (L18), next, for the frame buffer FBb of the double-buffered display device DS2, an index space that serves as a "write area" for drawing contents based on the current display list DL. Identify the IDX (L19). The index number of this index space IDX is the index number that does not correspond to the display area (0)/(1) specified in step ST6 of the main control process with respect to the frame buffer FBb.

After that, instruction command strings L20 to L22 for the sub display device DS2 are listed in the same manner as the instruction command strings L14 to L16 for the main display device DS1. It is also possible to use the effect image completed in the index space _IDX0 .

As described above, the instruction commands L11 to L22 forming the display list DL are all limited to commands having an integral multiple of 32 bits in the present embodiment. As described above, the data volume value (total amount of data) of the display list DL in this embodiment is adjusted to a fixed length (256 bytes), and the necessary number of NOP commands (L23) as dummy commands are added. After that, it ends with the EODL command (L24). That is, the embodiment of FIG. 28 adopts the standard method (B) described above.

However, even if the standard method (B) is adopted, it is not essential to fix the total amount of data in the display list DL to 256 bytes in all operating cycles. That is, in another embodiment, if the total data amount of the display list DL excluding the NOP command exceeds 256 bytes (for example, during a special performance period), the total data amount of the display list DL may be added with the NOP command. , adjusted to N×256 bytes of 512 bytes or more. As described above, when the standard method (B) is adopted, the end of N×256 bytes is terminated with the EODL command.

Although the embodiments of the present invention have been described in detail above, each configuration can be suitably applied not only to the pinball game machine but also, for example, to the reel game machine. Note that the power factor correction circuit may be omitted. Also, the game balls do not necessarily have to be paid out to the players, and the present invention can of course be applied to a so-called management game machine in which the number of prize balls is stored in an electronic card.

GM Game machine RL1, RL2 Relay coil RL Relay circuit RL
CUT energization cutoff circuit Q0 switch circuit Drec, Crec direct current generation circuit

Claims (1)

A gaming machine that executes various control operations based on a lottery result resulting from a predetermined switch signal,
A relay circuit having a relay coil through which a coil current for turning on a relay contact is energized between a power supply terminal that receives an AC voltage received from the outside and a rectifier circuit that rectifies the AC voltage, and energizing the relay coil. a energization cut-off circuit to be controlled , and a DC/DC conversion means downstream of the rectifier circuit,
The energization cut-off circuit has a switch circuit that is normally ON, and a DC generation circuit that generates a predetermined DC voltage based on the AC voltage when the switch circuit is ON, and
When the AC voltage exceeds a predetermined level, the switch circuit is turned OFF, so that the relay coil is energized and the relay contact is turned OFF ,
Said DC/DC conversion means includes an asynchronous rectification converter that generates the first type of direct current voltage distributed to the main control means responsible for centrally and centrally responsible for game control operations, and various a synchronous rectification type converter for generating the second type DC voltage to be distributed to the effect control means for controlling the effect operation of the game machine.

Images