JP7312997B2 - semiconductor light emitting device - Google Patents

Description

The technical field of the present specification relates to semiconductor light emitting devices.

A semiconductor light emitting device emits light by recombination of holes and electrons in an active layer. Conventionally, a flat sheet-like well layer has been used as an active layer. In recent years, active layers having three-dimensional structures such as columns have been studied.

For example, Patent Document 1 discloses a technique of forming a hexagonal prism-shaped nanowire semiconductor on a flat semiconductor layer and forming a transparent conductive film such as ITO on the side surface of the nanowire semiconductor (see claims 1 and 2 of Patent Document 1 and FIGS. 3A and 3B).

Japanese Patent Application Publication No. 2016-518703

Such a nanowire-structured semiconductor is considered to be a minute microstructure itself. Therefore, Patent Document 1 actually attempts to extract light from a nanowire structure, which is a fine structure.

However, intensive research by the present inventors has revealed that total reflection can occur between a material such as ITO and the atmosphere when trying to extract light directly from the nanowire structure. This is due to the difference in the refractive indices of these two materials. This problem was clarified for the first time as a result of performing calculations in consideration of the fine structure.

The problem to be solved by the technique of the present specification is to provide a semiconductor light emitting device having an active layer with a three-dimensional fine structure, in which the light extraction efficiency is improved.

第１の態様における半導体発光素子は、サファイア基板と、前記サファイア基板上に形成されたIII族窒化物半導体からなる下地層と、前記下地層の上にハニカム状配置で立設され立設方向の軸に垂直な断面が正六角形の柱状半導体であって、この柱状半導体の中心部に位置し、側面がｍ面であるｎ型ＧａＮから成る柱状ｎ型半導体と、その柱状ｎ型半導体層の外側に発光領域をＩｎＧａＮとする筒状の活性層と、その活性層の外側にｐ型ＧａＮから成る筒状のｐ型半導体層とが形成された複数の柱状半導体と、前記複数の柱状半導体の間の隙間を埋める表面が光取り出し面であるｎ型ＧａＮから成る埋込層と、前記筒状のp型半導体層と前記埋込層との間に形成されたｐ＋層とｎ＋層との接合から成るトンネル接合層と、を有する。 The light extraction surface has a plurality of conical convex portions having a base diameter in the range of 100 nm or more and 500 nm or less and a height in the range of 100 nm or more and 500 nm or less, which are two-dimensionally arranged in a honeycomb-like arrangement periodically at a second pitch in the range of 100 nm or more and 500 nm or less. The second pitch interval is shorter than the first pitch interval.

This semiconductor light emitting device has a higher light extraction efficiency than a conventional light emitting device having a nanowire structure.

The present specification provides a semiconductor light-emitting device that has an active layer with a three-dimensional fine structure and is intended to improve the light extraction efficiency of the semiconductor light-emitting device.

1 is a perspective view showing a schematic configuration of a semiconductor light emitting device according to a first embodiment; FIG. 1 is a cross-sectional view showing a cross section of a semiconductor light emitting device according to a first embodiment; FIG. 2 is a schematic configuration diagram of a columnar semiconductor of the semiconductor light emitting device of the first embodiment; FIG. FIG. 4 is a first cross-sectional view showing the IV-IV cross section of FIG. 3; FIG. 4 is a second cross-sectional view showing a VV cross section of FIG. 3; FIG. 2 is a diagram (part 1) for explaining the method for manufacturing the semiconductor light emitting device according to the first embodiment; FIG. 2 is a diagram (part 2) for explaining the method for manufacturing the semiconductor light emitting device according to the first embodiment; 3 is a diagram (part 3) for explaining the method for manufacturing the semiconductor light emitting device of the first embodiment; FIG. 4 is a diagram (part 4) for explaining the method for manufacturing the semiconductor light emitting device of the first embodiment; FIG. FIG. 5 is a diagram (No. 5) for explaining the method for manufacturing the semiconductor light emitting device according to the first embodiment; FIG. 4 is a cross-sectional view (part 1) showing a cross section of a semiconductor light-emitting device in a modified example of the first embodiment; FIG. 2 is a cross-sectional view (part 2) showing a cross section of a semiconductor light emitting device in a modified example of the first embodiment; FIG. 13 is a cross-sectional view (No. 3) showing a cross-section of a semiconductor light emitting device in a modified example of the first embodiment; FIG. 5 is a cross-sectional view showing the periphery of a columnar semiconductor of a semiconductor light emitting device according to a second embodiment; FIG. 11 is a diagram (part 1) for explaining the method for manufacturing the semiconductor light emitting device according to the second embodiment; FIG. 10 is a diagram (part 2) for explaining the method for manufacturing the semiconductor light emitting device according to the second embodiment; FIG. 13 is a diagram (part 3) for explaining the method for manufacturing the semiconductor light emitting device according to the second embodiment; FIG. 11 is a diagram (part 4) for explaining the method for manufacturing the semiconductor light emitting device of the second embodiment; FIG. 10 is a diagram (No. 5) for explaining the method for manufacturing the semiconductor light emitting device according to the second embodiment; It is a figure which shows schematic structure of the semiconductor light-emitting device of 3rd Embodiment.

Specific embodiments will be described below by taking a semiconductor light emitting device as an example and referring to the drawings. However, the technology herein is not limited to these embodiments. In addition, the lamination structure and electrode structure of each layer of the semiconductor light emitting device, which will be described later, are examples. A laminated structure different from the embodiment may be used in some cases. The thickness ratio of each layer in each figure is conceptually shown, and does not represent the actual thickness ratio.

(First embodiment)
1. 1. Semiconductor Light Emitting Device FIG. 1 is a perspective view showing a schematic configuration of a semiconductor light emitting device 100 according to a first embodiment. The semiconductor light emitting device 100 has a three-dimensional active layer. As shown in FIG. 1, the semiconductor light emitting device 100 has a substrate 110, a mask 120, a columnar semiconductor 130, a buried layer 140, a cathode electrode N1, and an anode electrode P1.

The substrate 110 is for supporting the mask 120 , the columnar semiconductor 130 and the buried layer 140 . The substrate 110 has a growth substrate 111, a buffer layer 112, an intermediate layer 113, and an n-type semiconductor layer 114 (see FIG. 3). The growth substrate 111 is for supporting the buffer layer 112, the intermediate layer 113, the n-type semiconductor layer 114, and the upper semiconductor layers. The growth substrate 111 is, for example, a sapphire substrate, a GaN substrate, an AlN substrate, or other growth substrates. The buffer layer 112 is, for example, a non-doped GaN layer. The intermediate layer 113 is, for example, an n-type GaN layer. The n-type semiconductor layer 114 is a base layer for growing the columnar semiconductor 130 . The n-type semiconductor layer 114 has a first surface 114a for growing the columnar semiconductor 130 thereon. The n-type semiconductor layer 114 is, for example, an n-type AlGaN layer. These are examples, and structures other than those described above may be used.

Mask 120 is a material from which semiconductors do not grow from the surface. As will be described later, the mask 120 has through holes. The mask 120 is preferably a transparent insulating film. In this case, mask 120 absorbs very little light. The current preferably flows through the columnar semiconductor 130 without passing through the mask 120 . Examples of materials for the mask 120 include SiO ₂ , SiNx, and Al ₂ O ₃ .

As shown in FIG. 1, the columnar semiconductor 130 is a columnar Group III nitride semiconductor. A columnar semiconductor 130 is formed on the substrate 110 . More specifically, the columnar semiconductor 130 is a semiconductor selectively grown from the surface of the substrate 110 exposed in the opening 120a of the mask 120 (see FIG. 3). The columnar semiconductor 130 has a hexagonal prism shape. A cross section of the columnar semiconductor 130 perpendicular to the central axis direction is a regular hexagon or a flattened hexagon.

The embedding layer 140 is a layer for embedding the gap between the columnar semiconductors 130 and the columnar semiconductors 130 . The embedded layer 140 covers the columnar semiconductor 130 . The material of the buried layer 140 is, for example, p-GaN.

Cathode electrode N1 is formed on substrate 110 .

Anode electrode P1 is formed on buried layer 140 . Anode electrode P<b>1 may be formed of a semiconductor other than embedded layer 140 .

2. Relationship between columnar semiconductor and light extraction surface 2-1. Arrangement of Columnar Semiconductors FIG. 2 is a conceptual diagram showing a cross section of the semiconductor light emitting device 100 . The columnar semiconductors 130 are arranged in a square lattice. As shown in FIG. 2, the plurality of columnar semiconductors 130 are periodically arranged at a first pitch interval J1.

The height of the columnar semiconductor 130 is, for example, 0.5 μm or more and 5 μm or less. The diameter of the columnar semiconductor 130 is, for example, 50 nm or more and 500 nm or less. Here, the diameter is the distance between the facing vertices of the hexagon in the cross section perpendicular to the central axis direction. If there is a long side, it is the distance in the long side direction. The first pitch interval J1 between the columnar semiconductors 130 is, for example, 0.5 μm or more and 5 μm or less. These numerical values are examples, and numerical values other than the above may be used.

2-2. Light-Extracting Surface As shown in FIG. 2, the embedded layer 140 has a light-extracting surface S1. The light extraction surface S1 has a plurality of convex portions D1. The multiple convex portions D1 are conical. The plurality of convex portions D1 are arranged in a square lattice. The multiple convex portions D1 are periodically arranged at a second pitch interval J2.

The diameter of the bottom of the convex portion D1 is, for example, 100 nm or more and 500 nm or less. The height of the convex portion D1 is, for example, 100 nm or more and 500 nm or less. The second pitch distance J2 is, for example, 100 nm or more and 500 nm or less. These numerical values are examples, and numerical values other than the above may be used.

2-3. Relationship Between Columnar Semiconductors and Protruding Portions As shown in FIG. 2, a first pitch interval J1 between adjacent columnar semiconductors 130 and 130 is different from a second pitch interval J2 between adjacent protruding portions D1 and D1.

When a first point group in which the vertices of the plurality of convex portions D1 are projected onto the first surface 114a of the n-type semiconductor layer 114 (underlying layer) and a second point group in which the apexes of the plurality of columnar semiconductors 130 are projected onto the first surface 114a of the n-type semiconductor layer 114 (underlying layer), the probability that the second point group falls within a radius of 0.01 μm from each point in the first point group is 3%. It is below. More preferably, the second point group should not overlap the first point group. Here, the vertex of the columnar semiconductor 130 is a point on the surface of the columnar semiconductor 130 through which the central axis of the hexagonal column passes.

3. Columnar Semiconductor FIG. 3 is a schematic configuration diagram of the columnar semiconductor 130 of the semiconductor light emitting device 100 of the first embodiment. The columnar semiconductor 130 has a columnar n-type semiconductor 131 , an active layer 132 and a cylindrical p-type semiconductor 133 . The side surface of the columnar n-type semiconductor 131 is an m-plane. Alternatively, it is a plane close to the m-plane. The m-plane is a non-polar plane. Therefore, in the active layer 132, there is almost no decrease in luminous efficiency due to piezoelectric polarization.

3-1. Structure of Columnar Semiconductor The columnar n-type semiconductor 131 is a semiconductor layer selectively grown in a columnar shape starting from the n-type semiconductor layer 114 exposed in the opening 120 a of the mask 120 . As described above, the n-type semiconductor layer 114 is a base layer for growing the columnar semiconductor 130 . The columnar n-type semiconductor 131 has a hexagonal prism shape. A cross section perpendicular to the axial direction of this hexagonal prism is a regular hexagon or a flattened hexagon. The columnar n-type semiconductor 131 actually grows laterally as well. Therefore, the thickness of columnar n-type semiconductor 131 is slightly larger than the opening width of opening 120 a of mask 120 . The columnar n-type semiconductor 131 is, for example, an n-type GaN layer.

The active layer 132 is formed along the periphery of the hexagonal columnar n-type semiconductor 131 . Therefore, the active layer 132 has a hexagonal cylindrical shape. The active layer 132 has, for example, one to five well layers and barrier layers sandwiching the well layers. A well layer of the active layer 132 is substantially perpendicular to the plane of the substrate 110 . However, the top of the active layer 132 may cover the top of the columnar n-type semiconductor 131 . The top of the active layer 132 may be substantially parallel to the surface of the substrate 110 . For example, the well layer is an InGaN layer and the barrier layer is an AlGaN layer.

Cylindrical p-type semiconductor 133 is formed along the outer periphery of active layer 132 having a hexagonal cylindrical shape. Therefore, cylindrical p-type semiconductor 133 has a hexagonal cylindrical shape. The cylindrical p-type semiconductor 133 is in direct contact with the active layer 132 , but does not have to be in direct contact with the columnar n-type semiconductor 131 . Also, the cylindrical p-type semiconductor 133 is in contact with the buried layer 140 . The tubular p-type semiconductor 133 is, for example, a p-type GaN layer.

3-2. First Sectional Shape FIG. 4 is a first sectional view showing a section IV-IV of FIG. FIG. 4 shows a cross section of the columnar semiconductor 130 parallel to the board surface of the substrate 110 . As shown in FIG. 4, the shape of the cross section of the columnar semiconductor 130 perpendicular to the axial direction is a regular hexagon. A columnar n-type semiconductor 131 , an active layer 132 , and a cylindrical p-type semiconductor 133 are arranged from the inside of the hexagonal columnar semiconductor 130 .

3-3. Second Sectional Shape FIG. 5 is a second sectional view showing the VV section of FIG. FIG. 5 shows a cross section of the columnar semiconductor 130 parallel to the board surface of the substrate 110 . In a cross section parallel to the plate surface of substrate 110, the cross section of columnar n-type semiconductor 131 is a flattened hexagon.

The active layer 132 has a pair of long sides 132a and 132b facing each other and two pairs of short sides 132c, 132d, 132e and 132f facing each other. The long side portions 132 a and 132 b and the short side portions 132 c, 132 d, 132 e and 132 f are layers grown from the m-plane of the columnar n-type semiconductor 131 . The long side portions 132a and 132b are, of course, portions that form sides longer than the short side portions 132c, 132d, 132e and 132f. The long side portion 132a faces the long side portion 132b.

The length W1 of the long side portions 132a and 132b of the active layer 132 in the long side direction K1 is longer than the length W2 of the short side portions 132c, 132d, 132e and 132f of the active layer 132 in the short side direction K2. Here, the length W1 in the long side direction K1 of the long side portion 132a is the length in the long side direction K1 at the central portion of the film thickness of the long side portion 132a. The same applies to the short sides. The length of the long side portion 132a is equal to the length of the long side portion 132b. The length of the short side portion 132c is equal to the lengths of the other short side portions 132d, 132e, and 132f. Of course, there may be slight differences due to crystallinity issues.

4. Manufacturing Method of Semiconductor Light Emitting Device 4-1. Substrate Preparing Step As shown in FIG. 6, a substrate 110 is prepared. The substrate 110 is obtained by laminating a buffer layer 112, an intermediate layer 113, and an n-type semiconductor layer 114 on a growth substrate 111 in this order.

4-2. Mask Forming Step As shown in FIG. 7, a mask 120 is formed on the n-type semiconductor layer 114 of the substrate 110 . It should be noted that FIG. 7 depicts an opening 120a formed in an opening forming step, which will be described later.

4-3. Step of Forming Openings As shown in FIG. 8, a plurality of openings 120 a are formed in a mask 120 to expose the n-type semiconductor layer 114 . Therefore, a technique such as etching may be used. FIG. 8 is a diagram showing the arrangement of the openings 120a of the mask 120. As shown in FIG. FIG. 8 is a view of the substrate 110 viewed from a direction perpendicular to the surface of the substrate 110. FIG. In FIG. 8, the shape of the columnar semiconductor 130 is drawn with broken lines for reference. As shown in FIG. 8, the openings 120a of the mask 120 are circular and arranged in a square lattice.

By changing the shape of the opening 120a of the mask 120, the shape of the columnar semiconductor 130 can be controlled. When the shape of opening 120a is circular, columnar semiconductor 130 having a cross-sectional shape close to a regular hexagon can be formed. When the shape of the opening 120a is an oval shape, the columnar semiconductor 130 having a cross-sectional shape close to a flat shape can be formed.

4-4. Step of Forming Columnar Semiconductor As shown in FIG. 9, starting from the n-type semiconductor layer 114 exposed under the opening 120a of the mask 120, the hexagonal columnar n-type semiconductor 131 is selectively grown. For that purpose, a known selective growth technique may be used. When the semiconductor layer is selectively grown in this way, the m-plane tends to appear as a facet.

As described above, since the opening 120a of the mask 120 has a circular shape, the columnar n-type semiconductor 131 grows with a hexagonal prism shape whose cross section is close to a regular hexagon.

Next, an active layer 132 is formed around the columnar n-type semiconductor 131 . The active layer 132 is formed on the side surface of the columnar n-type semiconductor 131 having a cross section of a shape close to a regular hexagon. In some cases, the active layer 132 is also formed on the top of the columnar n-type semiconductor 131 .

Next, a cylindrical p-type semiconductor 133 is formed on the active layer 132 so as to cover the outer periphery of the active layer 132 . Cylindrical p-type semiconductor 133 has a hexagonal cylindrical shape. A cylindrical p-type semiconductor 133 is formed on the side surface of the active layer 132 . A cylindrical p-type semiconductor 133 may also be formed on top of the columnar n-type semiconductor 131 or the active layer 132 . Thus, columnar semiconductors 130 are formed.

4-5. Buried Layer Forming Step As shown in FIG. 10 , the gap between the columnar semiconductors 130 is filled with the buried layer 140 .

4-6. Protruding Portion Forming Step Next, for example, the surface of the embedded layer 140 is roughened by dry etching using ICP. As a result, a plurality of convex portions D1 are formed on the surface of the embedding layer 140. As shown in FIG.

4-7. Electrode Forming Step Next, a cathode electrode N1 is formed on the n-type semiconductor layer 114 of the substrate 110 . Also, an anode electrode P1 is formed on the buried layer 140. Next, as shown in FIG.

4-8. Other Steps A heat treatment step, a step of forming a passivation film or the like on the surface of the semiconductor layer, or other steps may be performed.

5. Effect of First Embodiment The semiconductor light emitting device 100 of the first embodiment has higher light extraction efficiency than a conventional light emitting device that directly extracts light from nanowires to the outside of the device.

Conventionally, a nanowire (corresponding to the columnar semiconductor 130 of this embodiment) is a fine structure. Therefore, it has been thought that the shape of the nanowire itself improves the light extraction efficiency. However, the inventors of the present invention have found that when light is extracted from the nanowires, total reflection is likely to occur due to the difference in refractive index between the nanowires and air, despite the fine structure. For this reason, the inventors intentionally buried nanowires, which were conventionally thought to have high light extraction efficiency, as shown in FIG. 2, and set a separate light extraction surface. Therefore, the semiconductor light emitting device 100 of this embodiment has sufficiently high light extraction efficiency.

6. Modification 6-1. Surface Layer In this embodiment, the embedded layer 140 has a light extraction surface S1. Light extraction surface S<b>1 may be formed in a layer other than embedded layer 140 .

A surface layer 150 may be formed over the buried layer 140, as shown in FIG. The surface layer 150 has a light extraction surface S1 formed with a plurality of convex portions D1. The material of the surface layer 150 is, for example, a p-GaN layer with a doping amount different from that of the buried layer 140 . Also, the material of the surface layer 150 may be a transparent conductive oxide such as ITO or IZO.

As shown in FIG. 12, the convex portion D1 may be formed by forming unevenness on the surface of the embedding layer 140 and forming the surface layer 150 on the unevenness. Here, the embedded layer 140 is, for example, a Group III nitride semiconductor such as p-GaN. The surface layer 150 is, for example, a transparent conductive oxide such as ITO.

6-2. Arrangement of Columnar Semiconductors and Arrangement of Protrusive Portions The plurality of columnar semiconductors 130 may be arranged in a honeycomb shape, and the plurality of protruding portions D1 may be arranged in a honeycomb shape. It is sufficient that the pitch interval J1 between the columnar semiconductors 130 and the pitch interval J2 between the convex portions D1 are different.

The plurality of columnar semiconductors 130 may be arranged in a honeycomb pattern, and the plurality of convex portions D1 may be arranged in a square lattice pattern. Alternatively, the plurality of columnar semiconductors 130 may be arranged in a square lattice pattern, and the plurality of convex portions D1 may be arranged in a honeycomb pattern. As described above, the pitch interval J1 and the pitch interval J2 may be the same or different as long as the arrangement of the columnar semiconductors 130 and the arrangement of the convex portions D1 are different.

In order to change the arrangement of the columnar semiconductors 130, the arrangement of the openings 120a of the mask 120 may be changed. In order to change the arrangement of the plurality of convex portions D1, the mask pattern used when etching the embedded layer 140 may be changed.

6-3. Composition of Columnar Semiconductor In this embodiment, the columnar n-type semiconductor 131 is an n-type GaN layer, the well layer is an InGaN layer, the barrier layer is an AlGaN layer, and the cylindrical p-type semiconductor 133 is a p-type GaN layer. These are examples, and other Group III nitride semiconductors may be used. Alternatively, other semiconductors may be used.

6-4. Buried Layer Composition In this embodiment, the material of the buried layer 140 is a p-GaN layer. However, a p-AlGaN layer can be used as the buried layer 140 instead of the p-GaN layer. The AlGaN layer has a lower refractive index than the p-type GaN layer. Therefore, light extraction efficiency is improved. Alternatively, buried layer 140 may be another p-AlInGaN layer.

6-5. Current Blocking Layer of Columnar Semiconductor It is preferable to promote current injection from the side surface of the columnar semiconductor 130 . For example, as shown in FIG. 13, a transparent insulating film 165 is provided on top of the columnar semiconductor 130 . As a result, the current flowing through the top of the columnar semiconductor 130 is blocked, and the current can be properly injected from the side surface of the columnar semiconductor 130 .

6-6. Concavo-convex Processed Substrate The growth substrate 111 of the substrate 110 may be processed with concavo-convex processes. That is, the growth substrate 111 has an uneven portion in which unevenness is periodically arranged on the surface on the semiconductor layer side. Concave and convex shapes include, for example, a conical shape and a hemispherical shape. These convex shapes may be arranged, for example, in a square grid pattern or a honeycomb pattern. This further improves the light extraction efficiency.

Assuming that the uneven shape is hemispherical, the diameter of the bottom of the hemispherical shape is 1 μm or more and 5 μm or less, the height of the hemispherical shape is 0.5 μm or more and 5 μm or less, and the pitch of the hemispherical shape is preferably 1 μm or more and 15 μm or less. The above numerical ranges are examples, and numerical ranges other than the above may be used.

6-7. Concave portion Instead of the convex portion D1 of the present embodiment, a concave portion may be formed on the light extraction surface.

6-8. Reflective Layer The semiconductor light emitting device 100 may have a reflective layer on the back surface of the substrate 110 opposite to the mask layer 120 .

6-9. Combination The above modifications may be freely combined.

(Second embodiment)
A second embodiment will be described.

1. Semiconductor Light Emitting Device FIG. 14 is a cross-sectional view showing the periphery of the columnar semiconductor 130 of the semiconductor light emitting device 200 of the second embodiment. As shown in FIG. 14, the semiconductor light emitting device 200 has a tunnel junction on the side surface of the columnar semiconductor 130. As shown in FIG.

The semiconductor light emitting device 200 has a p+ layer 271 and an n+ layer 272 on the side surface of the columnar semiconductor 130 . The p+ layer 271 is located between the columnar semiconductor 130 and the n+ layer 272 . The p+ layer 271 is a layer having a high p-type impurity concentration. The Mg concentration of the p+ layer 271 is, for example, 2×10 ²⁰ cm ⁻³ . The n+ layer 272 is a layer having a high n-type impurity concentration. The Si concentration of the n+ layer 272 is, for example, 2×10 ²⁰ cm ⁻³ .

The embedded layer 140 covers the columnar semiconductor 130 , the p + layer 271 and the n + layer 272 . Buried layer 140 is an n-GaN layer.

2. Effect of Second Embodiment Thereby, current can be efficiently injected from the side surface of the columnar semiconductor 130 . At this time, the buried layer 140 can be composed of an n-type semiconductor layer. Therefore, it is effective in reducing light absorption loss and reducing device resistance.

3. Manufacturing method of semiconductor light emitting device 3-1. Substrate Preparing Step As shown in FIG. 15, a substrate 110 is prepared in the same manner as in the first embodiment.

3-2. Mask Forming Step A mask layer 120 is formed on the substrate 110 in the same manner as in the first embodiment.

3-3. Opening Formation Step As shown in FIG. 16, an opening 120a is formed in the mask layer 120 in the same manner as in the first embodiment.

3-4. Columnar Semiconductor Forming Step Similar to the first embodiment, a columnar n-type semiconductor 131, an active layer 132, and a cylindrical p-type semiconductor 133 are grown from the n-type semiconductor layer 114 exposed in the opening 120a.

3-5. Tunnel Junction Forming Step Next, the p+ layer 271 is formed on the side surface of the cylindrical p-type semiconductor 133 of the columnar semiconductor 130 . After that, an n+ layer 272 is formed on the side surface of the p+ layer 271 . FIG. 17 shows the state at this time. Thereafter, upper portions of the p+ layer 271 and the n+ layer 272 are removed by etching. As a result, p+ layers 271 and n+ layers 272 are formed on the side surfaces of the columnar semiconductors 130, as shown in FIG.

3-6. Buried Layer Forming Step Next, as shown in FIG. 19 , the buried layer 140 fills the gap between the columnar semiconductors 130 each including the p+ layer 271 and the n+ layer 272 .

3-7. Concavo-convex Shape Forming Step Next, the surface of the embedding layer 140 is roughened to form a plurality of convex portions D1.

3-8. Electrode Forming Step Then, an anode electrode P1 is formed on the buried layer 140. As shown in FIG. Also, a cathode electrode N1 is formed on the n-type semiconductor layer 114 .

4. Modifications Modifications of the first embodiment can be used.

(Third embodiment)
A third embodiment will be described.

1. Semiconductor Light Emitting Device FIG. 20 is a diagram showing a schematic configuration of a semiconductor light emitting device 300 according to the third embodiment. The semiconductor light emitting device 300 has a substrate 110 , a mask layer 120 , a columnar semiconductor 130 , a transparent conductive film 340 and an embedded layer 350 .

A transparent conductive film 340 covers the plurality of columnar semiconductors 130 . The material of the transparent conductive film 340 is, for example, a transparent conductive oxide such as ITO. The transparent conductive film 340 is electrically connected to the anode electrode P1.

The embedding layer 350 is a layer that is in contact with the transparent conductive film 340 and fills the gap between the columnar semiconductors 130 having the transparent conductive films 340 . The material of the embedded layer 350 is resin. Since the transparent conductive film 340 plays a role of conducting the columnar semiconductor 130 and the anode electrode P1, the resin of the embedding layer 350 may be insulating. In addition, a plurality of convex portions D1 are formed on the surface of the embedded layer 350. As shown in FIG. That is, the embedded layer 350 has a light extraction surface S1.

2. Modification 2-1. Material of Embedded Layer The embedded layer 350 may be made of a material with high electrical resistivity other than resin. However, the material of the embedded layer 350 is a transparent material.

2-2. Combination In some cases, the first and second embodiments may be freely combined with these modifications.

(simulation)
The light extraction efficiency was calculated by changing the arrangement of the plurality of columnar semiconductors and the plurality of convex portions. The size of the columnar semiconductor and the size of the convex portion of the light extraction surface are different by orders of magnitude. Therefore, in the conventional calculation method, it was not easy to calculate considering the columnar semiconductor and the convex portion.

1. Calculated structure 1-1. First Structure (Modification of First Embodiment)
The first structure is the structure shown in Table 1. That is, the first structure uses an uneven substrate and has a plurality of convex portions in the embedded layer in which the columnar semiconductors are embedded. The emission wavelength of the light emitting element of the first structure is 405 nm. Further, conical convex portions are arranged in a honeycomb pattern. The diameter of the bottom of the convex portion is 200 nm, the height of the convex portion is 170 nm, and the pitch interval between the convex portions is 200 nm.

The buried layer is made of n-GaN and has a height of 2 μm. The columnar semiconductors are arranged in a honeycomb shape, the height of the columnar semiconductors is 1.5 μm, and the pitch of the columnar semiconductors is 1.2 μm. The material of the cylindrical p-type semiconductor is p-GaN, and the film thickness of the cylindrical p-type semiconductor is 100 nm. The material of the active layer is InGaN, and the thickness of the active layer is 37 nm. The material of the columnar n-type semiconductor is n-GaN, and the diameter of the columnar n-type semiconductor is 200 nm. Here, the diameter of the columnar n-type semiconductor is the length between opposing vertices of a regular hexagon.

The substrate is laminated in the order of a reflective layer, a sapphire substrate, an n-GaN layer, and an n-Al _0.03 Ga _0.97 N layer from the far side from the semiconductor. The film thickness of the sapphire substrate is 120 μm. The thickness of the n-GaN layer is 2.6 μm. The thickness of the n-Al _0.03 Ga _0.97 N layer is 1.2 μm. The uneven shape of the sapphire substrate is hemispherical and arranged in a honeycomb pattern. The diameter of the unevenness is 2.8 μm, the height of the unevenness is 1.5 μm, and the pitch of the unevenness is 6 μm.

[Table 1]
First structure Emission wavelength 405 nm
Convex part Shape of convex part Conical Arrangement of convex part Honeycomb shape (triangular lattice)
Diameter of the bottom of the convex portion 200 nm
Height of convex portion 170 nm
Pitch interval 200nm
Embedded layer Embedded layer material n-GaN
Buried layer height 2 μm
Columnar semiconductor Shape of columnar semiconductor Hexagonal column (cross section is a regular hexagon)
Arrangement of columnar semiconductors Honeycomb shape (triangular lattice)
Columnar semiconductor height 1.5 μm
Pitch interval 1.2 μm
Cylindrical p-type semiconductor material p-GaN
Film thickness of cylindrical p-type semiconductor 100 nm
Active layer material InGaN
Active layer thickness 37 nm
Columnar n-type semiconductor material n-GaN
Columnar n-type semiconductor diameter 200 nm
Substrate n-Al _0.03 Ga _0.97 N layer 1.2 μm (thickness)
n-GaN layer 2.6 μm (thickness)
Sapphire substrate 120 μm (film thickness)
Reflective layer material Al
Sapphire substrate unevenness Shape of unevenness Hemispherical shape Arrangement of unevenness Honeycomb shape (triangular lattice)
Concave and convex diameter 2.8 μm
Height of unevenness 1.5 μm
Concavo-convex pitch interval 6 μm

Structures that are thought to have little effect on the analysis results are omitted for calculation purposes. The omitted structures are, for example, a buffer layer between the sapphire substrate and the n-GaN layer, a p+ layer for tunnel junction, and an n+ layer. This is because these film thicknesses are very thin.

1-2. Second structure (first embodiment)
The second structure is a structure in which the uneven sapphire substrate in Table 1 is changed to a flat sapphire substrate.

1-3. Third structure (conventional structure)
The third structure is a structure in which the uneven sapphire substrate in Table 1 is changed to a flat sapphire substrate, the buried layer is removed, and the columnar semiconductor is covered with ITO.

2. Calculation Results Table 2 shows the results of the simulation. As shown in Table 2, the conventional third structure had a light extraction efficiency of 31%. On the other hand, in the first structure corresponding to the modified example of the first embodiment, the light extraction efficiency was 56%. In the second structure corresponding to the first embodiment, the light extraction efficiency was 53%.

[Table 2]
Structure Buried layer Substrate processing Light extraction efficiency First structure Yes Yes 56%
Second structure Yes No 53%
Third structure None None 31%

As described above, the light extraction efficiency is higher when the columnar semiconductor is intentionally embedded and a separate light extraction surface is provided than when the light is directly extracted from the columnar semiconductor, which should have a fine structure.

(Appendix)
A semiconductor light emitting device according to a first aspect includes a base layer, a plurality of columnar semiconductors on the base layer, a buried layer filling gaps between the plurality of columnar semiconductors, and a light extraction surface. The light extraction surface has a plurality of convex portions. The plurality of columnar semiconductors have a hexagonal prism shape and are arranged at a first pitch. The plurality of convex portions are arranged at second pitch intervals. The first pitch spacing and the second pitch spacing are different.

A semiconductor light emitting device according to a second aspect has a base layer having a first surface, a plurality of columnar semiconductors on the base layer, a buried layer filling gaps between the plurality of columnar semiconductors, and a light extraction surface. The light extraction surface has a plurality of periodically arranged convex portions. The plurality of columnar semiconductors have a hexagonal prism shape and are arranged periodically. When a first point group obtained by projecting the vertices of a plurality of convex portions onto the first surface of the base layer and a second point group obtained by projecting the vertices of a plurality of columnar semiconductors onto the first surface of the base layer are set virtually, the probability that the second point group falls within a radius of 0.01 μm from each point in the first point group is 3% or less.

In the semiconductor light emitting device according to the third aspect, the second point group does not overlap the first point group.

In the semiconductor light emitting device according to the fourth aspect, the embedded layer has a light extraction surface.

A semiconductor light emitting device according to a fifth aspect has a surface layer on the buried layer. A surface layer has a light extraction surface.

In the semiconductor light emitting device according to the sixth aspect, the embedded layer is an n-GaN layer.

In the semiconductor light emitting device according to the seventh aspect, the embedded layer is a p-GaN layer.

A semiconductor light emitting device according to an eighth aspect has a transparent conductive film covering a plurality of columnar semiconductors.

In the semiconductor light emitting device according to the ninth aspect, the embedded layer is made of resin and is in contact with the transparent conductive film.

In the semiconductor light emitting device according to the tenth aspect, the plurality of columnar semiconductors are Group III nitride semiconductors. The plurality of columnar semiconductors are arranged in a honeycomb shape.

In the semiconductor light emitting device according to the eleventh aspect, the plurality of convex portions are arranged in a honeycomb pattern.

A semiconductor light emitting device according to a twelfth aspect has a substrate that supports an underlying layer. The substrate has an uneven portion.

DESCRIPTION OF SYMBOLS 100... Semiconductor light emitting element 110... Substrate 111... Growth substrate 112... Buffer layer 113... Intermediate layer 114... N-type semiconductor layer 114a... First surface 120... Mask 120a... Opening 130... Columnar semiconductor 131... Columnar n-type semiconductor 132... Active layer 133... Cylindrical p-type semiconductor 140... Buried layer 150... Surface layer N1... Cathode electrode P1... Anode electrode S1... Light extraction surface D1... Convex part

Claims (3)

a sapphire substrate;
a base layer made of a Group III nitride semiconductor formed on the sapphire substrate ;
columnar semiconductors having a regular hexagonal cross- section perpendicular to the axis in the erecting direction erected on the underlayer in a honeycomb-like arrangement, the columnar n-type semiconductors located in the center of the columnar semiconductors and made of n-type GaN having m-plane side surfaces, a plurality of columnar semiconductors in which a cylindrical active layer having an InGaN light emitting region outside the columnar n-type semiconductor layers, and a cylindrical p-type semiconductor layer made of p-type GaN outside the active layers are formed;
a buried layer made of n-type GaN, the surface filling the gaps between the plurality of columnar semiconductors being a light extraction surface;
a tunnel junction layer composed of a junction of a p+ layer and an n+ layer formed between the cylindrical p-type semiconductor layer and the buried layer;
has
The light extraction surface has a plurality of conical convex portions with a bottom diameter in the range of 100 nm or more and 500 nm or less and a height in the range of 100 nm or more and 500 nm or less, which are two-dimensionally arranged in a honeycomb-like arrangement periodically at a second pitch in the range of 100 nm or more and 500 nm or less,
The plurality of columnar semiconductors have a regular hexagonal prism shape with m-plane side surfaces, and are periodically arranged two-dimensionally at a first pitch interval in the range of 0.5 μm or more and 5 μm or less,
The semiconductor light emitting device, wherein the second pitch interval is shorter than the first pitch interval. In the semiconductor light emitting device according to claim 1,
A semiconductor light-emitting device, wherein a projection of the first point group and a projection of the second point group do not overlap when a first point group obtained by projecting the vertices of the plurality of convex portions onto the first surface of the base layer and a second point group obtained by projecting the vertexes of the plurality of columnar semiconductors onto the first surface of the base layer are set virtually. In the semiconductor light emitting device according to claim 1 or 2 ,
A semiconductor light-emitting device , wherein the sapphire substrate has an uneven portion on the surface on the underlayer side .

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