JP7312029B2 - Imaging signal processing method and solid-state imaging device using the same - Google Patents

Description

1. Field of the Invention The present invention relates to a signal processing method for an image signal and a solid-state image sensor using the same, and more particularly, to a method in which the potential changes with the passage of time when converting a pixel signal (analog value) obtained from a pixel into a digital value. The present invention relates to an AD (Analog to Digital) converter (ADC) using a ramp signal as a reference signal, and a solid-state imaging device having the same.

FIG. 9 shows a configuration diagram of a general CMOS (Complementary Metal Oxide Semiconductor) image sensor. The CMOS image sensor 100 shown in FIG. 9 includes a pixel control signal generator 1, a pixel array 2, a ramp signal generator 3, a counter circuit 4, a column ADC block 5 having an ADC for each column of the pixel array 2, and a logic circuit. 6, has an output I/F unit 7; The ADC is intended for single-slope integrating ADCs. The pixel array has normal pixels (R, G, B) (effective pixels) and optical black (OB) pixels (light-shielded pixels).

CMOS image sensors are known to deteriorate in characteristics at high temperatures. This is mainly due to what is called a dark current, which causes charges to occur in photodiodes (PDs) even in areas where light does not enter (dark), resulting in a phenomenon that the image appears white. It is generally known that the dark current component increases approximately twice as the temperature rises by 8° C., and reaches a non-negligible level at high temperatures. Therefore, conventionally, a light-shielded pixel called optical black (OB) is provided, and dark current information obtained therefrom is subtracted from pixel signal information obtained from an unshielded normal pixel. Therefore, a method for suppressing the whitening phenomenon described above has been used (Patent Document 1).

Japanese Patent Application Laid-Open No. 2001-186419

FIG. 10 is a diagram showing a simple configuration of a single-slope integrating ADC 500. As shown in FIG. The operation of the ADC shown in FIG. 10 is such that the levels of a ramp signal (Ramp Input) supplied as a reference signal potential from the ramp signal generation circuit 3 and an input signal (Signal), which is a pixel signal from the pixel array 2, are detected by a comparator. (Comparator) 501 compares. Then, the time (counter value) during which the signal level and the potential of the ramp signal match is latched (counted) by a counter latch circuit 502 using the digital code output from the counter circuit 4 and converted into an analog value. The value of the pixel signal obtained is output as a digital value.

Conventionally, OB pixels and normal pixels are AD-converted using the same ramp signal (a signal whose potential changes with the lapse of time). Correction is performed by taking a difference in a processing circuit at a later stage from the dark current component obtained from . Therefore, as will be described later, in the AD conversion of normal pixels, signals containing dark current components are AD converted without considering how much dark current components are included. There was an adverse effect of narrowing the range.

Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

A signal processing method for an imaging signal according to an embodiment is a signal processing method for an imaging signal that performs analog-to-digital conversion of an imaging signal output from a semiconductor imaging device using a ramp signal whose potential changes with the lapse of time. performing a first analog-to-digital conversion using a first ramp signal on a first imaging signal output from a light-shielded pixel after exposure through PD reset and FD reset of the semiconductor imaging device; and a second analog-to-digital conversion step using a second ramp signal for a second imaging signal output from an effective pixel after exposure through PD reset and FD reset, wherein the second ramp signal is , a signal obtained by offsetting the voltage value of the first ramp signal in accordance with the first analog-to-digital converted output value.

A signal processing method for an imaging signal according to an embodiment is a signal processing method for an imaging signal that performs analog-to-digital conversion of an imaging signal output from a semiconductor imaging device using a ramp signal whose potential changes with the lapse of time. performing a first analog-to-digital conversion using a first ramp signal on a first imaging signal output from a light-shielded pixel after exposure through PD reset and FD reset of the semiconductor imaging device; a second analog-to-digital conversion of a second imaging signal output from effective pixels after exposure through PD reset and FD reset using a second ramp signal, wherein the second imaging signal is A signal output from an effective pixel after exposure of the semiconductor imaging device is a signal obtained by offsetting a voltage value in accordance with the first analog-to-digital converted output value.

A solid-state imaging device according to an embodiment is a solid-state imaging device, and includes a pixel array including a plurality of pixels arranged in a row direction and a column direction, and each provided corresponding to a corresponding column. A plurality of vertical signal lines that transmit signals output from pixels in columns, a column ADC circuit that AD-converts signals transmitted through the plurality of vertical signal lines in parallel, and a potential that changes with the passage of time. a ramp signal generation circuit for outputting a ramp signal for outputting a ramp signal, the pixel array having light-shielded pixels and effective pixels, and the column ADC circuits each having a plurality of columns provided for corresponding columns. An AD converter is provided, and the AD converter AD-converts the imaging signals output from the light-shielded pixels based on the first ramp signal, and the imaging signals output from the effective pixels based on the second ramp signal. The second ramp signal is a signal obtained by offsetting the voltage value of the first ramp signal according to the value of the output result of AD conversion of the imaging signal output from the light-shielded pixel. is.

According to the signal processing method of the imaging signal and the solid-state imaging device using the same according to the embodiment, it is possible to suppress the decrease in the dynamic range and suppress the whitening phenomenon caused by the dark current.

FIG. 1 is a diagram showing an outline of a circuit configuration of an AD converter according to Embodiment 1 together with connections with pixels of an imaging device. FIG. 2 is a diagram showing an outline of the processing flow of the AD converter according to the first embodiment. FIG. 3 is a diagram schematically showing a timing chart of AD conversion of imaging signals from OB pixels (light-shielded pixels) after exposure and imaging signals from normal pixels (effective pixels) according to the second embodiment. FIG. 4 shows an outline of the circuit configuration of the AD converter according to Embodiment 2 together with the connection with the pixels of the imaging device. FIG. 5 shows the outline of the timing chart of AD conversion according to the second embodiment shown in FIG. It is a figure showing. FIG. 6 shows an outline of the circuit configuration of the AD converter according to Embodiment 3 together with the connection with the pixels of the imaging device. FIG. 7 is a diagram schematically showing a timing chart of AD conversion of imaging signals from OB pixels (light-shielded pixels) after exposure and imaging signals from normal pixels (effective pixels) according to the third embodiment. FIG. 8 shows an outline of the circuit configuration of the AD converter according to Embodiment 4 together with the connection with the pixels of the imaging device. FIG. 9 is a diagram showing the configuration of a general CMOS image sensor. FIG. 10 is a diagram showing a simple configuration of a general single-slope integrating ADC 500. As shown in FIG. FIG. 11A is a diagram schematically showing a conventional timing chart of AD conversion of imaging signals from OB pixels (light-shielded pixels) after exposure. FIG. 11B is a diagram schematically showing a conventional timing chart of AD conversion of imaging signals from normal pixels (effective pixels) after exposure.

Hereinafter, semiconductor devices according to embodiments will be described in detail with reference to the drawings. In addition, in the specification and the drawings, the same components or corresponding components are denoted by the same reference numerals, and overlapping descriptions are omitted. Also, in the drawings, the configuration may be omitted or simplified for convenience of explanation. Moreover, at least a part of the embodiment and each modification may be arbitrarily combined with each other.

(Embodiment 1)
FIG. 1 shows an outline of the circuit configuration of the AD converter according to Embodiment 1 together with the connection with the pixels of the imaging device. Single-slope integrating ADC 5001 further includes offset control block 504 compared to general single-slope integrating ADC 500 noted in FIG. The offset control block 504 has a function of adding a desired voltage offset to the input signal and outputting it. The OB data recording circuit 503 receives and stores the output of the single slope integration type ADC 5001 . The stored value is output to the offset control block 504 as reference data for determining the voltage offset value to be used in the offset control block 504 . The output of the ramp signal generation circuit 3 is input to the offset control block 504 , a desired offset voltage is added thereto, and the result is output to one input of the comparator 501 . Alternatively, the offset control block 504 receives signals output from effective pixels (R, G, B) and light-shielded pixels (OB) via vertical readout lines, adds a desired offset voltage, and Output to the other input of comparator 501 . The vertical readout line is connected to the source terminals of the selection transistors of each pixel including effective pixels (R, G, B) and light-shielded pixels (OB), and is also connected to the ground potential GND via a constant current source. ing.

Effective pixels (R, G, B) and light-shielded pixels (OB) are each composed of photodiodes (PD1, PD0), transfer transistors (MT1, MT0), reset transistors (MR1, MR0), amplification It has transistors (MA0, MA1) and select transistors (MS1, MS0). Compared to the effective pixels, the light-shielded pixels are configured such that at least the photodiode PD0 portion is shielded from light signals from the outside. Gate control signal lines (TX1, TX0) are connected to the gate electrodes of both the effective pixels and the light-shielded pixels in order to control the transfer transistors. Similarly, to control the reset transistors, reset control signal wirings (RST1, RST0) are connected to the respective gate electrodes. In addition, select signal wirings (SEL1, SEL0) are connected to the respective gate electrodes in order to control the select transistors. Three types of control signal wirings are connected from the pixel control signal generator 1 to each of these pixels.

Furthermore, the charges generated in the respective photodiodes (PD1, PD0) are transferred to the floating diffusion regions (FD1, FD0) via the transfer transistors (MT1, MT0). The respective floating diffusion regions (FD1, FD0) are reset (initialized) to the power supply potential PWR (VDD) by the reset transistors (MR1, MR0) turning on the reset transistors (MR1, MR0). Which pixel is read out by the vertical signal readout line is selected by activating one of the selection transistors (MS1, MS0).

The OB data recording circuit 503 has a function of storing and recording the output of the single-slope integration type ADC 5001. In particular, the signal output from the light-shielded pixel (OB) is input via the vertical readout line. It targets the output value of the integrating ADC5001. The value stored in the OB data recording circuit 503 at this time corresponds to the value of the noise level (dark level) caused by the dark current component.

The offset control block 504 adds an offset value corresponding to the dark level value from the OB data recording circuit 503 to the output of the ramp signal generation circuit 3, and the effective pixels ( R, G, and B) are output as digital values (corresponding to Embodiment 2 described later).

Alternatively, the offset control block 504 adds an offset value corresponding to the value of the dark level from the OB data recording circuit 503 to the signal output from the effective pixels (R, G, B) to perform single slope integration in the latter stage. A type ADC outputs signals output from effective pixels (R, G, B) as digital values (corresponding to a third embodiment described later).

FIG. 2 is a flowchart simply showing these processing flows. As a first step (S1), post-exposure AD conversion of OB pixels is performed. As the next step (S2), the output values AD-converted in the previous step (S1) are recorded. In the next step (S3), a value corresponding to the dark level is obtained from the AD conversion output value recorded in the previous step (S2), and added as an offset to the lamp signal or signal input. As the final step (S4), AD conversion of effective pixels after exposure is performed by adding the offset obtained in the previous step (S3) to the ramp signal or signal input. .

In the flowchart shown in FIG. 2, a characteristic point compared to the conventional art is that an offset equivalent to a dark level is applied to the lamp signal or signal input for AD conversion after exposure of effective pixels executed in step S4. This is an additional point. Then, S1, or S1 and S2, or S1, S2, and S3 are executed before S4 in order to obtain the offset to be added in advance.

With the configuration (FIG. 1) and the processing flow (FIG. 2) based on the first embodiment, the signals output from the effective pixels (R, G, B) are converted into digital values by the single-slope integration type ADC 5001. When outputting, an offset corresponding to the pre-obtained dark level value is added. Since the AD conversion is performed by the ramp signal or the input signal to which such an offset is added, the dynamic range does not decrease, and the whitening phenomenon caused by the dark current can be suppressed.

(Embodiment 2)
FIG. 3 is a diagram schematically showing a timing chart of AD conversion of imaging signals from post-exposure OB pixels (light-shielded pixels) and post-exposure imaging signals from normal pixels (effective pixels) according to the second embodiment. be. In the timing chart of FIG. 3, ramp signal 1 is drawn in addition to ramp signal 0. In FIG. Ramp signal 0 performs AD conversion of imaging signals from OB pixels (light-shielded pixels) after exposure, and ramp signal 1 performs AD conversion of imaging signals from normal pixels (effective pixels) after exposure. The AD conversion by the ramp signal 0 is the same as the conventional one, but the AD conversion by the ramp signal 1 reflecting the result of the AD conversion is characteristic. Specifically, the ramp signal 1 has the same slope as the ramp signal 0, but has a waveform offset in the negative direction by the voltage value corresponding to the dark level obtained by AD conversion of the imaging signal of the OB pixels. It's becoming In FIG. 3, steps S2 and S3 referred to in FIG. 2 are omitted and not shown.

As shown in FIG. 3, in the AD conversion by the ramp signal 1, the AD conversion is started from the voltage value indicated as a1 on the ramp signal 1 at the time when the counter of the counter latch is 0. This voltage value is equal to the voltage value corresponding to the dark level. In the range from the potential of a1 to the potential of b1, which is the applicable range of the AD converter, and the count value in the range of 0 to 4095 counts in terms of counter value, it is possible to AD convert from signals equivalent to dark level to large signals. . As for the dynamic range, the range indicated as "D range 1" in FIG. 3 is the dynamic range. By offsetting the ramp signal by the dark level, as shown in FIG. 3, from 0 count to 4095 counts in the counter operation of the counter latch, from a1 to b1 in terms of the voltage of the ramp signal, the analog level is maximized. It can be seen that the voltage value can be detected and AD-converted into a digital value.

In order to explain the effect of the dynamic range of AD conversion according to the second embodiment, the dynamic range in a comparative example will be explained below using FIGS. 11A and 11B. 11A and 11B are schematic timing charts of the single-slope integrating ADC 500 shown in FIG. FIG. 11A shows a timing chart of AD conversion of imaging signals from OB pixels (light-shielded pixels) after exposure. Since the imaging signals are from OB pixels (light-shielded pixels) after exposure, the noise level (dark level) caused by dark current is measured. FIG. 11B shows a timing chart of AD conversion of imaging signals from normal pixels (effective pixels) after exposure. As described in Background Art, a net pixel signal value can be obtained by subtracting the dark current signal value obtained in the procedure of FIG. 11A from the pixel signal value obtained in the procedure of FIG. 11B. become.

Detailed operations will be described with reference to FIGS. 11A and 11B. As described with reference to FIG. 10, first, a signal and a ramp signal 0 are input to the comparator, the counter latch performs a counting operation, and AD conversion of the input signal levels in FIGS. 11A and 11B is performed. That is, in the ramp signal 0 of FIG. 11A, the count operation starts from the point a of the ramp signal 0, and the D count is performed until the point x, which is the same level as the dark level, and this becomes the digital value of the dark level. Similarly, with ramp signal 0 in FIG. 11B, the count operation starts from point a of ramp signal 0, and counts S0 until point y, which is the same level as the signal level, and this is the digital value of the signal level.

In the examples depicted in FIGS. 11A and 11B, the AD converter can handle from 0 count to 4095 counts, and the level on the ramp signal 0 is a signal that changes from the potential level at point a to the potential level at point b. can be AD converted. A variable range of potential levels that can be converted is called a dynamic range, and in the case of FIG. 11A, the range indicated as "D range 01" in the drawing indicates the magnitude of the dynamic range.

On the other hand, in the case of FIG. 11B, as indicated by gray hatching in the figure, the dark current component constantly exists as noise. A small signal is drowned out by noise and is not output as a signal. Therefore, the dynamic range in the case of FIG. 11B is the range indicated as "D range 02" in the drawing of FIG. 11B, which is smaller than the dynamic range in the case of FIG. 11A by the magnitude of the dark current component.

In this comparative example, a net pixel signal value is obtained by subtracting the dark current signal value obtained in the procedure of FIG. 11A from the pixel signal value obtained in the procedure of FIG. 11B. As shown, when the value of the pixel signal is obtained in the procedure of FIG. 11B, the AD conversion is performed under the characteristics of the narrowed dynamic range. . Further, in the case of the comparative example, when subtracting the dark current signal value obtained by the procedure of FIG. 11A from the value of the pixel signal obtained by the procedure of FIG. The value of the current signal and the value of the pixel signal obtained by the procedure of FIG. 11B can be obtained independently, and the difference is finally taken. There is no restriction that it must be performed temporally before the procedure of 11B.

Regarding the dynamic range according to the first embodiment, looking again at the values of the ramp signal 1 in FIG. By comparison, the dynamic range is from 0 count to 4095 counts in the counter operation of the counter latch, and when indicated by the voltage of the ramp signal, the maximum range is secured from a1 to b1, which is an improvement compared to the comparative example. I know there is.

FIG. 5 shows an outline of the circuit configuration of the AD converter according to Embodiment 2 together with the connection with the pixels of the imaging device. Compared with the circuit configuration of the AD converter shown in FIG. 1, the details of the offset control block 504 are shown as an offset control circuit 1 (506) as an example.

FIG. 5 shows the outline of the timing chart of AD conversion according to the second embodiment shown in FIG. It is a figure showing. The outline of the operation will be described below in order from t1 to t13. In FIG. 5, as in FIG. 3, steps S2 and S3 referred to in FIG. 2 are omitted and not shown.

In FIG. 5, between times t1 and t2, both the reset signal RST0 of the reset transistor MR0 of the light-shielded pixel and the control signal TX0 of the transfer transistor MT0 are at high level, and the reset operation (PD reset) of the photodiode PD0 is performed. is done. Next, between times t3 and t4, only the reset signal RST0 of the reset transistor MR0 of the light-shielded pixel becomes high level, and the reset operation (FD reset) of the floating diffusion region FD0 of the light-shielded pixel is performed. From time t3, the control signal SEL0 of the selection transistor MS0 of the light-shielded pixel also becomes high level, the signal of the light-shielded pixel is selected, and it starts to be output to the AD converter via the vertical signal readout line.

After that, between times t5 and t6, the control signal TX0 of the transfer transistor MT0 of the light-shielded pixel becomes high level, and the light-shielded pixel is actually light-shielded during the exposure period of time t2-t5. A dark current component is transferred to the floating diffusion region FD0. The selection signal SEL0 has already been at high level from time t3, and immediately after time t6, the AD conversion operation in the AD converter using the ramp signal 0 is started together with the count operation in the counter latch.

Through the AD conversion up to this point, the light-shielded pixels are exposed and the digital value of the imaging signal is obtained. This is the dark current component, which indicates the value of the dark level. As shown in FIG. 4, this value is stored in the OB data recording circuit, and used as the offset value of the ramp signal 1 for AD conversion of the imaging signal of the effective pixels thereafter. Between times t4 and t5, a process involving AD conversion for reading noise components in the FD area is generally performed using a ramp signal, but this is omitted in the present invention.

In FIG. 5, between times t7 and t8, both the reset signal RST1 of the reset transistor MR1 of the effective pixel and the control signal TX1 of the transfer transistor MT1 are at high level, and the reset operation of the photodiode PD1 (PD reset ) is performed. Next, during time t10 to t11, only the reset signal RST1 of the reset transistor MR1 of the effective pixel becomes high level, and the reset operation (FD reset) of the floating diffusion region FD1 of the effective pixel is performed. From time t10, the control signal SEL1 of the select transistor MS1 of the effective pixel also becomes high level, the signal of the effective pixel is selected, and it starts to be output to the AD converter via the vertical signal readout line. Between times t11 and t12, a process involving AD conversion for reading noise components in the FD area is generally performed using a ramp signal, but this is omitted in the present invention.

After that, during time t12 to t13, the control signal TX1 of the transfer transistor MT1 of the effective pixel becomes high level, and the pixel signal information of the effective pixel exposed to the effective pixel during the exposure period of time t8 to t12 is floating. Diffusion area FD1 is transferred. The selection signal SEL0 has already been at the low level from time t9, and instead the selection signal SEL1 has been at the high level from time t10. It starts with the count operation in the latch.

As described above, the ramp signal 1 used for AD conversion of effective pixels is offset from the ramp signal 0 as a voltage value by a value corresponding to the dark current component obtained from the light-shielded pixels. As a result, in the AD conversion of the signal output from the effective pixel, the dynamic range does not decrease, and the whitening phenomenon caused by the dark current can be suppressed.

(Embodiment 3)
FIG. 6 shows an outline of the circuit configuration of the AD converter according to Embodiment 3 together with the connection with the pixels of the imaging device. Compared with the circuit configuration of the AD converter shown in FIG. 1, details of an example of the offset control block 504 are shown as an offset control circuit 2 (507).

As can be seen from FIG. 6, in the AD converter according to the third embodiment, a value corresponding to the dark current component obtained from the light-shielded pixel is obtained from the effective pixel when AD-converting the imaging signal obtained from the effective pixel. A voltage value is added as an offset to the captured image signal.

FIG. 7 is a diagram schematically showing a timing chart of AD conversion of imaging signals from OB pixels (light-shielded pixels) after exposure and imaging signals from normal pixels (effective pixels) according to the third embodiment.
In the third embodiment, as shown in FIGS. 11A and 11B, the same ramp signal 0 is used for both the AD conversion of the light-shielded pixels and the AD conversion of the effective pixels. In FIG. 7, steps S2 and S3 referred to in FIG. 2 are omitted and not shown.

As shown in FIG. 7, in the third embodiment, during AD conversion of effective pixels, the signal level 2 from the effective pixels is offset to the positive side by a value corresponding to the dark current component. . As a result, when the counter latch starts the counting operation, the point a2 on the ramp signal 0 shown in FIG. As described above, the dynamic range for the net signal is the range indicated by D range 2 in FIG. 7, which is larger than the conventional dynamic range (D range 02) indicated in FIG. 11B. It can be seen that

Therefore, in the AD converter according to the third embodiment, the voltage value is offset by a value corresponding to the dark current component obtained from the light-shielded pixel in the AD conversion of the signal output from the effective pixel. As a result, in the AD conversion of the signal output from the effective pixel, the dynamic range does not decrease, and the whitening phenomenon caused by the dark current can be suppressed.

(Embodiment 4)
FIG. 8 shows an outline of the circuit configuration of the AD converter according to Embodiment 4 together with the connection with the pixels of the imaging device. In FIG. 1 showing a similar configuration, one light-shielded pixel and one effective pixel are extracted as representatives for one column in the cell array 2 shown in FIG. 9 showing the overall configuration. . FIG. 8 shows an image of two columns extracted from the cell array. For each column, in addition to the light-shielding pixel (OB) and effective pixels (R, G, B) shown in FIG. 1, light-shielding pixel 2 (OB2) and effective pixel 2 (R2, G2, B2) ) has been added.

A column ADC (single-slope integrating ADC with offset control function) 5001 corresponding to the columns already drawn in FIG. 1 is also drawn in FIG. , an offset control block 504 is included. A column ADC (single-slope integration type ADC with offset control function) 5002 corresponding to the added column is additionally drawn in FIG. A column ADC (single slope integration type ADC with offset control function) 5002 includes a counter latch circuit 5022 , a comparator 5012 and an offset control block 5042 .

In the two column ADCs 5001 and 5002, the input ramp signal generation circuit 3 is connected in common. A common ramp signal is then supplied to each ADC. Similarly, in the two column ADCs 5001 and 5002, the outputs of the counter latch circuits 502 and 5022 are connected to the OB data recording circuit 503 in common. Also, the output of this OB data recording circuit 503 is input to the offset control blocks 504 and 5042 of the two column ADCs 5001 and 5002, respectively. The other inputs of the offset control blocks 504 and 5042 are connected to the vertical signal readout lines of the corresponding columns.

In FIG. 1, one column ADC 5001 AD-converts signals from light-shielded pixels in the same column, stores dark current components (dark levels) in the OB data recording circuit 503, and outputs signals from effective pixels in the same column. is added to follow the ramp signal from the ramp signal generation circuit 3 according to the value of the dark current component (dark level) stored in the OB data recording circuit 503. AD conversion was performed in the dynamic range.

However, in FIG. 8, one column ADC stores the dark current component (dark level) from the light-shielded pixel of the corresponding column in the OB data recording circuit 503, and another column ADC stores the imaging signal from the effective pixel of another column. When performing AD conversion, an offset is added as a voltage value to the ramp signal from the ramp signal generation circuit 3 according to the value of the dark current component (dark level) stored in the OB data recording circuit 503, and AD conversion is performed. The method of use is also possible. Even in such a configuration, in the AD conversion of the signal output from the effective pixel, the dynamic range does not decrease, and the whitening phenomenon caused by the dark current can be suppressed.

Alternatively, in FIG. 8, one column ADC stores the dark current component (dark level) from the light-shielded pixels of the corresponding column in the OB data recording circuit 503, and another column ADC stores the imaging signal from the effective pixels of another column. When performing AD conversion, an offset is added as a voltage value to the pixel signal from each column according to the value of the dark current component (dark level) stored in the OB data recording circuit 503, and AD conversion is performed. How to do it is also possible. Even in such a configuration, in the AD conversion of the signal output from the effective pixel, the dynamic range does not decrease, and the whitening phenomenon caused by the dark current can be suppressed.

In the AD converter according to the fourth embodiment, since the OB data recording circuit 503 can be shared among a plurality of columns, it can be expected to be effective in reducing area and cost.

The invention made by the present inventor has been specifically described above based on the embodiments, but the present invention is not limited to the embodiments already described, and various modifications can be made without departing from the scope of the invention. It goes without saying that this is possible.

1: Pixel control signal generator
2: Pixel Array 3: Ramp Signal Generation Circuit 4: Counter Circuit 5: Column ADC Block 6: Logic Circuit Section 7: Output I/F Section 100: CMOS Image Sensor 500: Single Slope Integration ADC
5001, 5002: Single-slope integrating ADC with offset control function
501, 5012: Comparator
502, 5022: Counter Latch Circuit 503: OB Data Recording Circuit 504, 5042: Offset Control Block 506: Offset Control Circuit 1
507: Offset control circuit 2
FD0, FD1: floating diffusion area 0, floating diffusion area 1
MA0, MA1: amplification transistor 0, amplification transistor 1
MR0, MR1: reset transistor 0, reset transistor 1
MS0, MS1: select transistor 0, select transistor 1
MT0, MT1: transfer transistor 0, transfer transistor 1
PD0, PD1: Photodiode 0, Photodiode 1

Claims (4)

A signal processing method for an image signal output from a semiconductor image pickup device for analog-to-digital conversion using a ramp signal whose potential changes with the passage of time, comprising:
A step of first analog-to-digital converting a first imaging signal output from a light-shielded pixel after exposure through PD reset and FD reset of the semiconductor imaging device using a first ramp signal;
a second analog-to-digital conversion step using a second ramp signal for a second imaging signal output from an effective pixel after exposure through PD reset and FD reset of the semiconductor imaging device;
the second ramp signal is a signal obtained by offsetting the voltage value of the first ramp signal according to the first analog-to-digital converted output value ;
the light-shielded pixels are included in a first column corresponding to the first column ADC;
the effective pixels are included in a second column corresponding to a second column ADC different from the first column ADC;
the first column ADC stores dark current components from the light-shielded pixels of the first column in a recording circuit;
The second column ADC converts the image signal from the effective pixel of the second column from analog to digital according to the value of the dark current component stored in the recording circuit. Add an offset as a voltage value to the signal and perform analog-to-digital conversion,
A signal processing method for imaging signals. A signal processing method for an image signal output from a semiconductor image pickup device for analog-to-digital conversion using a ramp signal whose potential changes with the passage of time, comprising:
A step of first analog-to-digital converting a first imaging signal output from a light-shielded pixel after exposure through PD reset and FD reset of the semiconductor imaging device using a first ramp signal;
a second analog-to-digital conversion step using a second ramp signal for a second imaging signal output from an effective pixel after exposure through PD reset and FD reset of the semiconductor imaging device;
the second imaging signal is a signal obtained by offsetting a voltage value of a signal output from an effective pixel after exposure of the semiconductor imaging device according to the first analog-to-digital converted output value;
the light-shielded pixels are included in a first column corresponding to the first column ADC;
the effective pixels are included in a second column corresponding to a second column ADC different from the first column ADC;
the first column ADC stores dark current components from the light-shielded pixels of the first column in a recording circuit;
The second column ADC converts the image signal from the effective pixel of the second column from analog to digital according to the value of the dark current component stored in the recording circuit. Adds an offset as a voltage value to the pixel signal and performs analog-to-digital conversion.
A signal processing method for imaging signals. A solid-state imaging device ,
a pixel array including a plurality of pixels arranged in a row direction and a column direction;
a plurality of vertical signal lines each provided corresponding to a corresponding column and transmitting a signal output from a pixel in the corresponding column;
a column ADC circuit that AD-converts signals transmitted through the plurality of vertical signal lines in parallel;
a ramp signal generation circuit that outputs a ramp signal whose potential changes with the passage of time;
a recording circuit;
with
The pixel array has light-shielded pixels and effective pixels,
The column ADC circuit includes a plurality of AD converters each provided for a corresponding column,
The AD converter is
AD-converting the imaging signal output from the light-shielded pixel based on the first ramp signal,
AD-converting the imaging signal output from the effective pixel based on the second ramp signal;
The second ramp signal is a signal obtained by offsetting the voltage value of the first ramp signal according to the value of the output result of AD conversion of the imaging signal output from the light-shielded pixel,
the light-shielded pixels are included in a first column corresponding to a first column ADC circuit;
the effective pixels are included in a second column corresponding to a second column ADC circuit different from the first column ADC circuit;
The first column ADC circuit stores dark current components from the light-shielded pixels of the first column in the recording circuit;
The second column ADC circuit performs analog-to-digital conversion of imaging signals from the effective pixels of the second column, according to the value of the dark current component stored in the recording circuit. Add an offset as a voltage value to the ramp signal and perform analog-to-digital conversion.
Solid-state imaging device. A solid-state imaging device,
a pixel array including a plurality of pixels arranged in a row direction and a column direction;
a plurality of vertical signal lines each provided corresponding to a corresponding column and transmitting a signal output from a pixel in the corresponding column;
a column ADC circuit that AD-converts signals transmitted through the plurality of vertical signal lines in parallel;
a ramp signal generation circuit that outputs a ramp signal whose potential changes with the passage of time;
a recording circuit;
with
The pixel array has light-shielded pixels and effective pixels,
The column ADC circuit includes a plurality of AD converters each provided for a corresponding column,
The AD converter is
AD-converting the imaging signal output from the light-shielded pixel based on the first ramp signal,
AD-converting the imaging signal output from the effective pixel based on the second ramp signal;
The second ramp signal is a signal obtained by offsetting the voltage value of the first ramp signal according to the value of the output result of AD conversion of the imaging signal output from the light-shielded pixel,
the light-shielded pixels are included in a first column corresponding to a first column ADC circuit;
the effective pixels are included in a second column corresponding to a second column ADC circuit different from the first column ADC circuit;
The first column ADC circuit stores dark current components from the light-shielded pixels of the first column in the recording circuit;
The second column ADC circuit, when performing analog-to-digital conversion of imaging signals from the effective pixels of the second column, converts each column to Add an offset as a voltage value to the pixel signal of , and perform analog-to-digital conversion.
Solid-state imaging device.

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