JP7297488B2 - Digital output circuit - Google Patents

Description

The present invention relates to a digital output circuit that outputs digital values.

The following techniques are known as techniques for correcting a digital value output from an analog-to-digital conversion circuit. For example, in Patent Document 1, a correction unit receives a digital output from an analog-to-digital converter, searches for a correction coefficient for each bit of the analog-to-digital converter based on an adaptive control algorithm, and uses the searched correction coefficient. A technique for correcting the digital output from the analog-to-digital converter is described.

WO2014/207870

In a resistive voltage dividing circuit that converts an input voltage into an arbitrary voltage, if individual variations occur in the elements that make up the resistive voltage dividing circuit due to fluctuations in the manufacturing process, etc., the level of the output voltage will be the ideal value. It may deviate. In this case, it may be necessary to correct the level of the output voltage so that it matches the ideal value.

As a means for correcting the output voltage of the resistive voltage dividing circuit, a decoder circuit is generally used that selects one of the connection points between a plurality of series-connected resistive elements constituting the resistive voltage dividing circuit according to the input code. used.

However, according to the method of adjusting the output voltage of the resistance voltage dividing circuit using the decoder circuit, it is necessary to increase the number of bits of the decoder circuit in order to increase the adjustment resolution of the output voltage or expand the adjustment range. be. In this case, there is a problem that the circuit scale of the decoder circuit becomes large, and the chip size of the semiconductor chip on which the decoder circuit is mounted becomes large.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a digital output circuit for outputting a corrected digital value that can be configured with a relatively small circuit scale.

A digital output circuit according to the present invention includes an analog circuit that outputs an output voltage corresponding to an input voltage, a conversion circuit that converts the output voltage into a digital value and outputs the digital value, and a digital value that can be output from the conversion circuit. and a correction amount, extracting the correction amount corresponding to the digital value output from the conversion circuit from the table, and using the extracted correction amount, the digital value output from the conversion circuit and a correction unit that corrects the The table has divided areas obtained by dividing the output range of the digital value that can be output from the conversion circuit, and the divided areas correspond to the amount of error in the digital value when a predetermined voltage is input as the input voltage. A region obtained by dividing the output range by the number of divisions, a change in the correction amount with respect to a change in the digital value has a proportional relationship, and an absolute value of the correction amount assigned to the digital value corresponding to the predetermined voltage is the above A correction amount is assigned to each of the divided regions so as to match the absolute value of the error amount in the digital value corresponding to the predetermined voltage.

According to the present invention, there is provided a digital output circuit that outputs a corrected digital value that can be configured with a relatively small circuit scale.

It is a figure which shows an example of a structure of the digital output circuit based on embodiment of this invention. It is a figure which shows an example of a structure of the correction|amendment part which concerns on embodiment of this invention. 4 is a diagram showing an example of the relationship between the input voltage of the resistance voltage dividing circuit and the digital value output from the AD conversion circuit according to the embodiment of the present invention; FIG. 4 is a diagram showing an example of the relationship between the input voltage of the resistive voltage dividing circuit and the error amount of the digital value output from the AD conversion circuit according to the embodiment of the present invention; FIG. It is a figure which shows an example of a structure of the correction amount table which concerns on embodiment of this invention. FIG. 10 is a diagram showing an example of the relationship between the input voltage of the resistive voltage dividing circuit and the error amount of the digital value output from the AD conversion circuit according to another embodiment of the present invention; It is a figure which shows an example of a structure of the correction amount table which concerns on other embodiment of this invention. FIG. 5 is a diagram showing an example of the configuration of a digital output circuit according to another embodiment of the invention;

An example of an embodiment of the present invention will be described below with reference to the drawings. In each drawing, the same or equivalent constituent elements and parts are given the same reference numerals, and overlapping descriptions are omitted as appropriate.

[First embodiment]
FIG. 1 is a diagram showing an example of the configuration of a digital output circuit 1 according to the first embodiment of the invention. The digital output circuit 1 includes a resistance voltage dividing circuit 10 as an analog circuit, an analog-to-digital conversion circuit 20 (hereinafter referred to as AD conversion circuit 20), a correction section 30, an input terminal 41 and an output terminal 42. there is

The resistive voltage dividing circuit 10 divides the input voltage Vin _input to the input terminal 41 to output an output voltage _Vout . The resistive voltage dividing circuit 10 includes an operational amplifier circuit 11 , a resistive element 12 and a resistive element 13 .

The operational amplifier circuit 11 has a non-inverting input terminal connected to the input terminal 41 and an inverting input terminal connected to the output terminal of the operational amplifier circuit 11 . That is, the operational amplifier circuit 11 constitutes a voltage follower. The resistance element 12 has one end connected to the output terminal of the operational amplifier circuit 11 and the other end connected to one end of the resistance element 13 . The other end of the resistance element 13 is connected to the ground line. An output voltage V _out represented by the following equation (1) is output from the connection of the resistance element 12 and the resistance element 13 . In the equation (1), R1 is the resistance value of the resistance element 13 and R2 is the resistance value of the resistance element 12.
_Vout =(R1/(R1+R2)) _Vin (1)

Hereinafter, R1/(R1+R2) in the formula (1) is called a voltage division ratio. It is assumed that the voltage dividing ratio of the resistance voltage dividing circuit 10 fluctuates due to fluctuations in the manufacturing process or the like. When the voltage dividing ratio of the resistance voltage dividing circuit 10 fluctuates, the output voltage _Vout deviates from the ideal value.

The AD conversion circuit 20 converts the output voltage _Vout output from the resistance voltage dividing circuit 10 into a digital value Dout and outputs the digital value _Dout .

The correction unit 30 corrects the digital value D _out output from the AD conversion circuit 20 and outputs the corrected digital value C _out obtained by the correction from the output terminal 42 . FIG. 2 is a diagram showing an example of the configuration of the correction unit 30. As shown in FIG. The corrector 30 includes an adder 31 and a correction amount table 32 . The correction amount table 32 records each of a plurality of digital values _Dout that can be output from the AD conversion circuit 20 and a correction amount for correcting an error occurring in the digital value _Dout in association with each other. In the correction unit 30 , the correction amount ε corresponding to the digital value _Dout output from the AD conversion circuit 20 is extracted from the correction amount table 32 . The correction amount ε extracted from the correction amount table 32 and the digital value _Dout output from the AD conversion circuit 20 are added in the adder 31 to derive the correction digital value _Cout . The correction amount table 32 is stored in a nonvolatile memory (not shown).

FIG. 3 is a diagram showing an example of the relationship between the input voltage V _in of the resistance voltage dividing circuit 10 and the digital value D _out output from the AD conversion circuit 20. As shown in FIG. If the voltage division ratio of the resistance voltage dividing circuit 10 deviates from the ideal value due to fluctuations in the manufacturing process _, etc., the output voltage V _out also deviates from the ideal value. deviation occurs.

In FIG. 3, the straight line a corresponds to the case where the voltage dividing ratio of the resistance voltage dividing circuit 10 matches the ideal value, the straight line b corresponds to the case where the voltage dividing ratio of the resistance voltage dividing circuit 10 is greater than the ideal value, A straight line c corresponds to a case where the voltage dividing ratio of the resistance voltage dividing circuit 10 is smaller than the ideal value. As shown in FIG. 3, the slope of the straight line b is greater than the slope of the straight line a, and the slope of the straight line c is smaller than the slope of the straight line a. The difference between the straight lines b and a and the difference between the straight lines c and a correspond to deviations (errors) from the ideal values in the digital value D _out .

FIG. 4 is a diagram showing an example of the relationship between the input voltage V _in of the resistive voltage dividing circuit 10 and the amount of error (hereinafter referred to as error amount) occurring in the digital value D _out output from the AD conversion circuit 20. In FIG. . In this embodiment, the error amount is defined as the difference between the actual value and the ideal value. In FIG. 4, the straight line a corresponds to the case where the voltage dividing ratio of the resistance voltage dividing circuit 10 matches the ideal value, the straight line b corresponds to the case where the voltage dividing ratio of the resistance voltage dividing circuit 10 is greater than the ideal value, A straight line c corresponds to a case where the voltage dividing ratio of the resistance voltage dividing circuit 10 is larger than the ideal value.

When the voltage division ratio of the resistance voltage dividing circuit 10 is larger than the ideal value (indicated by the straight line b), the error amount of the digital value _Dout when the voltage _VA is input _as the input voltage Vin is +n [LSB ]. Further, when the voltage dividing ratio of the resistance voltage dividing circuit 10 is smaller than the ideal value (indicated by the straight line c), the error amount of the digital value D _out when the voltage V _A is input as the input voltage V _in is − Let n [LSB].

When the voltage dividing ratio of the resistance voltage dividing circuit 10 is larger than the ideal value (indicated by the straight line b), the error amount of the digital value Dout and the _input voltage _Vin are in a proportional relationship, and the error amount of the digital value _{Dout is} increases linearly with _increasing input voltage Vin. Therefore, the error amount of the digital value _Dout with respect to the voltage _VB lower than the voltage _VA is +αn [LSB]. However, 0<α<1.

Similarly, when the voltage dividing ratio of the resistance voltage dividing circuit 10 is smaller than the ideal value (indicated by the straight line c), the error amount _{of the} digital value Dout and the input voltage _Vin are in a proportional relationship, and the digital value _Dout , decreases linearly as the input voltage _Vin increases. Therefore, the error amount of the digital value D _out with respect to the voltage V _B lower than the voltage _VA is -αn [LSB]. However, 0<α<1.

When the voltage dividing ratio of the resistance voltage dividing circuit 10 matches the ideal value (indicated by the straight line a), the error amount of the digital value D _out is always zero regardless of the input voltage _Vin .

In this way, since the input voltage _Vin and the error amount of the digital value _Dout are in a proportional relationship, the correction amount for correcting the error occurring in the digital value _Dout is assumed to be proportional to the digital value _Dout . It is possible to map to the digital value D _out .

FIG. 5 is a diagram showing an example of the configuration of the correction amount table 32. As shown in FIG. As described above, the correction amount table 32 records each of the plurality of digital values _Dout that can be output from the AD conversion circuit 20 and the correction amount for correcting the error occurring in the digital value _Dout in association with each other. It is what I did. The correction amount table 32 has divided areas 35 obtained by dividing the output range of the digital value _Dout that can be output from the AD conversion circuit 20 .

The output range of the digital value _Dout that can be output from _the AD conversion circuit 20 is the number of divisions according to the amount of error in the digital value Dout that is output from the conversion circuit 20 when a predetermined voltage is input as the input voltage _Vin . evenly divided. For example, if the error amount in the digital value _DA output from the AD conversion circuit 20 when the voltage _VA is input _as the input voltage Vin is +n [LSB], the digital value D that can be output from the AD conversion circuit 20 The output range (0 to D _A ) of _out is divided by n+1.

In the correction amount table 32, the change in the correction amount is proportional to the change in the digital value D _out output from the AD conversion circuit 20, and the digital value D _A when a predetermined voltage V _A is input as the input voltage V _in . A correction amount is assigned to each of the divided areas 35 such that the absolute value of the correction amount assigned to corresponds to the absolute value of the error amount+n [LSB] in the digital value _DA . In this embodiment, the correction amount assigned to the digital value _DA is -n [LSB] obtained by inverting the polarity of the error amount +n [LSB] in the digital value _DA . If the amount of error in the digital value _DA is defined as the value obtained by subtracting the actual value from the ideal value, the correction amount assigned to the digital value _DA will be the amount of error in the digital value _DA and the polarity are the same, including

In the correction amount table 32, each digital value Dout that can be _output from the AD conversion circuit and the correction amount are associated and recorded for each of a plurality of cases in which the error amount in the digital value _DA is different. That is, the correspondence relationship between each digital value _Dout corresponding to one error amount and the correction amount is set as one record, and a plurality of records for cases where the error amounts are different from each other are stored in the correction amount table 32. there is

For example, when the error amount in the digital value _DA is +3 [LSB], the output range of the AD conversion circuit 20 is divided into four equal parts. Then, a correction amount of 0 [LSB] is assigned to the divided regions corresponding to 0≦V _out <D _A /4. A correction amount of −1 [LSB] is assigned to the divided area corresponding to D _A /4≦V _out <2D _A /4. A correction amount of −2 [LSB] is assigned to the divided area corresponding to 2D _A /4≦V _out <3D _A /4. A correction amount of −3 [LSB] is assigned to the divided area corresponding to 3D _A /4≦V _out ≦D _A .

The operation of the digital output circuit 1 according to this embodiment will be described below. When the input voltage V _in is input to the input terminal 41, the resistive voltage dividing circuit 10 outputs the output voltage V _out shown by equation (1). The output voltage V _out is supplied to the AD conversion circuit 20 .

The AD conversion circuit 20 converts the output voltage _Vout into a digital value _Dout and outputs the digital value Dout. The digital value D _out is supplied to the corrector 30 .

It is assumed that the amount of error in the digital value _DA when a predetermined voltage _{VA is input as the input voltage Vin is} known in the correction unit 30 . The correction unit 30 selects a record corresponding to a known error amount from the correction amount table. Next, the correction unit 30 extracts the correction amount ε corresponding to the digital value _Dout output from the AD conversion circuit 20 from the selected record. Next, the adder 31 adds the correction amount ε extracted from the correction amount table 32 and the digital value _Dout output from the AD conversion circuit 20 . The corrector 30 outputs the result of calculation by the adder 31 as a corrected digital value _Cout .

As is clear from the above description, according to the digital output circuit 1 according to the present embodiment, an error occurs in the digital value _Dout due to individual variations in the elements constituting the resistance voltage dividing circuit 10. Even in this case, since the digital value _Dout is corrected in the correcting section 30, an appropriate digital output value can be obtained.

Further, according to the digital output circuit 1 according to the present embodiment, the corrected digital value C _out is obtained by adding the correction amount ε extracted from the correction amount table 32 and the digital value D _out output from the AD conversion circuit 20. Therefore, the circuit scale can be reduced compared to the case of adjusting the output voltage V _out using a decoder circuit and the case of obtaining the correction value of the digital value D _out using a multiplier or a divider. is possible.

In the present embodiment, the resistance voltage dividing circuit 10 was exemplified as an analog circuit that outputs the output voltage _Vout according to the input voltage _Vin . It is possible to apply various analog circuits in which the output voltage changes linearly.

Further, in the present embodiment, the correction unit 30 includes the adder 31 as an example, but the correction amount ε recorded in the correction amount table 32 has a polarity different from that of the present embodiment. When recording in an inverted state, a subtractor is used instead of the adder 31 .

[Second embodiment]
FIG. 6 is a diagram showing an example of the relationship between the input voltage V _in of the resistance voltage dividing circuit 10 and the error amount of the digital value D _out output from the AD conversion circuit 20 according to the second embodiment of the present invention. is. In FIG. 6, a straight line a corresponds to the case where the voltage dividing ratio of the resistance voltage dividing circuit 10 matches the ideal value, a straight line b corresponds to the case where the voltage dividing ratio of the resistance voltage dividing circuit 10 is greater than the ideal value, A straight line c corresponds to a case where the voltage dividing ratio of the resistance voltage dividing circuit 10 is smaller than the ideal value. In this embodiment, the range of input voltage _Vin is expanded compared to the first embodiment. As a result, the output range of the digital value _Dout output from the AD conversion circuit 20 is expanded compared to the first embodiment.

FIG. 7 is a diagram showing an example of the configuration of the correction amount table 32A according to the second embodiment of the invention. The correction amount table 32A according to the present embodiment has a wider output range of the digital value _Dout output from the AD conversion circuit 20 than the correction amount table 32 according to the first embodiment. The correction amount table 32 has divided areas 35 that equally divide the extended output range of the digital value _Dout .

Specifically, when the error amount in the digital value D _A whose error amount is known is +n [LSB], the range of 0≦D _out ≦D _A is evenly divided so that the number of divisions is n+1. be. In the range of D _A <D _out , the output range is equally divided so that the width of the divided area 35 is the same as the width of each divided area 35 in the range of 0≦D _out ≦ _DA . The change in the correction amount with respect to the change in the digital value _Dout output from the AD conversion circuit 20 has a proportional relationship, and the absolute value of the correction amount assigned to the digital value _DA is the error amount +n in the digital value _DA . A correction amount is assigned to each divided area 35 so as to match the absolute value of [LSB].

According to the correction amount table 32A according to the present embodiment, since the output range of the digital value Dout is expanded to a region larger than the digital value D _A whose error amount is known, _the input voltage when obtaining the error amount _VA can be any voltage.

[Third Embodiment]
FIG. 8 is a diagram showing an example of the configuration of a digital output circuit 1A according to the third embodiment of the invention. The analog circuit of the digital output circuit 1A according to the present embodiment is composed of a non-inverting amplifier circuit 50. As shown in FIG.

The non-inverting amplifier circuit 50 amplifies the input voltage Vin _input to the input terminal 41 and outputs an output voltage _Vout . The non-inverting amplifier circuit 50 includes an operational amplifier circuit 14, a resistance element 15 and a resistance element 16. FIG.

The operational amplifier circuit 14 has a non-inverting input terminal connected to the input terminal 41 and an inverting input terminal connected to the connection point between the resistance element 15 and the resistance element 16 . The resistance element 15 has one end connected to the output terminal of the operational amplifier circuit 14 and the other end connected to one end of the resistance element 16 . The other end of the resistance element 16 is connected to the ground line. An output voltage V _out represented by the following equation (2) is output from the output terminal of the operational amplifier circuit 14 and supplied to the AD conversion circuit 20 . In the equation (2), R3 is the resistance value of the resistance element 15 and R4 is the resistance value of the resistance element 16.
_Vout =(1+(R3+R4)) _Vin (2)

As described above, even when the non-inverting amplifier circuit 50 is applied as an analog circuit that outputs the output voltage _Vout corresponding to the input voltage _Vin , the error generated in the digital value _Dout obtained by converting the output voltage _Vout into a digital value is is corrected in the correction unit 30, a proper digital output value can be obtained.

1, 1A Digital output circuit 10 Resistance voltage dividing circuit 11 Operational amplifier circuits 12, 13, 15, 16 Resistance element 14 Operational amplifier circuit 20 Analog-to-digital conversion circuit 30 Correction unit 31 Adders 32, 32A Correction amount table 35 Division area 41 Input Terminal 42 Output terminal 50 Non-inverting amplifier circuit

Claims (5)

an analog circuit that outputs an output voltage corresponding to an input voltage;
a conversion circuit that converts the output voltage into a digital value and outputs the digital value;
a table that associates each digital value that can be output from the conversion circuit with a correction amount, extracts the correction amount corresponding to the digital value output from the conversion circuit from the table, and calculates the extracted correction amount; a correction unit that corrects the digital value output from the conversion circuit using
including
The table has divided areas obtained by dividing an output range of digital values that can be output from the conversion circuit,
The divided regions are regions obtained by dividing the output range by a division number corresponding to an amount of error in the digital value when a predetermined voltage is input as the input voltage,
A change in the correction amount with respect to a change in the digital value has a proportional relationship, and the absolute value of the correction amount assigned to the digital value corresponding to the predetermined voltage is the absolute value of the error amount in the digital value corresponding to the predetermined voltage. A correction amount is assigned to each of the divided regions so as to match with
Digital output circuit. 2. The digital output circuit according to claim 1 , wherein in the table, for each of a plurality of cases in which the error amounts are different from each other, each digital value that can be output from the conversion circuit and a correction amount are associated and recorded. . 3. The digital output circuit according to claim 1, wherein the correction unit includes an adder that adds the digital value output from the conversion circuit and the correction amount extracted from the table. 4. The digital output circuit according to any one of claims 1 to 3 , wherein the analog circuit is a voltage dividing circuit that outputs a voltage obtained by dividing the input voltage as the output voltage. 4. The digital output circuit according to any one of claims 1 to 3 , wherein the analog circuit is an amplifier circuit that outputs a voltage obtained by amplifying the input voltage as the output voltage.

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