JP7294406B2 - Imaging device and imaging device - Google Patents

Description

The present invention relates to an imaging device and an imaging device.

2. Description of the Related Art Conventionally, there has been known an imaging device that outputs pixel signals by arranging a plurality of signal lines (for example, Japanese Unexamined Patent Application Publication No. 2002-100000).

WO2010/113393

According to the first aspect of the invention, the imaging element generates electric charges by photoelectric conversion , and the first and second photoelectric conversion units provided in the row direction , and the electric charges generated by the first photoelectric conversion units to output a first signal based on the first signal line wired in the column direction and a second signal based on the charge generated by the second photoelectric conversion unit , and the second signal wired in the column direction a line, a first AD converter that converts at least one of the first signal and the second signal, which are analog signals, into a digital signal; and a second AD converter that converts the second signal, which is an analog signal, into a digital signal. a first output unit that outputs at least one of the first signal and the second signal converted into a digital signal by the first AD conversion unit to a processing unit that performs signal processing; and a digital signal generated by the second AD conversion unit. a second output section for outputting the second signal converted to the processing section to the processing section; a first control for outputting the first signal and the second signal to the processing section by the first output section; a control unit that outputs a first signal to the processing unit through the first output unit and performs second control to output the second signal to the processing unit through the second output unit.
According to a second aspect of the invention, an imaging device includes the imaging element according to the first aspect, and a generator that generates image data based on the signal processed by the processor.

1 is a diagram illustrating a configuration example of an imaging device according to a first embodiment; FIG. It is a figure which shows the structural example of the image pick-up element based on 1st Embodiment. 2A and 2B are diagrams illustrating configuration examples of pixels of an image sensor according to the first embodiment; FIG. It is a figure showing an example of composition of some image sensors concerning a 1st embodiment. FIG. 3 is a diagram showing a layout example of part of the imaging device according to the first embodiment; FIG. 5 is a diagram for comparing read control according to the first embodiment and read control according to a comparative example; FIG. 10 is a diagram showing a configuration example of part of an imaging device according to Modification 1; FIG. 10 is a diagram showing a configuration example of part of an imaging element according to modification 2; FIG. 11 is a diagram showing a configuration example of part of an imaging device according to Modification 3;

(First embodiment)
FIG. 1 is a diagram showing a configuration example of a camera 1, which is an example of an imaging device according to the first embodiment. The camera 1 includes a photographing optical system (imaging optical system) 2 , an imaging device 3 , a control section 4 , a memory 5 , a display section 6 and an operation section 7 . The photographing optical system 2 has a plurality of lenses including a focusing lens (focus lens) and an aperture stop, and forms a subject image on the image sensor 3 . Note that the photographing optical system 2 may be detachable from the camera 1 .

The imaging element 3 is an imaging element such as a CMOS image sensor or a CCD image sensor. The imaging device 3 receives the light flux that has passed through the imaging optical system 2 and captures the subject image formed by the imaging optical system 2 . In the imaging element 3, a plurality of pixels having photoelectric conversion units are arranged two-dimensionally (row direction and column direction). A photoelectric conversion element is configured by a photodiode (PD). The imaging device 3 photoelectrically converts the received light to generate a signal, and outputs the generated signal to the control unit 4 .

The memory 5 is a recording medium such as a memory card. Image data, control programs, and the like are recorded in the memory 5 . Writing data to the memory 5 and reading data from the memory 5 are controlled by the controller 4 . The display unit 6 displays an image based on image data, information related to shooting such as shutter speed and aperture value, menu screens, and the like. The operation unit 7 includes various setting switches such as a release button, a power switch, and switches for switching various modes, and outputs signals based on respective operations to the control unit 4 .

The control unit 4 includes a processor such as a CPU, FPGA, and ASIC, and memory such as a ROM and a RAM, and controls each unit of the camera 1 based on a control program. The control unit 4 supplies signals for controlling the image pickup device 3 to the image pickup device 3 to control the operation of the image pickup device 3 . Further, the control unit 4 performs various image processing on the signal output from the imaging device 3 to generate image data. The control unit 4 is also an image generation unit that generates image data, and generates still image data and moving image data based on signals output from the imaging device 3 . Image processing includes known image processing such as tone conversion processing and color interpolation processing.

The control unit 4 performs a process of individually reading the signal of each pixel of the image sensor 3 and a process of adding and reading the signals of a plurality of pixels. For example, when displaying a through image (live view image) of a subject on the display unit 6 or when shooting a moving image, the control unit 4 adds and reads signals of a plurality of pixels. Further, the control unit 4 performs a process of individually reading the signal of each pixel when performing high-resolution still image shooting.

FIG. 2 is a diagram showing a configuration example of an imaging device according to the first embodiment. The imaging element 3 includes a pixel section (pixel region) 20, a column circuit section 40 (column circuit section 40a, column circuit section 40b), a horizontal transfer section 50 (horizontal transfer section 50a, horizontal transfer section 50b), and a processing section. 60 (processing unit 60a, processing unit 60b) and a signal output unit 70 (signal output unit 70a, signal output unit 70b). The imaging device 3 includes a read control unit 100, a first supply unit 110 (first supply unit 110a, first supply unit 110b), and a second supply unit 120 (second supply unit 120a, a second supply 120b). Note that the number and arrangement of pixels arranged in the pixel unit 20 are not limited to the illustrated example.

The pixel 10 is provided with one of three color filters (color filters) 18 having different spectral characteristics of red (R), green (G), and blue (B). The pixel 10 includes a pixel (hereinafter referred to as an R pixel) having a color filter 18 having a spectral characteristic for dispersing light (red (R) light) in a first wavelength band among incident light, and a pixel (hereinafter referred to as an R pixel). A pixel (hereinafter referred to as a G pixel) having a color filter 18 having a spectral characteristic that disperses light in the second wavelength range (green (G) light) out of light, and a third wavelength out of incident light. and a pixel (hereinafter referred to as a B pixel) having a color filter 18 having a spectral characteristic for dispersing light (blue (B) light) in a wide range.

As shown in FIG. 2, the image sensor 3 includes a first pixel row in which R pixels 10 and G pixels 10 are alternately arranged in the left-right direction, that is, the row direction (horizontal direction), G pixels 10 and B pixels. 10 are alternately arranged in the row direction. The first pixel rows and the second pixel rows are alternately arranged in the column direction. Thus, in this embodiment, the R pixels 10, the G pixels 10, and the B pixels 10 are arranged according to the Bayer array.

The imaging element 3 is provided with a vertical signal line 25 (vertical signal line 25a, vertical signal line 25b) for each pixel column, which is a column of a plurality of pixels 10 arranged in the vertical direction (vertical direction). . In the example shown in FIG. 2, the plurality of vertical signal lines 25a are connected to odd-numbered pixel columns. The plurality of vertical signal lines 25b are connected to even-numbered pixel columns.

A readout control unit 100 is provided in common for a plurality of pixel columns. The readout control unit 100 is controlled by the control unit 4 of the camera 1 , supplies signals such as a signal TX, a signal RST, and a signal SEL, which will be described later, to each pixel 10 to control the operation of each pixel 10 . The readout control unit 100 supplies a signal to the gate of each transistor of the pixel 10 to turn the transistor on (connected state, conducting state, short-circuited state) or off state (disconnected state, non-conducting state, open state, cutoff state). ). A pixel signal of the pixel unit 20 selected by the readout control unit 100 is output to the vertical signal line 25 connected to the pixel 10 .

A column circuit section 40 a is provided for the odd-numbered pixel columns among the plurality of pixels 10 of the pixel section 20 . The column circuit section 40a includes a plurality of current sources 41a, a horizontal addition section 42a, and a plurality of analog/digital conversion sections (AD conversion sections) 43a. A current source 41a and an AD conversion section 43a in the column circuit section 40a are provided for each vertical signal line 25a. The current source 41a is connected to each pixel 10 via the vertical signal line 25a. The current source 41 a generates a current for reading out signals from the pixels 10 and supplies the generated current to the vertical signal line 25 a and each pixel 10 .

The horizontal addition unit 42a, which will be described later, is composed of a plurality of switches and performs addition between pixel signals output to the vertical signal line 25a. The read control unit 100 controls the addition process of the signals of the pixels arranged in the row direction (horizontal direction) by controlling the ON/OFF of the plurality of switches forming the horizontal addition unit 42a. The AD conversion section 43a converts the signal input from each pixel 10 via the horizontal addition section 42a into a digital signal, and outputs the converted digital signal to the horizontal transfer section 50a.

A column circuit section 40 b is provided for even-numbered pixel columns among the plurality of pixels 10 of the pixel section 20 . The column circuit section 40b includes a plurality of current sources 41b, a horizontal addition section 42b, and a plurality of AD conversion sections 43b. A current source 41b and an AD conversion section 43b in the column circuit section 40b are provided for each vertical signal line 25b. The current source 41b is connected to each pixel 10 via the vertical signal line 25b. The current source 41 b generates a current for reading out signals from the pixels 10 and supplies the generated current to the vertical signal line 25 b and each pixel 10 .

The horizontal addition unit 42b, which will be described later, is composed of a plurality of switches and performs addition between pixel signals output to the vertical signal line 25b. The readout control unit 100 controls the addition of signals between a plurality of pixels arranged in the row direction (horizontal direction) by on/off controlling a plurality of switches constituting the horizontal addition unit 42b. The AD conversion unit 43b converts the signal input from each pixel 10 via the horizontal addition unit 42b into a digital signal, and outputs the converted digital signal to the horizontal transfer unit 50b.

The horizontal transfer section 50a is provided for the plurality of AD conversion sections 43a, and sequentially outputs the signals converted into digital signals by the respective AD conversion sections 43a to the processing section 60a. The horizontal transfer section 50b is provided for the plurality of AD conversion sections 43b, and sequentially outputs the signals converted into digital signals by the respective AD conversion sections 43b to the processing section 60b. In this manner, in the image pickup device 3, the signals of the pixels in the odd-numbered columns and the signals of the pixels in the even-numbered columns are read out through separate paths.

The first supply unit 110a has a current source, generates a current for operating the AD conversion unit 43a, and supplies the generated current to the AD conversion unit 43a. The first supply unit 110b has a current source, generates a current for operating the AD conversion unit 43b, and supplies the generated current to the AD conversion unit 43b. The first supply unit 110a and the first supply unit 110b are controlled by the read control unit 100, respectively.

Each of the processing units 60a and 60b includes an amplifier circuit, a decoder circuit, and the like. Pixel signals converted into digital signals from the horizontal transfer unit 50a are input to the processing unit 60a. The processing unit 60a performs signal processing such as code conversion processing and correlated double sampling on the signal input from the horizontal transfer unit 50a, and outputs the processed signal to the signal output unit 70a. Pixel signals converted into digital signals from the horizontal transfer unit 50b are input to the processing unit 60b. The processing unit 60b performs signal processing such as code conversion processing and correlated double sampling on the signal input from the horizontal transfer unit 50b, and outputs the processed signal to the signal output unit 70b.

The second supply unit 120a generates a control signal for operating the processing unit 60a, which is a pulse signal (pulse) in this embodiment, and supplies the generated pulse signal to the processing unit 60a. The second supply unit 120b generates a control signal for operating the processing unit 60b, which is a pulse signal in this embodiment, and supplies the generated pulse signal to the processing unit 60b. The second supply section 120a and the second supply section 120b are controlled by the read control section 100, respectively. Note that these control signals may be signals of a constant potential (for example, power supply potential).

The signal output section 70a and the signal output section 70b each have an output circuit compatible with high-speed interfaces such as SLVS and LVDS. The signal output unit 70a outputs (transmits) the signal input from the processing unit 60a to the control unit 4 of the camera 1 at high speed. The signal output unit 70b outputs the signal input from the processing unit 60b to the control unit 4 at high speed.

FIG. 3 is a diagram showing a configuration example of a pixel of the imaging device according to the first embodiment. The pixel 10 has a photoelectric conversion unit 11 , a transfer unit 12 , a reset unit 13 , a floating diffusion (FD) 14 , an amplification unit 15 and a selection unit 16 . The photoelectric conversion unit 11 is a photodiode PD that converts incident light into charges and accumulates the photoelectrically converted charges.

The transfer unit 12 is composed of a transistor M1 controlled by a signal TX, and transfers charges photoelectrically converted by the photoelectric conversion unit 11 to the FD14. Transistor M1 is a transfer transistor. The capacitance C of the FD 14 accumulates (holds) the charge transferred to the FD 14 and converts it into voltage.

The amplifying unit 15 includes a transistor M3 whose gate (terminal) is connected to the FD14, and outputs a signal based on the voltage of the capacitor C of the FD14. The amplification section 15 is connected to the vertical signal line 25 via the selection section 16 . Transistor M3 is an amplification transistor. The amplification unit 15 and the selection unit 16 constitute an output unit that generates and outputs a signal based on the charges generated by the photoelectric conversion unit 11 .

The reset unit 13 is composed of the transistor M2 controlled by the signal RST, discharges the charge accumulated in the FD14, and resets the voltage of the FD14. Transistor M2 is a reset transistor. The selection unit 16 is composed of a transistor M4 controlled by a signal SEL, and electrically connects or disconnects the amplification unit 15 and the vertical signal line 25 . The transistor M4 of the selection unit 16 outputs the signal from the amplification unit 15 to the vertical signal line 25 when in the ON state. Transistor M4 is a select transistor.

The pixel 10 transmits a signal (dark signal) when the voltage of the FD 14 is reset and a signal (photoelectric conversion signal) corresponding to the charge transferred from the photoelectric conversion unit 11 to the FD 14 by the transfer unit 12 via the vertical signal line 25. sequentially output to The dark signal becomes an analog signal indicating a reference level for the photoelectric conversion signal. Also, the photoelectric conversion signal is an analog signal generated based on the charge photoelectrically converted by the photoelectric conversion unit 11 . Dark signals and photoelectric conversion signals sequentially output from the pixels 10 are input to the horizontal addition section 42 via the vertical signal line 25 .

FIG. 4 is a diagram showing a configuration example of part of the imaging device according to the first embodiment. FIG. 4 shows some pixels 10 out of a plurality of pixels provided in the imaging element 3, a column circuit section 40a, a horizontal transfer section 50a, a processing section 60a, and a signal output section 70a. . In FIG. 4, the pixel 10 in the upper left corner is the pixel 10 (1,1) in the first row and the first column, and the pixel 10 in the lower right corner is the pixel 10 (5,17) in the fifth row and the 17th column. , 85 pixels 10 of 17 pixels in the row direction×5 pixels in the column direction are shown.

The horizontal addition unit 42a is a switch that connects or disconnects the vertical signal line 25a (the vertical signal lines 25a1 to 25a9 in FIG. 4) and the AD conversion unit 43a (the AD conversion units 43a1 to 43a9 in FIG. 4). It has SW1 (SW1a to SW1i in FIG. 4). The horizontal addition unit 42a also has switches SW2 (SW2a to SW2f in FIG. 4) for connecting or disconnecting adjacent vertical signal lines 25a. The switch SW2 is a connecting portion that connects between the vertical signal lines 25 . The switches SW1 and SW2 are on/off-controlled by the read control unit 100 (see FIG. 2).

The AD conversion section 43a includes a comparison section 44 and a storage section 45, and converts the pixel signal input via the horizontal addition section 42a into a digital signal having a predetermined number of bits. The comparison unit 44 is configured including a comparator circuit. A current for operating the comparator circuit is supplied from the first supply unit 110a (see FIG. 2) to the comparison unit 44 of the AD conversion unit 43a. The comparison unit 44 compares the signal output from the pixel 10 with a reference signal (ramp signal) that changes constantly over time, and outputs the output signal, which is the comparison result, to the storage unit 45 .

The storage unit 45 is composed of a plurality of latch circuits corresponding to the number of bits of the digital signal to be stored. The storage unit 45 receives an output signal indicating the comparison result from the comparison unit 44 and receives a clock signal indicating a count value from a counter circuit (not shown). The storage unit 45 stores, as a digital signal, a count value corresponding to the elapsed time from the start of comparison by the comparison unit 44 to the inversion of the comparison result, based on the output signal of the comparison unit 44 and the clock signal from the counter circuit. . In other words, based on the signal output from the comparison unit 44, the storage unit 45 determines the time until the magnitude relationship between the level of the signal output from the pixel 10 and the level of the reference signal changes (inverts). The count value is stored as a digital signal.

When the dark signal of the pixel 10 is input to the comparison section 44 via the horizontal addition section 42a, the comparison section 44 compares the dark signal with the reference signal and outputs the comparison result to the storage section 45. FIG. Based on the comparison result of the comparison unit 44 and the clock signal, the storage unit 45 stores the count value corresponding to the elapsed time from the start of the comparison by the comparison unit 44 to the inversion of the comparison result as a digital signal corresponding to the dark signal. Remember. Further, when the photoelectric conversion signal of the pixel 10 is input to the comparison unit 44 via the horizontal addition unit 42a, the comparison unit 44 compares the photoelectric conversion signal with the reference signal and outputs the comparison result to the storage unit 45. do. Based on the comparison result of the comparison unit 44 and the clock signal, the storage unit 45 stores a count value corresponding to the elapsed time from the start of comparison by the comparison unit 44 to the inversion of the comparison result as a digital signal corresponding to the photoelectric conversion signal. remember as

In this manner, the AD converter 43a converts the photoelectric conversion signal, which is an analog signal, into a digital signal of a predetermined number of bits, and converts the dark signal, which is an analog signal, into a digital signal of a predetermined number of bits. The AD conversion section 43a also has an output circuit (not shown) that operates with the current supplied from the first supply section 110a, and outputs the digital signal stored in the storage section 45 to the horizontal transfer section 50a.

The horizontal transfer section 50a has switches SW3 (SW3a to SW3i in FIG. 4), data lanes 55 (data lanes 55a to 55c), sense amplifiers 62 (sense amplifiers 62a to 62c), and an AND circuit 61. The switch SW3 is ON/OFF-controlled by the read control unit 100 (see FIG. 2) to connect or disconnect the AD conversion unit 43a and the data lane 55. FIG.

The data lane 55 is provided for the plurality of AD converters 43 a and transfers (transmits) digital signals input from each AD converter 43 a via the switch SW 3 to the sense amplifier 62 . The data lane 55 is a transmission path for transmitting pixel signals converted into digital signals. In the example shown in FIG. 4, the horizontal transfer section 50a has a data lane 55a, a data lane 55b, and a data lane 55c. Each of the data lanes 55a-55c is composed of a plurality of signal lines corresponding to the number of bits of the digital signal to be transmitted.

The sense amplifier 62 is composed of a plurality of amplifier circuits corresponding to the number of bits of the input digital signal and arranged for each data lane 55 . Sense amplifier 62a is provided for data lane 55a, sense amplifier 62b is provided for data lane 55b, and sense amplifier 62c is provided for data lane 55c. The sense amplifiers 62a to 62c are each supplied with a control signal for operating the amplifier circuit, which is a pulse signal in this embodiment, from the second supply unit 120a (see FIG. 2). The sense amplifiers 62a to 62c amplify and read signals input to the data lanes 55 connected thereto. Thus, the digital signals stored in the storage section 45 are sequentially output to the processing section 60a via the data lane 55 and the sense amplifier 62. FIG. Note that the control signal for operating the amplifier circuit may be a signal of a constant potential (for example, power supply potential).

The signal V1 and the signal V2 are input to the AND circuit 61 . The signal V1 is also input to the sense amplifier 62b. The output signal of the AND circuit 61 is input to the sense amplifiers 62a and 62c respectively. A signal V1 and a signal V2 are signals used for controlling the sense amplifiers 62a to 62c. The read control unit 100 controls the operating states of the sense amplifiers 62a to 62c by controlling the signals V1 and V2.
In this manner, the horizontal transfer section 50a sequentially outputs the signals converted into digital signals by the respective AD conversion sections 43a to the processing section 60a.

The processing unit 60a has a signal processing unit 64 (signal processing units 64a to 64c). A signal processing unit 64 is provided for each sense amplifier 62 . The signal processing portion 64a is provided for the sense amplifier 62a, the signal processing portion 64b is provided for the sense amplifier 62b, and the signal processing portion 64c is provided for the sense amplifier 62c. The signal processing unit 64 is composed of a decoding circuit, a memory circuit, and the like. The signal processing unit 64 performs signal processing such as code conversion processing and correlated double sampling on the signal input from the sense amplifier 62 . The signal processing unit 64 outputs the processed signal to the signal output unit 70a.

The signal output section 70a has output I/F sections 71a to 71c. The output I/F units 71a to 71c are configured by output circuits compatible with high-speed interfaces such as SLVS. The output I/F section 71 a outputs the signal input from the signal processing section 64 a to the control section 4 of the camera 1 . Further, the output I/F unit 71b outputs the signal input from the signal processing unit 64b to the control unit 4, and the output I/F unit 71c outputs the signal input from the signal processing unit 64c to the control unit 4. do. The configurations of the column circuit section 40b, the horizontal transfer section 50b, the processing section 60b, and the signal output section 70b are the same as the configurations of the column circuit section 40a, the horizontal transfer section 50a, the processing section 60a, and the signal output section 70a, respectively. It is the same.

The readout control unit 100 (see FIG. 2) controls each switch of the horizontal addition unit 42 and the horizontal transfer unit 50 to individually read out the signal of each pixel of the image sensor 3 (individual readout control), and A process of adding and reading out pixel signals (addition readout control) is performed. The control unit 4 of the camera 1 controls the readout control unit 100 to switch the readout method of the pixel signal.

In the individual readout control, the readout control unit 100 turns off the switch SW2 of the horizontal addition unit 42, sequentially selects a plurality of pixels of the image sensor 3 in row units, and converts the signals of the selected pixels to the AD conversion unit 43. output to In addition, the read control unit 100 uses the plurality of data lanes 55 of the horizontal transfer unit 50 to sequentially output the pixel signals converted into digital signals by the respective AD conversion units 43 to the processing unit 60 .

In addition readout control, the readout control unit 100 turns on the switch SW2 of the horizontal addition unit 42, sequentially selects a plurality of pixels of the image sensor 3 in units of rows, and outputs the signals of the plurality of pixels to the vertical signal line 25. to add. The readout control unit 100 outputs the added pixel signals to some of the plurality of AD conversion units 43 arranged in the image sensor 3 .

In the present embodiment, some of the AD converters 43 to which added pixel signals are input are connected to some of the data lanes 55 of the horizontal transfer unit 50, as will be described later. be done. Therefore, in the addition readout control, the readout control unit 100 uses only some of the data lanes 55 out of the plurality of data lanes 55 to process the pixel signals converted into digital signals by the respective AD conversion units 43. It becomes possible to cause the unit 60 to sequentially output.

As described above, the read control unit 100 uses part of the AD converters 43 and part of the data lanes 55 when performing addition read control. Other AD converters 43 to which added pixel signals are not input, data lanes 55 to which these AD converters 43 are connected, and sense amplifiers 62 to which these data lanes 55 are connected are subjected to addition readout control. not used in For this reason, the readout control unit 100 controls the first supply unit 110 to stop supplying the current to the AD conversion unit 43 that is not used when performing addition readout control. Further, the read control unit 100 stops the operation of the data lane 55 that is not used when performing addition read control. Further, the read control unit 100 controls the second supply unit 120 to stop the operation of the sense amplifier 62 that is not used when performing addition read control. Thereby, the power consumption of the imaging device 3 can be reduced. Therefore, when performing moving image shooting at a high frame rate, it is possible to suppress an increase in power consumption due to addition readout control.

In the example shown in FIG. 4, the AD converters 43 used when performing addition readout control are, for example, an AD converter 43a2, an AD converter 43a5, and an AD converter 43a8. The AD converters 43a2, 43a5, and 43a8 are connected to the same data lane 55b among the plurality of data lanes 55a to 55c via switches SW3b, SW3e, and SW3h, respectively.

Some AD converters 43 (AD converters 43a2, 43a5, and 43a8 in FIG. 4), some data lanes 55 (data lanes 55b in FIG. 4), and some sense amplifiers 62 (in FIG. The sense amplifier 62 b ) constitutes a first output unit that outputs the pixel signal output to the vertical signal line 25 to the processing unit 60 . The first output section is supplied with the current from the first supply section 110 and the pulse signal from the second supply section 120 both when the individual readout control is performed and when the addition readout control is performed. It becomes operational.

Other AD converters 43 (AD converters 43a1, 43a3, 43a4, 43a6, 43a7, 43a9 in FIG. 4) of the imaging device 3, other data lanes 55 (data lanes 55a and 55c in FIG. 4), and other sense amplifiers 62 (sense amplifiers 62 a and 62 c in FIG. 4 ) constitute a second output section for outputting pixel signals output to the vertical signal line 25 to the processing section 60 . When individual readout control is performed, the second output section is supplied with a current from the first supply section 110 and a pulse signal is supplied from the second supply section 120 to be in an operating state. When addition readout control is performed, no pixel signal is input to the second output section. Therefore, when performing addition readout control, the readout control unit 100 causes the first supply unit 110 to stop supplying current to the second output unit, and causes the second supply unit 120 to supply a pulse to the second output unit. Stop the signal supply. As a result, when the addition readout control is performed, the second output section is not supplied with current from the first supply section 110 and is not supplied with the pulse signal from the second supply section 120, and is in a stopped state.

As described above, the second output sense amplifiers 62 (sense amplifiers 62a and 62c in FIG. 4) are not used in the addition read control. The read control unit 100 causes the second supply unit 120 to stop supplying pulse signals to the sense amplifiers 62a and 62c when performing addition read control. As a result, the sense amplifiers 62a and 62c are not supplied with the pulse signal from the second supply unit 120 and are in a stopped (idle) state when the addition readout control is performed. When performing addition readout control, the second output section is in a stopped state, and the power consumption of the imaging device 3 is reduced.
The individual readout control and the addition readout control will be described in more detail below.

When the control unit 4 selects (sets) the individual read control, the read control unit 100 turns on the switches SW1a to SW1i of the horizontal addition unit 42 and turns off the switches SW2a to SW2f. Also, the read control unit 100 sets both the signal V1 and the signal V2 to high level. As a result, the sense amplifiers 62a to 62c are ready for the operation of amplifying and reading the input signals.

The read control unit 100 turns on the reset units 13 of the R pixels 10(1,1) to 10(1,17), which are the pixels in the first row. Thereby, the voltage of each FD 14 is reset in the pixels 10 of the first row. Also, the selectors 16 of the pixels 10 in the first row are turned on. The read control unit 100 turns off the selection units 16 of the pixels 10 in the rows other than the first row. As a result, the dark signal of each of the R pixels 10(1,1) to 10(1,17) in the first row is applied to the selection section 16 of each pixel and the vertical signal line connected to each pixel. 25a1 to vertical signal line 25a9 and switch SW1a to switch SW1i, and output to AD converters 43a1 to 43a9, respectively.

The AD converters 43a1 to 43a9 convert the input dark signals into digital signals. The read control unit 100 controls the switches SW3a to SW3i of the horizontal transfer unit 50a to sequentially output the dark signals converted into digital signals by the respective AD conversion units 43a to the processing unit 60a via the sense amplifiers 62. . The read control unit 100 turns ON only the switches SW3a to SW3c among the switches SW3a to SW3i, and outputs the digital signals converted by the AD conversion units 43a1 to 43a3 to the processing unit 60a via the data lanes 55a to 55c, respectively. Let After that, the read control unit 100 turns ON only the switches SW3d to SW3f out of the switches SW3a to SW3i, and transmits the digital signals converted by the AD conversion units 43a4 to 43a6 to the processing unit 60a via the data lanes 55a to 55c, respectively. output to After that, the read control unit 100 turns ON only the switches SW3g to SW3i out of the switches SW3a to SW3i, and transmits the digital signals converted by the AD conversion units 43a7 to 43a9 to the processing unit 60a through the data lanes 55a to 55c, respectively. output to

The readout control unit 100 turns on the transfer units 12 of the R pixels 10(1,1) to 10(1,17), which are pixels in the first row. As a result, in the pixels 10 on the first row, charges photoelectrically converted by the respective PDs 11 are transferred to the FDs 14 . Each photoelectric conversion signal of the R pixel 10 (1, 1) to R pixel 10 (1, 17) in the first row is supplied to the selector 16 of each pixel, the vertical signal line 25 connected to each pixel, and through the switch SW1 to the AD converters 43a1 to 43a9, respectively.

The AD converters 43a1 to 43a9 convert the input photoelectric conversion signals into digital signals. The photoelectric conversion signals converted into digital signals by the AD converters 43a1 to 43a9 are processed via the data lanes 55a to 55c, respectively, in the same manner as the dark signals converted into digital signals are sequentially output to the processing unit 60a. They are sequentially output to the unit 60a.

The readout control unit 100 reads a dark signal and a photoelectric signal from pixels 10(2,1) to 10(2,17), which are pixels in the second row, in the same manner as when signals are read out from the pixels in the first row. Read conversion signal. Similarly, the readout control unit 100 sequentially selects pixels on the third and subsequent rows one by one in the order of the third, fourth, fifth, and sixth rows, and outputs a signal from each selected pixel. read out.

In this manner, in the individual readout control, the readout control unit 100 individually reads out the signals of the pixels of the image sensor 3 . The dark signal and photoelectric conversion signal sequentially output to the data lanes 55a to 55c are subjected to signal processing such as correlated double sampling by the processing unit 60a. The signal output to the data lane 55a is input to the signal processing section 64a via the sense amplifier 62a, subjected to signal processing by the signal processing section 64a, and then output to the control section 4 by the output I/F section 71a. be. The signal output to the data lane 55b is input to the signal processing section 64b via the sense amplifier 62b, subjected to signal processing by the signal processing section 64b, and then output to the control section 4 by the output I/F section 71b. be. Further, the signal output to the data lane 55c is input to the signal processing section 64c via the sense amplifier 62c, subjected to signal processing by the signal processing section 64c, and sent to the control section 4 by the output I/F section 71c. output.
Next, as an example of addition readout control, a case of adding and reading out the signals of pixels of the same color every three pixels in the row direction will be described.

When the control unit 4 selects addition readout control, the readout control unit 100 turns on the switches SW1b, SW1e, and SW1h of the horizontal addition unit 42 . The read control unit 100 turns off the switch SW1a, the switch SW1c, the switch SW1d, the switch SW1f, the switch SW1g, and the switch SW1i. Further, the read control unit 100 turns on the switches SW2a to SW2f. The read control unit 100 controls the first supply unit 110a to stop supplying current to the AD conversion units 43a1, 43a3, 43a4, 43a6, 43a7, and 43a9. Further, the read control unit 100 sets the signal V1 to high level to enable the sense amplifier 62b, and sets the signal V2 to low level to stop the sense amplifiers 62a and 62c.

The read control unit 100 turns on the reset units 13 of the R pixels 10(1,1) to 10(1,17), which are the pixels in the first row. Also, the selectors 16 of the pixels in the first row are turned on. The read control unit 100 turns off the selectors 16 of the pixels in the rows other than the first row. Since both the switches SW2a and SW2b are in the ON state, the amplification units 15 of the R pixels 10(1,1), R pixels 10(1,3), and R pixels 10(1,5) generate vertical signals They are electrically connected via lines 25a1 to 25a3. As a result, the dark signal of the R pixel 10(1,1), the dark signal of the R pixel 10(1,3), and the dark signal of the R pixel 10(1,5) are averaged. Also, since the switch SW1b is in the ON state, the added dark signal is output to the AD converter 43a2.

Similarly, the dark signal of the R pixel 10 (1, 7), the dark signal of the R pixel 10 (1, 9), and the dark signal of the R pixel 10 (1, 11) are averaged and passed through the switch SW1e. It is output to the AD converter 43a5. Further, the dark signal of the R pixel 10 (1, 13), the dark signal of the R pixel 10 (1, 15), and the dark signal of the R pixel 10 (1, 17) are added and averaged, and the AD signal is output through the switch SW1h. It is output to the conversion unit 43a8.

The AD converters 43a2, 43a5, and 43a8 each convert the added dark signal into a digital signal. The read control unit 100 sequentially turns on the switch SW3b, the switch SW3e, and the switch SW3h of the horizontal transfer unit 50a, and transmits the digital signal converted by each AD conversion unit 43a to the processing unit 60a via the sense amplifier 62. output sequentially. The read control unit 100 turns ON only the switch SW3b among the switches SW3a to SW3i to output the digital signal converted by the AD conversion unit 43a2 to the processing unit 60a via the data lane 55b. After that, the read control unit 100 turns ON only the switch SW3e among the switches SW3a to SW3i to output the digital signal converted by the AD conversion unit 43a5 to the processing unit 60a via the data lane 55b. After that, the read control unit 100 turns on only the switch SW3h among the switches SW3a to SW3i to output the digital signal converted by the AD conversion unit 43a8 to the processing unit 60a via the data lane 55b.

The readout control unit 100 turns on the transfer units 12 of the R pixels 10(1,1) to 10(1,17), which are pixels in the first row. As a result, in the pixels 10 on the first row, charges photoelectrically converted by the respective PDs 11 are transferred to the FDs 14 . Since both the switches SW2a and SW2b are in the ON state, the amplification units 15 of the R pixels 10(1,1), R pixels 10(1,3), and R pixels 10(1,5) generate vertical signals They are electrically connected via lines 25a1 to 25a3. As a result, the photoelectric conversion signal of the R pixel 10(1,1), the photoelectric conversion signal of the R pixel 10(1,3), and the photoelectric conversion signal of the R pixel 10(1,5) are averaged. Further, since the switch SW1b is in the ON state, the photoelectrically converted signal obtained by adding and averaging is output to the AD conversion section 43a2.

Similarly, the photoelectric conversion signal of the R pixel 10 (1, 7), the photoelectric conversion signal of the R pixel 10 (1, 9), and the photoelectric conversion signal of the R pixel 10 (1, 11) are added and averaged to obtain the switch SW1e. to the AD converter 43a5. Further, the photoelectric conversion signal of the R pixel 10 (1, 13), the photoelectric conversion signal of the R pixel 10 (1, 15), and the photoelectric conversion signal of the R pixel 10 (1, 17) are added and averaged, and the switch SW1h is turned on. output to the AD converter 43a8 via the

The AD converters 43a2, 43a5, and 43a8 convert the added photoelectric conversion signals into digital signals. The read control unit 100 sequentially turns on the switch SW3b, the switch SW3e, and the switch SW3h of the horizontal transfer unit 50a, and transmits the digital signal converted by each AD conversion unit 43a to the processing unit 60a via the sense amplifier 62. output sequentially. The read control unit 100 turns ON only the switch SW3b among the switches SW3a to SW3i to output the digital signal converted by the AD conversion unit 43a2 to the processing unit 60a via the data lane 55b. After that, the read control unit 100 turns ON only the switch SW3e among the switches SW3a to SW3i to output the digital signal converted by the AD conversion unit 43a5 to the processing unit 60a via the data lane 55b. After that, the read control unit 100 turns on only the switch SW3h among the switches SW3a to SW3i to output the digital signal converted by the AD conversion unit 43a8 to the processing unit 60a via the data lane 55b.

The readout control unit 100 reads out the signals added from the pixels in the first row, and adds the signals from the pixels 10(2,1) to 10(2,17), which are the pixels in the second row. read out the dark signal and the photoelectric conversion signal. Similarly, the readout control unit 100 sequentially selects pixels on the third and subsequent rows one by one in the order of the third, fourth, fifth, and sixth rows, and outputs a signal from each selected pixel. read out.

In this way, in addition readout control, the readout control unit 100 adds up and reads out the signals of a plurality of pixels of the image sensor 3 . The added dark signal and photoelectric conversion signal are converted into digital signals by the AD converter 43, and then sequentially output to the data lane 55b. The dark signal and the photoelectric conversion signal that are sequentially output to the data lane 55b are input to the signal processing unit 64b via the sense amplifier 62b. It is output to the control section 4 by the I/F section 71b.

FIG. 5 is a diagram showing a layout example of part of the imaging device according to the first embodiment. The imaging element 3 is configured using a semiconductor substrate having p-wells 201 and 202 . P-well 201 is provided with region 210 and region 211 formed to surround region 210 . P-well 202 is provided with region 220 and region 221 formed to surround region 220 .

A region 210 in the p-well 201 is a region (analog circuit region) in which elements forming an analog circuit are formed. A comparison unit 44 of the AD conversion unit 43 is provided in the analog circuit area 210 . A region 220 in the p-well 202 is a region (digital circuit region) in which elements forming a digital circuit are formed. The storage section 45 and the horizontal transfer section 50 are provided in the digital circuit area 220 . Regions 211 and 221 are p+ regions formed using p-type impurities. The regions 211 and 221 each function as a guard ring to suppress charge leakage to adjacent regions.

The analog circuit area 210 and the digital circuit area 220 are arranged close to each other, and a parasitic capacitance 90 is formed between the analog circuit area 210 and the digital circuit area 220 . Also, since the comparison unit 44 in the analog circuit area 210 and the horizontal transfer unit 50 in the digital circuit area 220 are arranged relatively close to each other, they may interfere with each other through the parasitic capacitance 90 and generate noise. If the operating state of the horizontal transfer unit 50 changes while the AD conversion unit 43 is performing AD conversion, the noise interference state changes during the AD conversion, which may cause variations in AD conversion results. Due to the change in the magnitude of the noise that the horizontal transfer section 50 exerts on the AD conversion section 43, the accuracy of AD conversion can be lowered.

In the present embodiment, as described above, only one data lane 55 out of the three data lanes 55 is used to perform the addition readout control for adding and reading out the signals of the three pixels in the horizontal direction. Transfer signals. During a period in which signals are read out from pixels in one row, the one data lane 55 is in a state of repeating transfer of digital signals, and the other two data lanes 55 are in a stop state in which digital signals are not transferred. This makes it possible to prevent the operation state of the data lane 55 from changing when performing addition read control. As a result, the noise received by the AD converter 43 is suppressed from being changed, and it is possible to prevent variations in AD conversion results. Suppression of a change in noise received by the AD converter 43 will be described below in comparison with a comparative example.

In the comparative example, the AD converters 43 used in addition readout control are connected to different data lanes 55 . The AD converter 43a2 is connected to the data lane 55a, the AD converter 43a5 is connected to the data lane 55b, and the AD converter 43a8 is connected to the data lane 55c. In the comparative example, when performing addition readout control, the readout control unit 100 outputs the digital signal converted by the AD conversion unit 43a2 to the data lane 55a, and outputs the digital signal converted by the AD conversion unit 43a5 to the data lane 55a. 55b and the operation of outputting the digital signal converted by the AD converter 43a8 to the data lane 55c are performed simultaneously.

FIG. 6 is a diagram for comparing read control according to the first embodiment and read control according to a comparative example. FIG. 6(a) shows the operating state of the AD converter 43 and the data lanes 55a to 55c when the imaging device according to the present embodiment performs individual readout control. FIG. 6B shows the operational state of the AD converter 43 and the data lanes 55a to 55c when the imaging device according to the comparative example performs addition readout control. FIG. 6(c) shows the operation state of the AD converter 43 and the data lanes 55a to 55c when the imaging device according to the present embodiment performs addition readout control. 6(a) to 6(c) show the case where the horizontal transfer section 50 reads out the signals of the pixels in the N-th row on the same time axis. 6A to 6C, in order to compare the operation states of the data lanes 55a to 55c during the AD conversion processing by the AD conversion unit 43, the signal of the pixel in the (N+1)th row is , and the transfer processing of the signals of the pixels in the N-th row are shown side by side.

In the case of individual readout control, as described above, the readout control unit 100 uses the three data lanes 55a to 55c of the horizontal transfer unit 50 to sequentially output pixel signals converted into digital signals to the processing unit 60. . In the example shown in FIG. 6A, the data lanes 55a to 55c sequentially output the signals of the pixels in the Nth row to the processing unit 60 during the period from time t1 to time t4. A period from time t1 to time t4 is a period (read period) for reading the signals of the pixels in the Nth row to the processing unit 60 .

Also, in the period from time t1 to time t4, the AD converters 43a1 to 43a9 sequentially convert photoelectric conversion signals and dark signals output from the pixels in the (N+1)th row into digital signals. A period from time t1 to time t4 is a period for converting the signals of the pixels in the (N+1)th row into digital signals. Note that the individual readout control in the case of the comparative example is also the same as in FIG. 6(a).

When addition readout control is performed in the comparative example, the readout control unit 100 sequentially outputs pixel signals to the processing unit 60 using the three data lanes 55a to 55c. Since the signals of three pixels in the horizontal direction are added and read out, the number of signals (data amount) transferred from the horizontal transfer unit 50 to the processing unit 60 is 1/3 of that in the case of individual readout control. Become. In addition, in order to read the signals of pixels with 1/3 the number of signals to the processing unit 60 using the three data lanes 55a to 55c as in the case of the individual readout control, the readout in the case of the addition readout control according to the comparative example is performed. The period is approximately ⅓ of the read period in the case of individual read control.

In the case of the addition readout control according to the comparative example shown in FIG. 6B, in the period from time t1 to time t2, the data lanes 55a to 55c receive data from the Nth row input from the AD converters 43a2, 43a5, and 43a8. Eye pixel signals are sequentially output to the processing unit 60 . At time t2, reading out of the signals of the pixels of the Nth row to the processing unit 60 is completed. During the period from time t2 to time t4, the data lanes 55a to 55c do not receive pixel signals from the AD converter 43 and are not used for data transfer. Also, in the period from time t1 to time t4, the AD converters 43a2, 43a5, and 43a8 sequentially convert the added photoelectric conversion signals and dark signals of the (N+1)-th row pixels into digital signals. A period from time t1 to time t4 is a period for converting the signals of the pixels of the (N+1)th row into digital signals, as in the case of the individual readout control.

As described above, in the comparative example, the data lanes 55a to 55c change from the operating state to the stopped state in the middle of the period in which the signals of the pixels of the (N+1)th row are AD-converted. Therefore, in the comparative example, when the addition readout control is performed, the noise received by the AD conversion unit 43 changes during the period in which the AD conversion processing is performed by the AD conversion unit 43 . As a result, in the comparative example, the accuracy of AD conversion is lowered. It is conceivable that the data lanes 55a to 55c are also allowed to transfer signals during the period from time t2 to time t4 to suppress changes in the noise received by the AD conversion unit 43, but in this case power consumption increases. Resulting in.

The readout control unit 100 according to the present embodiment sequentially outputs pixel signals to the processing unit 60 using one data lane 55b when performing addition readout control. The data lanes 55 used for addition readout control are aggregated into one data lane 55b. In the example shown in FIG. 6C, the data lane 55b outputs to the processing unit 60 the pixel signals sequentially input from the AD conversion units 43a2, 43a5, and 43a8 during the period from time t1 to time t4. During the period from time t1 to time t4, the data lane 55b is in an operating state and the data lanes 55a and 55c are in a stopped state. In the present embodiment, even when performing addition readout control, similarly to when performing individual readout control, the period from time t1 to time t4 is the period during which the signals of the pixels in the N-th row are read out to the processing unit 60. .

As described above, in the present embodiment, the data lane 55b remains in the operating state, and the data lanes 55a and 55c are in the stopped state during the AD conversion processing of the signals of the pixels of the (N+1)th row. remain. As a result, it is possible to prevent the noise received by the AD conversion section 43 from changing during the period in which the AD conversion processing is performed by the AD conversion section 43 . As a result, in the present embodiment, it is possible to prevent the accuracy of AD conversion from deteriorating. Moreover, in the present embodiment, the data lane 55 used for addition readout control is narrowed down, so power consumption can be reduced.

According to the embodiment described above, the following effects are obtained.
(1) The image sensor 3 has a photoelectric conversion unit 11 that generates electric charges by photoelectric conversion, and has first and second pixels (pixels 10) that output signals based on the electric charges generated by the photoelectric conversion unit 11. , a first signal line (eg, vertical signal line 25a2) for outputting the signal of the first pixel, a second signal line (eg, vertical signal line 25a3) for outputting the signal of the second pixel, and the first signal line. a first output unit (for example, an AD conversion unit 43a2, a data lane 55b, and a sense amplifier 62b) that outputs at least one of the signal output to the second signal line and the signal output to the second signal line to the processing unit 60 for signal processing; A second output unit (for example, the AD conversion unit 43a3, the data lane 55c, and the sense amplifier 62c) that outputs the signal output to the signal line to the processing unit 60, and the signal of the first pixel and the signal of the second pixel. First control for outputting to the processing unit 60 by the first output unit, outputting the signal of the first pixel to the processing unit 60 by the first output unit, and outputting the signal of the second pixel to the processing unit 60 by the second output unit and a control unit (read control unit 100) that performs a second control to cause the reading to be performed. In the present embodiment, the imaging device 3 performs addition readout control to operate the first output unit of the first and second output units and output the added pixel signals to the processing unit 60 . Therefore, power consumption of the image sensor 3 can be reduced by stopping the second output unit when performing addition readout control.

(2) In the present embodiment, the image sensor 3 uses the data lane 55b out of the data lanes 55a to 55c when performing addition readout control for adding and reading out pixel signals for each three pixels in the horizontal direction. , causes the processing unit 60 to sequentially output the signals of the added pixels. In this case, the data lane 55b remains active, and the data lanes 55a and 55c remain inactive. Therefore, it is possible to suppress a change in the noise received by the AD conversion section 43 due to a change in the operating state of the data lane 55 during the period in which the AD conversion processing is performed by the AD conversion section 43 . As a result, it is possible to suppress deterioration in accuracy of AD conversion.

The following modifications are also within the scope of the present invention, and it is also possible to combine one or more of the modifications with the above-described embodiments.

(Modification 1)
FIG. 7 is a diagram showing a configuration example of part of an imaging device according to Modification 1. As shown in FIG. The imaging device 3 according to Modification 1 includes an AND circuit 63 . The clock signal CLK and the signal V3 are input to the AND circuit 63 . The clock signal CLK is also input to the signal processing section 64b. The output signal of the AND circuit 63 is input to the signal processing section 64a and the signal processing section 64c. The read control unit 100 controls the operating states of the signal processing units 64a and 64c by controlling the signal V3.

When the control unit 4 selects the individual read control, the read control unit 100 sets the signal V3 to high level. As a result, the clock signal CLK is input to the signal processing units 64a and 64c via the AND circuit 63. FIG. Since the clock signal CLK is also input to the signal processing section 64b, the signal processing sections 64a to 64c can perform signal processing on the signal output from the sense amplifier 62 based on the clock signal CLK. state.

When the control unit 4 selects addition readout control, the readout control unit 100 sets the signal V3 to low level. As a result, the signal processing units 64a and 64c are not input with the clock signal and are in a stopped state. Note that the signal processing unit 64b is in an operable state because the clock signal CLK is input.

As described above, the read control unit 100 controls the signal V3 input to the AND circuit 63 to control the operating states of the signal processing units 64a and 64c. Therefore, the readout control unit 100 can stop the signal processing units 64a and 64c to reduce the power consumption of the imaging element 3 when performing the addition readout control.

(Modification 2)
FIG. 8 is a diagram showing a configuration example of part of an imaging device according to Modification 2. As shown in FIG. The imaging device 3 according to Modification 2 includes a conversion section 65 and multiplexers 66a to 66c. The conversion unit 65 is connected to the signal processing unit 64b, and divides the signals input from the signal processing unit 64b to the multiplexers 66a to 66c and outputs them.

The multiplexer 66a is controlled by the read control unit 100, and selects a signal to be output to the output I/F unit 71a from the signal output by the signal processing unit 64a and the signal output by the conversion unit 65. FIG. The multiplexer 66b is controlled by the read control unit 100 and selects a signal to be output to the output I/F unit 71b from the signal output by the signal processing unit 64b and the signal output by the conversion unit 65. FIG. The multiplexer 66c is controlled by the read control unit 100, and selects a signal to be output to the output I/F unit 71c from the signal output by the signal processing unit 64c and the signal output by the conversion unit 65.

In the individual readout control, the multiplexer 66a outputs the pixel signal input from the signal processing section 64a to the output I/F section 71a. The multiplexer 66b outputs the pixel signal input from the signal processing section 64b to the output I/F section 71b. The multiplexer 66c also outputs the pixel signal input from the signal processing unit 64c to the output I/F unit 71c. The output I/F units 71a, 71b, and 71c output signals input from the signal processing units 64a, 64b, and 64c to the control unit 4, respectively.

In addition readout control, the signal processing unit 64b performs signal processing on pixel signals that are sequentially input via the data lane 55b and the sense amplifier 62b, and outputs the processed signals to the conversion unit 65 in sequence. The conversion unit 65 divides the signals sequentially input from the signal processing unit 64b to multiplexers 66a to 66c and outputs them. The multiplexer 66a outputs the pixel signal input from the conversion unit 65 to the output I/F unit 71a, and the multiplexer 66b outputs the pixel signal input from the conversion unit 65 to the output I/F unit 71b. Further, the multiplexer 66c outputs the pixel signal input from the conversion unit 65 to the output I/F unit 71c. The output I/F units 71 a , 71 b , and 71 c each output the signal input from the conversion unit 65 to the control unit 4 .

In the above-described embodiment, when addition readout control is performed, the pixel signal is output to the control unit 4 by one output I/F unit 71b out of the three output I/F units 71a to 71c. In this modified example, when performing addition readout control, pixel signals are output to the control unit 4 by the output I/F units 71a to 71c. Signals can be output to the control unit 4 from the three output I/F units 71a to 71c both when individual readout control is performed and when addition readout control is performed. The number of output I/F units 71 used for individual readout control can be the same as the number of output I/F units 71 used for addition readout control. Therefore, pixel signals can be communicated between the image sensor 3 and the control unit 4 in the same manner as in the case of performing the addition readout control and the case of performing the individual readout control.

(Modification 3)
In the above-described embodiment, an example in which the imaging device 3 has three data lanes 55 for one horizontal transfer section 50 has been described. However, the imaging device may be configured to have three or more data lanes per horizontal transfer unit.

FIG. 9 is a diagram showing a configuration example of part of an imaging device according to Modification 3. As shown in FIG. In this modification, the horizontal transfer section 50 (horizontal transfer section 50a in FIG. 9) has four data lanes 55: data lane 55a, data lane 55b, data lane 55c, and data lane 55d. The horizontal transfer section 50 further has a sense amplifier 62d. The processing unit 60 (processing unit 60a in FIG. 9) further includes a signal processing unit 64d and a multiplexer 66d. The signal output section 70 (the signal output section 70a in FIG. 9) further has an output I/F section 71d.

In this modification, the AD converters 43 (AD converters 43a2, 43a5, and 43a8 in FIG. 9) used in addition readout control are connected to either of the two data lanes 55 (data lanes 55a and 55b in FIG. 9). Connected. The AD converter 43a2 is connected to the data lane 55b, the AD converter 43a5 is connected to the data lane 55a, and the AD converter 43a8 is connected to the data lane 55b.

In the case of individual readout control, the signals of the pixels in each row are output through the selector 16 of each pixel, the vertical signal lines 25a1 to 25a9 connected to each pixel, and the switches SW1a to SW1i, respectively. It is output to the conversion section 43a1 to AD conversion section 43a9. The AD converters 43a1 to 43a9 respectively convert the input pixel signals into digital signals. The read control unit 100 controls the switches SW3a to SW3i of the horizontal transfer unit 50a to sequentially output the digital signals converted by the AD conversion units 43a1 to 43a9 to the processing unit 60a through the data lanes 55a to 55d. The signals output to the data lanes 55a-55d are input to the signal processing units 64a-64d via the sense amplifiers 62a-62d, respectively. It is output to the control unit 4 by the F units 71a to 71d.

In addition readout control, the readout control unit 100 sequentially outputs pixel signals to the processing unit 60 using the two data lanes 55a and 55b. The read control unit 100 outputs a digital signal converted by one AD conversion unit 43a (for example, an AD conversion unit 43a2) to the data lane 55b, and another AD conversion unit 43 (for example, an AD conversion unit 43a5) to output the converted digital signal to the data lane 55a at the same time. The signal output to the data lane 55a is input to the signal processing section 64a via the sense amplifier 62a, subjected to signal processing by the signal processing section 64a, and then output to the control section 4 by the output I/F section 71a. be. The signal output to the data lane 55b is input to the signal processing section 64b via the sense amplifier 62b, subjected to signal processing by the signal processing section 64b, and then output to the control section 4 by the output I/F section 71b. be. In addition readout control in the case of this modification, the data lanes 55c and 55d do not receive pixel signals from the AD converter 43 and are not used for data transfer. Therefore, the power consumption of the imaging device 3 can be reduced by stopping the AD conversion section 43, the sense amplifiers 62c and 62d, and the signal processing sections 64c and 64d connected to the data lanes 55c and 55d.

(Modification 4)
An amplifier section may be provided between the switch SW1 connected to the vertical signal line 25 and the AD conversion section 43 . The amplifier unit is provided for each vertical signal line 25 , amplifies the pixel signal input via the vertical signal line 25 with a predetermined gain (amplification factor), and outputs the amplified pixel signal to the AD conversion unit 43 . do. A current for operating the amplifier section is supplied from the first supply section 110 to the amplifier section. The AD converter 43 converts the amplified pixel signal into a digital signal and outputs the digital signal to the horizontal transfer unit 50 .

Some AD converters 43 (AD converters 43a2, 43a5, and 43a8 in FIG. 4) of the image sensor 3, amplifiers connected to some of these AD converters 43, and some data lanes 55 (FIG. 4A). 4) and some of the sense amplifiers 62 (sense amplifiers 62b in FIG. 4) constitute a first output section for outputting pixel signals output to the vertical signal line 25 to the processing section 60. . Further, the other AD converters 43 of the imaging device 3 (AD converters 43a1, 43a3, 43a4, 43a6, 43a7, and 43a9 in FIG. 4), the amplifiers connected to these other AD converters 43, and other The data lane 55 (data lanes 55a and 55c in FIG. 4) and other sense amplifiers 62 (sense amplifiers 62a and 62c in FIG. 4) output pixel signals output to the vertical signal line 25 to the processing unit 60. configure a second output unit for

When addition readout control is performed, no pixel signal is input to the second output section. Therefore, when performing addition readout control, the readout control unit 100 causes the first supply unit 110 to stop supplying current to the second output unit, and causes the second supply unit 120 to supply a pulse to the second output unit. Stop the signal supply. As a result, when performing addition readout control, the second output section is in a stopped state, and the power consumption of the image sensor 3 can be reduced.

(Modification 5)
The readout control unit 100 may turn on the switches SW1a to SW1i of the horizontal addition unit 42 when performing addition readout control, as in the case of performing individual readout control. The added pixel signals are also input to the AD conversion unit 43 of the second output unit. In this case, the readout control section 100 may control the second output section so as not to output the pixel signal from the second output section to the processing section 60 .

The read control unit 100 may prevent the pixel signal from being output from the second output unit to the processing unit 60 by causing the first supply unit 110 to stop supplying the current to the second output unit. The readout control unit 100 causes the second supply unit 120 to stop supplying the pulse signal to the sense amplifiers 62 (sense amplifiers 62a and 62c in FIG. 4) of the second output unit, thereby outputting the pixel signal to the second output. It is also possible not to output from the unit to the processing unit 60 . At this time, the read control unit 100 causes the second supply unit 120 to supply a signal of a constant potential (for example, 0 V or ground potential) to the sense amplifier 62 of the second output unit for a predetermined period of time. The sense amplifier 62 in the output section may be stopped.

Further, when performing addition readout control, the readout control unit 100 prevents the signal processing units 64 (the signal processing units 64a and 64c in FIG. 4) connected to the second output unit from processing the pixel signals. A signal processing unit 64 connected to the two output units may be controlled. In this case, the read control unit 100 stops the supply of the clock signal to the signal processing unit 64 connected to the second output unit as in the example shown in FIG. The signal processing unit 64 may not process the pixel signals.

(Modification 6)
The imaging elements and imaging devices described in the above embodiments and modifications are applicable to cameras, smartphones, tablets, cameras built into PCs, vehicle-mounted cameras, cameras mounted on unmanned aerial vehicles (drones, radio-controlled machines, etc.), etc. may be

Although various embodiments and modifications have been described above, the present invention is not limited to these contents. Other aspects conceivable within the scope of the technical idea of the present invention are also included in the scope of the present invention.

The disclosures of the following priority applications are hereby incorporated by reference:
Japanese Patent Application No. 2019-69146 (filed on March 29, 2019)

DESCRIPTION OF SYMBOLS 1... Imaging device 3... Imaging element 4... Control part 10... Pixel 11... Photoelectric conversion part 25... Vertical signal line 40... Column circuit part 43... AD conversion part 50... Horizontal transfer part 60 Processing unit 65 Conversion unit 70 Signal output unit 71 Output I/F unit 100 Read control unit 110 First supply unit 120 Second supply unit

Claims (18)

a first photoelectric conversion unit and a second photoelectric conversion unit that generate charges by photoelectric conversion and are provided in the row direction ;
a first signal line that outputs a first signal based on the charge generated by the first photoelectric conversion unit and is arranged in a column direction ;
a second signal line that outputs a second signal based on the charge generated by the second photoelectric conversion unit and is wired in the column direction ;
a first AD converter that converts at least one of the first signal and the second signal, which are analog signals, into a digital signal;
a second AD converter that converts the second signal, which is an analog signal, into a digital signal;
a first output unit that outputs at least one of the first signal and the second signal converted into digital signals by the first AD conversion unit to a processing unit that performs signal processing;
a second output unit that outputs the second signal converted into a digital signal by the second AD conversion unit to the processing unit;
a first control for outputting the first signal and the second signal to the processing unit by the first output unit; outputting the first signal to the processing unit by the first output unit and outputting the second signal A control unit that performs a second control for outputting to the processing unit by the second output unit;
An image sensor. In the imaging device according to claim 1,
In the first control, the control section transmits a control signal to the first output section and does not transmit a control signal to the second output section. In the imaging device according to claim 1 or claim 2,
The control unit, in the first control, controls the second output unit so as not to output the second signal to the processing unit. In the imaging device according to any one of claims 1 to 3,
The processing unit has a first processing unit connected to at least one of the first output unit and the second output unit, and a second processing unit connected to the second output unit,
The processing unit is an imaging device that processes the first signal and the second signal in the first control in the first control. In the imaging device according to claim 4,
In the first control, the control section transmits a control signal to the first processing section and does not transmit a control signal to the second processing section. In the imaging device according to claim 4 or claim 5,
The control section controls the second processing section so as not to process at least one of the first signal and the second signal in the first control. In the imaging device according to any one of claims 4 to 6,
In the second control, the processing section processes the first signal with the first processing section and processes the second signal with the second processing section. In the imaging device according to any one of claims 1 to 7,
An imaging device comprising a conversion section that converts a signal processed by the processing section so that the signal can be divided and output to a plurality of output circuits. In the imaging device according to any one of claims 1 to 8,
In the first control, the control section causes the first output section to output a signal obtained by adding the first signal and the second signal to the processing section. In the imaging device according to any one of claims 1 to 9,
a connecting portion capable of connecting the first signal line and the second signal line;
In the first control, the connection section electrically connects the first signal line and the second signal line. In the imaging device according to any one of claims 1 to 9,
A connection section capable of connecting the first output section and the second output section,
The connection section is an imaging device that electrically connects the first output section and the second output section in the first control. In the imaging device according to any one of claims 1 to 11,
The first output unit has a first output line for outputting at least one of the first signal and the second signal to the processing unit,
A said 2nd output part is an imaging device which has a 2nd output line which outputs a said 2nd signal to the said process part. In the imaging device according to claim 12,
The first output unit has an amplifier that amplifies the signal output from the first output line,
The image pickup device, wherein the second output section has an amplification section that amplifies the signal output from the second output line. In the imaging device according to any one of claims 1 to 13 ,
The first AD converter converts an analog signal obtained by adding the first signal and the second signal into a first digital signal in the first control, and converts the first digital signal, which is an analog signal, in the second control. converting the signal into a second digital signal;
The first output section outputs the first digital signal to the processing section in the first control, and outputs the second digital signal to the processing section in the second control. In the imaging device according to any one of claims 1 to 14 ,
the first photoelectric conversion unit and the second photoelectric conversion unit are provided in a row direction,
The first signal line and the second signal line are provided in a column direction ,
The first output section and the second output section are provided in the row direction of the imaging device. In the imaging device according to claim 15,
The imaging device, wherein the first output section and the second output section are signal lines wired in the row direction. In the imaging device according to claim 15,
The imaging device, wherein the first output section and the second output section are connection sections provided in the row direction. an imaging device according to any one of claims 1 to 17 ;
a generation unit that generates image data based on the signal processed by the processing unit;
An imaging device comprising:

Images